1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include <linux/string_helpers.h>
7
8 #include <drm/drm_fixed.h>
9 #include <drm/drm_print.h>
10
11 #include "i915_reg.h"
12 #include "i915_utils.h"
13 #include "intel_atomic.h"
14 #include "intel_crtc.h"
15 #include "intel_ddi.h"
16 #include "intel_de.h"
17 #include "intel_display_regs.h"
18 #include "intel_display_types.h"
19 #include "intel_dp.h"
20 #include "intel_fdi.h"
21 #include "intel_fdi_regs.h"
22 #include "intel_link_bw.h"
23
24 struct intel_fdi_funcs {
25 void (*fdi_link_train)(struct intel_crtc *crtc,
26 const struct intel_crtc_state *crtc_state);
27 };
28
assert_fdi_tx(struct intel_display * display,enum pipe pipe,bool state)29 static void assert_fdi_tx(struct intel_display *display,
30 enum pipe pipe, bool state)
31 {
32 bool cur_state;
33
34 if (HAS_DDI(display)) {
35 /*
36 * DDI does not have a specific FDI_TX register.
37 *
38 * FDI is never fed from EDP transcoder
39 * so pipe->transcoder cast is fine here.
40 */
41 enum transcoder cpu_transcoder = (enum transcoder)pipe;
42 cur_state = intel_de_read(display,
43 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
44 } else {
45 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
46 }
47 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
48 "FDI TX state assertion failure (expected %s, current %s)\n",
49 str_on_off(state), str_on_off(cur_state));
50 }
51
assert_fdi_tx_enabled(struct intel_display * display,enum pipe pipe)52 void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe)
53 {
54 assert_fdi_tx(display, pipe, true);
55 }
56
assert_fdi_tx_disabled(struct intel_display * display,enum pipe pipe)57 void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe)
58 {
59 assert_fdi_tx(display, pipe, false);
60 }
61
assert_fdi_rx(struct intel_display * display,enum pipe pipe,bool state)62 static void assert_fdi_rx(struct intel_display *display,
63 enum pipe pipe, bool state)
64 {
65 bool cur_state;
66
67 cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;
68 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
69 "FDI RX state assertion failure (expected %s, current %s)\n",
70 str_on_off(state), str_on_off(cur_state));
71 }
72
assert_fdi_rx_enabled(struct intel_display * display,enum pipe pipe)73 void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe)
74 {
75 assert_fdi_rx(display, pipe, true);
76 }
77
assert_fdi_rx_disabled(struct intel_display * display,enum pipe pipe)78 void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe)
79 {
80 assert_fdi_rx(display, pipe, false);
81 }
82
assert_fdi_tx_pll_enabled(struct intel_display * display,enum pipe pipe)83 void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe)
84 {
85 bool cur_state;
86
87 /* ILK FDI PLL is always enabled */
88 if (display->platform.ironlake)
89 return;
90
91 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
92 if (HAS_DDI(display))
93 return;
94
95 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;
96 INTEL_DISPLAY_STATE_WARN(display, !cur_state,
97 "FDI TX PLL assertion failure, should be active but is disabled\n");
98 }
99
assert_fdi_rx_pll(struct intel_display * display,enum pipe pipe,bool state)100 static void assert_fdi_rx_pll(struct intel_display *display,
101 enum pipe pipe, bool state)
102 {
103 bool cur_state;
104
105 cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
106 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
107 "FDI RX PLL assertion failure (expected %s, current %s)\n",
108 str_on_off(state), str_on_off(cur_state));
109 }
110
assert_fdi_rx_pll_enabled(struct intel_display * display,enum pipe pipe)111 void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)
112 {
113 assert_fdi_rx_pll(display, pipe, true);
114 }
115
assert_fdi_rx_pll_disabled(struct intel_display * display,enum pipe pipe)116 void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)
117 {
118 assert_fdi_rx_pll(display, pipe, false);
119 }
120
intel_fdi_link_train(struct intel_crtc * crtc,const struct intel_crtc_state * crtc_state)121 void intel_fdi_link_train(struct intel_crtc *crtc,
122 const struct intel_crtc_state *crtc_state)
123 {
124 struct intel_display *display = to_intel_display(crtc);
125
126 display->funcs.fdi->fdi_link_train(crtc, crtc_state);
127 }
128
129 /**
130 * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs
131 * @state: intel atomic state
132 *
133 * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is
134 * known to affect the available FDI BW for the former CRTC. In practice this
135 * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by
136 * CRTC C) and CRTC C is getting disabled.
137 *
138 * Returns 0 in case of success, or a negative error code otherwise.
139 */
intel_fdi_add_affected_crtcs(struct intel_atomic_state * state)140 int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
141 {
142 struct intel_display *display = to_intel_display(state);
143 const struct intel_crtc_state *old_crtc_state;
144 const struct intel_crtc_state *new_crtc_state;
145 struct intel_crtc *crtc;
146
147 if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3)
148 return 0;
149
150 crtc = intel_crtc_for_pipe(display, PIPE_C);
151 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
152 if (!new_crtc_state)
153 return 0;
154
155 if (!intel_crtc_needs_modeset(new_crtc_state))
156 return 0;
157
158 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
159 if (!old_crtc_state->fdi_lanes)
160 return 0;
161
162 crtc = intel_crtc_for_pipe(display, PIPE_B);
163 new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
164 if (IS_ERR(new_crtc_state))
165 return PTR_ERR(new_crtc_state);
166
167 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
168 if (!old_crtc_state->fdi_lanes)
169 return 0;
170
171 return intel_modeset_pipes_in_mask_early(state,
172 "FDI link BW decrease on pipe C",
173 BIT(PIPE_B));
174 }
175
176 /* units of 100MHz */
pipe_required_fdi_lanes(struct intel_crtc_state * crtc_state)177 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
178 {
179 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
180 return crtc_state->fdi_lanes;
181
182 return 0;
183 }
184
ilk_check_fdi_lanes(struct intel_display * display,enum pipe pipe,struct intel_crtc_state * pipe_config,enum pipe * pipe_to_reduce)185 static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe,
186 struct intel_crtc_state *pipe_config,
187 enum pipe *pipe_to_reduce)
188 {
189 struct drm_atomic_state *state = pipe_config->uapi.state;
190 struct intel_crtc *other_crtc;
191 struct intel_crtc_state *other_crtc_state;
192
193 *pipe_to_reduce = pipe;
194
195 drm_dbg_kms(display->drm,
196 "checking fdi config on pipe %c, lanes %i\n",
197 pipe_name(pipe), pipe_config->fdi_lanes);
198 if (pipe_config->fdi_lanes > 4) {
199 drm_dbg_kms(display->drm,
200 "invalid fdi lane config on pipe %c: %i lanes\n",
201 pipe_name(pipe), pipe_config->fdi_lanes);
202 return -EINVAL;
203 }
204
205 if (display->platform.haswell || display->platform.broadwell) {
206 if (pipe_config->fdi_lanes > 2) {
207 drm_dbg_kms(display->drm,
208 "only 2 lanes on haswell, required: %i lanes\n",
209 pipe_config->fdi_lanes);
210 return -EINVAL;
211 } else {
212 return 0;
213 }
214 }
215
216 if (INTEL_NUM_PIPES(display) == 2)
217 return 0;
218
219 /* Ivybridge 3 pipe is really complicated */
220 switch (pipe) {
221 case PIPE_A:
222 return 0;
223 case PIPE_B:
224 if (pipe_config->fdi_lanes <= 2)
225 return 0;
226
227 other_crtc = intel_crtc_for_pipe(display, PIPE_C);
228 other_crtc_state =
229 intel_atomic_get_crtc_state(state, other_crtc);
230 if (IS_ERR(other_crtc_state))
231 return PTR_ERR(other_crtc_state);
232
233 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
234 drm_dbg_kms(display->drm,
235 "invalid shared fdi lane config on pipe %c: %i lanes\n",
236 pipe_name(pipe), pipe_config->fdi_lanes);
237 return -EINVAL;
238 }
239 return 0;
240 case PIPE_C:
241 if (pipe_config->fdi_lanes > 2) {
242 drm_dbg_kms(display->drm,
243 "only 2 lanes on pipe %c: required %i lanes\n",
244 pipe_name(pipe), pipe_config->fdi_lanes);
245 return -EINVAL;
246 }
247
248 other_crtc = intel_crtc_for_pipe(display, PIPE_B);
249 other_crtc_state =
250 intel_atomic_get_crtc_state(state, other_crtc);
251 if (IS_ERR(other_crtc_state))
252 return PTR_ERR(other_crtc_state);
253
254 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
255 drm_dbg_kms(display->drm,
256 "fdi link B uses too many lanes to enable link C\n");
257
258 *pipe_to_reduce = PIPE_B;
259
260 return -EINVAL;
261 }
262 return 0;
263 default:
264 MISSING_CASE(pipe);
265 return 0;
266 }
267 }
268
intel_fdi_pll_freq_update(struct intel_display * display)269 void intel_fdi_pll_freq_update(struct intel_display *display)
270 {
271 if (display->platform.ironlake) {
272 u32 fdi_pll_clk;
273
274 fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
275
276 display->fdi.pll_freq = (fdi_pll_clk + 2) * 10000;
277 } else if (display->platform.sandybridge || display->platform.ivybridge) {
278 display->fdi.pll_freq = 270000;
279 } else {
280 return;
281 }
282
283 drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq);
284 }
285
intel_fdi_link_freq(struct intel_display * display,const struct intel_crtc_state * pipe_config)286 int intel_fdi_link_freq(struct intel_display *display,
287 const struct intel_crtc_state *pipe_config)
288 {
289 if (HAS_DDI(display))
290 return pipe_config->port_clock; /* SPLL */
291 else
292 return display->fdi.pll_freq;
293 }
294
295 /**
296 * intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp
297 * @crtc_state: the crtc state
298 *
299 * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
300 * call this function during state computation in the simple case where the
301 * link bpp will always match the pipe bpp. This is the case for all non-DP
302 * encoders, while DP encoders will use a link bpp lower than pipe bpp in case
303 * of DSC compression.
304 *
305 * Returns %true in case of success, %false if pipe bpp would need to be
306 * reduced below its valid range.
307 */
intel_fdi_compute_pipe_bpp(struct intel_crtc_state * crtc_state)308 bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
309 {
310 int pipe_bpp = min(crtc_state->pipe_bpp,
311 fxp_q4_to_int(crtc_state->max_link_bpp_x16));
312
313 pipe_bpp = rounddown(pipe_bpp, 2 * 3);
314
315 if (pipe_bpp < 6 * 3)
316 return false;
317
318 crtc_state->pipe_bpp = pipe_bpp;
319
320 return true;
321 }
322
ilk_fdi_compute_config(struct intel_crtc * crtc,struct intel_crtc_state * pipe_config)323 int ilk_fdi_compute_config(struct intel_crtc *crtc,
324 struct intel_crtc_state *pipe_config)
325 {
326 struct intel_display *display = to_intel_display(crtc);
327 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
328 int lane, link_bw, fdi_dotclock;
329
330 /* FDI is a binary signal running at ~2.7GHz, encoding
331 * each output octet as 10 bits. The actual frequency
332 * is stored as a divider into a 100MHz clock, and the
333 * mode pixel clock is stored in units of 1KHz.
334 * Hence the bw of each lane in terms of the mode signal
335 * is:
336 */
337 link_bw = intel_fdi_link_freq(display, pipe_config);
338
339 fdi_dotclock = adjusted_mode->crtc_clock;
340
341 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
342 pipe_config->pipe_bpp);
343
344 pipe_config->fdi_lanes = lane;
345
346 intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp),
347 lane, fdi_dotclock,
348 link_bw,
349 intel_dp_bw_fec_overhead(false),
350 &pipe_config->fdi_m_n);
351
352 return 0;
353 }
354
intel_fdi_atomic_check_bw(struct intel_atomic_state * state,struct intel_crtc * crtc,struct intel_crtc_state * pipe_config,struct intel_link_bw_limits * limits)355 static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
356 struct intel_crtc *crtc,
357 struct intel_crtc_state *pipe_config,
358 struct intel_link_bw_limits *limits)
359 {
360 struct intel_display *display = to_intel_display(crtc);
361 enum pipe pipe_to_reduce;
362 int ret;
363
364 ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config,
365 &pipe_to_reduce);
366 if (ret != -EINVAL)
367 return ret;
368
369 ret = intel_link_bw_reduce_bpp(state, limits,
370 BIT(pipe_to_reduce),
371 "FDI link BW");
372
373 return ret ? : -EAGAIN;
374 }
375
376 /**
377 * intel_fdi_atomic_check_link - check all modeset FDI link configuration
378 * @state: intel atomic state
379 * @limits: link BW limits
380 *
381 * Check the link configuration for all modeset FDI outputs. If the
382 * configuration is invalid @limits will be updated if possible to
383 * reduce the total BW, after which the configuration for all CRTCs in
384 * @state must be recomputed with the updated @limits.
385 *
386 * Returns:
387 * - 0 if the configuration is valid
388 * - %-EAGAIN, if the configuration is invalid and @limits got updated
389 * with fallback values with which the configuration of all CRTCs
390 * in @state must be recomputed
391 * - Other negative error, if the configuration is invalid without a
392 * fallback possibility, or the check failed for another reason
393 */
intel_fdi_atomic_check_link(struct intel_atomic_state * state,struct intel_link_bw_limits * limits)394 int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
395 struct intel_link_bw_limits *limits)
396 {
397 struct intel_crtc *crtc;
398 struct intel_crtc_state *crtc_state;
399 int i;
400
401 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
402 int ret;
403
404 if (!crtc_state->has_pch_encoder ||
405 !intel_crtc_needs_modeset(crtc_state) ||
406 !crtc_state->hw.enable)
407 continue;
408
409 ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
410 if (ret)
411 return ret;
412 }
413
414 return 0;
415 }
416
cpt_set_fdi_bc_bifurcation(struct intel_display * display,bool enable)417 static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable)
418 {
419 u32 temp;
420
421 temp = intel_de_read(display, SOUTH_CHICKEN1);
422 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
423 return;
424
425 drm_WARN_ON(display->drm,
426 intel_de_read(display, FDI_RX_CTL(PIPE_B)) &
427 FDI_RX_ENABLE);
428 drm_WARN_ON(display->drm,
429 intel_de_read(display, FDI_RX_CTL(PIPE_C)) &
430 FDI_RX_ENABLE);
431
432 temp &= ~FDI_BC_BIFURCATION_SELECT;
433 if (enable)
434 temp |= FDI_BC_BIFURCATION_SELECT;
435
436 drm_dbg_kms(display->drm, "%sabling fdi C rx\n",
437 enable ? "en" : "dis");
438 intel_de_write(display, SOUTH_CHICKEN1, temp);
439 intel_de_posting_read(display, SOUTH_CHICKEN1);
440 }
441
ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state * crtc_state)442 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
443 {
444 struct intel_display *display = to_intel_display(crtc_state);
445 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
446
447 switch (crtc->pipe) {
448 case PIPE_A:
449 break;
450 case PIPE_B:
451 if (crtc_state->fdi_lanes > 2)
452 cpt_set_fdi_bc_bifurcation(display, false);
453 else
454 cpt_set_fdi_bc_bifurcation(display, true);
455
456 break;
457 case PIPE_C:
458 cpt_set_fdi_bc_bifurcation(display, true);
459
460 break;
461 default:
462 MISSING_CASE(crtc->pipe);
463 }
464 }
465
intel_fdi_normal_train(struct intel_crtc * crtc)466 void intel_fdi_normal_train(struct intel_crtc *crtc)
467 {
468 struct intel_display *display = to_intel_display(crtc);
469 enum pipe pipe = crtc->pipe;
470 i915_reg_t reg;
471 u32 temp;
472
473 /* enable normal train */
474 reg = FDI_TX_CTL(pipe);
475 temp = intel_de_read(display, reg);
476 if (display->platform.ivybridge) {
477 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
478 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
479 } else {
480 temp &= ~FDI_LINK_TRAIN_NONE;
481 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
482 }
483 intel_de_write(display, reg, temp);
484
485 reg = FDI_RX_CTL(pipe);
486 temp = intel_de_read(display, reg);
487 if (HAS_PCH_CPT(display)) {
488 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
489 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
490 } else {
491 temp &= ~FDI_LINK_TRAIN_NONE;
492 temp |= FDI_LINK_TRAIN_NONE;
493 }
494 intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
495
496 /* wait one idle pattern time */
497 intel_de_posting_read(display, reg);
498 udelay(1000);
499
500 /* IVB wants error correction enabled */
501 if (display->platform.ivybridge)
502 intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
503 }
504
505 /* The FDI link training functions for ILK/Ibexpeak. */
ilk_fdi_link_train(struct intel_crtc * crtc,const struct intel_crtc_state * crtc_state)506 static void ilk_fdi_link_train(struct intel_crtc *crtc,
507 const struct intel_crtc_state *crtc_state)
508 {
509 struct intel_display *display = to_intel_display(crtc);
510 enum pipe pipe = crtc->pipe;
511 i915_reg_t reg;
512 u32 temp, tries;
513
514 /*
515 * Write the TU size bits before fdi link training, so that error
516 * detection works.
517 */
518 intel_de_write(display, FDI_RX_TUSIZE1(pipe),
519 intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
520
521 /* FDI needs bits from pipe first */
522 assert_transcoder_enabled(display, crtc_state->cpu_transcoder);
523
524 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
525 for train result */
526 reg = FDI_RX_IMR(pipe);
527 temp = intel_de_read(display, reg);
528 temp &= ~FDI_RX_SYMBOL_LOCK;
529 temp &= ~FDI_RX_BIT_LOCK;
530 intel_de_write(display, reg, temp);
531 intel_de_read(display, reg);
532 udelay(150);
533
534 /* enable CPU FDI TX and PCH FDI RX */
535 reg = FDI_TX_CTL(pipe);
536 temp = intel_de_read(display, reg);
537 temp &= ~FDI_DP_PORT_WIDTH_MASK;
538 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
539 temp &= ~FDI_LINK_TRAIN_NONE;
540 temp |= FDI_LINK_TRAIN_PATTERN_1;
541 intel_de_write(display, reg, temp | FDI_TX_ENABLE);
542
543 reg = FDI_RX_CTL(pipe);
544 temp = intel_de_read(display, reg);
545 temp &= ~FDI_LINK_TRAIN_NONE;
546 temp |= FDI_LINK_TRAIN_PATTERN_1;
547 intel_de_write(display, reg, temp | FDI_RX_ENABLE);
548
549 intel_de_posting_read(display, reg);
550 udelay(150);
551
552 /* Ironlake workaround, enable clock pointer after FDI enable*/
553 intel_de_write(display, FDI_RX_CHICKEN(pipe),
554 FDI_RX_PHASE_SYNC_POINTER_OVR);
555 intel_de_write(display, FDI_RX_CHICKEN(pipe),
556 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
557
558 reg = FDI_RX_IIR(pipe);
559 for (tries = 0; tries < 5; tries++) {
560 temp = intel_de_read(display, reg);
561 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
562
563 if ((temp & FDI_RX_BIT_LOCK)) {
564 drm_dbg_kms(display->drm, "FDI train 1 done.\n");
565 intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK);
566 break;
567 }
568 }
569 if (tries == 5)
570 drm_err(display->drm, "FDI train 1 fail!\n");
571
572 /* Train 2 */
573 intel_de_rmw(display, FDI_TX_CTL(pipe),
574 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
575 intel_de_rmw(display, FDI_RX_CTL(pipe),
576 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
577 intel_de_posting_read(display, FDI_RX_CTL(pipe));
578 udelay(150);
579
580 reg = FDI_RX_IIR(pipe);
581 for (tries = 0; tries < 5; tries++) {
582 temp = intel_de_read(display, reg);
583 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
584
585 if (temp & FDI_RX_SYMBOL_LOCK) {
586 intel_de_write(display, reg,
587 temp | FDI_RX_SYMBOL_LOCK);
588 drm_dbg_kms(display->drm, "FDI train 2 done.\n");
589 break;
590 }
591 }
592 if (tries == 5)
593 drm_err(display->drm, "FDI train 2 fail!\n");
594
595 drm_dbg_kms(display->drm, "FDI train done\n");
596
597 }
598
599 static const int snb_b_fdi_train_param[] = {
600 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
601 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
602 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
603 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
604 };
605
606 /* The FDI link training functions for SNB/Cougarpoint. */
gen6_fdi_link_train(struct intel_crtc * crtc,const struct intel_crtc_state * crtc_state)607 static void gen6_fdi_link_train(struct intel_crtc *crtc,
608 const struct intel_crtc_state *crtc_state)
609 {
610 struct intel_display *display = to_intel_display(crtc);
611 enum pipe pipe = crtc->pipe;
612 i915_reg_t reg;
613 u32 temp, i, retry;
614
615 /*
616 * Write the TU size bits before fdi link training, so that error
617 * detection works.
618 */
619 intel_de_write(display, FDI_RX_TUSIZE1(pipe),
620 intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
621
622 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
623 for train result */
624 reg = FDI_RX_IMR(pipe);
625 temp = intel_de_read(display, reg);
626 temp &= ~FDI_RX_SYMBOL_LOCK;
627 temp &= ~FDI_RX_BIT_LOCK;
628 intel_de_write(display, reg, temp);
629
630 intel_de_posting_read(display, reg);
631 udelay(150);
632
633 /* enable CPU FDI TX and PCH FDI RX */
634 reg = FDI_TX_CTL(pipe);
635 temp = intel_de_read(display, reg);
636 temp &= ~FDI_DP_PORT_WIDTH_MASK;
637 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
638 temp &= ~FDI_LINK_TRAIN_NONE;
639 temp |= FDI_LINK_TRAIN_PATTERN_1;
640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
641 /* SNB-B */
642 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
643 intel_de_write(display, reg, temp | FDI_TX_ENABLE);
644
645 intel_de_write(display, FDI_RX_MISC(pipe),
646 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
647
648 reg = FDI_RX_CTL(pipe);
649 temp = intel_de_read(display, reg);
650 if (HAS_PCH_CPT(display)) {
651 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
652 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
653 } else {
654 temp &= ~FDI_LINK_TRAIN_NONE;
655 temp |= FDI_LINK_TRAIN_PATTERN_1;
656 }
657 intel_de_write(display, reg, temp | FDI_RX_ENABLE);
658
659 intel_de_posting_read(display, reg);
660 udelay(150);
661
662 for (i = 0; i < 4; i++) {
663 intel_de_rmw(display, FDI_TX_CTL(pipe),
664 FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
665 intel_de_posting_read(display, FDI_TX_CTL(pipe));
666 udelay(500);
667
668 for (retry = 0; retry < 5; retry++) {
669 reg = FDI_RX_IIR(pipe);
670 temp = intel_de_read(display, reg);
671 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
672 if (temp & FDI_RX_BIT_LOCK) {
673 intel_de_write(display, reg,
674 temp | FDI_RX_BIT_LOCK);
675 drm_dbg_kms(display->drm,
676 "FDI train 1 done.\n");
677 break;
678 }
679 udelay(50);
680 }
681 if (retry < 5)
682 break;
683 }
684 if (i == 4)
685 drm_err(display->drm, "FDI train 1 fail!\n");
686
687 /* Train 2 */
688 reg = FDI_TX_CTL(pipe);
689 temp = intel_de_read(display, reg);
690 temp &= ~FDI_LINK_TRAIN_NONE;
691 temp |= FDI_LINK_TRAIN_PATTERN_2;
692 if (display->platform.sandybridge) {
693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
694 /* SNB-B */
695 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
696 }
697 intel_de_write(display, reg, temp);
698
699 reg = FDI_RX_CTL(pipe);
700 temp = intel_de_read(display, reg);
701 if (HAS_PCH_CPT(display)) {
702 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
703 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
704 } else {
705 temp &= ~FDI_LINK_TRAIN_NONE;
706 temp |= FDI_LINK_TRAIN_PATTERN_2;
707 }
708 intel_de_write(display, reg, temp);
709
710 intel_de_posting_read(display, reg);
711 udelay(150);
712
713 for (i = 0; i < 4; i++) {
714 intel_de_rmw(display, FDI_TX_CTL(pipe),
715 FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
716 intel_de_posting_read(display, FDI_TX_CTL(pipe));
717 udelay(500);
718
719 for (retry = 0; retry < 5; retry++) {
720 reg = FDI_RX_IIR(pipe);
721 temp = intel_de_read(display, reg);
722 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
723 if (temp & FDI_RX_SYMBOL_LOCK) {
724 intel_de_write(display, reg,
725 temp | FDI_RX_SYMBOL_LOCK);
726 drm_dbg_kms(display->drm,
727 "FDI train 2 done.\n");
728 break;
729 }
730 udelay(50);
731 }
732 if (retry < 5)
733 break;
734 }
735 if (i == 4)
736 drm_err(display->drm, "FDI train 2 fail!\n");
737
738 drm_dbg_kms(display->drm, "FDI train done.\n");
739 }
740
741 /* Manual link training for Ivy Bridge A0 parts */
ivb_manual_fdi_link_train(struct intel_crtc * crtc,const struct intel_crtc_state * crtc_state)742 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
743 const struct intel_crtc_state *crtc_state)
744 {
745 struct intel_display *display = to_intel_display(crtc);
746 enum pipe pipe = crtc->pipe;
747 i915_reg_t reg;
748 u32 temp, i, j;
749
750 ivb_update_fdi_bc_bifurcation(crtc_state);
751
752 /*
753 * Write the TU size bits before fdi link training, so that error
754 * detection works.
755 */
756 intel_de_write(display, FDI_RX_TUSIZE1(pipe),
757 intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
758
759 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
760 for train result */
761 reg = FDI_RX_IMR(pipe);
762 temp = intel_de_read(display, reg);
763 temp &= ~FDI_RX_SYMBOL_LOCK;
764 temp &= ~FDI_RX_BIT_LOCK;
765 intel_de_write(display, reg, temp);
766
767 intel_de_posting_read(display, reg);
768 udelay(150);
769
770 drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n",
771 intel_de_read(display, FDI_RX_IIR(pipe)));
772
773 /* Try each vswing and preemphasis setting twice before moving on */
774 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
775 /* disable first in case we need to retry */
776 reg = FDI_TX_CTL(pipe);
777 temp = intel_de_read(display, reg);
778 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
779 temp &= ~FDI_TX_ENABLE;
780 intel_de_write(display, reg, temp);
781
782 reg = FDI_RX_CTL(pipe);
783 temp = intel_de_read(display, reg);
784 temp &= ~FDI_LINK_TRAIN_AUTO;
785 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
786 temp &= ~FDI_RX_ENABLE;
787 intel_de_write(display, reg, temp);
788
789 /* enable CPU FDI TX and PCH FDI RX */
790 reg = FDI_TX_CTL(pipe);
791 temp = intel_de_read(display, reg);
792 temp &= ~FDI_DP_PORT_WIDTH_MASK;
793 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
794 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
795 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
796 temp |= snb_b_fdi_train_param[j/2];
797 temp |= FDI_COMPOSITE_SYNC;
798 intel_de_write(display, reg, temp | FDI_TX_ENABLE);
799
800 intel_de_write(display, FDI_RX_MISC(pipe),
801 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
802
803 reg = FDI_RX_CTL(pipe);
804 temp = intel_de_read(display, reg);
805 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
806 temp |= FDI_COMPOSITE_SYNC;
807 intel_de_write(display, reg, temp | FDI_RX_ENABLE);
808
809 intel_de_posting_read(display, reg);
810 udelay(1); /* should be 0.5us */
811
812 for (i = 0; i < 4; i++) {
813 reg = FDI_RX_IIR(pipe);
814 temp = intel_de_read(display, reg);
815 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
816
817 if (temp & FDI_RX_BIT_LOCK ||
818 (intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {
819 intel_de_write(display, reg,
820 temp | FDI_RX_BIT_LOCK);
821 drm_dbg_kms(display->drm,
822 "FDI train 1 done, level %i.\n",
823 i);
824 break;
825 }
826 udelay(1); /* should be 0.5us */
827 }
828 if (i == 4) {
829 drm_dbg_kms(display->drm,
830 "FDI train 1 fail on vswing %d\n", j / 2);
831 continue;
832 }
833
834 /* Train 2 */
835 intel_de_rmw(display, FDI_TX_CTL(pipe),
836 FDI_LINK_TRAIN_NONE_IVB,
837 FDI_LINK_TRAIN_PATTERN_2_IVB);
838 intel_de_rmw(display, FDI_RX_CTL(pipe),
839 FDI_LINK_TRAIN_PATTERN_MASK_CPT,
840 FDI_LINK_TRAIN_PATTERN_2_CPT);
841 intel_de_posting_read(display, FDI_RX_CTL(pipe));
842 udelay(2); /* should be 1.5us */
843
844 for (i = 0; i < 4; i++) {
845 reg = FDI_RX_IIR(pipe);
846 temp = intel_de_read(display, reg);
847 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
848
849 if (temp & FDI_RX_SYMBOL_LOCK ||
850 (intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {
851 intel_de_write(display, reg,
852 temp | FDI_RX_SYMBOL_LOCK);
853 drm_dbg_kms(display->drm,
854 "FDI train 2 done, level %i.\n",
855 i);
856 goto train_done;
857 }
858 udelay(2); /* should be 1.5us */
859 }
860 if (i == 4)
861 drm_dbg_kms(display->drm,
862 "FDI train 2 fail on vswing %d\n", j / 2);
863 }
864
865 train_done:
866 drm_dbg_kms(display->drm, "FDI train done.\n");
867 }
868
869 /* Starting with Haswell, different DDI ports can work in FDI mode for
870 * connection to the PCH-located connectors. For this, it is necessary to train
871 * both the DDI port and PCH receiver for the desired DDI buffer settings.
872 *
873 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
874 * please note that when FDI mode is active on DDI E, it shares 2 lines with
875 * DDI A (which is used for eDP)
876 */
hsw_fdi_link_train(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)877 void hsw_fdi_link_train(struct intel_encoder *encoder,
878 const struct intel_crtc_state *crtc_state)
879 {
880 struct intel_display *display = to_intel_display(crtc_state);
881 u32 temp, i, rx_ctl_val;
882 int n_entries;
883
884 encoder->get_buf_trans(encoder, crtc_state, &n_entries);
885
886 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
887
888 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
889 * mode set "sequence for CRT port" document:
890 * - TP1 to TP2 time with the default value
891 * - FDI delay to 90h
892 *
893 * WaFDIAutoLinkSetTimingOverrride:hsw
894 */
895 intel_de_write(display, FDI_RX_MISC(PIPE_A),
896 FDI_RX_PWRDN_LANE1_VAL(2) |
897 FDI_RX_PWRDN_LANE0_VAL(2) |
898 FDI_RX_TP1_TO_TP2_48 |
899 FDI_RX_FDI_DELAY_90);
900
901 /* Enable the PCH Receiver FDI PLL */
902 rx_ctl_val = display->fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
903 FDI_RX_PLL_ENABLE |
904 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
905 intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
906 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
907 udelay(220);
908
909 /* Switch from Rawclk to PCDclk */
910 rx_ctl_val |= FDI_PCDCLK;
911 intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
912
913 /* Configure Port Clock Select */
914 drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);
915 intel_ddi_enable_clock(encoder, crtc_state);
916
917 /* Start the training iterating through available voltages and emphasis,
918 * testing each value twice. */
919 for (i = 0; i < n_entries * 2; i++) {
920 /* Configure DP_TP_CTL with auto-training */
921 intel_de_write(display, DP_TP_CTL(PORT_E),
922 DP_TP_CTL_FDI_AUTOTRAIN |
923 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
924 DP_TP_CTL_LINK_TRAIN_PAT1 |
925 DP_TP_CTL_ENABLE);
926
927 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
928 * DDI E does not support port reversal, the functionality is
929 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
930 * port reversal bit */
931 intel_de_write(display, DDI_BUF_CTL(PORT_E),
932 DDI_BUF_CTL_ENABLE |
933 ((crtc_state->fdi_lanes - 1) << 1) |
934 DDI_BUF_TRANS_SELECT(i / 2));
935 intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));
936
937 udelay(600);
938
939 /* Program PCH FDI Receiver TU */
940 intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
941
942 /* Enable PCH FDI Receiver with auto-training */
943 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
944 intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
945 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
946
947 /* Wait for FDI receiver lane calibration */
948 udelay(30);
949
950 /* Unset FDI_RX_MISC pwrdn lanes */
951 intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
952 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
953 intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
954
955 /* Wait for FDI auto training time */
956 udelay(5);
957
958 temp = intel_de_read(display, DP_TP_STATUS(PORT_E));
959 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
960 drm_dbg_kms(display->drm,
961 "FDI link training done on step %d\n", i);
962 break;
963 }
964
965 /*
966 * Leave things enabled even if we failed to train FDI.
967 * Results in less fireworks from the state checker.
968 */
969 if (i == n_entries * 2 - 1) {
970 drm_err(display->drm, "FDI link training failed!\n");
971 break;
972 }
973
974 rx_ctl_val &= ~FDI_RX_ENABLE;
975 intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
976 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
977
978 intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
979 intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));
980
981 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
982 intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);
983 intel_de_posting_read(display, DP_TP_CTL(PORT_E));
984
985 intel_wait_ddi_buf_idle(display, PORT_E);
986
987 /* Reset FDI_RX_MISC pwrdn lanes */
988 intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
989 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
990 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
991 intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
992 }
993
994 /* Enable normal pixel sending for FDI */
995 intel_de_write(display, DP_TP_CTL(PORT_E),
996 DP_TP_CTL_FDI_AUTOTRAIN |
997 DP_TP_CTL_LINK_TRAIN_NORMAL |
998 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
999 DP_TP_CTL_ENABLE);
1000 }
1001
hsw_fdi_disable(struct intel_encoder * encoder)1002 void hsw_fdi_disable(struct intel_encoder *encoder)
1003 {
1004 struct intel_display *display = to_intel_display(encoder);
1005
1006 /*
1007 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
1008 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
1009 * step 13 is the correct place for it. Step 18 is where it was
1010 * originally before the BUN.
1011 */
1012 intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
1013 intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
1014 intel_wait_ddi_buf_idle(display, PORT_E);
1015 intel_ddi_disable_clock(encoder);
1016 intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
1017 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
1018 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
1019 intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
1020 intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
1021 }
1022
ilk_fdi_pll_enable(const struct intel_crtc_state * crtc_state)1023 void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
1024 {
1025 struct intel_display *display = to_intel_display(crtc_state);
1026 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1027 enum pipe pipe = crtc->pipe;
1028 i915_reg_t reg;
1029 u32 temp;
1030
1031 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1032 reg = FDI_RX_CTL(pipe);
1033 temp = intel_de_read(display, reg);
1034 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
1035 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1036 temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
1037 intel_de_write(display, reg, temp | FDI_RX_PLL_ENABLE);
1038
1039 intel_de_posting_read(display, reg);
1040 udelay(200);
1041
1042 /* Switch from Rawclk to PCDclk */
1043 intel_de_rmw(display, reg, 0, FDI_PCDCLK);
1044 intel_de_posting_read(display, reg);
1045 udelay(200);
1046
1047 /* Enable CPU FDI TX PLL, always on for Ironlake */
1048 reg = FDI_TX_CTL(pipe);
1049 temp = intel_de_read(display, reg);
1050 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1051 intel_de_write(display, reg, temp | FDI_TX_PLL_ENABLE);
1052
1053 intel_de_posting_read(display, reg);
1054 udelay(100);
1055 }
1056 }
1057
ilk_fdi_pll_disable(struct intel_crtc * crtc)1058 void ilk_fdi_pll_disable(struct intel_crtc *crtc)
1059 {
1060 struct intel_display *display = to_intel_display(crtc);
1061 enum pipe pipe = crtc->pipe;
1062
1063 /* Switch from PCDclk to Rawclk */
1064 intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
1065
1066 /* Disable CPU FDI TX PLL */
1067 intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
1068 intel_de_posting_read(display, FDI_TX_CTL(pipe));
1069 udelay(100);
1070
1071 /* Wait for the clocks to turn off. */
1072 intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
1073 intel_de_posting_read(display, FDI_RX_CTL(pipe));
1074 udelay(100);
1075 }
1076
ilk_fdi_disable(struct intel_crtc * crtc)1077 void ilk_fdi_disable(struct intel_crtc *crtc)
1078 {
1079 struct intel_display *display = to_intel_display(crtc);
1080 enum pipe pipe = crtc->pipe;
1081 i915_reg_t reg;
1082 u32 temp;
1083
1084 /* disable CPU FDI tx and PCH FDI rx */
1085 intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
1086 intel_de_posting_read(display, FDI_TX_CTL(pipe));
1087
1088 reg = FDI_RX_CTL(pipe);
1089 temp = intel_de_read(display, reg);
1090 temp &= ~(0x7 << 16);
1091 temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
1092 intel_de_write(display, reg, temp & ~FDI_RX_ENABLE);
1093
1094 intel_de_posting_read(display, reg);
1095 udelay(100);
1096
1097 /* Ironlake workaround, disable clock pointer after downing FDI */
1098 if (HAS_PCH_IBX(display))
1099 intel_de_write(display, FDI_RX_CHICKEN(pipe),
1100 FDI_RX_PHASE_SYNC_POINTER_OVR);
1101
1102 /* still set train pattern 1 */
1103 intel_de_rmw(display, FDI_TX_CTL(pipe),
1104 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
1105
1106 reg = FDI_RX_CTL(pipe);
1107 temp = intel_de_read(display, reg);
1108 if (HAS_PCH_CPT(display)) {
1109 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1110 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1111 } else {
1112 temp &= ~FDI_LINK_TRAIN_NONE;
1113 temp |= FDI_LINK_TRAIN_PATTERN_1;
1114 }
1115 /* BPC in FDI rx is consistent with that in TRANSCONF */
1116 temp &= ~(0x07 << 16);
1117 temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
1118 intel_de_write(display, reg, temp);
1119
1120 intel_de_posting_read(display, reg);
1121 udelay(100);
1122 }
1123
1124 static const struct intel_fdi_funcs ilk_funcs = {
1125 .fdi_link_train = ilk_fdi_link_train,
1126 };
1127
1128 static const struct intel_fdi_funcs gen6_funcs = {
1129 .fdi_link_train = gen6_fdi_link_train,
1130 };
1131
1132 static const struct intel_fdi_funcs ivb_funcs = {
1133 .fdi_link_train = ivb_manual_fdi_link_train,
1134 };
1135
1136 void
intel_fdi_init_hook(struct intel_display * display)1137 intel_fdi_init_hook(struct intel_display *display)
1138 {
1139 if (display->platform.ironlake) {
1140 display->funcs.fdi = &ilk_funcs;
1141 } else if (display->platform.sandybridge) {
1142 display->funcs.fdi = &gen6_funcs;
1143 } else if (display->platform.ivybridge) {
1144 /* FIXME: detect B0+ stepping and use auto training */
1145 display->funcs.fdi = &ivb_funcs;
1146 }
1147 }
1148