1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments ICSSG Ethernet Driver 3 * 4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/types.h> 10 #include <linux/regmap.h> 11 12 #include "icssg_prueth.h" 13 14 #define ICSSG_NUM_CLASSIFIERS 16 15 #define ICSSG_NUM_FT1_SLOTS 8 16 #define ICSSG_NUM_FT3_SLOTS 16 17 18 #define ICSSG_NUM_CLASSIFIERS_IN_USE 5 19 20 /* Filter 1 - FT1 */ 21 #define FT1_NUM_SLOTS 8 22 #define FT1_SLOT_SIZE 0x10 /* bytes */ 23 24 /* offsets from FT1 slot base i.e. slot 1 start */ 25 #define FT1_DA0 0x0 26 #define FT1_DA1 0x4 27 #define FT1_DA0_MASK 0x8 28 #define FT1_DA1_MASK 0xc 29 30 #define FT1_N_REG(slice, n, reg) \ 31 (offs[slice].ft1_slot_base + FT1_SLOT_SIZE * (n) + (reg)) 32 33 #define FT1_LEN_MASK GENMASK(19, 16) 34 #define FT1_LEN_SHIFT 16 35 #define FT1_LEN(len) (((len) << FT1_LEN_SHIFT) & FT1_LEN_MASK) 36 #define FT1_START_MASK GENMASK(14, 0) 37 #define FT1_START(start) ((start) & FT1_START_MASK) 38 #define FT1_MATCH_SLOT(n) (GENMASK(23, 16) & (BIT(n) << 16)) 39 40 /* FT1 config type */ 41 enum ft1_cfg_type { 42 FT1_CFG_TYPE_DISABLED = 0, 43 FT1_CFG_TYPE_EQ, 44 FT1_CFG_TYPE_GT, 45 FT1_CFG_TYPE_LT, 46 }; 47 48 #define FT1_CFG_SHIFT(n) (2 * (n)) 49 #define FT1_CFG_MASK(n) (0x3 << FT1_CFG_SHIFT((n))) 50 51 /* Filter 3 - FT3 */ 52 #define FT3_NUM_SLOTS 16 53 #define FT3_SLOT_SIZE 0x20 /* bytes */ 54 55 /* offsets from FT3 slot n's base */ 56 #define FT3_START 0 57 #define FT3_START_AUTO 0x4 58 #define FT3_START_OFFSET 0x8 59 #define FT3_JUMP_OFFSET 0xc 60 #define FT3_LEN 0x10 61 #define FT3_CFG 0x14 62 #define FT3_T 0x18 63 #define FT3_T_MASK 0x1c 64 65 #define FT3_N_REG(slice, n, reg) \ 66 (offs[slice].ft3_slot_base + FT3_SLOT_SIZE * (n) + (reg)) 67 68 /* offsets from rx_class n's base */ 69 #define RX_CLASS_AND_EN 0 70 #define RX_CLASS_OR_EN 0x4 71 #define RX_CLASS_NUM_SLOTS 16 72 #define RX_CLASS_EN_SIZE 0x8 /* bytes */ 73 74 #define RX_CLASS_N_REG(slice, n, reg) \ 75 (offs[slice].rx_class_base + RX_CLASS_EN_SIZE * (n) + (reg)) 76 77 #define RX_CLASS_OR_REG(slice, n, reg) \ 78 (offs[slice].rx_class_or_base + RX_CLASS_EN_SIZE * (n) + (reg)) 79 80 /* RX Class Gates */ 81 #define RX_CLASS_GATES_SIZE 0x4 /* bytes */ 82 83 #define RX_CLASS_GATES_N_REG(slice, n) \ 84 (offs[slice].rx_class_gates_base + RX_CLASS_GATES_SIZE * (n)) 85 86 #define RX_CLASS_GATES_ALLOW_MASK BIT(6) 87 #define RX_CLASS_GATES_RAW_MASK BIT(5) 88 #define RX_CLASS_GATES_PHASE_MASK BIT(4) 89 90 /* RX Class traffic data matching bits */ 91 #define RX_CLASS_FT_UC BIT(31) 92 #define RX_CLASS_FT_MC BIT(30) 93 #define RX_CLASS_FT_BC BIT(29) 94 #define RX_CLASS_FT_FW BIT(28) 95 #define RX_CLASS_FT_RCV BIT(27) 96 #define RX_CLASS_FT_VLAN BIT(26) 97 #define RX_CLASS_FT_DA_P BIT(25) 98 #define RX_CLASS_FT_DA_I BIT(24) 99 #define RX_CLASS_FT_FT1_MATCH_MASK GENMASK(23, 16) 100 #define RX_CLASS_FT_FT1_MATCH_SHIFT 16 101 #define RX_CLASS_FT_FT3_MATCH_MASK GENMASK(15, 0) 102 #define RX_CLASS_FT_FT3_MATCH_SHIFT 0 103 104 #define RX_CLASS_FT_FT1_MATCH(slot) \ 105 ((BIT(slot) << RX_CLASS_FT_FT1_MATCH_SHIFT) & \ 106 RX_CLASS_FT_FT1_MATCH_MASK) 107 108 /* HSR/PRP protocol frame filtering */ 109 #define HSR_PTP_ETHERTYPE_OFFSET 0x12 110 #define PRP_PTP_ETHERTYPE_OFFSET 0x0C 111 #define FT3_PTP_PATTERN 0xF788 112 #define FT3_ETHERTYPE_MASK 0xFFFF0000U 113 #define FT3_VLAN_MODE_BOTH 0x1 114 #define RX_CLASS_OR_DUP_PTP 0x4200 115 #define RX_CLASS_OR_HSR_TAG 0x4000 116 #define RX_CLASS_GATE_PTP 0x50 117 #define RX_CLASS_DISABLE 0x0 118 119 /* HSR/PRP classifier indices */ 120 #define CLASSIFIER_PTP_DUP 10 121 #define CLASSIFIER_HSR_TAG 11 122 #define FT3_PTP_SLOT 14 123 124 /* RX class type */ 125 enum rx_class_sel_type { 126 RX_CLASS_SEL_TYPE_OR = 0, 127 RX_CLASS_SEL_TYPE_AND = 1, 128 RX_CLASS_SEL_TYPE_OR_AND_AND = 2, 129 RX_CLASS_SEL_TYPE_OR_OR_AND = 3, 130 }; 131 132 #define FT1_CFG_SHIFT(n) (2 * (n)) 133 #define FT1_CFG_MASK(n) (0x3 << FT1_CFG_SHIFT((n))) 134 135 #define RX_CLASS_SEL_SHIFT(n) (2 * (n)) 136 #define RX_CLASS_SEL_MASK(n) (0x3 << RX_CLASS_SEL_SHIFT((n))) 137 138 #define ICSSG_CFG_OFFSET 0 139 #define MAC_INTERFACE_0 0x18 140 #define MAC_INTERFACE_1 0x1c 141 142 #define ICSSG_CFG_RX_L2_G_EN BIT(2) 143 144 /* These are register offsets per PRU */ 145 struct miig_rt_offsets { 146 u32 mac0; 147 u32 mac1; 148 u32 ft1_start_len; 149 u32 ft1_cfg; 150 u32 ft1_slot_base; 151 u32 ft3_slot_base; 152 u32 ft3_p_base; 153 u32 ft_rx_ptr; 154 u32 rx_class_base; 155 u32 rx_class_or_base; 156 u32 rx_class_cfg1; 157 u32 rx_class_cfg2; 158 u32 rx_class_gates_base; 159 u32 rx_green; 160 u32 rx_rate_cfg_base; 161 u32 rx_rate_src_sel0; 162 u32 rx_rate_src_sel1; 163 u32 tx_rate_cfg_base; 164 u32 stat_base; 165 u32 tx_hsr_tag; 166 u32 tx_hsr_seq; 167 u32 tx_vlan_type; 168 u32 tx_vlan_ins; 169 }; 170 171 /* These are the offset values for miig_rt_offsets registers */ 172 static const struct miig_rt_offsets offs[] = { 173 /* PRU0 */ 174 { 175 0x8, 176 0xc, 177 0x80, 178 0x84, 179 0x88, 180 0x108, 181 0x308, 182 0x408, 183 0x40c, 184 0x410, 185 0x48c, 186 0x490, 187 0x494, 188 0x4d4, 189 0x4e4, 190 0x504, 191 0x508, 192 0x50c, 193 0x54c, 194 0x63c, 195 0x640, 196 0x644, 197 0x648, 198 }, 199 /* PRU1 */ 200 { 201 0x10, 202 0x14, 203 0x64c, 204 0x650, 205 0x654, 206 0x6d4, 207 0x8d4, 208 0x9d4, 209 0x9d8, 210 0x9dc, 211 0xa58, 212 0xa5c, 213 0xa60, 214 0xaa0, 215 0xab0, 216 0xad0, 217 0xad4, 218 0xad8, 219 0xb18, 220 0xc08, 221 0xc0c, 222 0xc10, 223 0xc14, 224 }, 225 }; 226 227 static void rx_class_ft1_set_start_len(struct regmap *miig_rt, int slice, 228 u16 start, u8 len) 229 { 230 u32 offset, val; 231 232 offset = offs[slice].ft1_start_len; 233 val = FT1_LEN(len) | FT1_START(start); 234 regmap_write(miig_rt, offset, val); 235 } 236 237 static void rx_class_ft1_set_da(struct regmap *miig_rt, int slice, 238 int n, const u8 *addr) 239 { 240 u32 offset; 241 242 offset = FT1_N_REG(slice, n, FT1_DA0); 243 regmap_write(miig_rt, offset, (u32)(addr[0] | addr[1] << 8 | 244 addr[2] << 16 | addr[3] << 24)); 245 offset = FT1_N_REG(slice, n, FT1_DA1); 246 regmap_write(miig_rt, offset, (u32)(addr[4] | addr[5] << 8)); 247 } 248 249 static void rx_class_ft1_set_da_mask(struct regmap *miig_rt, int slice, 250 int n, const u8 *addr) 251 { 252 u32 offset; 253 254 offset = FT1_N_REG(slice, n, FT1_DA0_MASK); 255 regmap_write(miig_rt, offset, (u32)(addr[0] | addr[1] << 8 | 256 addr[2] << 16 | addr[3] << 24)); 257 offset = FT1_N_REG(slice, n, FT1_DA1_MASK); 258 regmap_write(miig_rt, offset, (u32)(addr[4] | addr[5] << 8)); 259 } 260 261 static void rx_class_ft1_cfg_set_type(struct regmap *miig_rt, int slice, int n, 262 enum ft1_cfg_type type) 263 { 264 u32 offset; 265 266 offset = offs[slice].ft1_cfg; 267 regmap_update_bits(miig_rt, offset, FT1_CFG_MASK(n), 268 type << FT1_CFG_SHIFT(n)); 269 } 270 271 static void rx_class_sel_set_type(struct regmap *miig_rt, int slice, int n, 272 enum rx_class_sel_type type) 273 { 274 u32 offset; 275 276 offset = offs[slice].rx_class_cfg1; 277 regmap_update_bits(miig_rt, offset, RX_CLASS_SEL_MASK(n), 278 type << RX_CLASS_SEL_SHIFT(n)); 279 } 280 281 static void rx_class_set_and(struct regmap *miig_rt, int slice, int n, 282 u32 data) 283 { 284 u32 offset; 285 286 offset = RX_CLASS_N_REG(slice, n, RX_CLASS_AND_EN); 287 regmap_write(miig_rt, offset, data); 288 } 289 290 static void rx_class_set_or(struct regmap *miig_rt, int slice, int n, 291 u32 data) 292 { 293 u32 offset; 294 295 offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN); 296 regmap_write(miig_rt, offset, data); 297 } 298 299 static u32 rx_class_get_or(struct regmap *miig_rt, int slice, int n) 300 { 301 u32 offset, val; 302 303 offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN); 304 regmap_read(miig_rt, offset, &val); 305 306 return val; 307 } 308 309 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac) 310 { 311 regmap_write(miig_rt, MAC_INTERFACE_0, (u32)(mac[0] | mac[1] << 8 | 312 mac[2] << 16 | mac[3] << 24)); 313 regmap_write(miig_rt, MAC_INTERFACE_1, (u32)(mac[4] | mac[5] << 8)); 314 } 315 EXPORT_SYMBOL_GPL(icssg_class_set_host_mac_addr); 316 317 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac) 318 { 319 regmap_write(miig_rt, offs[slice].mac0, (u32)(mac[0] | mac[1] << 8 | 320 mac[2] << 16 | mac[3] << 24)); 321 regmap_write(miig_rt, offs[slice].mac1, (u32)(mac[4] | mac[5] << 8)); 322 } 323 EXPORT_SYMBOL_GPL(icssg_class_set_mac_addr); 324 325 static void icssg_class_ft1_add_mcast(struct regmap *miig_rt, int slice, 326 int slot, const u8 *addr, const u8 *mask) 327 { 328 u32 val; 329 int i; 330 331 WARN(slot >= FT1_NUM_SLOTS, "invalid slot: %d\n", slot); 332 333 rx_class_ft1_set_da(miig_rt, slice, slot, addr); 334 rx_class_ft1_set_da_mask(miig_rt, slice, slot, mask); 335 rx_class_ft1_cfg_set_type(miig_rt, slice, slot, FT1_CFG_TYPE_EQ); 336 337 /* Enable the FT1 slot in OR enable for all classifiers */ 338 for (i = 0; i < ICSSG_NUM_CLASSIFIERS_IN_USE; i++) { 339 val = rx_class_get_or(miig_rt, slice, i); 340 val |= RX_CLASS_FT_FT1_MATCH(slot); 341 rx_class_set_or(miig_rt, slice, i, val); 342 } 343 } 344 345 /* disable all RX traffic */ 346 void icssg_class_disable(struct regmap *miig_rt, int slice) 347 { 348 u32 data, offset; 349 int n; 350 351 /* Enable RX_L2_G */ 352 regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, ICSSG_CFG_RX_L2_G_EN, 353 ICSSG_CFG_RX_L2_G_EN); 354 355 for (n = 0; n < ICSSG_NUM_CLASSIFIERS; n++) { 356 /* AND_EN = 0 */ 357 rx_class_set_and(miig_rt, slice, n, 0); 358 /* OR_EN = 0 */ 359 rx_class_set_or(miig_rt, slice, n, 0); 360 361 /* set CFG1 to OR */ 362 rx_class_sel_set_type(miig_rt, slice, n, RX_CLASS_SEL_TYPE_OR); 363 364 /* configure gate */ 365 offset = RX_CLASS_GATES_N_REG(slice, n); 366 regmap_read(miig_rt, offset, &data); 367 /* clear class_raw so we go through filters */ 368 data &= ~RX_CLASS_GATES_RAW_MASK; 369 /* set allow and phase mask */ 370 data |= RX_CLASS_GATES_ALLOW_MASK | RX_CLASS_GATES_PHASE_MASK; 371 regmap_write(miig_rt, offset, data); 372 } 373 374 /* FT1 Disabled */ 375 for (n = 0; n < ICSSG_NUM_FT1_SLOTS; n++) { 376 const u8 addr[] = { 0, 0, 0, 0, 0, 0, }; 377 378 rx_class_ft1_cfg_set_type(miig_rt, slice, n, 379 FT1_CFG_TYPE_DISABLED); 380 rx_class_ft1_set_da(miig_rt, slice, n, addr); 381 rx_class_ft1_set_da_mask(miig_rt, slice, n, addr); 382 } 383 384 /* clear CFG2 */ 385 regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); 386 } 387 EXPORT_SYMBOL_GPL(icssg_class_disable); 388 389 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti, 390 bool is_sr1) 391 { 392 int num_classifiers = is_sr1 ? ICSSG_NUM_CLASSIFIERS_IN_USE : 1; 393 u32 data; 394 int n; 395 396 /* defaults */ 397 icssg_class_disable(miig_rt, slice); 398 399 /* Setup Classifier */ 400 for (n = 0; n < num_classifiers; n++) { 401 /* match on Broadcast or MAC_PRU address */ 402 data = RX_CLASS_FT_BC | RX_CLASS_FT_DA_P; 403 404 /* multicast */ 405 if (allmulti) 406 data |= RX_CLASS_FT_MC; 407 408 rx_class_set_or(miig_rt, slice, n, data); 409 410 /* set CFG1 for OR_OR_AND for classifier */ 411 rx_class_sel_set_type(miig_rt, slice, n, 412 RX_CLASS_SEL_TYPE_OR_OR_AND); 413 } 414 415 /* clear CFG2 */ 416 regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); 417 } 418 EXPORT_SYMBOL_GPL(icssg_class_default); 419 420 void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice) 421 { 422 u32 data, offset; 423 int n; 424 425 /* defaults */ 426 icssg_class_disable(miig_rt, slice); 427 428 /* Setup Classifier */ 429 for (n = 0; n < ICSSG_NUM_CLASSIFIERS_IN_USE; n++) { 430 /* set RAW_MASK to bypass filters */ 431 offset = RX_CLASS_GATES_N_REG(slice, n); 432 regmap_read(miig_rt, offset, &data); 433 data |= RX_CLASS_GATES_RAW_MASK; 434 regmap_write(miig_rt, offset, data); 435 } 436 } 437 EXPORT_SYMBOL_GPL(icssg_class_promiscuous_sr1); 438 439 void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice, 440 struct net_device *ndev) 441 { 442 u8 mask_addr[6] = { 0, 0, 0, 0, 0, 0xff }; 443 struct netdev_hw_addr *ha; 444 int slot = 2; 445 446 rx_class_ft1_set_start_len(miig_rt, slice, 0, 6); 447 /* reserve first 2 slots for 448 * 1) 01-80-C2-00-00-XX Known Service Ethernet Multicast addresses 449 * 2) 01-00-5e-00-00-XX Local Network Control Block 450 * (224.0.0.0 - 224.0.0.255 (224.0.0/24)) 451 */ 452 icssg_class_ft1_add_mcast(miig_rt, slice, 0, 453 eth_reserved_addr_base, mask_addr); 454 icssg_class_ft1_add_mcast(miig_rt, slice, 1, 455 eth_ipv4_mcast_addr_base, mask_addr); 456 mask_addr[5] = 0; 457 netdev_for_each_mc_addr(ha, ndev) { 458 /* skip addresses matching reserved slots */ 459 if (!memcmp(eth_reserved_addr_base, ha->addr, 5) || 460 !memcmp(eth_ipv4_mcast_addr_base, ha->addr, 5)) { 461 netdev_dbg(ndev, "mcast skip %pM\n", ha->addr); 462 continue; 463 } 464 465 if (slot >= FT1_NUM_SLOTS) { 466 netdev_dbg(ndev, 467 "can't add more than %d MC addresses, enabling allmulti\n", 468 FT1_NUM_SLOTS); 469 icssg_class_default(miig_rt, slice, 1, true); 470 break; 471 } 472 473 netdev_dbg(ndev, "mcast add %pM\n", ha->addr); 474 icssg_class_ft1_add_mcast(miig_rt, slice, slot, 475 ha->addr, mask_addr); 476 slot++; 477 } 478 } 479 EXPORT_SYMBOL_GPL(icssg_class_add_mcast_sr1); 480 481 /* required for SAV check */ 482 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr) 483 { 484 const u8 mask_addr[] = { 0, 0, 0, 0, 0, 0, }; 485 486 rx_class_ft1_set_start_len(miig_rt, slice, ETH_ALEN, ETH_ALEN); 487 rx_class_ft1_set_da(miig_rt, slice, 0, mac_addr); 488 rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr); 489 rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ); 490 } 491 EXPORT_SYMBOL_GPL(icssg_ft1_set_mac_addr); 492 493 /** 494 * icssg_ft3_hsr_configurations - Configure filter table for HSR/PRP protocol frames 495 * @miig_rt: Pointer to the MII-G register map 496 * @slice: ICSSG slice number (0 or 1) 497 * @prueth: Pointer to prueth structure to determine HSR/PRP mode 498 * 499 * Configures FT3 to detect PTP frames (EtherType 0x88F7) in HSR/PRP tagged packets. 500 * HSR frames have a 6-byte tag, while PRP has no tag offset for EtherType detection. 501 */ 502 void icssg_ft3_hsr_configurations(struct regmap *miig_rt, int slice, 503 struct prueth *prueth) 504 { 505 u8 offset = (prueth->hsr_prp_version == PRP_V1) ? 506 PRP_PTP_ETHERTYPE_OFFSET : HSR_PTP_ETHERTYPE_OFFSET; 507 508 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_START), offset); 509 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_START_AUTO), 0); 510 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_START_OFFSET), 0); 511 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_JUMP_OFFSET), 0); 512 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_LEN), 0); 513 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_CFG), FT3_VLAN_MODE_BOTH); 514 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_T), FT3_PTP_PATTERN); 515 regmap_write(miig_rt, FT3_N_REG(slice, FT3_PTP_SLOT, FT3_T_MASK), 516 FT3_ETHERTYPE_MASK); 517 518 regmap_write(miig_rt, RX_CLASS_N_REG(slice, CLASSIFIER_PTP_DUP, RX_CLASS_AND_EN), 519 RX_CLASS_DISABLE); 520 regmap_write(miig_rt, RX_CLASS_OR_REG(slice, CLASSIFIER_PTP_DUP, RX_CLASS_AND_EN), 521 RX_CLASS_OR_DUP_PTP); 522 regmap_write(miig_rt, RX_CLASS_GATES_N_REG(slice, CLASSIFIER_PTP_DUP), 523 RX_CLASS_GATE_PTP); 524 525 if (prueth->hsr_prp_version != PRP_V1) { 526 regmap_write(miig_rt, RX_CLASS_N_REG(slice, CLASSIFIER_HSR_TAG, RX_CLASS_AND_EN), 527 RX_CLASS_DISABLE); 528 regmap_write(miig_rt, RX_CLASS_OR_REG(slice, CLASSIFIER_HSR_TAG, RX_CLASS_AND_EN), 529 RX_CLASS_OR_HSR_TAG); 530 regmap_write(miig_rt, RX_CLASS_GATES_N_REG(slice, CLASSIFIER_HSR_TAG), 531 RX_CLASS_GATE_PTP); 532 } 533 } 534 EXPORT_SYMBOL_GPL(icssg_ft3_hsr_configurations); 535