1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "trace.h"
31 #include "qemu/timer.h"
32 #include "hw/ppc/xics.h"
33 #include "hw/qdev-properties.h"
34 #include "qemu/error-report.h"
35 #include "qemu/module.h"
36 #include "qapi/visitor.h"
37 #include "migration/vmstate.h"
38 #include "hw/intc/intc.h"
39 #include "hw/irq.h"
40 #include "system/kvm.h"
41 #include "system/reset.h"
42 #include "target/ppc/cpu.h"
43
icp_pic_print_info(ICPState * icp,GString * buf)44 void icp_pic_print_info(ICPState *icp, GString *buf)
45 {
46 int cpu_index;
47
48 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
49 * are hot plugged or unplugged.
50 */
51 if (!icp) {
52 return;
53 }
54
55 cpu_index = icp->cs ? icp->cs->cpu_index : -1;
56
57 if (!icp->output) {
58 return;
59 }
60
61 if (kvm_irqchip_in_kernel()) {
62 icp_synchronize_state(icp);
63 }
64
65 g_string_append_printf(buf, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
66 cpu_index, icp->xirr, icp->xirr_owner,
67 icp->pending_priority, icp->mfrr);
68 }
69
ics_pic_print_info(ICSState * ics,GString * buf)70 void ics_pic_print_info(ICSState *ics, GString *buf)
71 {
72 uint32_t i;
73
74 g_string_append_printf(buf, "ICS %4x..%4x %p\n",
75 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
76
77 if (!ics->irqs) {
78 return;
79 }
80
81 if (kvm_irqchip_in_kernel()) {
82 ics_synchronize_state(ics);
83 }
84
85 for (i = 0; i < ics->nr_irqs; i++) {
86 ICSIRQState *irq = ics->irqs + i;
87
88 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
89 continue;
90 }
91 g_string_append_printf(buf, " %4x %s %02x %02x\n",
92 ics->offset + i,
93 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
94 "LSI" : "MSI",
95 irq->priority, irq->status);
96 }
97 }
98
99 /*
100 * ICP: Presentation layer
101 */
102
103 #define XISR_MASK 0x00ffffff
104 #define CPPR_MASK 0xff000000
105
106 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
107 #define CPPR(icp) (((icp)->xirr) >> 24)
108
109 static void ics_reject(ICSState *ics, uint32_t nr);
110 static void ics_eoi(ICSState *ics, uint32_t nr);
111
icp_check_ipi(ICPState * icp)112 static void icp_check_ipi(ICPState *icp)
113 {
114 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
115 return;
116 }
117
118 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
119
120 if (XISR(icp) && icp->xirr_owner) {
121 ics_reject(icp->xirr_owner, XISR(icp));
122 }
123
124 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
125 icp->pending_priority = icp->mfrr;
126 icp->xirr_owner = NULL;
127 qemu_irq_raise(icp->output);
128 }
129
icp_resend(ICPState * icp)130 void icp_resend(ICPState *icp)
131 {
132 XICSFabric *xi = icp->xics;
133 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
134
135 if (icp->mfrr < CPPR(icp)) {
136 icp_check_ipi(icp);
137 }
138
139 xic->ics_resend(xi);
140 }
141
icp_set_cppr(ICPState * icp,uint8_t cppr)142 void icp_set_cppr(ICPState *icp, uint8_t cppr)
143 {
144 uint8_t old_cppr;
145 uint32_t old_xisr;
146
147 old_cppr = CPPR(icp);
148 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
149
150 if (cppr < old_cppr) {
151 if (XISR(icp) && (cppr <= icp->pending_priority)) {
152 old_xisr = XISR(icp);
153 icp->xirr &= ~XISR_MASK; /* Clear XISR */
154 icp->pending_priority = 0xff;
155 qemu_irq_lower(icp->output);
156 if (icp->xirr_owner) {
157 ics_reject(icp->xirr_owner, old_xisr);
158 icp->xirr_owner = NULL;
159 }
160 }
161 } else {
162 if (!XISR(icp)) {
163 icp_resend(icp);
164 }
165 }
166 }
167
icp_set_mfrr(ICPState * icp,uint8_t mfrr)168 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
169 {
170 icp->mfrr = mfrr;
171 if (mfrr < CPPR(icp)) {
172 icp_check_ipi(icp);
173 }
174 }
175
icp_accept(ICPState * icp)176 uint32_t icp_accept(ICPState *icp)
177 {
178 uint32_t xirr = icp->xirr;
179
180 qemu_irq_lower(icp->output);
181 icp->xirr = icp->pending_priority << 24;
182 icp->pending_priority = 0xff;
183 icp->xirr_owner = NULL;
184
185 trace_xics_icp_accept(xirr, icp->xirr);
186
187 return xirr;
188 }
189
icp_ipoll(ICPState * icp,uint32_t * mfrr)190 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
191 {
192 if (mfrr) {
193 *mfrr = icp->mfrr;
194 }
195 return icp->xirr;
196 }
197
icp_eoi(ICPState * icp,uint32_t xirr)198 void icp_eoi(ICPState *icp, uint32_t xirr)
199 {
200 XICSFabric *xi = icp->xics;
201 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
202 ICSState *ics;
203 uint32_t irq;
204
205 /* Send EOI -> ICS */
206 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
207 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
208 irq = xirr & XISR_MASK;
209
210 ics = xic->ics_get(xi, irq);
211 if (ics) {
212 ics_eoi(ics, irq);
213 }
214 if (!XISR(icp)) {
215 icp_resend(icp);
216 }
217 }
218
icp_irq(ICSState * ics,int server,int nr,uint8_t priority)219 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
220 {
221 ICPState *icp = xics_icp_get(ics->xics, server);
222
223 trace_xics_icp_irq(server, nr, priority);
224
225 if ((priority >= CPPR(icp))
226 || (XISR(icp) && (icp->pending_priority <= priority))) {
227 ics_reject(ics, nr);
228 } else {
229 if (XISR(icp) && icp->xirr_owner) {
230 ics_reject(icp->xirr_owner, XISR(icp));
231 icp->xirr_owner = NULL;
232 }
233 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
234 icp->xirr_owner = ics;
235 icp->pending_priority = priority;
236 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
237 qemu_irq_raise(icp->output);
238 }
239 }
240
icp_pre_save(void * opaque)241 static int icp_pre_save(void *opaque)
242 {
243 ICPState *icp = opaque;
244
245 if (kvm_irqchip_in_kernel()) {
246 icp_get_kvm_state(icp);
247 }
248
249 return 0;
250 }
251
icp_post_load(void * opaque,int version_id)252 static int icp_post_load(void *opaque, int version_id)
253 {
254 ICPState *icp = opaque;
255
256 if (kvm_irqchip_in_kernel()) {
257 Error *local_err = NULL;
258 int ret;
259
260 ret = icp_set_kvm_state(icp, &local_err);
261 if (ret < 0) {
262 error_report_err(local_err);
263 return ret;
264 }
265 }
266
267 return 0;
268 }
269
270 static const VMStateDescription vmstate_icp_server = {
271 .name = "icp/server",
272 .version_id = 1,
273 .minimum_version_id = 1,
274 .pre_save = icp_pre_save,
275 .post_load = icp_post_load,
276 .fields = (const VMStateField[]) {
277 /* Sanity check */
278 VMSTATE_UINT32(xirr, ICPState),
279 VMSTATE_UINT8(pending_priority, ICPState),
280 VMSTATE_UINT8(mfrr, ICPState),
281 VMSTATE_END_OF_LIST()
282 },
283 };
284
icp_reset(ICPState * icp)285 void icp_reset(ICPState *icp)
286 {
287 icp->xirr = 0;
288 icp->pending_priority = 0xff;
289 icp->mfrr = 0xff;
290
291 if (kvm_irqchip_in_kernel()) {
292 Error *local_err = NULL;
293
294 icp_set_kvm_state(icp, &local_err);
295 if (local_err) {
296 error_report_err(local_err);
297 }
298 }
299 }
300
icp_realize(DeviceState * dev,Error ** errp)301 static void icp_realize(DeviceState *dev, Error **errp)
302 {
303 ICPState *icp = ICP(dev);
304 PowerPCCPU *cpu;
305 CPUPPCState *env;
306 Error *err = NULL;
307
308 assert(icp->xics);
309 assert(icp->cs);
310
311 cpu = POWERPC_CPU(icp->cs);
312 env = &cpu->env;
313 switch (PPC_INPUT(env)) {
314 case PPC_FLAGS_INPUT_POWER7:
315 icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER7_INPUT_INT);
316 break;
317 case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
318 icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT);
319 break;
320
321 case PPC_FLAGS_INPUT_970:
322 icp->output = qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT);
323 break;
324
325 default:
326 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
327 return;
328 }
329
330 /* Connect the presenter to the VCPU (required for CPU hotplug) */
331 if (kvm_irqchip_in_kernel()) {
332 icp_kvm_realize(dev, &err);
333 if (err) {
334 error_propagate(errp, err);
335 return;
336 }
337 }
338 }
339
icp_unrealize(DeviceState * dev)340 static void icp_unrealize(DeviceState *dev)
341 {
342 ICPState *icp = ICP(dev);
343
344 vmstate_unregister(NULL, &vmstate_icp_server, icp);
345 }
346
347 static const Property icp_properties[] = {
348 DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
349 XICSFabric *),
350 DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *),
351 };
352
icp_class_init(ObjectClass * klass,const void * data)353 static void icp_class_init(ObjectClass *klass, const void *data)
354 {
355 DeviceClass *dc = DEVICE_CLASS(klass);
356
357 dc->realize = icp_realize;
358 dc->unrealize = icp_unrealize;
359 device_class_set_props(dc, icp_properties);
360 /*
361 * Reason: part of XICS interrupt controller, needs to be wired up
362 * by icp_create().
363 */
364 dc->user_creatable = false;
365 }
366
367 static const TypeInfo icp_info = {
368 .name = TYPE_ICP,
369 .parent = TYPE_DEVICE,
370 .instance_size = sizeof(ICPState),
371 .class_init = icp_class_init,
372 .class_size = sizeof(ICPStateClass),
373 };
374
icp_create(Object * cpu,const char * type,XICSFabric * xi,Error ** errp)375 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
376 {
377 Object *obj;
378
379 obj = object_new(type);
380 object_property_add_child(cpu, type, obj);
381 object_unref(obj);
382 object_property_set_link(obj, ICP_PROP_XICS, OBJECT(xi), &error_abort);
383 object_property_set_link(obj, ICP_PROP_CPU, cpu, &error_abort);
384 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
385 object_unparent(obj);
386 obj = NULL;
387 }
388
389 return obj;
390 }
391
icp_destroy(ICPState * icp)392 void icp_destroy(ICPState *icp)
393 {
394 Object *obj = OBJECT(icp);
395
396 object_unparent(obj);
397 }
398
399 /*
400 * ICS: Source layer
401 */
ics_resend_msi(ICSState * ics,int srcno)402 static void ics_resend_msi(ICSState *ics, int srcno)
403 {
404 ICSIRQState *irq = ics->irqs + srcno;
405
406 /* FIXME: filter by server#? */
407 if (irq->status & XICS_STATUS_REJECTED) {
408 irq->status &= ~XICS_STATUS_REJECTED;
409 if (irq->priority != 0xff) {
410 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
411 }
412 }
413 }
414
ics_resend_lsi(ICSState * ics,int srcno)415 static void ics_resend_lsi(ICSState *ics, int srcno)
416 {
417 ICSIRQState *irq = ics->irqs + srcno;
418
419 if ((irq->priority != 0xff)
420 && (irq->status & XICS_STATUS_ASSERTED)
421 && !(irq->status & XICS_STATUS_SENT)) {
422 irq->status |= XICS_STATUS_SENT;
423 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
424 }
425 }
426
ics_set_irq_msi(ICSState * ics,int srcno,int val)427 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
428 {
429 ICSIRQState *irq = ics->irqs + srcno;
430
431 trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
432
433 if (val) {
434 if (irq->priority == 0xff) {
435 irq->status |= XICS_STATUS_MASKED_PENDING;
436 trace_xics_masked_pending();
437 } else {
438 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
439 }
440 }
441 }
442
ics_set_irq_lsi(ICSState * ics,int srcno,int val)443 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
444 {
445 ICSIRQState *irq = ics->irqs + srcno;
446
447 trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
448 if (val) {
449 irq->status |= XICS_STATUS_ASSERTED;
450 } else {
451 irq->status &= ~XICS_STATUS_ASSERTED;
452 }
453 ics_resend_lsi(ics, srcno);
454 }
455
ics_set_irq(void * opaque,int srcno,int val)456 void ics_set_irq(void *opaque, int srcno, int val)
457 {
458 ICSState *ics = (ICSState *)opaque;
459
460 if (kvm_irqchip_in_kernel()) {
461 ics_kvm_set_irq(ics, srcno, val);
462 return;
463 }
464
465 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
466 ics_set_irq_lsi(ics, srcno, val);
467 } else {
468 ics_set_irq_msi(ics, srcno, val);
469 }
470 }
471
ics_write_xive_msi(ICSState * ics,int srcno)472 static void ics_write_xive_msi(ICSState *ics, int srcno)
473 {
474 ICSIRQState *irq = ics->irqs + srcno;
475
476 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
477 || (irq->priority == 0xff)) {
478 return;
479 }
480
481 irq->status &= ~XICS_STATUS_MASKED_PENDING;
482 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
483 }
484
ics_write_xive_lsi(ICSState * ics,int srcno)485 static void ics_write_xive_lsi(ICSState *ics, int srcno)
486 {
487 ics_resend_lsi(ics, srcno);
488 }
489
ics_write_xive(ICSState * ics,int srcno,int server,uint8_t priority,uint8_t saved_priority)490 void ics_write_xive(ICSState *ics, int srcno, int server,
491 uint8_t priority, uint8_t saved_priority)
492 {
493 ICSIRQState *irq = ics->irqs + srcno;
494
495 irq->server = server;
496 irq->priority = priority;
497 irq->saved_priority = saved_priority;
498
499 trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
500
501 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
502 ics_write_xive_lsi(ics, srcno);
503 } else {
504 ics_write_xive_msi(ics, srcno);
505 }
506 }
507
ics_reject(ICSState * ics,uint32_t nr)508 static void ics_reject(ICSState *ics, uint32_t nr)
509 {
510 ICSStateClass *isc = ICS_GET_CLASS(ics);
511 ICSIRQState *irq = ics->irqs + nr - ics->offset;
512
513 if (isc->reject) {
514 isc->reject(ics, nr);
515 return;
516 }
517
518 trace_xics_ics_reject(nr, nr - ics->offset);
519 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
520 irq->status |= XICS_STATUS_REJECTED;
521 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
522 irq->status &= ~XICS_STATUS_SENT;
523 }
524 }
525
ics_resend(ICSState * ics)526 void ics_resend(ICSState *ics)
527 {
528 ICSStateClass *isc = ICS_GET_CLASS(ics);
529 int i;
530
531 if (isc->resend) {
532 isc->resend(ics);
533 return;
534 }
535
536 for (i = 0; i < ics->nr_irqs; i++) {
537 /* FIXME: filter by server#? */
538 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
539 ics_resend_lsi(ics, i);
540 } else {
541 ics_resend_msi(ics, i);
542 }
543 }
544 }
545
ics_eoi(ICSState * ics,uint32_t nr)546 static void ics_eoi(ICSState *ics, uint32_t nr)
547 {
548 int srcno = nr - ics->offset;
549 ICSIRQState *irq = ics->irqs + srcno;
550
551 trace_xics_ics_eoi(nr);
552
553 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
554 irq->status &= ~XICS_STATUS_SENT;
555 }
556 }
557
ics_reset_irq(ICSIRQState * irq)558 static void ics_reset_irq(ICSIRQState *irq)
559 {
560 irq->priority = 0xff;
561 irq->saved_priority = 0xff;
562 }
563
ics_reset_hold(Object * obj,ResetType type)564 static void ics_reset_hold(Object *obj, ResetType type)
565 {
566 ICSState *ics = ICS(obj);
567 g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
568 int i;
569
570 for (i = 0; i < ics->nr_irqs; i++) {
571 flags[i] = ics->irqs[i].flags;
572 }
573
574 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
575
576 for (i = 0; i < ics->nr_irqs; i++) {
577 ics_reset_irq(ics->irqs + i);
578 ics->irqs[i].flags = flags[i];
579 }
580
581 if (kvm_irqchip_in_kernel()) {
582 Error *local_err = NULL;
583
584 ics_set_kvm_state(ics, &local_err);
585 if (local_err) {
586 error_report_err(local_err);
587 }
588 }
589 }
590
ics_reset_handler(void * dev)591 static void ics_reset_handler(void *dev)
592 {
593 device_cold_reset(dev);
594 }
595
ics_realize(DeviceState * dev,Error ** errp)596 static void ics_realize(DeviceState *dev, Error **errp)
597 {
598 ICSState *ics = ICS(dev);
599
600 assert(ics->xics);
601
602 if (!ics->nr_irqs) {
603 error_setg(errp, "Number of interrupts needs to be greater 0");
604 return;
605 }
606 ics->irqs = g_new0(ICSIRQState, ics->nr_irqs);
607
608 qemu_register_reset(ics_reset_handler, ics);
609 }
610
ics_instance_init(Object * obj)611 static void ics_instance_init(Object *obj)
612 {
613 ICSState *ics = ICS(obj);
614
615 ics->offset = XICS_IRQ_BASE;
616 }
617
ics_pre_save(void * opaque)618 static int ics_pre_save(void *opaque)
619 {
620 ICSState *ics = opaque;
621
622 if (kvm_irqchip_in_kernel()) {
623 ics_get_kvm_state(ics);
624 }
625
626 return 0;
627 }
628
ics_post_load(void * opaque,int version_id)629 static int ics_post_load(void *opaque, int version_id)
630 {
631 ICSState *ics = opaque;
632
633 if (kvm_irqchip_in_kernel()) {
634 Error *local_err = NULL;
635 int ret;
636
637 ret = ics_set_kvm_state(ics, &local_err);
638 if (ret < 0) {
639 error_report_err(local_err);
640 return ret;
641 }
642 }
643
644 return 0;
645 }
646
647 static const VMStateDescription vmstate_ics_irq = {
648 .name = "ics/irq",
649 .version_id = 2,
650 .minimum_version_id = 1,
651 .fields = (const VMStateField[]) {
652 VMSTATE_UINT32(server, ICSIRQState),
653 VMSTATE_UINT8(priority, ICSIRQState),
654 VMSTATE_UINT8(saved_priority, ICSIRQState),
655 VMSTATE_UINT8(status, ICSIRQState),
656 VMSTATE_UINT8(flags, ICSIRQState),
657 VMSTATE_END_OF_LIST()
658 },
659 };
660
661 static const VMStateDescription vmstate_ics = {
662 .name = "ics",
663 .version_id = 1,
664 .minimum_version_id = 1,
665 .pre_save = ics_pre_save,
666 .post_load = ics_post_load,
667 .fields = (const VMStateField[]) {
668 /* Sanity check */
669 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
670
671 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
672 vmstate_ics_irq,
673 ICSIRQState),
674 VMSTATE_END_OF_LIST()
675 },
676 };
677
678 static const Property ics_properties[] = {
679 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
680 DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
681 XICSFabric *),
682 };
683
ics_class_init(ObjectClass * klass,const void * data)684 static void ics_class_init(ObjectClass *klass, const void *data)
685 {
686 DeviceClass *dc = DEVICE_CLASS(klass);
687 ResettableClass *rc = RESETTABLE_CLASS(klass);
688
689 dc->realize = ics_realize;
690 device_class_set_props(dc, ics_properties);
691 dc->vmsd = &vmstate_ics;
692 /*
693 * Reason: part of XICS interrupt controller, needs to be wired up,
694 * e.g. by spapr_irq_init().
695 */
696 dc->user_creatable = false;
697 rc->phases.hold = ics_reset_hold;
698 }
699
700 static const TypeInfo ics_info = {
701 .name = TYPE_ICS,
702 .parent = TYPE_DEVICE,
703 .instance_size = sizeof(ICSState),
704 .instance_init = ics_instance_init,
705 .class_init = ics_class_init,
706 .class_size = sizeof(ICSStateClass),
707 };
708
709 static const TypeInfo xics_fabric_info = {
710 .name = TYPE_XICS_FABRIC,
711 .parent = TYPE_INTERFACE,
712 .class_size = sizeof(XICSFabricClass),
713 };
714
715 /*
716 * Exported functions
717 */
xics_icp_get(XICSFabric * xi,int server)718 ICPState *xics_icp_get(XICSFabric *xi, int server)
719 {
720 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
721
722 return xic->icp_get(xi, server);
723 }
724
ics_set_irq_type(ICSState * ics,int srcno,bool lsi)725 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
726 {
727 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
728
729 ics->irqs[srcno].flags |=
730 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
731
732 if (kvm_irqchip_in_kernel()) {
733 Error *local_err = NULL;
734
735 ics_reset_irq(ics->irqs + srcno);
736 ics_set_kvm_state_one(ics, srcno, &local_err);
737 if (local_err) {
738 error_report_err(local_err);
739 }
740 }
741 }
742
xics_register_types(void)743 static void xics_register_types(void)
744 {
745 type_register_static(&ics_info);
746 type_register_static(&icp_info);
747 type_register_static(&xics_fabric_info);
748 }
749
750 type_init(xics_register_types)
751