1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #ifndef _ICE_TXRX_H_
5 #define _ICE_TXRX_H_
6
7 #include <net/libeth/types.h>
8
9 #include "ice_type.h"
10
11 #define ICE_DFLT_IRQ_WORK 256
12 #define ICE_RXBUF_3072 3072
13 #define ICE_RXBUF_2048 2048
14 #define ICE_RXBUF_1664 1664
15 #define ICE_RXBUF_1536 1536
16 #define ICE_MAX_CHAINED_RX_BUFS 5
17 #define ICE_MAX_BUF_TXD 8
18 #define ICE_MIN_TX_LEN 17
19 #define ICE_MAX_FRAME_LEGACY_RX 8320
20
21 /* The size limit for a transmit buffer in a descriptor is (16K - 1).
22 * In order to align with the read requests we will align the value to
23 * the nearest 4K which represents our maximum read request size.
24 */
25 #define ICE_MAX_READ_REQ_SIZE 4096
26 #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1)
27 #define ICE_MAX_DATA_PER_TXD_ALIGNED \
28 (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
29
30 #define ICE_MAX_TXQ_PER_TXQG 128
31
32 /* We are assuming that the cache line is always 64 Bytes here for ice.
33 * In order to make sure that is a correct assumption there is a check in probe
34 * to print a warning if the read from GLPCI_CNF2 tells us that the cache line
35 * size is 128 bytes. We do it this way because we do not want to read the
36 * GLPCI_CNF2 register or a variable containing the value on every pass through
37 * the Tx path.
38 */
39 #define ICE_CACHE_LINE_BYTES 64
40 #define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \
41 sizeof(struct ice_tx_desc))
42 #define ICE_DESCS_FOR_CTX_DESC 1
43 #define ICE_DESCS_FOR_SKB_DATA_PTR 1
44 /* Tx descriptors needed, worst case */
45 #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
46 ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
47 #define ICE_DESC_UNUSED(R) \
48 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
49 (R)->next_to_clean - (R)->next_to_use - 1)
50
51 #define ICE_RING_QUARTER(R) ((R)->count >> 2)
52
53 #define ICE_TX_FLAGS_TSO BIT(0)
54 #define ICE_TX_FLAGS_HW_VLAN BIT(1)
55 #define ICE_TX_FLAGS_SW_VLAN BIT(2)
56 /* Free, was ICE_TX_FLAGS_DUMMY_PKT */
57 #define ICE_TX_FLAGS_TSYN BIT(4)
58 #define ICE_TX_FLAGS_IPV4 BIT(5)
59 #define ICE_TX_FLAGS_IPV6 BIT(6)
60 #define ICE_TX_FLAGS_TUNNEL BIT(7)
61 #define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(8)
62
63 #define ICE_XDP_PASS 0
64 #define ICE_XDP_CONSUMED BIT(0)
65 #define ICE_XDP_TX BIT(1)
66 #define ICE_XDP_REDIR BIT(2)
67 #define ICE_XDP_EXIT BIT(3)
68 #define ICE_SKB_CONSUMED ICE_XDP_CONSUMED
69
70 #define ICE_RX_DMA_ATTR \
71 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
72
73 #define ICE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
74
75 #define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)
76
77 /**
78 * enum ice_tx_buf_type - type of &ice_tx_buf to act on Tx completion
79 * @ICE_TX_BUF_EMPTY: unused OR XSk frame, no action required
80 * @ICE_TX_BUF_DUMMY: dummy Flow Director packet, unmap and kfree()
81 * @ICE_TX_BUF_FRAG: mapped skb OR &xdp_buff frag, only unmap DMA
82 * @ICE_TX_BUF_SKB: &sk_buff, unmap and consume_skb(), update stats
83 * @ICE_TX_BUF_XDP_TX: &xdp_buff, unmap and page_frag_free(), stats
84 * @ICE_TX_BUF_XDP_XMIT: &xdp_frame, unmap and xdp_return_frame(), stats
85 * @ICE_TX_BUF_XSK_TX: &xdp_buff on XSk queue, xsk_buff_free(), stats
86 */
87 enum ice_tx_buf_type {
88 ICE_TX_BUF_EMPTY = 0U,
89 ICE_TX_BUF_DUMMY,
90 ICE_TX_BUF_FRAG,
91 ICE_TX_BUF_SKB,
92 ICE_TX_BUF_XDP_TX,
93 ICE_TX_BUF_XDP_XMIT,
94 ICE_TX_BUF_XSK_TX,
95 };
96
97 struct ice_tx_buf {
98 union {
99 struct ice_tx_desc *next_to_watch;
100 u32 rs_idx;
101 };
102 union {
103 void *raw_buf; /* used for XDP_TX and FDir rules */
104 struct sk_buff *skb; /* used for .ndo_start_xmit() */
105 struct xdp_frame *xdpf; /* used for .ndo_xdp_xmit() */
106 struct xdp_buff *xdp; /* used for XDP_TX ZC */
107 };
108 unsigned int bytecount;
109 union {
110 unsigned int gso_segs;
111 unsigned int nr_frags; /* used for mbuf XDP */
112 };
113 u32 tx_flags:12;
114 u32 type:4; /* &ice_tx_buf_type */
115 u32 vid:16;
116 DEFINE_DMA_UNMAP_LEN(len);
117 DEFINE_DMA_UNMAP_ADDR(dma);
118 };
119
120 struct ice_tx_offload_params {
121 u64 cd_qw1;
122 struct ice_tx_ring *tx_ring;
123 u32 td_cmd;
124 u32 td_offset;
125 u32 td_l2tag1;
126 u32 cd_tunnel_params;
127 u16 cd_l2tag2;
128 u16 cd_gcs_params;
129 u8 header_len;
130 };
131
132 struct ice_ring_stats {
133 struct rcu_head rcu; /* to avoid race on free */
134 struct u64_stats_sync syncp;
135 struct_group(stats,
136 u64_stats_t pkts;
137 u64_stats_t bytes;
138 union {
139 struct_group(tx,
140 u64_stats_t tx_restart_q;
141 u64_stats_t tx_busy;
142 u64_stats_t tx_linearize;
143 /* negative if no pending Tx descriptors */
144 int prev_pkt;
145 );
146 struct_group(rx,
147 u64_stats_t rx_non_eop_descs;
148 u64_stats_t rx_page_failed;
149 u64_stats_t rx_buf_failed;
150 );
151 };
152 );
153 };
154
155 /**
156 * ice_stats_read - Read a single ring stat value
157 * @stats: pointer to ring_stats structure for a queue
158 * @member: the ice_ring_stats member to read
159 *
160 * Shorthand for reading a single 64-bit stat value from struct
161 * ice_ring_stats.
162 *
163 * Return: the value of the requested stat.
164 */
165 #define ice_stats_read(stats, member) ({ \
166 struct ice_ring_stats *__stats = (stats); \
167 unsigned int start; \
168 u64 val; \
169 do { \
170 start = u64_stats_fetch_begin(&__stats->syncp); \
171 val = u64_stats_read(&__stats->member); \
172 } while (u64_stats_fetch_retry(&__stats->syncp, start)); \
173 val; \
174 })
175
176 /**
177 * ice_stats_inc - Increment a single ring stat value
178 * @stats: pointer to the ring_stats structure for a queue
179 * @member: the ice_ring_stats member to increment
180 *
181 * Shorthand for incrementing a single 64-bit stat value in struct
182 * ice_ring_stats.
183 */
184 #define ice_stats_inc(stats, member) do { \
185 struct ice_ring_stats *__stats = (stats); \
186 u64_stats_update_begin(&__stats->syncp); \
187 u64_stats_inc(&__stats->member); \
188 u64_stats_update_end(&__stats->syncp); \
189 } while (0)
190
191 enum ice_ring_state_t {
192 ICE_TX_XPS_INIT_DONE,
193 ICE_TX_NBITS,
194 };
195
196 /* this enum matches hardware bits and is meant to be used by DYN_CTLN
197 * registers and QINT registers or more generally anywhere in the manual
198 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
199 * register but instead is a special value meaning "don't update" ITR0/1/2.
200 */
201 enum ice_dyn_idx_t {
202 ICE_IDX_ITR0 = 0,
203 ICE_IDX_ITR1 = 1,
204 ICE_IDX_ITR2 = 2,
205 ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
206 };
207
208 /* Header split modes defined by DTYPE field of Rx RLAN context */
209 enum ice_rx_dtype {
210 ICE_RX_DTYPE_NO_SPLIT = 0,
211 ICE_RX_DTYPE_HEADER_SPLIT = 1,
212 ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
213 };
214
215 struct ice_pkt_ctx {
216 u64 cached_phctime;
217 __be16 vlan_proto;
218 };
219
220 /* indices into GLINT_ITR registers */
221 #define ICE_RX_ITR ICE_IDX_ITR0
222 #define ICE_TX_ITR ICE_IDX_ITR1
223 #define ICE_ITR_8K 124
224 #define ICE_ITR_20K 50
225 #define ICE_ITR_MAX 8160 /* 0x1FE0 */
226 #define ICE_DFLT_TX_ITR ICE_ITR_20K
227 #define ICE_DFLT_RX_ITR ICE_ITR_20K
228 enum ice_dynamic_itr {
229 ITR_STATIC = 0,
230 ITR_DYNAMIC = 1
231 };
232
233 #define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
234 #define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */
235 #define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S)
236 #define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */
237 #define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK)
238
239 #define ICE_DFLT_INTRL 0
240 #define ICE_MAX_INTRL 236
241
242 #define ICE_IN_WB_ON_ITR_MODE 255
243 /* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
244 * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
245 * set the write-back latency to the usecs passed in.
246 */
247 #define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \
248 ((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
249 GLINT_DYN_CTL_INTERVAL_M) | \
250 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
251 GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
252 GLINT_DYN_CTL_WB_ON_ITR_M)
253
254 /* Legacy or Advanced Mode Queue */
255 #define ICE_TX_ADVANCED 0
256 #define ICE_TX_LEGACY 1
257
258 /* descriptor ring, associated with a VSI */
259 struct ice_tstamp_ring {
260 struct ice_tx_ring *tx_ring; /* Backreference to associated Tx ring */
261 dma_addr_t dma; /* physical address of ring */
262 struct rcu_head rcu; /* to avoid race on free */
263 u8 __iomem *tail;
264 void *desc;
265 u16 next_to_use;
266 u16 count;
267 } ____cacheline_internodealigned_in_smp;
268
269 struct ice_rx_ring {
270 __cacheline_group_begin_aligned(read_mostly);
271 void *desc; /* Descriptor ring memory */
272 struct page_pool *pp;
273 struct net_device *netdev; /* netdev ring maps to */
274 struct ice_q_vector *q_vector; /* Backreference to associated vector */
275 u8 __iomem *tail;
276
277 union {
278 struct libeth_fqe *rx_fqes;
279 struct xdp_buff **xdp_buf;
280 };
281
282 u16 count; /* Number of descriptors */
283 u8 ptp_rx;
284
285 u8 flags;
286 #define ICE_RX_FLAGS_CRC_STRIP_DIS BIT(2)
287 #define ICE_RX_FLAGS_MULTIDEV BIT(3)
288 #define ICE_RX_FLAGS_RING_GCS BIT(4)
289
290 u32 truesize;
291
292 struct page_pool *hdr_pp;
293 struct libeth_fqe *hdr_fqes;
294
295 struct bpf_prog *xdp_prog;
296 struct ice_tx_ring *xdp_ring;
297 struct xsk_buff_pool *xsk_pool;
298
299 /* stats structs */
300 struct ice_ring_stats *ring_stats;
301 struct ice_rx_ring *next; /* pointer to next ring in q_vector */
302
303 u32 hdr_truesize;
304
305 struct xdp_rxq_info xdp_rxq;
306 __cacheline_group_end_aligned(read_mostly);
307
308 __cacheline_group_begin_aligned(read_write);
309 union {
310 struct libeth_xdp_buff_stash xdp;
311 struct libeth_xdp_buff *xsk;
312 };
313 union {
314 struct ice_pkt_ctx pkt_ctx;
315 struct {
316 u64 cached_phctime;
317 __be16 vlan_proto;
318 };
319 };
320
321 /* used in interrupt processing */
322 u16 next_to_use;
323 u16 next_to_clean;
324 __cacheline_group_end_aligned(read_write);
325
326 __cacheline_group_begin_aligned(cold);
327 struct rcu_head rcu; /* to avoid race on free */
328 struct ice_vsi *vsi; /* Backreference to associated VSI */
329 struct ice_channel *ch;
330
331 dma_addr_t dma; /* physical address of ring */
332 u16 q_index; /* Queue number of ring */
333 u16 reg_idx; /* HW register index of the ring */
334 u8 dcb_tc; /* Traffic class of ring */
335
336 u16 rx_hdr_len;
337 u16 rx_buf_len;
338 __cacheline_group_end_aligned(cold);
339 } ____cacheline_internodealigned_in_smp;
340
341 struct ice_tx_ring {
342 __cacheline_group_begin_aligned(read_mostly);
343 void *desc; /* Descriptor ring memory */
344 struct device *dev; /* Used for DMA mapping */
345 u8 __iomem *tail;
346 struct ice_tx_buf *tx_buf;
347
348 struct ice_q_vector *q_vector; /* Backreference to associated vector */
349 struct net_device *netdev; /* netdev ring maps to */
350 struct ice_vsi *vsi; /* Backreference to associated VSI */
351
352 u16 count; /* Number of descriptors */
353 u16 q_index; /* Queue number of ring */
354
355 u8 flags;
356 #define ICE_TX_FLAGS_RING_XDP BIT(0)
357 #define ICE_TX_FLAGS_RING_VLAN_L2TAG1 BIT(1)
358 #define ICE_TX_FLAGS_RING_VLAN_L2TAG2 BIT(2)
359 #define ICE_TX_FLAGS_TXTIME BIT(3)
360
361 struct xsk_buff_pool *xsk_pool;
362
363 /* stats structs */
364 struct ice_ring_stats *ring_stats;
365 struct ice_tx_ring *next; /* pointer to next ring in q_vector */
366
367 struct ice_tstamp_ring *tstamp_ring;
368 struct ice_ptp_tx *tx_tstamps;
369 __cacheline_group_end_aligned(read_mostly);
370
371 __cacheline_group_begin_aligned(read_write);
372 u16 next_to_use;
373 u16 next_to_clean;
374
375 u16 xdp_tx_active;
376 spinlock_t tx_lock;
377 __cacheline_group_end_aligned(read_write);
378
379 __cacheline_group_begin_aligned(cold);
380 struct rcu_head rcu; /* to avoid race on free */
381 DECLARE_BITMAP(xps_state, ICE_TX_NBITS); /* XPS Config State */
382 struct ice_channel *ch;
383
384 dma_addr_t dma; /* physical address of ring */
385 u16 q_handle; /* Queue handle per TC */
386 u16 reg_idx; /* HW register index of the ring */
387 u8 dcb_tc; /* Traffic class of ring */
388
389 u16 quanta_prof_id;
390 u32 txq_teid; /* Added Tx queue TEID */
391 __cacheline_group_end_aligned(cold);
392 } ____cacheline_internodealigned_in_smp;
393
ice_ring_ch_enabled(struct ice_tx_ring * ring)394 static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring)
395 {
396 return !!ring->ch;
397 }
398
ice_ring_is_xdp(struct ice_tx_ring * ring)399 static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring)
400 {
401 return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
402 }
403
404 enum ice_container_type {
405 ICE_RX_CONTAINER,
406 ICE_TX_CONTAINER,
407 };
408
409 struct ice_ring_container {
410 /* head of linked-list of rings */
411 union {
412 struct ice_rx_ring *rx_ring;
413 struct ice_tx_ring *tx_ring;
414 };
415 struct dim dim; /* data for net_dim algorithm */
416 u16 itr_idx; /* index in the interrupt vector */
417 /* this matches the maximum number of ITR bits, but in usec
418 * values, so it is shifted left one bit (bit zero is ignored)
419 */
420 union {
421 struct {
422 u16 itr_setting:13;
423 u16 itr_reserved:2;
424 u16 itr_mode:1;
425 };
426 u16 itr_settings;
427 };
428 enum ice_container_type type;
429 };
430
431 struct ice_coalesce_stored {
432 u16 itr_tx;
433 u16 itr_rx;
434 u8 intrl;
435 u8 tx_valid;
436 u8 rx_valid;
437 };
438
439 /* iterator for handling rings in ring container */
440 #define ice_for_each_rx_ring(pos, head) \
441 for (pos = (head).rx_ring; pos; pos = pos->next)
442
443 #define ice_for_each_tx_ring(pos, head) \
444 for (pos = (head).tx_ring; pos; pos = pos->next)
445
ice_rx_pg_order(struct ice_rx_ring * ring)446 static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring)
447 {
448 return 0;
449 }
450
451 union ice_32b_rx_flex_desc;
452
453 void ice_init_ctrl_rx_descs(struct ice_rx_ring *rx_ring, u32 num_descs);
454 void ice_rxq_pp_destroy(struct ice_rx_ring *rq);
455 bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, unsigned int cleaned_count);
456 netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
457 u16
458 ice_select_queue(struct net_device *dev, struct sk_buff *skb,
459 struct net_device *sb_dev);
460 void ice_clean_tx_ring(struct ice_tx_ring *tx_ring);
461 void ice_clean_rx_ring(struct ice_rx_ring *rx_ring);
462 int ice_setup_tx_ring(struct ice_tx_ring *tx_ring);
463 int ice_setup_rx_ring(struct ice_rx_ring *rx_ring);
464 int ice_alloc_setup_tstamp_ring(struct ice_tx_ring *tx_ring);
465 void ice_free_tx_ring(struct ice_tx_ring *tx_ring);
466 void ice_free_rx_ring(struct ice_rx_ring *rx_ring);
467 int ice_napi_poll(struct napi_struct *napi, int budget);
468 int
469 ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
470 u8 *raw_packet);
471 void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring);
472 void ice_clean_ctrl_rx_irq(struct ice_rx_ring *rx_ring);
473 void ice_free_tx_tstamp_ring(struct ice_tx_ring *tx_ring);
474 void ice_free_tstamp_ring(struct ice_tx_ring *tx_ring);
475 #endif /* _ICE_TXRX_H_ */
476