1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/timekeeping.h>
6 #if defined(__FreeBSD__)
7 #include <linux/delay.h>
8 #include <linux/math64.h>
9 #endif
10 #include "coredump.h"
11 #include "mt7915.h"
12 #include "../dma.h"
13 #include "mac.h"
14 #include "mcu.h"
15
16 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2)
17
18 static const struct mt7915_dfs_radar_spec etsi_radar_specs = {
19 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
20 .radar_pattern = {
21 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
22 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
23 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
24 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
25 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
26 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
27 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
28 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
29 },
30 };
31
32 static const struct mt7915_dfs_radar_spec fcc_radar_specs = {
33 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
34 .radar_pattern = {
35 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
36 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
37 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
38 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
39 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
40 },
41 };
42
43 static const struct mt7915_dfs_radar_spec jp_radar_specs = {
44 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
45 .radar_pattern = {
46 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
47 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
48 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
49 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
50 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
51 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 },
52 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 },
53 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 },
54 },
55 };
56
mt7915_rx_get_wcid(struct mt7915_dev * dev,u16 idx,bool unicast)57 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev,
58 u16 idx, bool unicast)
59 {
60 struct mt7915_sta *sta;
61 struct mt76_wcid *wcid;
62
63 wcid = mt76_wcid_ptr(dev, idx);
64 if (unicast || !wcid)
65 return wcid;
66
67 if (!wcid->sta)
68 return NULL;
69
70 sta = container_of(wcid, struct mt7915_sta, wcid);
71 if (!sta->vif)
72 return NULL;
73
74 return &sta->vif->sta.wcid;
75 }
76
mt7915_mac_wtbl_update(struct mt7915_dev * dev,int idx,u32 mask)77 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask)
78 {
79 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
80 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
81
82 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
83 0, 5000);
84 }
85
mt7915_mac_wtbl_lmac_addr(struct mt7915_dev * dev,u16 wcid,u8 dw)86 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw)
87 {
88 mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
89 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7)));
90
91 return MT_WTBL_LMAC_OFFS(wcid, dw);
92 }
93
mt7915_mac_sta_poll(struct mt7915_dev * dev)94 static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
95 {
96 static const u8 ac_to_tid[] = {
97 [IEEE80211_AC_BE] = 0,
98 [IEEE80211_AC_BK] = 1,
99 [IEEE80211_AC_VI] = 4,
100 [IEEE80211_AC_VO] = 6
101 };
102 struct ieee80211_sta *sta;
103 struct mt7915_sta *msta;
104 struct rate_info *rate;
105 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
106 #if defined(__linux__)
107 LIST_HEAD(sta_poll_list);
108 #elif defined(__FreeBSD__)
109 LINUX_LIST_HEAD(sta_poll_list);
110 #endif
111 int i;
112
113 spin_lock_bh(&dev->mt76.sta_poll_lock);
114 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list);
115 spin_unlock_bh(&dev->mt76.sta_poll_lock);
116
117 rcu_read_lock();
118
119 while (true) {
120 bool clear = false;
121 u32 addr, val;
122 u16 idx;
123 s8 rssi[4];
124 u8 bw;
125
126 spin_lock_bh(&dev->mt76.sta_poll_lock);
127 if (list_empty(&sta_poll_list)) {
128 spin_unlock_bh(&dev->mt76.sta_poll_lock);
129 break;
130 }
131 msta = list_first_entry(&sta_poll_list,
132 struct mt7915_sta, wcid.poll_list);
133 list_del_init(&msta->wcid.poll_list);
134 spin_unlock_bh(&dev->mt76.sta_poll_lock);
135
136 idx = msta->wcid.idx;
137
138 /* refresh peer's airtime reporting */
139 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20);
140
141 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
142 u32 tx_last = msta->airtime_ac[i];
143 u32 rx_last = msta->airtime_ac[i + 4];
144
145 msta->airtime_ac[i] = mt76_rr(dev, addr);
146 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
147
148 if (msta->airtime_ac[i] <= tx_last)
149 tx_time[i] = 0;
150 else
151 tx_time[i] = msta->airtime_ac[i] - tx_last;
152
153 if (msta->airtime_ac[i + 4] <= rx_last)
154 rx_time[i] = 0;
155 else
156 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
157
158 if ((tx_last | rx_last) & BIT(30))
159 clear = true;
160
161 addr += 8;
162 }
163
164 if (clear) {
165 mt7915_mac_wtbl_update(dev, idx,
166 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
167 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
168 }
169
170 if (!msta->wcid.sta)
171 continue;
172
173 sta = container_of((void *)msta, struct ieee80211_sta,
174 drv_priv);
175 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
176 u8 queue = mt76_connac_lmac_mapping(i);
177 u32 tx_cur = tx_time[queue];
178 u32 rx_cur = rx_time[queue];
179 u8 tid = ac_to_tid[i];
180
181 if (!tx_cur && !rx_cur)
182 continue;
183
184 ieee80211_sta_register_airtime(sta, tid, tx_cur,
185 rx_cur);
186 }
187
188 /*
189 * We don't support reading GI info from txs packets.
190 * For accurate tx status reporting and AQL improvement,
191 * we need to make sure that flags match so polling GI
192 * from per-sta counters directly.
193 */
194 rate = &msta->wcid.rate;
195 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7);
196 val = mt76_rr(dev, addr);
197
198 switch (rate->bw) {
199 case RATE_INFO_BW_160:
200 bw = IEEE80211_STA_RX_BW_160;
201 break;
202 case RATE_INFO_BW_80:
203 bw = IEEE80211_STA_RX_BW_80;
204 break;
205 case RATE_INFO_BW_40:
206 bw = IEEE80211_STA_RX_BW_40;
207 break;
208 default:
209 bw = IEEE80211_STA_RX_BW_20;
210 break;
211 }
212
213 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) {
214 u8 offs = 24 + 2 * bw;
215
216 rate->he_gi = (val & (0x3 << offs)) >> offs;
217 } else if (rate->flags &
218 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) {
219 if (val & BIT(12 + bw))
220 rate->flags |= RATE_INFO_FLAGS_SHORT_GI;
221 else
222 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI;
223 }
224
225 /* get signal strength of resp frames (CTS/BA/ACK) */
226 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30);
227 val = mt76_rr(dev, addr);
228
229 rssi[0] = to_rssi(GENMASK(7, 0), val);
230 rssi[1] = to_rssi(GENMASK(15, 8), val);
231 rssi[2] = to_rssi(GENMASK(23, 16), val);
232 rssi[3] = to_rssi(GENMASK(31, 14), val);
233
234 msta->ack_signal =
235 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi);
236
237 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal);
238 }
239
240 rcu_read_unlock();
241 }
242
mt7915_mac_enable_rtscts(struct mt7915_dev * dev,struct ieee80211_vif * vif,bool enable)243 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev,
244 struct ieee80211_vif *vif, bool enable)
245 {
246 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
247 u32 addr;
248
249 addr = mt7915_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5);
250 if (enable)
251 mt76_set(dev, addr, BIT(5));
252 else
253 mt76_clear(dev, addr, BIT(5));
254 }
255
256 static void
mt7915_wed_check_ppe(struct mt7915_dev * dev,struct mt76_queue * q,struct mt7915_sta * msta,struct sk_buff * skb,u32 info)257 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q,
258 struct mt7915_sta *msta, struct sk_buff *skb,
259 u32 info)
260 {
261 struct ieee80211_vif *vif;
262 struct wireless_dev *wdev;
263
264 if (!msta || !msta->vif)
265 return;
266
267 if (!mt76_queue_is_wed_rx(q))
268 return;
269
270 if (!(info & MT_DMA_INFO_PPE_VLD))
271 return;
272
273 vif = container_of((void *)msta->vif, struct ieee80211_vif,
274 drv_priv);
275 wdev = ieee80211_vif_to_wdev(vif);
276 skb->dev = wdev->netdev;
277
278 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb,
279 FIELD_GET(MT_DMA_PPE_CPU_REASON, info),
280 FIELD_GET(MT_DMA_PPE_ENTRY, info));
281 }
282
283 static int
mt7915_mac_fill_rx(struct mt7915_dev * dev,struct sk_buff * skb,enum mt76_rxq_id q,u32 * info)284 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
285 enum mt76_rxq_id q, u32 *info)
286 {
287 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
288 struct mt76_phy *mphy = &dev->mt76.phy;
289 struct mt7915_phy *phy = &dev->phy;
290 struct ieee80211_supported_band *sband;
291 __le32 *rxd = (__le32 *)skb->data;
292 __le32 *rxv = NULL;
293 u32 rxd0 = le32_to_cpu(rxd[0]);
294 u32 rxd1 = le32_to_cpu(rxd[1]);
295 u32 rxd2 = le32_to_cpu(rxd[2]);
296 u32 rxd3 = le32_to_cpu(rxd[3]);
297 u32 rxd4 = le32_to_cpu(rxd[4]);
298 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
299 bool unicast, insert_ccmp_hdr = false;
300 u8 remove_pad, amsdu_info;
301 u8 mode = 0, qos_ctl = 0;
302 struct mt7915_sta *msta = NULL;
303 u32 csum_status = *(u32 *)skb->cb;
304 bool hdr_trans;
305 u16 hdr_gap;
306 u16 seq_ctrl = 0;
307 __le16 fc = 0;
308 int idx;
309
310 memset(status, 0, sizeof(*status));
311
312 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) {
313 mphy = dev->mt76.phys[MT_BAND1];
314 if (!mphy)
315 return -EINVAL;
316
317 phy = mphy->priv;
318 status->phy_idx = 1;
319 }
320
321 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
322 return -EINVAL;
323
324 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
325 return -EINVAL;
326
327 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS;
328 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM))
329 return -EINVAL;
330
331 /* ICV error or CCMP/BIP/WPI MIC error */
332 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR)
333 status->flag |= RX_FLAG_ONLY_MONITOR;
334
335 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
336 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
337 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast);
338
339 if (status->wcid) {
340 msta = container_of(status->wcid, struct mt7915_sta, wcid);
341 mt76_wcid_add_poll(&dev->mt76, &msta->wcid);
342 }
343
344 status->freq = mphy->chandef.chan->center_freq;
345 status->band = mphy->chandef.chan->band;
346 if (status->band == NL80211_BAND_5GHZ)
347 sband = &mphy->sband_5g.sband;
348 else if (status->band == NL80211_BAND_6GHZ)
349 sband = &mphy->sband_6g.sband;
350 else
351 sband = &mphy->sband_2g.sband;
352
353 if (!sband->channels)
354 return -EINVAL;
355
356 if ((rxd0 & csum_mask) == csum_mask &&
357 !(csum_status & (BIT(0) | BIT(2) | BIT(3))))
358 skb->ip_summed = CHECKSUM_UNNECESSARY;
359
360 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
361 status->flag |= RX_FLAG_FAILED_FCS_CRC;
362
363 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
364 status->flag |= RX_FLAG_MMIC_ERROR;
365
366 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
367 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
368 status->flag |= RX_FLAG_DECRYPTED;
369 status->flag |= RX_FLAG_IV_STRIPPED;
370 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
371 }
372
373 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
374
375 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
376 return -EINVAL;
377
378 rxd += 6;
379 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
380 u32 v0 = le32_to_cpu(rxd[0]);
381 u32 v2 = le32_to_cpu(rxd[2]);
382
383 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));
384 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2);
385 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2);
386
387 rxd += 4;
388 if ((u8 *)rxd - skb->data >= skb->len)
389 return -EINVAL;
390 }
391
392 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
393 u8 *data = (u8 *)rxd;
394
395 if (status->flag & RX_FLAG_DECRYPTED) {
396 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) {
397 case MT_CIPHER_AES_CCMP:
398 case MT_CIPHER_CCMP_CCX:
399 case MT_CIPHER_CCMP_256:
400 insert_ccmp_hdr =
401 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
402 fallthrough;
403 case MT_CIPHER_TKIP:
404 case MT_CIPHER_TKIP_NO_MIC:
405 case MT_CIPHER_GCMP:
406 case MT_CIPHER_GCMP_256:
407 status->iv[0] = data[5];
408 status->iv[1] = data[4];
409 status->iv[2] = data[3];
410 status->iv[3] = data[2];
411 status->iv[4] = data[1];
412 status->iv[5] = data[0];
413 break;
414 default:
415 break;
416 }
417 }
418 rxd += 4;
419 if ((u8 *)rxd - skb->data >= skb->len)
420 return -EINVAL;
421 }
422
423 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
424 status->timestamp = le32_to_cpu(rxd[0]);
425 status->flag |= RX_FLAG_MACTIME_START;
426
427 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
428 status->flag |= RX_FLAG_AMPDU_DETAILS;
429
430 /* all subframes of an A-MPDU have the same timestamp */
431 if (phy->rx_ampdu_ts != status->timestamp) {
432 if (!++phy->ampdu_ref)
433 phy->ampdu_ref++;
434 }
435 phy->rx_ampdu_ts = status->timestamp;
436
437 status->ampdu_ref = phy->ampdu_ref;
438 }
439
440 rxd += 2;
441 if ((u8 *)rxd - skb->data >= skb->len)
442 return -EINVAL;
443 }
444
445 /* RXD Group 3 - P-RXV */
446 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
447 u32 v0, v1;
448 int ret;
449
450 rxv = rxd;
451 rxd += 2;
452 if ((u8 *)rxd - skb->data >= skb->len)
453 return -EINVAL;
454
455 v0 = le32_to_cpu(rxv[0]);
456 v1 = le32_to_cpu(rxv[1]);
457
458 if (v0 & MT_PRXV_HT_AD_CODE)
459 status->enc_flags |= RX_ENC_FLAG_LDPC;
460
461 status->chains = mphy->antenna_mask;
462 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
463 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
464 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
465 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
466
467 /* RXD Group 5 - C-RXV */
468 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
469 rxd += 18;
470 if ((u8 *)rxd - skb->data >= skb->len)
471 return -EINVAL;
472 }
473
474 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) {
475 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status,
476 sband, rxv, &mode);
477 if (ret < 0)
478 return ret;
479 }
480 }
481
482 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4);
483 status->amsdu = !!amsdu_info;
484 if (status->amsdu) {
485 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME;
486 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME;
487 }
488
489 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
490 if (hdr_trans && ieee80211_has_morefrags(fc)) {
491 struct ieee80211_vif *vif;
492 int err;
493
494 if (!msta || !msta->vif)
495 return -EINVAL;
496
497 vif = container_of((void *)msta->vif, struct ieee80211_vif,
498 drv_priv);
499 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap);
500 if (err)
501 return err;
502
503 hdr_trans = false;
504 } else {
505 int pad_start = 0;
506
507 skb_pull(skb, hdr_gap);
508 if (!hdr_trans && status->amsdu) {
509 pad_start = ieee80211_get_hdrlen_from_skb(skb);
510 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) {
511 /*
512 * When header translation failure is indicated,
513 * the hardware will insert an extra 2-byte field
514 * containing the data length after the protocol
515 * type field. This happens either when the LLC-SNAP
516 * pattern did not match, or if a VLAN header was
517 * detected.
518 */
519 pad_start = 12;
520 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q)
521 pad_start += 4;
522 else
523 pad_start = 0;
524 }
525
526 if (pad_start) {
527 memmove(skb->data + 2, skb->data, pad_start);
528 skb_pull(skb, 2);
529 }
530 }
531
532 if (!hdr_trans) {
533 struct ieee80211_hdr *hdr;
534
535 if (insert_ccmp_hdr) {
536 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
537
538 mt76_insert_ccmp_hdr(skb, key_id);
539 }
540
541 hdr = mt76_skb_get_hdr(skb);
542 fc = hdr->frame_control;
543 if (ieee80211_is_data_qos(fc)) {
544 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
545 qos_ctl = *ieee80211_get_qos_ctl(hdr);
546 }
547 } else {
548 status->flag |= RX_FLAG_8023;
549 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb,
550 *info);
551 }
552
553 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
554 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode);
555
556 if (!status->wcid || !ieee80211_is_data_qos(fc))
557 return 0;
558
559 status->aggr = unicast &&
560 !ieee80211_is_qos_nullfunc(fc);
561 status->qos_ctl = qos_ctl;
562 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
563
564 return 0;
565 }
566
567 static void
mt7915_mac_fill_rx_vector(struct mt7915_dev * dev,struct sk_buff * skb)568 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb)
569 {
570 #ifdef CONFIG_NL80211_TESTMODE
571 struct mt7915_phy *phy = &dev->phy;
572 __le32 *rxd = (__le32 *)skb->data;
573 __le32 *rxv_hdr = rxd + 2;
574 __le32 *rxv = rxd + 4;
575 u32 rcpi, ib_rssi, wb_rssi, v20, v21;
576 u8 band_idx;
577 s32 foe;
578 u8 snr;
579 int i;
580
581 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX);
582 if (band_idx && !phy->mt76->band_idx) {
583 phy = mt7915_ext_phy(dev);
584 if (!phy)
585 goto out;
586 }
587
588 rcpi = le32_to_cpu(rxv[6]);
589 ib_rssi = le32_to_cpu(rxv[7]);
590 wb_rssi = le32_to_cpu(rxv[8]) >> 5;
591
592 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) {
593 if (i == 3)
594 wb_rssi = le32_to_cpu(rxv[9]);
595
596 phy->test.last_rcpi[i] = rcpi & 0xff;
597 phy->test.last_ib_rssi[i] = ib_rssi & 0xff;
598 phy->test.last_wb_rssi[i] = wb_rssi & 0xff;
599 }
600
601 v20 = le32_to_cpu(rxv[20]);
602 v21 = le32_to_cpu(rxv[21]);
603
604 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) |
605 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT);
606
607 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16;
608
609 phy->test.last_freq_offset = foe;
610 phy->test.last_snr = snr;
611 out:
612 #endif
613 dev_kfree_skb(skb);
614 }
615
616 static void
mt7915_mac_write_txwi_tm(struct mt7915_phy * phy,__le32 * txwi,struct sk_buff * skb)617 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
618 struct sk_buff *skb)
619 {
620 #ifdef CONFIG_NL80211_TESTMODE
621 struct mt76_testmode_data *td = &phy->mt76->test;
622 const struct ieee80211_rate *r;
623 u8 bw, mode, nss = td->tx_rate_nss;
624 u8 rate_idx = td->tx_rate_idx;
625 u16 rateval = 0;
626 u32 val;
627 bool cck = false;
628 int band;
629
630 if (skb != phy->mt76->test.tx_skb)
631 return;
632
633 switch (td->tx_rate_mode) {
634 case MT76_TM_TX_MODE_HT:
635 nss = 1 + (rate_idx >> 3);
636 mode = MT_PHY_TYPE_HT;
637 break;
638 case MT76_TM_TX_MODE_VHT:
639 mode = MT_PHY_TYPE_VHT;
640 break;
641 case MT76_TM_TX_MODE_HE_SU:
642 mode = MT_PHY_TYPE_HE_SU;
643 break;
644 case MT76_TM_TX_MODE_HE_EXT_SU:
645 mode = MT_PHY_TYPE_HE_EXT_SU;
646 break;
647 case MT76_TM_TX_MODE_HE_TB:
648 mode = MT_PHY_TYPE_HE_TB;
649 break;
650 case MT76_TM_TX_MODE_HE_MU:
651 mode = MT_PHY_TYPE_HE_MU;
652 break;
653 case MT76_TM_TX_MODE_CCK:
654 cck = true;
655 fallthrough;
656 case MT76_TM_TX_MODE_OFDM:
657 band = phy->mt76->chandef.chan->band;
658 if (band == NL80211_BAND_2GHZ && !cck)
659 rate_idx += 4;
660
661 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx];
662 val = cck ? r->hw_value_short : r->hw_value;
663
664 mode = val >> 8;
665 rate_idx = val & 0xff;
666 break;
667 default:
668 mode = MT_PHY_TYPE_OFDM;
669 break;
670 }
671
672 switch (phy->mt76->chandef.width) {
673 case NL80211_CHAN_WIDTH_40:
674 bw = 1;
675 break;
676 case NL80211_CHAN_WIDTH_80:
677 bw = 2;
678 break;
679 case NL80211_CHAN_WIDTH_80P80:
680 case NL80211_CHAN_WIDTH_160:
681 bw = 3;
682 break;
683 default:
684 bw = 0;
685 break;
686 }
687
688 if (td->tx_rate_stbc && nss == 1) {
689 nss++;
690 rateval |= MT_TX_RATE_STBC;
691 }
692
693 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
694 FIELD_PREP(MT_TX_RATE_MODE, mode) |
695 FIELD_PREP(MT_TX_RATE_NSS, nss - 1);
696
697 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
698
699 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT);
700 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT)
701 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
702
703 val = MT_TXD6_FIXED_BW |
704 FIELD_PREP(MT_TXD6_BW, bw) |
705 FIELD_PREP(MT_TXD6_TX_RATE, rateval) |
706 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi);
707
708 /* for HE_SU/HE_EXT_SU PPDU
709 * - 1x, 2x, 4x LTF + 0.8us GI
710 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
711 * for HE_MU PPDU
712 * - 2x, 4x LTF + 0.8us GI
713 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
714 * for HE_TB PPDU
715 * - 1x, 2x LTF + 1.6us GI
716 * - 4x LTF + 3.2us GI
717 */
718 if (mode >= MT_PHY_TYPE_HE_SU)
719 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
720
721 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
722 val |= MT_TXD6_LDPC;
723
724 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
725 txwi[6] |= cpu_to_le32(val);
726 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
727 phy->test.spe_idx));
728 #endif
729 }
730
mt7915_mac_write_txwi(struct mt76_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,int pid,struct ieee80211_key_conf * key,enum mt76_txq_id qid,u32 changed)731 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
732 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
733 struct ieee80211_key_conf *key,
734 enum mt76_txq_id qid, u32 changed)
735 {
736 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
737 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
738 struct mt76_phy *mphy = &dev->phy;
739
740 if (phy_idx && dev->phys[MT_BAND1])
741 mphy = dev->phys[MT_BAND1];
742
743 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed);
744
745 if (mt76_testmode_enabled(mphy))
746 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb);
747 }
748
mt7915_tx_prepare_skb(struct mt76_dev * mdev,void * txwi_ptr,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,struct mt76_tx_info * tx_info)749 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
750 enum mt76_txq_id qid, struct mt76_wcid *wcid,
751 struct ieee80211_sta *sta,
752 struct mt76_tx_info *tx_info)
753 {
754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
755 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
756 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
757 struct ieee80211_key_conf *key = info->control.hw_key;
758 struct ieee80211_vif *vif = info->control.vif;
759 struct mt76_connac_fw_txp *txp;
760 struct mt76_txwi_cache *t;
761 int id, i, nbuf = tx_info->nbuf - 1;
762 u8 *txwi = (u8 *)txwi_ptr;
763 int pid;
764
765 if (unlikely(tx_info->skb->len <= ETH_HLEN))
766 return -EINVAL;
767
768 if (!wcid)
769 wcid = &dev->mt76.global_wcid;
770
771 if (sta) {
772 struct mt7915_sta *msta;
773
774 msta = (struct mt7915_sta *)sta->drv_priv;
775
776 if (time_after(jiffies, msta->jiffies + HZ / 4)) {
777 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS;
778 msta->jiffies = jiffies;
779 }
780 }
781
782 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
783 t->skb = tx_info->skb;
784
785 id = mt76_token_consume(mdev, &t);
786 if (id < 0)
787 return id;
788
789 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
790 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key,
791 qid, 0);
792
793 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE);
794 for (i = 0; i < nbuf; i++) {
795 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
796 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
797 }
798 txp->nbuf = nbuf;
799
800 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST);
801
802 if (!key)
803 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
804
805 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
806 ieee80211_is_mgmt(hdr->frame_control))
807 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
808
809 if (vif) {
810 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
811
812 txp->bss_idx = mvif->mt76.idx;
813 }
814
815 txp->token = cpu_to_le16(id);
816 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags))
817 txp->rept_wds_wcid = cpu_to_le16(wcid->idx);
818 else
819 txp->rept_wds_wcid = cpu_to_le16(0x3ff);
820 tx_info->skb = NULL;
821
822 /* pass partial skb header to fw */
823 tx_info->buf[1].len = MT_CT_PARSE_LEN;
824 tx_info->buf[1].skip_unmap = true;
825 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
826
827 return 0;
828 }
829
mt7915_wed_init_buf(void * ptr,dma_addr_t phys,int token_id)830 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
831 {
832 #if defined(__linux__)
833 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE;
834 #elif defined(__FreeBSD__)
835 struct mt76_connac_fw_txp *txp = (void *)((u8 *)ptr + MT_TXD_SIZE);
836 #endif
837 __le32 *txwi = ptr;
838 u32 val;
839
840 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp));
841
842 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) |
843 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT);
844 txwi[0] = cpu_to_le32(val);
845
846 val = MT_TXD1_LONG_FORMAT |
847 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3);
848 txwi[1] = cpu_to_le32(val);
849
850 txp->token = cpu_to_le16(token_id);
851 txp->nbuf = 1;
852 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp));
853
854 return MT_TXD_SIZE + sizeof(*txp);
855 }
856
857 static void
mt7915_mac_tx_free_prepare(struct mt7915_dev * dev)858 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev)
859 {
860 struct mt76_dev *mdev = &dev->mt76;
861 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1];
862
863 /* clean DMA queues and unmap buffers first */
864 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
865 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
866 if (mphy_ext) {
867 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false);
868 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
869 }
870 }
871
872 static void
mt7915_mac_tx_free_done(struct mt7915_dev * dev,struct list_head * free_list,bool wake)873 mt7915_mac_tx_free_done(struct mt7915_dev *dev,
874 struct list_head *free_list, bool wake)
875 {
876 struct sk_buff *skb, *tmp;
877
878 mt7915_mac_sta_poll(dev);
879
880 if (wake)
881 mt76_set_tx_blocked(&dev->mt76, false);
882
883 mt76_worker_schedule(&dev->mt76.tx_worker);
884
885 list_for_each_entry_safe(skb, tmp, free_list, list) {
886 skb_list_del_init(skb);
887 napi_consume_skb(skb, 1);
888 }
889 }
890
891 static void
mt7915_mac_tx_free(struct mt7915_dev * dev,void * data,int len)892 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len)
893 {
894 struct mt76_connac_tx_free *free = data;
895 #if defined(__linux__)
896 __le32 *tx_info = (__le32 *)(data + sizeof(*free));
897 #elif defined(__FreeBSD__)
898 __le32 *tx_info = (__le32 *)((u8 *)data + sizeof(*free));
899 #endif
900 struct mt76_dev *mdev = &dev->mt76;
901 struct mt76_txwi_cache *txwi;
902 struct ieee80211_sta *sta = NULL;
903 struct mt76_wcid *wcid = NULL;
904 #if defined(__linux__)
905 LIST_HEAD(free_list);
906 void *end = data + len;
907 #elif defined(__FreeBSD__)
908 LINUX_LIST_HEAD(free_list);
909 void *end = (u8 *)data + len;
910 #endif
911 bool v3, wake = false;
912 u16 total, count = 0;
913 u32 txd = le32_to_cpu(free->txd);
914 __le32 *cur_info;
915
916 mt7915_mac_tx_free_prepare(dev);
917
918 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT);
919 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4);
920
921 for (cur_info = tx_info; count < total; cur_info++) {
922 u32 msdu, info;
923 u8 i;
924
925 if (WARN_ON_ONCE((void *)cur_info >= end))
926 return;
927
928 /*
929 * 1'b1: new wcid pair.
930 * 1'b0: msdu_id with the same 'wcid pair' as above.
931 */
932 info = le32_to_cpu(*cur_info);
933 if (info & MT_TX_FREE_PAIR) {
934 struct mt7915_sta *msta;
935 u16 idx;
936
937 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
938 wcid = mt76_wcid_ptr(dev, idx);
939 sta = wcid_to_sta(wcid);
940 if (!sta)
941 continue;
942
943 msta = container_of(wcid, struct mt7915_sta, wcid);
944 mt76_wcid_add_poll(&dev->mt76, &msta->wcid);
945 continue;
946 }
947
948 if (!mtk_wed_device_active(&mdev->mmio.wed) && wcid) {
949 u32 tx_retries = 0, tx_failed = 0;
950
951 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) {
952 tx_retries =
953 FIELD_GET(MT_TX_FREE_COUNT_V3, info) - 1;
954 tx_failed = tx_retries +
955 !!FIELD_GET(MT_TX_FREE_STAT_V3, info);
956 } else if (!v3 && (info & MT_TX_FREE_MPDU_HEADER)) {
957 tx_retries =
958 FIELD_GET(MT_TX_FREE_COUNT, info) - 1;
959 tx_failed = tx_retries +
960 !!FIELD_GET(MT_TX_FREE_STAT, info);
961 }
962 wcid->stats.tx_retries += tx_retries;
963 wcid->stats.tx_failed += tx_failed;
964 }
965
966 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3))
967 continue;
968
969 for (i = 0; i < 1 + v3; i++) {
970 if (v3) {
971 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3;
972 if (msdu == MT_TX_FREE_MSDU_ID_V3)
973 continue;
974 } else {
975 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
976 }
977 count++;
978 txwi = mt76_token_release(mdev, msdu, &wake);
979 if (!txwi)
980 continue;
981
982 mt76_connac2_txwi_free(mdev, txwi, sta, &free_list);
983 }
984 }
985
986 mt7915_mac_tx_free_done(dev, &free_list, wake);
987 }
988
989 static void
mt7915_mac_tx_free_v0(struct mt7915_dev * dev,void * data,int len)990 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len)
991 {
992 struct mt76_connac_tx_free *free = data;
993 #if defined(__linux__)
994 __le16 *info = (__le16 *)(data + sizeof(*free));
995 #elif defined(__FreeBSD__)
996 __le16 *info = (__le16 *)((u8 *)data + sizeof(*free));
997 #endif
998 struct mt76_dev *mdev = &dev->mt76;
999 #if defined(__linux__)
1000 void *end = data + len;
1001 LIST_HEAD(free_list);
1002 #elif defined(__FreeBSD__)
1003 void *end = (u8 *)data + len;
1004 LINUX_LIST_HEAD(free_list);
1005 #endif
1006 bool wake = false;
1007 u8 i, count;
1008
1009 mt7915_mac_tx_free_prepare(dev);
1010
1011 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl));
1012 if (WARN_ON_ONCE((void *)&info[count] > end))
1013 return;
1014
1015 for (i = 0; i < count; i++) {
1016 struct mt76_txwi_cache *txwi;
1017 u16 msdu = le16_to_cpu(info[i]);
1018
1019 txwi = mt76_token_release(mdev, msdu, &wake);
1020 if (!txwi)
1021 continue;
1022
1023 mt76_connac2_txwi_free(mdev, txwi, NULL, &free_list);
1024 }
1025
1026 mt7915_mac_tx_free_done(dev, &free_list, wake);
1027 }
1028
mt7915_mac_add_txs(struct mt7915_dev * dev,void * data)1029 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data)
1030 {
1031 struct mt7915_sta *msta = NULL;
1032 struct mt76_wcid *wcid;
1033 __le32 *txs_data = data;
1034 u16 wcidx;
1035 u8 pid;
1036
1037 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
1038 pid = le32_get_bits(txs_data[3], MT_TXS3_PID);
1039
1040 if (pid < MT_PACKET_ID_WED)
1041 return;
1042
1043 rcu_read_lock();
1044
1045 wcid = mt76_wcid_ptr(dev, wcidx);
1046 if (!wcid)
1047 goto out;
1048
1049 msta = container_of(wcid, struct mt7915_sta, wcid);
1050
1051 if (pid == MT_PACKET_ID_WED)
1052 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data);
1053 else
1054 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data);
1055
1056 if (!wcid->sta)
1057 goto out;
1058
1059 mt76_wcid_add_poll(&dev->mt76, &msta->wcid);
1060
1061 out:
1062 rcu_read_unlock();
1063 }
1064
mt7915_rx_check(struct mt76_dev * mdev,void * data,int len)1065 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
1066 {
1067 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1068 __le32 *rxd = (__le32 *)data;
1069 __le32 *end = (__le32 *)&rxd[len / 4];
1070 enum rx_pkt_type type;
1071
1072 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1073
1074 switch (type) {
1075 case PKT_TYPE_TXRX_NOTIFY:
1076 mt7915_mac_tx_free(dev, data, len);
1077 return false;
1078 case PKT_TYPE_TXRX_NOTIFY_V0:
1079 mt7915_mac_tx_free_v0(dev, data, len);
1080 return false;
1081 case PKT_TYPE_TXS:
1082 for (rxd += 2; rxd + 8 <= end; rxd += 8)
1083 mt7915_mac_add_txs(dev, rxd);
1084 return false;
1085 case PKT_TYPE_RX_FW_MONITOR:
1086 #if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS)
1087 mt7915_debugfs_rx_fw_monitor(dev, data, len);
1088 #endif
1089 return false;
1090 default:
1091 return true;
1092 }
1093 }
1094
mt7915_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb,u32 * info)1095 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1096 struct sk_buff *skb, u32 *info)
1097 {
1098 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1099 __le32 *rxd = (__le32 *)skb->data;
1100 __le32 *end = (__le32 *)&skb->data[skb->len];
1101 enum rx_pkt_type type;
1102
1103 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1104
1105 switch (type) {
1106 case PKT_TYPE_TXRX_NOTIFY:
1107 mt7915_mac_tx_free(dev, skb->data, skb->len);
1108 napi_consume_skb(skb, 1);
1109 break;
1110 case PKT_TYPE_TXRX_NOTIFY_V0:
1111 mt7915_mac_tx_free_v0(dev, skb->data, skb->len);
1112 napi_consume_skb(skb, 1);
1113 break;
1114 case PKT_TYPE_RX_EVENT:
1115 mt7915_mcu_rx_event(dev, skb);
1116 break;
1117 case PKT_TYPE_TXRXV:
1118 mt7915_mac_fill_rx_vector(dev, skb);
1119 break;
1120 case PKT_TYPE_TXS:
1121 for (rxd += 2; rxd + 8 <= end; rxd += 8)
1122 mt7915_mac_add_txs(dev, rxd);
1123 dev_kfree_skb(skb);
1124 break;
1125 case PKT_TYPE_RX_FW_MONITOR:
1126 #if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS)
1127 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len);
1128 #endif
1129 dev_kfree_skb(skb);
1130 break;
1131 case PKT_TYPE_NORMAL:
1132 if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
1133 mt76_rx(&dev->mt76, q, skb);
1134 return;
1135 }
1136 fallthrough;
1137 default:
1138 dev_kfree_skb(skb);
1139 break;
1140 }
1141 }
1142
mt7915_mac_cca_stats_reset(struct mt7915_phy * phy)1143 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy)
1144 {
1145 struct mt7915_dev *dev = phy->dev;
1146 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx);
1147
1148 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN);
1149 mt76_set(dev, reg, BIT(11) | BIT(9));
1150 }
1151
mt7915_mac_reset_counters(struct mt7915_phy * phy)1152 void mt7915_mac_reset_counters(struct mt7915_phy *phy)
1153 {
1154 struct mt7915_dev *dev = phy->dev;
1155 int i;
1156
1157 for (i = 0; i < 4; i++) {
1158 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i));
1159 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i));
1160 }
1161
1162 phy->mt76->survey_time = ktime_get_boottime();
1163 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats));
1164
1165 /* reset airtime counters */
1166 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx),
1167 MT_WF_RMAC_MIB_RXTIME_CLR);
1168
1169 mt7915_mcu_get_chan_mib_info(phy, true);
1170 }
1171
mt7915_mac_set_timing(struct mt7915_phy * phy)1172 void mt7915_mac_set_timing(struct mt7915_phy *phy)
1173 {
1174 s16 coverage_class = phy->coverage_class;
1175 struct mt7915_dev *dev = phy->dev;
1176 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
1177 u32 val, reg_offset;
1178 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
1179 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
1180 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
1181 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
1182 u8 band = phy->mt76->band_idx;
1183 int eifs_ofdm = 84, sifs = 10, offset;
1184 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ);
1185
1186 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1187 return;
1188
1189 if (ext_phy)
1190 coverage_class = max_t(s16, dev->phy.coverage_class,
1191 ext_phy->coverage_class);
1192
1193 mt76_set(dev, MT_ARB_SCR(band),
1194 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1195 udelay(1);
1196
1197 offset = 3 * coverage_class;
1198 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1199 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
1200
1201 if (!is_mt7915(&dev->mt76)) {
1202 if (!a_band) {
1203 mt76_wr(dev, MT_TMAC_ICR1(band),
1204 FIELD_PREP(MT_IFS_EIFS_CCK, 314));
1205 eifs_ofdm = 78;
1206 } else {
1207 eifs_ofdm = 84;
1208 }
1209 } else if (a_band) {
1210 sifs = 16;
1211 }
1212
1213 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset);
1214 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset);
1215 mt76_wr(dev, MT_TMAC_ICR0(band),
1216 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) |
1217 FIELD_PREP(MT_IFS_RIFS, 2) |
1218 FIELD_PREP(MT_IFS_SIFS, sifs) |
1219 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
1220
1221 if (phy->slottime < 20 || a_band)
1222 val = MT7915_CFEND_RATE_DEFAULT;
1223 else
1224 val = MT7915_CFEND_RATE_11B;
1225
1226 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val);
1227 mt76_clear(dev, MT_ARB_SCR(band),
1228 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1229 }
1230
mt7915_mac_enable_nf(struct mt7915_dev * dev,bool band)1231 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band)
1232 {
1233 u32 reg;
1234
1235 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) :
1236 MT_WF_PHY_RXTD12_MT7916(band);
1237 mt76_set(dev, reg,
1238 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY |
1239 MT_WF_PHY_RXTD12_IRPI_SW_CLR);
1240
1241 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) :
1242 MT_WF_PHY_RX_CTRL1_MT7916(band);
1243 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5));
1244 }
1245
1246 static u8
mt7915_phy_get_nf(struct mt7915_phy * phy,int idx)1247 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx)
1248 {
1249 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1250 struct mt7915_dev *dev = phy->dev;
1251 u32 val, sum = 0, n = 0;
1252 int nss, i;
1253
1254 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) {
1255 u32 reg = is_mt7915(&dev->mt76) ?
1256 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) :
1257 MT_WF_IRPI_NSS_MT7916(idx, nss);
1258
1259 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1260 val = mt76_rr(dev, reg);
1261 sum += val * nf_power[i];
1262 n += val;
1263 }
1264 }
1265
1266 if (!n)
1267 return 0;
1268
1269 return sum / n;
1270 }
1271
mt7915_update_channel(struct mt76_phy * mphy)1272 void mt7915_update_channel(struct mt76_phy *mphy)
1273 {
1274 struct mt7915_phy *phy = mphy->priv;
1275 struct mt76_channel_state *state = mphy->chan_state;
1276 int nf;
1277
1278 mt7915_mcu_get_chan_mib_info(phy, false);
1279
1280 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx);
1281 if (!phy->noise)
1282 phy->noise = nf << 4;
1283 else if (nf)
1284 phy->noise += nf - (phy->noise >> 4);
1285
1286 state->noise = -(phy->noise >> 4);
1287 }
1288
1289 static bool
mt7915_wait_reset_state(struct mt7915_dev * dev,u32 state)1290 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state)
1291 {
1292 bool ret;
1293
1294 ret = wait_event_timeout(dev->reset_wait,
1295 (READ_ONCE(dev->recovery.state) & state),
1296 MT7915_RESET_TIMEOUT);
1297
1298 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1299 return ret;
1300 }
1301
1302 static void
mt7915_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)1303 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1304 {
1305 struct ieee80211_hw *hw = priv;
1306
1307 switch (vif->type) {
1308 case NL80211_IFTYPE_MESH_POINT:
1309 case NL80211_IFTYPE_ADHOC:
1310 case NL80211_IFTYPE_AP:
1311 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon,
1312 BSS_CHANGED_BEACON_ENABLED);
1313 break;
1314 default:
1315 break;
1316 }
1317 }
1318
1319 static void
mt7915_update_beacons(struct mt7915_dev * dev)1320 mt7915_update_beacons(struct mt7915_dev *dev)
1321 {
1322 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1];
1323
1324 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1325 IEEE80211_IFACE_ITER_RESUME_ALL,
1326 mt7915_update_vif_beacon, dev->mt76.hw);
1327
1328 if (!mphy_ext)
1329 return;
1330
1331 ieee80211_iterate_active_interfaces(mphy_ext->hw,
1332 IEEE80211_IFACE_ITER_RESUME_ALL,
1333 mt7915_update_vif_beacon, mphy_ext->hw);
1334 }
1335
1336 static int
mt7915_mac_restart(struct mt7915_dev * dev)1337 mt7915_mac_restart(struct mt7915_dev *dev)
1338 {
1339 struct mt7915_phy *phy2;
1340 struct mt76_phy *ext_phy;
1341 struct mt76_dev *mdev = &dev->mt76;
1342 int i, ret;
1343
1344 ext_phy = dev->mt76.phys[MT_BAND1];
1345 phy2 = ext_phy ? ext_phy->priv : NULL;
1346
1347 if (dev->hif2) {
1348 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0);
1349 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0);
1350 }
1351
1352 if (dev_is_pci(mdev->dev)) {
1353 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
1354 if (dev->hif2) {
1355 if (is_mt7915(mdev))
1356 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0);
1357 else
1358 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0x0);
1359 }
1360 }
1361
1362 set_bit(MT76_RESET, &dev->mphy.state);
1363 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1364 wake_up(&dev->mt76.mcu.wait);
1365 if (ext_phy)
1366 set_bit(MT76_RESET, &ext_phy->state);
1367
1368 /* lock/unlock all queues to ensure that no tx is pending */
1369 mt76_txq_schedule_all(&dev->mphy);
1370 if (ext_phy)
1371 mt76_txq_schedule_all(ext_phy);
1372
1373 /* disable all tx/rx napi */
1374 mt76_worker_disable(&dev->mt76.tx_worker);
1375 mt76_for_each_q_rx(mdev, i) {
1376 if (mdev->q_rx[i].ndesc)
1377 napi_disable(&dev->mt76.napi[i]);
1378 }
1379 napi_disable(&dev->mt76.tx_napi);
1380
1381 /* token reinit */
1382 mt76_connac2_tx_token_put(&dev->mt76);
1383 idr_init(&dev->mt76.token);
1384
1385 mt7915_dma_reset(dev, true);
1386
1387 mt76_for_each_q_rx(mdev, i) {
1388 if (mdev->q_rx[i].ndesc) {
1389 napi_enable(&dev->mt76.napi[i]);
1390 }
1391 }
1392
1393 local_bh_disable();
1394 mt76_for_each_q_rx(mdev, i) {
1395 if (mdev->q_rx[i].ndesc) {
1396 napi_schedule(&dev->mt76.napi[i]);
1397 }
1398 }
1399 local_bh_enable();
1400 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1401 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
1402
1403 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask);
1404 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
1405
1406 if (dev->hif2) {
1407 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask);
1408 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0);
1409 }
1410 if (dev_is_pci(mdev->dev)) {
1411 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
1412 if (dev->hif2) {
1413 mt76_wr(dev, MT_PCIE_RECOG_ID,
1414 dev->hif2->index | MT_PCIE_RECOG_ID_SEM);
1415 if (is_mt7915(mdev))
1416 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff);
1417 else
1418 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0xff);
1419 }
1420 }
1421
1422 /* load firmware */
1423 ret = mt7915_mcu_init_firmware(dev);
1424 if (ret)
1425 goto out;
1426
1427 /* set the necessary init items */
1428 ret = mt7915_mcu_set_eeprom(dev);
1429 if (ret)
1430 goto out;
1431
1432 mt7915_mac_init(dev);
1433 mt7915_init_txpower(&dev->phy);
1434 mt7915_init_txpower(phy2);
1435 ret = mt7915_txbf_init(dev);
1436
1437 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) {
1438 ret = mt7915_run(dev->mphy.hw);
1439 if (ret)
1440 goto out;
1441 }
1442
1443 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) {
1444 ret = mt7915_run(ext_phy->hw);
1445 if (ret)
1446 goto out;
1447 }
1448
1449 out:
1450 /* reset done */
1451 clear_bit(MT76_RESET, &dev->mphy.state);
1452 if (phy2)
1453 clear_bit(MT76_RESET, &phy2->mt76->state);
1454
1455 napi_enable(&dev->mt76.tx_napi);
1456
1457 local_bh_disable();
1458 napi_schedule(&dev->mt76.tx_napi);
1459 local_bh_enable();
1460
1461 mt76_worker_enable(&dev->mt76.tx_worker);
1462
1463 return ret;
1464 }
1465
1466 static void
mt7915_mac_full_reset(struct mt7915_dev * dev)1467 mt7915_mac_full_reset(struct mt7915_dev *dev)
1468 {
1469 struct mt76_phy *ext_phy;
1470 struct mt7915_phy *phy2;
1471 int i;
1472
1473 ext_phy = dev->mt76.phys[MT_BAND1];
1474 phy2 = ext_phy ? ext_phy->priv : NULL;
1475
1476 dev->recovery.hw_full_reset = true;
1477
1478 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1479 wake_up(&dev->mt76.mcu.wait);
1480 ieee80211_stop_queues(mt76_hw(dev));
1481 if (ext_phy)
1482 ieee80211_stop_queues(ext_phy->hw);
1483
1484 cancel_delayed_work_sync(&dev->mphy.mac_work);
1485 if (ext_phy)
1486 cancel_delayed_work_sync(&ext_phy->mac_work);
1487
1488 mt76_abort_scan(&dev->mt76);
1489
1490 mutex_lock(&dev->mt76.mutex);
1491 for (i = 0; i < 10; i++) {
1492 if (!mt7915_mac_restart(dev))
1493 break;
1494 }
1495
1496 if (i == 10)
1497 dev_err(dev->mt76.dev, "chip full reset failed\n");
1498
1499 dev->phy.omac_mask = 0;
1500 if (phy2)
1501 phy2->omac_mask = 0;
1502
1503 mt76_reset_device(&dev->mt76);
1504
1505 INIT_LIST_HEAD(&dev->sta_rc_list);
1506 INIT_LIST_HEAD(&dev->twt_list);
1507
1508 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
1509 dev->mt76.global_wcid.idx = i;
1510 dev->recovery.hw_full_reset = false;
1511
1512 mutex_unlock(&dev->mt76.mutex);
1513
1514 ieee80211_restart_hw(mt76_hw(dev));
1515 if (ext_phy)
1516 ieee80211_restart_hw(ext_phy->hw);
1517 }
1518
1519 /* system error recovery */
mt7915_mac_reset_work(struct work_struct * work)1520 void mt7915_mac_reset_work(struct work_struct *work)
1521 {
1522 struct mt7915_phy *phy2;
1523 struct mt76_phy *ext_phy;
1524 struct mt7915_dev *dev;
1525 int i;
1526
1527 dev = container_of(work, struct mt7915_dev, reset_work);
1528 ext_phy = dev->mt76.phys[MT_BAND1];
1529 phy2 = ext_phy ? ext_phy->priv : NULL;
1530
1531 /* chip full reset */
1532 if (dev->recovery.restart) {
1533 /* disable WA/WM WDT */
1534 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA,
1535 MT_MCU_CMD_WDT_MASK);
1536
1537 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT)
1538 dev->recovery.wa_reset_count++;
1539 else
1540 dev->recovery.wm_reset_count++;
1541
1542 mt7915_mac_full_reset(dev);
1543
1544 /* enable mcu irq */
1545 mt7915_irq_enable(dev, MT_INT_MCU_CMD);
1546 mt7915_irq_disable(dev, 0);
1547
1548 /* enable WA/WM WDT */
1549 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK);
1550
1551 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE;
1552 dev->recovery.restart = false;
1553 return;
1554 }
1555
1556 /* chip partial reset */
1557 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA))
1558 return;
1559
1560 ieee80211_stop_queues(mt76_hw(dev));
1561 if (ext_phy)
1562 ieee80211_stop_queues(ext_phy->hw);
1563
1564 set_bit(MT76_RESET, &dev->mphy.state);
1565 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1566 wake_up(&dev->mt76.mcu.wait);
1567 cancel_delayed_work_sync(&dev->mphy.mac_work);
1568 if (phy2) {
1569 set_bit(MT76_RESET, &phy2->mt76->state);
1570 cancel_delayed_work_sync(&phy2->mt76->mac_work);
1571 }
1572
1573 mutex_lock(&dev->mt76.mutex);
1574
1575 mt76_worker_disable(&dev->mt76.tx_worker);
1576 mt76_for_each_q_rx(&dev->mt76, i)
1577 napi_disable(&dev->mt76.napi[i]);
1578 napi_disable(&dev->mt76.tx_napi);
1579
1580
1581 if (mtk_wed_device_active(&dev->mt76.mmio.wed))
1582 mtk_wed_device_stop(&dev->mt76.mmio.wed);
1583
1584 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
1585
1586 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1587 mt7915_dma_reset(dev, false);
1588
1589 mt76_connac2_tx_token_put(&dev->mt76);
1590 idr_init(&dev->mt76.token);
1591
1592 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
1593 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1594 }
1595
1596 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1597 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1598
1599 /* enable DMA Tx/Rx and interrupt */
1600 mt7915_dma_start(dev, false, false);
1601
1602 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1603 clear_bit(MT76_RESET, &dev->mphy.state);
1604 if (phy2)
1605 clear_bit(MT76_RESET, &phy2->mt76->state);
1606
1607 mt76_for_each_q_rx(&dev->mt76, i) {
1608 napi_enable(&dev->mt76.napi[i]);
1609 }
1610
1611 local_bh_disable();
1612 mt76_for_each_q_rx(&dev->mt76, i) {
1613 napi_schedule(&dev->mt76.napi[i]);
1614 }
1615 local_bh_enable();
1616
1617 tasklet_schedule(&dev->mt76.irq_tasklet);
1618
1619 mt76_worker_enable(&dev->mt76.tx_worker);
1620
1621 napi_enable(&dev->mt76.tx_napi);
1622 local_bh_disable();
1623 napi_schedule(&dev->mt76.tx_napi);
1624 local_bh_enable();
1625
1626 ieee80211_wake_queues(mt76_hw(dev));
1627 if (ext_phy)
1628 ieee80211_wake_queues(ext_phy->hw);
1629
1630 mutex_unlock(&dev->mt76.mutex);
1631
1632 mt7915_update_beacons(dev);
1633
1634 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1635 MT7915_WATCHDOG_TIME);
1636 if (phy2)
1637 ieee80211_queue_delayed_work(ext_phy->hw,
1638 &phy2->mt76->mac_work,
1639 MT7915_WATCHDOG_TIME);
1640 }
1641
1642 /* firmware coredump */
mt7915_mac_dump_work(struct work_struct * work)1643 void mt7915_mac_dump_work(struct work_struct *work)
1644 {
1645 const struct mt7915_mem_region *mem_region;
1646 struct mt7915_crash_data *crash_data;
1647 struct mt7915_dev *dev;
1648 struct mt7915_mem_hdr *hdr;
1649 size_t buf_len;
1650 int i;
1651 u32 num;
1652 u8 *buf;
1653
1654 dev = container_of(work, struct mt7915_dev, dump_work);
1655
1656 mutex_lock(&dev->dump_mutex);
1657
1658 crash_data = mt7915_coredump_new(dev);
1659 if (!crash_data) {
1660 mutex_unlock(&dev->dump_mutex);
1661 goto skip_coredump;
1662 }
1663
1664 mem_region = mt7915_coredump_get_mem_layout(dev, &num);
1665 if (!mem_region || !crash_data->memdump_buf_len) {
1666 mutex_unlock(&dev->dump_mutex);
1667 goto skip_memdump;
1668 }
1669
1670 buf = crash_data->memdump_buf;
1671 buf_len = crash_data->memdump_buf_len;
1672
1673 /* dumping memory content... */
1674 memset(buf, 0, buf_len);
1675 for (i = 0; i < num; i++) {
1676 if (mem_region->len > buf_len) {
1677 dev_warn(dev->mt76.dev, "%s len %lu is too large\n",
1678 mem_region->name,
1679 (unsigned long)mem_region->len);
1680 break;
1681 }
1682
1683 /* reserve space for the header */
1684 hdr = (void *)buf;
1685 buf += sizeof(*hdr);
1686 buf_len -= sizeof(*hdr);
1687
1688 mt7915_memcpy_fromio(dev, buf, mem_region->start,
1689 mem_region->len);
1690
1691 hdr->start = mem_region->start;
1692 hdr->len = mem_region->len;
1693
1694 if (!mem_region->len)
1695 /* note: the header remains, just with zero length */
1696 break;
1697
1698 buf += mem_region->len;
1699 buf_len -= mem_region->len;
1700
1701 mem_region++;
1702 }
1703
1704 mutex_unlock(&dev->dump_mutex);
1705
1706 skip_memdump:
1707 mt7915_coredump_submit(dev);
1708 skip_coredump:
1709 queue_work(dev->mt76.wq, &dev->reset_work);
1710 }
1711
mt7915_reset(struct mt7915_dev * dev)1712 void mt7915_reset(struct mt7915_dev *dev)
1713 {
1714 if (!dev->recovery.hw_init_done)
1715 return;
1716
1717 if (dev->recovery.hw_full_reset)
1718 return;
1719
1720 /* wm/wa exception: do full recovery */
1721 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) {
1722 dev->recovery.restart = true;
1723 dev_info(dev->mt76.dev,
1724 "%s indicated firmware crash, attempting recovery\n",
1725 wiphy_name(dev->mt76.hw->wiphy));
1726
1727 mt7915_irq_disable(dev, MT_INT_MCU_CMD);
1728 queue_work(dev->mt76.wq, &dev->dump_work);
1729 return;
1730 }
1731
1732 if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) {
1733 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1734 wake_up(&dev->mt76.mcu.wait);
1735 }
1736
1737 queue_work(dev->mt76.wq, &dev->reset_work);
1738 wake_up(&dev->reset_wait);
1739 }
1740
mt7915_mac_update_stats(struct mt7915_phy * phy)1741 void mt7915_mac_update_stats(struct mt7915_phy *phy)
1742 {
1743 struct mt76_mib_stats *mib = &phy->mib;
1744 struct mt7915_dev *dev = phy->dev;
1745 int i, aggr0 = 0, aggr1, cnt;
1746 u8 band = phy->mt76->band_idx;
1747 u32 val;
1748
1749 cnt = mt76_rr(dev, MT_MIB_SDR3(band));
1750 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ?
1751 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :
1752 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);
1753
1754 cnt = mt76_rr(dev, MT_MIB_SDR4(band));
1755 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt);
1756
1757 cnt = mt76_rr(dev, MT_MIB_SDR5(band));
1758 mib->rx_mpdu_cnt += cnt;
1759
1760 cnt = mt76_rr(dev, MT_MIB_SDR6(band));
1761 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt);
1762
1763 cnt = mt76_rr(dev, MT_MIB_SDR7(band));
1764 mib->rx_vector_mismatch_cnt +=
1765 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt);
1766
1767 cnt = mt76_rr(dev, MT_MIB_SDR8(band));
1768 mib->rx_delimiter_fail_cnt +=
1769 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt);
1770
1771 cnt = mt76_rr(dev, MT_MIB_SDR10(band));
1772 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ?
1773 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) :
1774 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt);
1775
1776 cnt = mt76_rr(dev, MT_MIB_SDR11(band));
1777 mib->rx_len_mismatch_cnt +=
1778 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt);
1779
1780 cnt = mt76_rr(dev, MT_MIB_SDR12(band));
1781 mib->tx_ampdu_cnt += cnt;
1782
1783 cnt = mt76_rr(dev, MT_MIB_SDR13(band));
1784 mib->tx_stop_q_empty_cnt +=
1785 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt);
1786
1787 cnt = mt76_rr(dev, MT_MIB_SDR14(band));
1788 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ?
1789 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) :
1790 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt);
1791
1792 cnt = mt76_rr(dev, MT_MIB_SDR15(band));
1793 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ?
1794 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) :
1795 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt);
1796
1797 cnt = mt76_rr(dev, MT_MIB_SDR16(band));
1798 mib->primary_cca_busy_time +=
1799 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt);
1800
1801 cnt = mt76_rr(dev, MT_MIB_SDR17(band));
1802 mib->secondary_cca_busy_time +=
1803 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt);
1804
1805 cnt = mt76_rr(dev, MT_MIB_SDR18(band));
1806 mib->primary_energy_detect_time +=
1807 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt);
1808
1809 cnt = mt76_rr(dev, MT_MIB_SDR19(band));
1810 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt);
1811
1812 cnt = mt76_rr(dev, MT_MIB_SDR20(band));
1813 mib->ofdm_mdrdy_time +=
1814 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt);
1815
1816 cnt = mt76_rr(dev, MT_MIB_SDR21(band));
1817 mib->green_mdrdy_time +=
1818 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt);
1819
1820 cnt = mt76_rr(dev, MT_MIB_SDR22(band));
1821 mib->rx_ampdu_cnt += cnt;
1822
1823 cnt = mt76_rr(dev, MT_MIB_SDR23(band));
1824 mib->rx_ampdu_bytes_cnt += cnt;
1825
1826 cnt = mt76_rr(dev, MT_MIB_SDR24(band));
1827 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ?
1828 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) :
1829 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt);
1830
1831 cnt = mt76_rr(dev, MT_MIB_SDR25(band));
1832 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt;
1833
1834 cnt = mt76_rr(dev, MT_MIB_SDR27(band));
1835 mib->tx_rwp_fail_cnt +=
1836 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt);
1837
1838 cnt = mt76_rr(dev, MT_MIB_SDR28(band));
1839 mib->tx_rwp_need_cnt +=
1840 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt);
1841
1842 cnt = mt76_rr(dev, MT_MIB_SDR29(band));
1843 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ?
1844 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) :
1845 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt);
1846
1847 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band));
1848 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ?
1849 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) :
1850 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt);
1851
1852 cnt = mt76_rr(dev, MT_MIB_SDR31(band));
1853 mib->rx_ba_cnt += cnt;
1854
1855 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band));
1856 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt);
1857
1858 cnt = mt76_rr(dev, MT_MIB_DR8(band));
1859 mib->tx_mu_mpdu_cnt += cnt;
1860
1861 cnt = mt76_rr(dev, MT_MIB_DR9(band));
1862 mib->tx_mu_acked_mpdu_cnt += cnt;
1863
1864 cnt = mt76_rr(dev, MT_MIB_DR11(band));
1865 mib->tx_su_acked_mpdu_cnt += cnt;
1866
1867 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band));
1868 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt);
1869 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt);
1870 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt);
1871
1872 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
1873 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
1874 mib->tx_amsdu[i] += cnt;
1875 mib->tx_amsdu_cnt += cnt;
1876 }
1877
1878 if (is_mt7915(&dev->mt76)) {
1879 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) {
1880 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4)));
1881 mib->ba_miss_cnt +=
1882 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1883 mib->ack_fail_cnt +=
1884 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1885
1886 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4)));
1887 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1888 mib->rts_retries_cnt +=
1889 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1890
1891 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i));
1892 phy->mt76->aggr_stats[aggr0++] += val & 0xffff;
1893 phy->mt76->aggr_stats[aggr0++] += val >> 16;
1894
1895 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i));
1896 phy->mt76->aggr_stats[aggr1++] += val & 0xffff;
1897 phy->mt76->aggr_stats[aggr1++] += val >> 16;
1898 }
1899
1900 cnt = mt76_rr(dev, MT_MIB_SDR32(band));
1901 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
1902
1903 cnt = mt76_rr(dev, MT_MIB_SDR33(band));
1904 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt);
1905
1906 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band));
1907 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt);
1908 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt);
1909
1910 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band));
1911 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt);
1912 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt);
1913
1914 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band));
1915 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt);
1916 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt);
1917 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt);
1918 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt);
1919 } else {
1920 for (i = 0; i < 2; i++) {
1921 /* rts count */
1922 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2)));
1923 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val);
1924 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val);
1925
1926 /* rts retry count */
1927 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2)));
1928 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val);
1929 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val);
1930
1931 /* ba miss count */
1932 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2)));
1933 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val);
1934 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val);
1935
1936 /* ack fail count */
1937 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2)));
1938 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val);
1939 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val);
1940 }
1941
1942 for (i = 0; i < 8; i++) {
1943 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i));
1944 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val);
1945 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val);
1946 }
1947
1948 cnt = mt76_rr(dev, MT_MIB_SDR32(band));
1949 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
1950 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
1951 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
1952 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
1953
1954 cnt = mt76_rr(dev, MT_MIB_BFCR7(band));
1955 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt);
1956
1957 cnt = mt76_rr(dev, MT_MIB_BFCR2(band));
1958 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt);
1959
1960 cnt = mt76_rr(dev, MT_MIB_BFCR0(band));
1961 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
1962 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
1963 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
1964 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
1965
1966 cnt = mt76_rr(dev, MT_MIB_BFCR1(band));
1967 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
1968 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
1969 }
1970 }
1971
mt7915_mac_severe_check(struct mt7915_phy * phy)1972 static void mt7915_mac_severe_check(struct mt7915_phy *phy)
1973 {
1974 struct mt7915_dev *dev = phy->dev;
1975 u32 trb;
1976
1977 if (!phy->omac_mask)
1978 return;
1979
1980 /* In rare cases, TRB pointers might be out of sync leads to RMAC
1981 * stopping Rx, so check status periodically to see if TRB hardware
1982 * requires minimal recovery.
1983 */
1984 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx));
1985
1986 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) !=
1987 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) &&
1988 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) !=
1989 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) &&
1990 trb == phy->trb_ts)
1991 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT,
1992 phy->mt76->band_idx);
1993
1994 phy->trb_ts = trb;
1995 }
1996
mt7915_mac_sta_rc_work(struct work_struct * work)1997 void mt7915_mac_sta_rc_work(struct work_struct *work)
1998 {
1999 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work);
2000 struct ieee80211_sta *sta;
2001 struct ieee80211_vif *vif;
2002 struct mt7915_sta *msta;
2003 u32 changed;
2004 #if defined(__linux__)
2005 LIST_HEAD(list);
2006 #elif defined(__FreeBSD__)
2007 LINUX_LIST_HEAD(list);
2008 #endif
2009
2010 spin_lock_bh(&dev->mt76.sta_poll_lock);
2011 list_splice_init(&dev->sta_rc_list, &list);
2012
2013 while (!list_empty(&list)) {
2014 msta = list_first_entry(&list, struct mt7915_sta, rc_list);
2015 list_del_init(&msta->rc_list);
2016 changed = msta->changed;
2017 msta->changed = 0;
2018 spin_unlock_bh(&dev->mt76.sta_poll_lock);
2019
2020 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
2021 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
2022
2023 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED |
2024 IEEE80211_RC_NSS_CHANGED |
2025 IEEE80211_RC_BW_CHANGED))
2026 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true);
2027
2028 if (changed & IEEE80211_RC_SMPS_CHANGED)
2029 mt7915_mcu_add_smps(dev, vif, sta);
2030
2031 spin_lock_bh(&dev->mt76.sta_poll_lock);
2032 }
2033
2034 spin_unlock_bh(&dev->mt76.sta_poll_lock);
2035 }
2036
mt7915_mac_work(struct work_struct * work)2037 void mt7915_mac_work(struct work_struct *work)
2038 {
2039 struct mt7915_phy *phy;
2040 struct mt76_phy *mphy;
2041
2042 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
2043 mac_work.work);
2044 phy = mphy->priv;
2045
2046 mutex_lock(&mphy->dev->mutex);
2047
2048 mt76_update_survey(mphy);
2049 if (++mphy->mac_work_count == 5) {
2050 mphy->mac_work_count = 0;
2051
2052 mt7915_mac_update_stats(phy);
2053 mt7915_mac_severe_check(phy);
2054
2055 if (phy->dev->muru_debug)
2056 mt7915_mcu_muru_debug_get(phy);
2057 }
2058
2059 mutex_unlock(&mphy->dev->mutex);
2060
2061 mt76_tx_status_check(mphy->dev, false);
2062
2063 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
2064 MT7915_WATCHDOG_TIME);
2065 }
2066
mt7915_dfs_stop_radar_detector(struct mt7915_phy * phy)2067 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy)
2068 {
2069 struct mt7915_dev *dev = phy->dev;
2070 int rdd_idx = mt7915_get_rdd_idx(phy, false);
2071
2072 if (rdd_idx < 0)
2073 return;
2074
2075 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, rdd_idx, 0, 0);
2076 }
2077
mt7915_dfs_start_rdd(struct mt7915_dev * dev,int rdd_idx)2078 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int rdd_idx)
2079 {
2080 int err, region;
2081
2082 switch (dev->mt76.region) {
2083 case NL80211_DFS_ETSI:
2084 region = 0;
2085 break;
2086 case NL80211_DFS_JP:
2087 region = 2;
2088 break;
2089 case NL80211_DFS_FCC:
2090 default:
2091 region = 1;
2092 break;
2093 }
2094
2095 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, rdd_idx, 0, region);
2096 if (err < 0)
2097 return err;
2098
2099 if (is_mt7915(&dev->mt76)) {
2100 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, rdd_idx,
2101 0, dev->dbdc_support ? 2 : 0);
2102 if (err < 0)
2103 return err;
2104 }
2105
2106 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, rdd_idx, 0, 1);
2107 }
2108
mt7915_dfs_start_radar_detector(struct mt7915_phy * phy)2109 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy)
2110 {
2111 struct mt7915_dev *dev = phy->dev;
2112 int err, rdd_idx;
2113
2114 rdd_idx = mt7915_get_rdd_idx(phy, false);
2115 if (rdd_idx < 0)
2116 return -EINVAL;
2117
2118 /* start CAC */
2119 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, rdd_idx, 0, 0);
2120 if (err < 0)
2121 return err;
2122
2123 err = mt7915_dfs_start_rdd(dev, rdd_idx);
2124 if (err < 0)
2125 return err;
2126
2127 return 0;
2128 }
2129
2130 static int
mt7915_dfs_init_radar_specs(struct mt7915_phy * phy)2131 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy)
2132 {
2133 const struct mt7915_dfs_radar_spec *radar_specs;
2134 struct mt7915_dev *dev = phy->dev;
2135 int err, i;
2136
2137 switch (dev->mt76.region) {
2138 case NL80211_DFS_FCC:
2139 radar_specs = &fcc_radar_specs;
2140 err = mt7915_mcu_set_fcc5_lpn(dev, 8);
2141 if (err < 0)
2142 return err;
2143 break;
2144 case NL80211_DFS_ETSI:
2145 radar_specs = &etsi_radar_specs;
2146 break;
2147 case NL80211_DFS_JP:
2148 radar_specs = &jp_radar_specs;
2149 break;
2150 default:
2151 return -EINVAL;
2152 }
2153
2154 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2155 err = mt7915_mcu_set_radar_th(dev, i,
2156 &radar_specs->radar_pattern[i]);
2157 if (err < 0)
2158 return err;
2159 }
2160
2161 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2162 }
2163
mt7915_dfs_init_radar_detector(struct mt7915_phy * phy)2164 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy)
2165 {
2166 struct mt7915_dev *dev = phy->dev;
2167 enum mt76_dfs_state dfs_state, prev_state;
2168 int err, rdd_idx = mt7915_get_rdd_idx(phy, false);
2169
2170 prev_state = phy->mt76->dfs_state;
2171 dfs_state = mt76_phy_dfs_state(phy->mt76);
2172
2173 if (prev_state == dfs_state || rdd_idx < 0)
2174 return 0;
2175
2176 if (prev_state == MT_DFS_STATE_UNKNOWN)
2177 mt7915_dfs_stop_radar_detector(phy);
2178
2179 if (dfs_state == MT_DFS_STATE_DISABLED)
2180 goto stop;
2181
2182 if (prev_state <= MT_DFS_STATE_DISABLED) {
2183 err = mt7915_dfs_init_radar_specs(phy);
2184 if (err < 0)
2185 return err;
2186
2187 err = mt7915_dfs_start_radar_detector(phy);
2188 if (err < 0)
2189 return err;
2190
2191 phy->mt76->dfs_state = MT_DFS_STATE_CAC;
2192 }
2193
2194 if (dfs_state == MT_DFS_STATE_CAC)
2195 return 0;
2196
2197 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, rdd_idx, 0, 0);
2198 if (err < 0) {
2199 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
2200 return err;
2201 }
2202
2203 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE;
2204 return 0;
2205
2206 stop:
2207 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, rdd_idx, 0, 0);
2208 if (err < 0)
2209 return err;
2210
2211 if (is_mt7915(&dev->mt76)) {
2212 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT,
2213 rdd_idx, 0, dev->dbdc_support ? 2 : 0);
2214 if (err < 0)
2215 return err;
2216 }
2217
2218 mt7915_dfs_stop_radar_detector(phy);
2219 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED;
2220
2221 return 0;
2222 }
2223
2224 static int
mt7915_mac_twt_duration_align(int duration)2225 mt7915_mac_twt_duration_align(int duration)
2226 {
2227 return duration << 8;
2228 }
2229
2230 static u64
mt7915_mac_twt_sched_list_add(struct mt7915_dev * dev,struct mt7915_twt_flow * flow)2231 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev,
2232 struct mt7915_twt_flow *flow)
2233 {
2234 struct mt7915_twt_flow *iter, *iter_next;
2235 u32 duration = flow->duration << 8;
2236 u64 start_tsf;
2237
2238 iter = list_first_entry_or_null(&dev->twt_list,
2239 struct mt7915_twt_flow, list);
2240 if (!iter || !iter->sched || iter->start_tsf > duration) {
2241 /* add flow as first entry in the list */
2242 list_add(&flow->list, &dev->twt_list);
2243 return 0;
2244 }
2245
2246 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) {
2247 start_tsf = iter->start_tsf +
2248 mt7915_mac_twt_duration_align(iter->duration);
2249 if (list_is_last(&iter->list, &dev->twt_list))
2250 break;
2251
2252 if (!iter_next->sched ||
2253 iter_next->start_tsf > start_tsf + duration) {
2254 list_add(&flow->list, &iter->list);
2255 goto out;
2256 }
2257 }
2258
2259 /* add flow as last entry in the list */
2260 list_add_tail(&flow->list, &dev->twt_list);
2261 out:
2262 return start_tsf;
2263 }
2264
mt7915_mac_check_twt_req(struct ieee80211_twt_setup * twt)2265 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt)
2266 {
2267 struct ieee80211_twt_params *twt_agrt;
2268 u64 interval, duration;
2269 u16 mantissa;
2270 u8 exp;
2271
2272 /* only individual agreement supported */
2273 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST)
2274 return -EOPNOTSUPP;
2275
2276 /* only 256us unit supported */
2277 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT)
2278 return -EOPNOTSUPP;
2279
2280 twt_agrt = (struct ieee80211_twt_params *)twt->params;
2281
2282 /* explicit agreement not supported */
2283 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT)))
2284 return -EOPNOTSUPP;
2285
2286 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP,
2287 le16_to_cpu(twt_agrt->req_type));
2288 mantissa = le16_to_cpu(twt_agrt->mantissa);
2289 duration = twt_agrt->min_twt_dur << 8;
2290
2291 interval = (u64)mantissa << exp;
2292 if (interval < duration)
2293 return -EOPNOTSUPP;
2294
2295 return 0;
2296 }
2297
2298 static bool
mt7915_mac_twt_param_equal(struct mt7915_sta * msta,struct ieee80211_twt_params * twt_agrt)2299 mt7915_mac_twt_param_equal(struct mt7915_sta *msta,
2300 struct ieee80211_twt_params *twt_agrt)
2301 {
2302 u16 type = le16_to_cpu(twt_agrt->req_type);
2303 u8 exp;
2304 int i;
2305
2306 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type);
2307 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) {
2308 struct mt7915_twt_flow *f;
2309
2310 if (!(msta->twt.flowid_mask & BIT(i)))
2311 continue;
2312
2313 f = &msta->twt.flow[i];
2314 if (f->duration == twt_agrt->min_twt_dur &&
2315 f->mantissa == twt_agrt->mantissa &&
2316 f->exp == exp &&
2317 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) &&
2318 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) &&
2319 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER))
2320 return true;
2321 }
2322
2323 return false;
2324 }
2325
mt7915_mac_add_twt_setup(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct ieee80211_twt_setup * twt)2326 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,
2327 struct ieee80211_sta *sta,
2328 struct ieee80211_twt_setup *twt)
2329 {
2330 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT;
2331 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
2332 struct ieee80211_twt_params *twt_agrt = (void *)twt->params;
2333 u16 req_type = le16_to_cpu(twt_agrt->req_type);
2334 enum ieee80211_twt_setup_cmd sta_setup_cmd;
2335 struct mt7915_dev *dev = mt7915_hw_dev(hw);
2336 struct mt7915_twt_flow *flow;
2337 int flowid, table_id;
2338 u8 exp;
2339
2340 if (mt7915_mac_check_twt_req(twt))
2341 goto out;
2342
2343 mutex_lock(&dev->mt76.mutex);
2344
2345 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT)
2346 goto unlock;
2347
2348 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow))
2349 goto unlock;
2350
2351 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) {
2352 setup_cmd = TWT_SETUP_CMD_DICTATE;
2353 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR;
2354 goto unlock;
2355 }
2356
2357 flowid = ffs(~msta->twt.flowid_mask) - 1;
2358 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID);
2359 twt_agrt->req_type |= le16_encode_bits(flowid,
2360 IEEE80211_TWT_REQTYPE_FLOWID);
2361
2362 table_id = ffs(~dev->twt.table_mask) - 1;
2363 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type);
2364 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type);
2365
2366 if (mt7915_mac_twt_param_equal(msta, twt_agrt))
2367 goto unlock;
2368
2369 flow = &msta->twt.flow[flowid];
2370 memset(flow, 0, sizeof(*flow));
2371 INIT_LIST_HEAD(&flow->list);
2372 flow->wcid = msta->wcid.idx;
2373 flow->table_id = table_id;
2374 flow->id = flowid;
2375 flow->duration = twt_agrt->min_twt_dur;
2376 flow->mantissa = twt_agrt->mantissa;
2377 flow->exp = exp;
2378 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION);
2379 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE);
2380 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER);
2381
2382 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST ||
2383 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) {
2384 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp;
2385 u64 flow_tsf, curr_tsf;
2386 u32 rem;
2387
2388 flow->sched = true;
2389 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow);
2390 curr_tsf = __mt7915_get_tsf(hw, msta->vif);
2391 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem);
2392 flow_tsf = curr_tsf + interval - rem;
2393 twt_agrt->twt = cpu_to_le64(flow_tsf);
2394 } else {
2395 list_add_tail(&flow->list, &dev->twt_list);
2396 }
2397 flow->tsf = le64_to_cpu(twt_agrt->twt);
2398
2399 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD))
2400 goto unlock;
2401
2402 setup_cmd = TWT_SETUP_CMD_ACCEPT;
2403 dev->twt.table_mask |= BIT(table_id);
2404 msta->twt.flowid_mask |= BIT(flowid);
2405 dev->twt.n_agrt++;
2406
2407 unlock:
2408 mutex_unlock(&dev->mt76.mutex);
2409 out:
2410 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD);
2411 twt_agrt->req_type |=
2412 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD);
2413 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) |
2414 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED);
2415 }
2416
mt7915_mac_twt_teardown_flow(struct mt7915_dev * dev,struct mt7915_sta * msta,u8 flowid)2417 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
2418 struct mt7915_sta *msta,
2419 u8 flowid)
2420 {
2421 struct mt7915_twt_flow *flow;
2422
2423 lockdep_assert_held(&dev->mt76.mutex);
2424
2425 if (flowid >= ARRAY_SIZE(msta->twt.flow))
2426 return;
2427
2428 if (!(msta->twt.flowid_mask & BIT(flowid)))
2429 return;
2430
2431 flow = &msta->twt.flow[flowid];
2432 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow,
2433 MCU_TWT_AGRT_DELETE))
2434 return;
2435
2436 list_del_init(&flow->list);
2437 msta->twt.flowid_mask &= ~BIT(flowid);
2438 dev->twt.table_mask &= ~BIT(flow->table_id);
2439 dev->twt.n_agrt--;
2440 }
2441