1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/aperture.h>
31 #include <linux/acpi.h>
32 #include <linux/device.h>
33 #include <linux/module.h>
34 #include <linux/oom.h>
35 #include <linux/pci.h>
36 #include <linux/pm.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/string_helpers.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_client.h>
45 #include <drm/drm_client_event.h>
46 #include <drm/drm_ioctl.h>
47 #include <drm/drm_managed.h>
48 #include <drm/drm_probe_helper.h>
49
50 #include "display/i9xx_display_sr.h"
51 #include "display/intel_bw.h"
52 #include "display/intel_cdclk.h"
53 #include "display/intel_crtc.h"
54 #include "display/intel_display_core.h"
55 #include "display/intel_display_driver.h"
56 #include "display/intel_dmc.h"
57 #include "display/intel_dp.h"
58 #include "display/intel_dpt.h"
59 #include "display/intel_encoder.h"
60 #include "display/intel_fbdev.h"
61 #include "display/intel_hotplug.h"
62 #include "display/intel_opregion.h"
63 #include "display/intel_overlay.h"
64 #include "display/intel_pch_refclk.h"
65 #include "display/intel_pps.h"
66 #include "display/intel_sbi.h"
67 #include "display/intel_sprite_uapi.h"
68 #include "display/skl_watermark.h"
69
70 #include "gem/i915_gem_context.h"
71 #include "gem/i915_gem_create.h"
72 #include "gem/i915_gem_dmabuf.h"
73 #include "gem/i915_gem_ioctls.h"
74 #include "gem/i915_gem_mman.h"
75 #include "gem/i915_gem_pm.h"
76 #include "gt/intel_gt.h"
77 #include "gt/intel_gt_pm.h"
78 #include "gt/intel_gt_print.h"
79 #include "gt/intel_rc6.h"
80
81 #include "pxp/intel_pxp.h"
82 #include "pxp/intel_pxp_debugfs.h"
83 #include "pxp/intel_pxp_pm.h"
84
85 #include "soc/intel_dram.h"
86 #include "soc/intel_gmch.h"
87
88 #include "i915_debugfs.h"
89 #include "i915_driver.h"
90 #include "i915_drm_client.h"
91 #include "i915_drv.h"
92 #include "i915_file_private.h"
93 #include "i915_getparam.h"
94 #include "i915_hwmon.h"
95 #include "i915_ioc32.h"
96 #include "i915_ioctl.h"
97 #include "i915_irq.h"
98 #include "i915_memcpy.h"
99 #include "i915_perf.h"
100 #include "i915_query.h"
101 #include "i915_reg.h"
102 #include "i915_switcheroo.h"
103 #include "i915_sysfs.h"
104 #include "i915_utils.h"
105 #include "i915_vgpu.h"
106 #include "intel_clock_gating.h"
107 #include "intel_cpu_info.h"
108 #include "intel_gvt.h"
109 #include "intel_memory_region.h"
110 #include "intel_pci_config.h"
111 #include "intel_pcode.h"
112 #include "intel_region_ttm.h"
113 #include "vlv_iosf_sb.h"
114 #include "vlv_suspend.h"
115
116 static const struct drm_driver i915_drm_driver;
117
i915_workqueues_init(struct drm_i915_private * dev_priv)118 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
119 {
120 /*
121 * The i915 workqueue is primarily used for batched retirement of
122 * requests (and thus managing bo) once the task has been completed
123 * by the GPU. i915_retire_requests() is called directly when we
124 * need high-priority retirement, such as waiting for an explicit
125 * bo.
126 *
127 * It is also used for periodic low-priority events, such as
128 * idle-timers and recording error state.
129 *
130 * All tasks on the workqueue are expected to acquire the dev mutex
131 * so there is no point in running more than one instance of the
132 * workqueue at any time. Use an ordered one.
133 */
134 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
135 if (dev_priv->wq == NULL)
136 goto out_err;
137
138 /*
139 * The unordered i915 workqueue should be used for all work
140 * scheduling that do not require running in order, which used
141 * to be scheduled on the system_wq before moving to a driver
142 * instance due deprecation of flush_scheduled_work().
143 */
144 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);
145 if (dev_priv->unordered_wq == NULL)
146 goto out_free_wq;
147
148 return 0;
149
150 out_free_wq:
151 destroy_workqueue(dev_priv->wq);
152 out_err:
153 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
154
155 return -ENOMEM;
156 }
157
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)158 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
159 {
160 destroy_workqueue(dev_priv->unordered_wq);
161 destroy_workqueue(dev_priv->wq);
162 }
163
164 /*
165 * We don't keep the workarounds for pre-production hardware, so we expect our
166 * driver to fail on these machines in one way or another. A little warning on
167 * dmesg may help both the user and the bug triagers.
168 *
169 * Our policy for removing pre-production workarounds is to keep the
170 * current gen workarounds as a guide to the bring-up of the next gen
171 * (workarounds have a habit of persisting!). Anything older than that
172 * should be removed along with the complications they introduce.
173 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)174 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
175 {
176 bool pre = false;
177
178 pre |= IS_HASWELL_EARLY_SDV(dev_priv);
179 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
180 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
181 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
182 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
183 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
184 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
185 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
186 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
187 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
188 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
189
190 if (pre) {
191 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
192 "It may not be fully functional.\n");
193 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
194 }
195 }
196
sanitize_gpu(struct drm_i915_private * i915)197 static void sanitize_gpu(struct drm_i915_private *i915)
198 {
199 if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) {
200 struct intel_gt *gt;
201 unsigned int i;
202
203 for_each_gt(gt, i915, i)
204 intel_gt_reset_all_engines(gt);
205 }
206 }
207
208 /**
209 * i915_driver_early_probe - setup state not requiring device access
210 * @dev_priv: device private
211 *
212 * Initialize everything that is a "SW-only" state, that is state not
213 * requiring accessing the device or exposing the driver via kernel internal
214 * or userspace interfaces. Example steps belonging here: lock initialization,
215 * system memory allocation, setting up device specific attributes and
216 * function hooks not requiring accessing the device.
217 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)218 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
219 {
220 struct intel_display *display = dev_priv->display;
221 int ret = 0;
222
223 if (i915_inject_probe_failure(dev_priv))
224 return -ENODEV;
225
226 intel_device_info_runtime_init_early(dev_priv);
227
228 intel_step_init(dev_priv);
229
230 intel_uncore_mmio_debug_init_early(dev_priv);
231
232 spin_lock_init(&dev_priv->gpu_error.lock);
233
234 intel_sbi_init(display);
235 vlv_iosf_sb_init(dev_priv);
236 mutex_init(&dev_priv->sb_lock);
237
238 i915_memcpy_init_early(dev_priv);
239 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
240
241 ret = i915_workqueues_init(dev_priv);
242 if (ret < 0)
243 return ret;
244
245 ret = vlv_suspend_init(dev_priv);
246 if (ret < 0)
247 goto err_workqueues;
248
249 ret = intel_region_ttm_device_init(dev_priv);
250 if (ret)
251 goto err_ttm;
252
253 ret = intel_root_gt_init_early(dev_priv);
254 if (ret < 0)
255 goto err_rootgt;
256
257 i915_gem_init_early(dev_priv);
258
259 intel_irq_init(dev_priv);
260 intel_display_driver_early_probe(display);
261 intel_clock_gating_hooks_init(dev_priv);
262
263 intel_detect_preproduction_hw(dev_priv);
264
265 return 0;
266
267 err_rootgt:
268 intel_region_ttm_device_fini(dev_priv);
269 err_ttm:
270 vlv_suspend_cleanup(dev_priv);
271 err_workqueues:
272 i915_workqueues_cleanup(dev_priv);
273 return ret;
274 }
275
276 /**
277 * i915_driver_late_release - cleanup the setup done in
278 * i915_driver_early_probe()
279 * @dev_priv: device private
280 */
i915_driver_late_release(struct drm_i915_private * dev_priv)281 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
282 {
283 struct intel_display *display = dev_priv->display;
284
285 intel_irq_fini(dev_priv);
286 intel_power_domains_cleanup(display);
287 i915_gem_cleanup_early(dev_priv);
288 intel_gt_driver_late_release_all(dev_priv);
289 intel_region_ttm_device_fini(dev_priv);
290 vlv_suspend_cleanup(dev_priv);
291 i915_workqueues_cleanup(dev_priv);
292
293 mutex_destroy(&dev_priv->sb_lock);
294 vlv_iosf_sb_fini(dev_priv);
295 intel_sbi_fini(display);
296
297 i915_params_free(&dev_priv->params);
298
299 intel_display_device_remove(display);
300 }
301
302 /**
303 * i915_driver_mmio_probe - setup device MMIO
304 * @dev_priv: device private
305 *
306 * Setup minimal device state necessary for MMIO accesses later in the
307 * initialization sequence. The setup here should avoid any other device-wide
308 * side effects or exposing the driver via kernel internal or user space
309 * interfaces.
310 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)311 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
312 {
313 struct intel_display *display = dev_priv->display;
314 struct intel_gt *gt;
315 int ret, i;
316
317 if (i915_inject_probe_failure(dev_priv))
318 return -ENODEV;
319
320 ret = intel_gmch_bridge_setup(dev_priv);
321 if (ret < 0)
322 return ret;
323
324 for_each_gt(gt, dev_priv, i) {
325 ret = intel_uncore_init_mmio(gt->uncore);
326 if (ret)
327 return ret;
328
329 ret = drmm_add_action_or_reset(&dev_priv->drm,
330 intel_uncore_fini_mmio,
331 gt->uncore);
332 if (ret)
333 return ret;
334 }
335
336 /* Try to make sure MCHBAR is enabled before poking at it */
337 intel_gmch_bar_setup(dev_priv);
338 intel_device_info_runtime_init(dev_priv);
339 intel_display_device_info_runtime_init(display);
340
341 for_each_gt(gt, dev_priv, i) {
342 ret = intel_gt_init_mmio(gt);
343 if (ret)
344 goto err_uncore;
345 }
346
347 /* As early as possible, scrub existing GPU state before clobbering */
348 sanitize_gpu(dev_priv);
349
350 return 0;
351
352 err_uncore:
353 intel_gmch_bar_teardown(dev_priv);
354
355 return ret;
356 }
357
358 /**
359 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
360 * @dev_priv: device private
361 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)362 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
363 {
364 intel_gmch_bar_teardown(dev_priv);
365 }
366
367 /**
368 * i915_set_dma_info - set all relevant PCI dma info as configured for the
369 * platform
370 * @i915: valid i915 instance
371 *
372 * Set the dma max segment size, device and coherent masks. The dma mask set
373 * needs to occur before i915_ggtt_probe_hw.
374 *
375 * A couple of platforms have special needs. Address them as well.
376 *
377 */
i915_set_dma_info(struct drm_i915_private * i915)378 static int i915_set_dma_info(struct drm_i915_private *i915)
379 {
380 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
381 int ret;
382
383 GEM_BUG_ON(!mask_size);
384
385 /*
386 * We don't have a max segment size, so set it to the max so sg's
387 * debugging layer doesn't complain
388 */
389 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
390
391 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
392 if (ret)
393 goto mask_err;
394
395 /* overlay on gen2 is broken and can't address above 1G */
396 if (GRAPHICS_VER(i915) == 2)
397 mask_size = 30;
398
399 /*
400 * 965GM sometimes incorrectly writes to hardware status page (HWS)
401 * using 32bit addressing, overwriting memory if HWS is located
402 * above 4GB.
403 *
404 * The documentation also mentions an issue with undefined
405 * behaviour if any general state is accessed within a page above 4GB,
406 * which also needs to be handled carefully.
407 */
408 if (IS_I965G(i915) || IS_I965GM(i915))
409 mask_size = 32;
410
411 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
412 if (ret)
413 goto mask_err;
414
415 return 0;
416
417 mask_err:
418 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
419 return ret;
420 }
421
422 /* Wa_14022698537:dg2 */
i915_enable_g8(struct drm_i915_private * i915)423 static void i915_enable_g8(struct drm_i915_private *i915)
424 {
425 if (IS_DG2(i915)) {
426 if (IS_DG2_D(i915) && !intel_match_g8_cpu())
427 return;
428
429 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
430 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0);
431 }
432 }
433
i915_pcode_init(struct drm_i915_private * i915)434 static int i915_pcode_init(struct drm_i915_private *i915)
435 {
436 struct intel_gt *gt;
437 int id, ret;
438
439 for_each_gt(gt, i915, id) {
440 ret = intel_pcode_init(gt->uncore);
441 if (ret) {
442 gt_err(gt, "intel_pcode_init failed %d\n", ret);
443 return ret;
444 }
445 }
446
447 i915_enable_g8(i915);
448 return 0;
449 }
450
451 /**
452 * i915_driver_hw_probe - setup state requiring device access
453 * @dev_priv: device private
454 *
455 * Setup state that requires accessing the device, but doesn't require
456 * exposing the driver via kernel internal or userspace interfaces.
457 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)458 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
459 {
460 struct intel_display *display = dev_priv->display;
461 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
462 int ret;
463
464 if (i915_inject_probe_failure(dev_priv))
465 return -ENODEV;
466
467 if (HAS_PPGTT(dev_priv)) {
468 if (intel_vgpu_active(dev_priv) &&
469 !intel_vgpu_has_full_ppgtt(dev_priv)) {
470 drm_err(&dev_priv->drm,
471 "incompatible vGPU found, support for isolated ppGTT required\n");
472 return -ENXIO;
473 }
474 }
475
476 if (HAS_EXECLISTS(dev_priv)) {
477 /*
478 * Older GVT emulation depends upon intercepting CSB mmio,
479 * which we no longer use, preferring to use the HWSP cache
480 * instead.
481 */
482 if (intel_vgpu_active(dev_priv) &&
483 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
484 drm_err(&dev_priv->drm,
485 "old vGPU host found, support for HWSP emulation required\n");
486 return -ENXIO;
487 }
488 }
489
490 /* needs to be done before ggtt probe */
491 intel_dram_edram_detect(dev_priv);
492
493 ret = i915_set_dma_info(dev_priv);
494 if (ret)
495 return ret;
496
497 ret = i915_perf_init(dev_priv);
498 if (ret)
499 return ret;
500
501 ret = i915_ggtt_probe_hw(dev_priv);
502 if (ret)
503 goto err_perf;
504
505 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name);
506 if (ret)
507 goto err_ggtt;
508
509 ret = i915_ggtt_init_hw(dev_priv);
510 if (ret)
511 goto err_ggtt;
512
513 /*
514 * Make sure we probe lmem before we probe stolen-lmem. The BAR size
515 * might be different due to bar resizing.
516 */
517 ret = intel_gt_tiles_init(dev_priv);
518 if (ret)
519 goto err_ggtt;
520
521 ret = intel_memory_regions_hw_probe(dev_priv);
522 if (ret)
523 goto err_ggtt;
524
525 ret = i915_ggtt_enable_hw(dev_priv);
526 if (ret) {
527 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
528 goto err_mem_regions;
529 }
530
531 pci_set_master(pdev);
532
533 /* On the 945G/GM, the chipset reports the MSI capability on the
534 * integrated graphics even though the support isn't actually there
535 * according to the published specs. It doesn't appear to function
536 * correctly in testing on 945G.
537 * This may be a side effect of MSI having been made available for PEG
538 * and the registers being closely associated.
539 *
540 * According to chipset errata, on the 965GM, MSI interrupts may
541 * be lost or delayed, and was defeatured. MSI interrupts seem to
542 * get lost on g4x as well, and interrupt delivery seems to stay
543 * properly dead afterwards. So we'll just disable them for all
544 * pre-gen5 chipsets.
545 *
546 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
547 * interrupts even when in MSI mode. This results in spurious
548 * interrupt warnings if the legacy irq no. is shared with another
549 * device. The kernel then disables that interrupt source and so
550 * prevents the other device from working properly.
551 */
552 if (GRAPHICS_VER(dev_priv) >= 5) {
553 if (pci_enable_msi(pdev) < 0)
554 drm_dbg(&dev_priv->drm, "can't enable MSI");
555 }
556
557 ret = intel_gvt_init(dev_priv);
558 if (ret)
559 goto err_msi;
560
561 intel_opregion_setup(display);
562
563 ret = i915_pcode_init(dev_priv);
564 if (ret)
565 goto err_opregion;
566
567 /*
568 * Fill the dram structure to get the system dram info. This will be
569 * used for memory latency calculation.
570 */
571 ret = intel_dram_detect(dev_priv);
572 if (ret)
573 goto err_opregion;
574
575 intel_bw_init_hw(display);
576
577 return 0;
578
579 err_opregion:
580 intel_opregion_cleanup(display);
581 err_msi:
582 if (pdev->msi_enabled)
583 pci_disable_msi(pdev);
584 err_mem_regions:
585 intel_memory_regions_driver_release(dev_priv);
586 err_ggtt:
587 i915_ggtt_driver_release(dev_priv);
588 i915_gem_drain_freed_objects(dev_priv);
589 i915_ggtt_driver_late_release(dev_priv);
590 err_perf:
591 i915_perf_fini(dev_priv);
592 return ret;
593 }
594
595 /**
596 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
597 * @dev_priv: device private
598 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)599 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
600 {
601 struct intel_display *display = dev_priv->display;
602 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
603
604 i915_perf_fini(dev_priv);
605
606 intel_opregion_cleanup(display);
607
608 if (pdev->msi_enabled)
609 pci_disable_msi(pdev);
610 }
611
612 /**
613 * i915_driver_register - register the driver with the rest of the system
614 * @dev_priv: device private
615 *
616 * Perform any steps necessary to make the driver available via kernel
617 * internal or userspace interfaces.
618 */
i915_driver_register(struct drm_i915_private * dev_priv)619 static int i915_driver_register(struct drm_i915_private *dev_priv)
620 {
621 struct intel_display *display = dev_priv->display;
622 struct intel_gt *gt;
623 unsigned int i;
624 int ret;
625
626 i915_gem_driver_register(dev_priv);
627 i915_pmu_register(dev_priv);
628
629 intel_vgpu_register(dev_priv);
630
631 /* Reveal our presence to userspace */
632 ret = drm_dev_register(&dev_priv->drm, 0);
633 if (ret) {
634 i915_probe_error(dev_priv,
635 "Failed to register driver for userspace access!\n");
636 drm_dev_unregister(&dev_priv->drm);
637 i915_pmu_unregister(dev_priv);
638 i915_gem_driver_unregister(dev_priv);
639 return ret;
640 }
641
642 i915_debugfs_register(dev_priv);
643 i915_setup_sysfs(dev_priv);
644
645 /* Depends on sysfs having been initialized */
646 i915_perf_register(dev_priv);
647
648 for_each_gt(gt, dev_priv, i)
649 intel_gt_driver_register(gt);
650
651 intel_pxp_debugfs_register(dev_priv->pxp);
652
653 i915_hwmon_register(dev_priv);
654
655 intel_display_driver_register(display);
656
657 intel_power_domains_enable(display);
658 intel_runtime_pm_enable(&dev_priv->runtime_pm);
659
660 if (i915_switcheroo_register(dev_priv))
661 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
662
663 return 0;
664 }
665
666 /**
667 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
668 * @dev_priv: device private
669 */
i915_driver_unregister(struct drm_i915_private * dev_priv)670 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
671 {
672 struct intel_display *display = dev_priv->display;
673 struct intel_gt *gt;
674 unsigned int i;
675
676 i915_switcheroo_unregister(dev_priv);
677
678 intel_runtime_pm_disable(&dev_priv->runtime_pm);
679 intel_power_domains_disable(display);
680
681 intel_display_driver_unregister(display);
682
683 intel_pxp_fini(dev_priv);
684
685 for_each_gt(gt, dev_priv, i)
686 intel_gt_driver_unregister(gt);
687
688 i915_hwmon_unregister(dev_priv);
689
690 i915_perf_unregister(dev_priv);
691 i915_pmu_unregister(dev_priv);
692
693 i915_teardown_sysfs(dev_priv);
694 drm_dev_unplug(&dev_priv->drm);
695
696 i915_gem_driver_unregister(dev_priv);
697 }
698
699 void
i915_print_iommu_status(struct drm_i915_private * i915,struct drm_printer * p)700 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
701 {
702 drm_printf(p, "iommu: %s\n",
703 str_enabled_disabled(i915_vtd_active(i915)));
704 }
705
i915_welcome_messages(struct drm_i915_private * dev_priv)706 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
707 {
708 if (drm_debug_enabled(DRM_UT_DRIVER)) {
709 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER,
710 "device info:");
711 struct intel_gt *gt;
712 unsigned int i;
713
714 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
715 INTEL_DEVID(dev_priv),
716 INTEL_REVID(dev_priv),
717 intel_platform_name(INTEL_INFO(dev_priv)->platform),
718 intel_subplatform(RUNTIME_INFO(dev_priv),
719 INTEL_INFO(dev_priv)->platform),
720 GRAPHICS_VER(dev_priv));
721
722 intel_device_info_print(INTEL_INFO(dev_priv),
723 RUNTIME_INFO(dev_priv), &p);
724 i915_print_iommu_status(dev_priv, &p);
725 for_each_gt(gt, dev_priv, i)
726 intel_gt_info_print(>->info, &p);
727 }
728
729 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
730 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
731 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
732 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
733 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
734 drm_info(&dev_priv->drm,
735 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
736 }
737
738 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)739 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
740 {
741 const struct intel_device_info *match_info =
742 (struct intel_device_info *)ent->driver_data;
743 struct drm_i915_private *i915;
744 struct intel_display *display;
745
746 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
747 struct drm_i915_private, drm);
748 if (IS_ERR(i915))
749 return i915;
750
751 pci_set_drvdata(pdev, &i915->drm);
752
753 /* Device parameters start as a copy of module parameters. */
754 i915_params_copy(&i915->params, &i915_modparams);
755
756 /* Set up device info and initial runtime info. */
757 intel_device_info_driver_create(i915, pdev->device, match_info);
758
759 display = intel_display_device_probe(pdev);
760 if (IS_ERR(display))
761 return ERR_CAST(display);
762
763 i915->display = display;
764
765 return i915;
766 }
767
768 /**
769 * i915_driver_probe - setup chip and create an initial config
770 * @pdev: PCI device
771 * @ent: matching PCI ID entry
772 *
773 * The driver probe routine has to do several things:
774 * - drive output discovery via intel_display_driver_probe()
775 * - initialize the memory manager
776 * - allocate initial config memory
777 * - setup the DRM framebuffer with the allocated memory
778 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)779 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
780 {
781 struct drm_i915_private *i915;
782 struct intel_display *display;
783 int ret;
784
785 ret = pci_enable_device(pdev);
786 if (ret) {
787 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
788 return ret;
789 }
790
791 i915 = i915_driver_create(pdev, ent);
792 if (IS_ERR(i915)) {
793 pci_disable_device(pdev);
794 return PTR_ERR(i915);
795 }
796
797 display = i915->display;
798
799 ret = i915_driver_early_probe(i915);
800 if (ret < 0)
801 goto out_pci_disable;
802
803 disable_rpm_wakeref_asserts(&i915->runtime_pm);
804
805 intel_vgpu_detect(i915);
806
807 ret = intel_gt_probe_all(i915);
808 if (ret < 0)
809 goto out_runtime_pm_put;
810
811 ret = i915_driver_mmio_probe(i915);
812 if (ret < 0)
813 goto out_runtime_pm_put;
814
815 ret = i915_driver_hw_probe(i915);
816 if (ret < 0)
817 goto out_cleanup_mmio;
818
819 ret = intel_display_driver_probe_noirq(display);
820 if (ret < 0)
821 goto out_cleanup_hw;
822
823 ret = intel_irq_install(i915);
824 if (ret)
825 goto out_cleanup_modeset;
826
827 ret = intel_display_driver_probe_nogem(display);
828 if (ret)
829 goto out_cleanup_irq;
830
831 ret = i915_gem_init(i915);
832 if (ret)
833 goto out_cleanup_modeset2;
834
835 ret = intel_pxp_init(i915);
836 if (ret && ret != -ENODEV)
837 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);
838
839 ret = intel_display_driver_probe(display);
840 if (ret)
841 goto out_cleanup_gem;
842
843 ret = i915_driver_register(i915);
844 if (ret)
845 goto out_cleanup_gem;
846
847 enable_rpm_wakeref_asserts(&i915->runtime_pm);
848
849 i915_welcome_messages(i915);
850
851 i915->do_release = true;
852
853 return 0;
854
855 out_cleanup_gem:
856 intel_pxp_fini(i915);
857 i915_gem_suspend(i915);
858 i915_gem_driver_remove(i915);
859 i915_gem_driver_release(i915);
860 out_cleanup_modeset2:
861 /* FIXME clean up the error path */
862 intel_display_driver_remove(display);
863 intel_irq_uninstall(i915);
864 intel_display_driver_remove_noirq(display);
865 goto out_cleanup_modeset;
866 out_cleanup_irq:
867 intel_irq_uninstall(i915);
868 out_cleanup_modeset:
869 intel_display_driver_remove_nogem(display);
870 out_cleanup_hw:
871 i915_driver_hw_remove(i915);
872 intel_memory_regions_driver_release(i915);
873 i915_ggtt_driver_release(i915);
874 i915_gem_drain_freed_objects(i915);
875 i915_ggtt_driver_late_release(i915);
876 out_cleanup_mmio:
877 i915_driver_mmio_release(i915);
878 out_runtime_pm_put:
879 enable_rpm_wakeref_asserts(&i915->runtime_pm);
880 i915_driver_late_release(i915);
881 out_pci_disable:
882 pci_disable_device(pdev);
883 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
884 return ret;
885 }
886
i915_driver_remove(struct drm_i915_private * i915)887 void i915_driver_remove(struct drm_i915_private *i915)
888 {
889 struct intel_display *display = i915->display;
890 intel_wakeref_t wakeref;
891
892 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
893
894 i915_driver_unregister(i915);
895
896 /* Flush any external code that still may be under the RCU lock */
897 synchronize_rcu();
898
899 i915_gem_suspend(i915);
900
901 intel_gvt_driver_remove(i915);
902
903 intel_display_driver_remove(display);
904
905 intel_irq_uninstall(i915);
906
907 intel_display_driver_remove_noirq(display);
908
909 i915_reset_error_state(i915);
910 i915_gem_driver_remove(i915);
911
912 intel_display_driver_remove_nogem(display);
913
914 i915_driver_hw_remove(i915);
915
916 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
917 }
918
i915_driver_release(struct drm_device * dev)919 static void i915_driver_release(struct drm_device *dev)
920 {
921 struct drm_i915_private *dev_priv = to_i915(dev);
922 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
923 intel_wakeref_t wakeref;
924
925 if (!dev_priv->do_release)
926 return;
927
928 wakeref = intel_runtime_pm_get(rpm);
929
930 i915_gem_driver_release(dev_priv);
931
932 intel_memory_regions_driver_release(dev_priv);
933 i915_ggtt_driver_release(dev_priv);
934 i915_gem_drain_freed_objects(dev_priv);
935 i915_ggtt_driver_late_release(dev_priv);
936
937 i915_driver_mmio_release(dev_priv);
938
939 intel_runtime_pm_put(rpm, wakeref);
940
941 intel_runtime_pm_driver_release(rpm);
942
943 i915_driver_late_release(dev_priv);
944 }
945
i915_driver_open(struct drm_device * dev,struct drm_file * file)946 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
947 {
948 struct drm_i915_private *i915 = to_i915(dev);
949 int ret;
950
951 ret = i915_gem_open(i915, file);
952 if (ret)
953 return ret;
954
955 return 0;
956 }
957
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)958 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
959 {
960 struct drm_i915_file_private *file_priv = file->driver_priv;
961
962 i915_gem_context_close(file);
963 i915_drm_client_put(file_priv->client);
964
965 kfree_rcu(file_priv, rcu);
966
967 /* Catch up with all the deferred frees from "this" client */
968 i915_gem_flush_free_objects(to_i915(dev));
969 }
970
i915_driver_shutdown(struct drm_i915_private * i915)971 void i915_driver_shutdown(struct drm_i915_private *i915)
972 {
973 struct intel_display *display = i915->display;
974
975 disable_rpm_wakeref_asserts(&i915->runtime_pm);
976 intel_runtime_pm_disable(&i915->runtime_pm);
977 intel_power_domains_disable(display);
978
979 drm_client_dev_suspend(&i915->drm, false);
980 if (HAS_DISPLAY(i915)) {
981 drm_kms_helper_poll_disable(&i915->drm);
982 intel_display_driver_disable_user_access(display);
983
984 drm_atomic_helper_shutdown(&i915->drm);
985 }
986
987 intel_dp_mst_suspend(display);
988
989 intel_irq_suspend(i915);
990 intel_hpd_cancel_work(display);
991
992 if (HAS_DISPLAY(i915))
993 intel_display_driver_suspend_access(display);
994
995 intel_encoder_suspend_all(display);
996 intel_encoder_shutdown_all(display);
997
998 intel_dmc_suspend(display);
999
1000 i915_gem_suspend(i915);
1001
1002 /*
1003 * The only requirement is to reboot with display DC states disabled,
1004 * for now leaving all display power wells in the INIT power domain
1005 * enabled.
1006 *
1007 * TODO:
1008 * - unify the pci_driver::shutdown sequence here with the
1009 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1010 * - unify the driver remove and system/runtime suspend sequences with
1011 * the above unified shutdown/poweroff sequence.
1012 */
1013 intel_power_domains_driver_remove(display);
1014 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1015
1016 intel_runtime_pm_driver_last_release(&i915->runtime_pm);
1017 }
1018
suspend_to_idle(struct drm_i915_private * dev_priv)1019 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1020 {
1021 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1022 if (acpi_target_system_state() < ACPI_STATE_S3)
1023 return true;
1024 #endif
1025 return false;
1026 }
1027
i915_drm_complete(struct drm_device * dev)1028 static void i915_drm_complete(struct drm_device *dev)
1029 {
1030 struct drm_i915_private *i915 = to_i915(dev);
1031
1032 intel_pxp_resume_complete(i915->pxp);
1033 }
1034
i915_drm_prepare(struct drm_device * dev)1035 static int i915_drm_prepare(struct drm_device *dev)
1036 {
1037 struct drm_i915_private *i915 = to_i915(dev);
1038
1039 intel_pxp_suspend_prepare(i915->pxp);
1040
1041 /*
1042 * NB intel_display_driver_suspend() may issue new requests after we've
1043 * ostensibly marked the GPU as ready-to-sleep here. We need to
1044 * split out that work and pull it forward so that after point,
1045 * the GPU is not woken again.
1046 */
1047 return i915_gem_backup_suspend(i915);
1048 }
1049
i915_drm_suspend(struct drm_device * dev)1050 static int i915_drm_suspend(struct drm_device *dev)
1051 {
1052 struct drm_i915_private *dev_priv = to_i915(dev);
1053 struct intel_display *display = dev_priv->display;
1054 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1055 pci_power_t opregion_target_state;
1056
1057 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1058
1059 /* We do a lot of poking in a lot of registers, make sure they work
1060 * properly. */
1061 intel_power_domains_disable(display);
1062 drm_client_dev_suspend(dev, false);
1063 if (HAS_DISPLAY(dev_priv)) {
1064 drm_kms_helper_poll_disable(dev);
1065 intel_display_driver_disable_user_access(display);
1066 }
1067
1068 pci_save_state(pdev);
1069
1070 intel_display_driver_suspend(display);
1071
1072 intel_irq_suspend(dev_priv);
1073 intel_hpd_cancel_work(display);
1074
1075 if (HAS_DISPLAY(dev_priv))
1076 intel_display_driver_suspend_access(display);
1077
1078 intel_encoder_suspend_all(display);
1079
1080 /* Must be called before GGTT is suspended. */
1081 intel_dpt_suspend(display);
1082 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1083
1084 i9xx_display_sr_save(display);
1085
1086 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1087 intel_opregion_suspend(display, opregion_target_state);
1088
1089 dev_priv->suspend_count++;
1090
1091 intel_dmc_suspend(display);
1092
1093 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1094
1095 i915_gem_drain_freed_objects(dev_priv);
1096
1097 return 0;
1098 }
1099
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1100 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1101 {
1102 struct drm_i915_private *dev_priv = to_i915(dev);
1103 struct intel_display *display = dev_priv->display;
1104 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1105 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1106 struct intel_gt *gt;
1107 int ret, i;
1108 bool s2idle = !hibernation && suspend_to_idle(dev_priv);
1109
1110 disable_rpm_wakeref_asserts(rpm);
1111
1112 intel_pxp_suspend(dev_priv->pxp);
1113
1114 i915_gem_suspend_late(dev_priv);
1115
1116 for_each_gt(gt, dev_priv, i)
1117 intel_uncore_suspend(gt->uncore);
1118
1119 intel_display_power_suspend_late(display, s2idle);
1120
1121 ret = vlv_suspend_complete(dev_priv);
1122 if (ret) {
1123 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1124 intel_display_power_resume_early(display);
1125
1126 goto out;
1127 }
1128
1129 pci_disable_device(pdev);
1130 /*
1131 * During hibernation on some platforms the BIOS may try to access
1132 * the device even though it's already in D3 and hang the machine. So
1133 * leave the device in D0 on those platforms and hope the BIOS will
1134 * power down the device properly. The issue was seen on multiple old
1135 * GENs with different BIOS vendors, so having an explicit blacklist
1136 * is impractical; apply the workaround on everything pre GEN6. The
1137 * platforms where the issue was seen:
1138 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1139 * Fujitsu FSC S7110
1140 * Acer Aspire 1830T
1141 */
1142 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1143 pci_set_power_state(pdev, PCI_D3hot);
1144
1145 out:
1146 enable_rpm_wakeref_asserts(rpm);
1147 if (!dev_priv->uncore.user_forcewake_count)
1148 intel_runtime_pm_driver_release(rpm);
1149
1150 return ret;
1151 }
1152
i915_driver_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1153 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1154 pm_message_t state)
1155 {
1156 int error;
1157
1158 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1159 state.event != PM_EVENT_FREEZE))
1160 return -EINVAL;
1161
1162 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1163 return 0;
1164
1165 error = i915_drm_suspend(&i915->drm);
1166 if (error)
1167 return error;
1168
1169 return i915_drm_suspend_late(&i915->drm, false);
1170 }
1171
i915_drm_resume(struct drm_device * dev)1172 static int i915_drm_resume(struct drm_device *dev)
1173 {
1174 struct drm_i915_private *dev_priv = to_i915(dev);
1175 struct intel_display *display = dev_priv->display;
1176 struct intel_gt *gt;
1177 int ret, i;
1178
1179 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1180
1181 ret = i915_pcode_init(dev_priv);
1182 if (ret)
1183 return ret;
1184
1185 sanitize_gpu(dev_priv);
1186
1187 ret = i915_ggtt_enable_hw(dev_priv);
1188 if (ret)
1189 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1190
1191 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1192
1193 for_each_gt(gt, dev_priv, i)
1194 if (GRAPHICS_VER(gt->i915) >= 8)
1195 setup_private_pat(gt);
1196
1197 /* Must be called after GGTT is resumed. */
1198 intel_dpt_resume(display);
1199
1200 intel_dmc_resume(display);
1201
1202 i9xx_display_sr_restore(display);
1203
1204 intel_gmbus_reset(display);
1205
1206 intel_pps_unlock_regs_wa(display);
1207
1208 intel_init_pch_refclk(display);
1209
1210 /*
1211 * Interrupts have to be enabled before any batches are run. If not the
1212 * GPU will hang. i915_gem_init_hw() will initiate batches to
1213 * update/restore the context.
1214 *
1215 * drm_mode_config_reset() needs AUX interrupts.
1216 *
1217 * Modeset enabling in intel_display_driver_init_hw() also needs working
1218 * interrupts.
1219 */
1220 intel_irq_resume(dev_priv);
1221
1222 if (HAS_DISPLAY(dev_priv))
1223 drm_mode_config_reset(dev);
1224
1225 i915_gem_resume(dev_priv);
1226
1227 intel_display_driver_init_hw(display);
1228
1229 intel_clock_gating_init(dev_priv);
1230
1231 if (HAS_DISPLAY(dev_priv))
1232 intel_display_driver_resume_access(display);
1233
1234 intel_hpd_init(display);
1235
1236 intel_display_driver_resume(display);
1237
1238 if (HAS_DISPLAY(dev_priv)) {
1239 intel_display_driver_enable_user_access(display);
1240 drm_kms_helper_poll_enable(dev);
1241 }
1242 intel_hpd_poll_disable(display);
1243
1244 intel_opregion_resume(display);
1245
1246 drm_client_dev_resume(dev, false);
1247
1248 intel_power_domains_enable(display);
1249
1250 intel_gvt_resume(dev_priv);
1251
1252 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1253
1254 return 0;
1255 }
1256
i915_drm_resume_early(struct drm_device * dev)1257 static int i915_drm_resume_early(struct drm_device *dev)
1258 {
1259 struct drm_i915_private *dev_priv = to_i915(dev);
1260 struct intel_display *display = dev_priv->display;
1261 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1262 struct intel_gt *gt;
1263 int ret, i;
1264
1265 /*
1266 * We have a resume ordering issue with the snd-hda driver also
1267 * requiring our device to be power up. Due to the lack of a
1268 * parent/child relationship we currently solve this with an early
1269 * resume hook.
1270 *
1271 * FIXME: This should be solved with a special hdmi sink device or
1272 * similar so that power domains can be employed.
1273 */
1274
1275 /*
1276 * Note that we need to set the power state explicitly, since we
1277 * powered off the device during freeze and the PCI core won't power
1278 * it back up for us during thaw. Powering off the device during
1279 * freeze is not a hard requirement though, and during the
1280 * suspend/resume phases the PCI core makes sure we get here with the
1281 * device powered on. So in case we change our freeze logic and keep
1282 * the device powered we can also remove the following set power state
1283 * call.
1284 */
1285 ret = pci_set_power_state(pdev, PCI_D0);
1286 if (ret) {
1287 drm_err(&dev_priv->drm,
1288 "failed to set PCI D0 power state (%d)\n", ret);
1289 return ret;
1290 }
1291
1292 /*
1293 * Note that pci_enable_device() first enables any parent bridge
1294 * device and only then sets the power state for this device. The
1295 * bridge enabling is a nop though, since bridge devices are resumed
1296 * first. The order of enabling power and enabling the device is
1297 * imposed by the PCI core as described above, so here we preserve the
1298 * same order for the freeze/thaw phases.
1299 *
1300 * TODO: eventually we should remove pci_disable_device() /
1301 * pci_enable_enable_device() from suspend/resume. Due to how they
1302 * depend on the device enable refcount we can't anyway depend on them
1303 * disabling/enabling the device.
1304 */
1305 if (pci_enable_device(pdev))
1306 return -EIO;
1307
1308 pci_set_master(pdev);
1309
1310 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1311
1312 ret = vlv_resume_prepare(dev_priv, false);
1313 if (ret)
1314 drm_err(&dev_priv->drm,
1315 "Resume prepare failed: %d, continuing anyway\n", ret);
1316
1317 for_each_gt(gt, dev_priv, i)
1318 intel_gt_resume_early(gt);
1319
1320 intel_display_power_resume_early(display);
1321
1322 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1323
1324 return ret;
1325 }
1326
i915_driver_resume_switcheroo(struct drm_i915_private * i915)1327 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1328 {
1329 int ret;
1330
1331 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1332 return 0;
1333
1334 ret = i915_drm_resume_early(&i915->drm);
1335 if (ret)
1336 return ret;
1337
1338 return i915_drm_resume(&i915->drm);
1339 }
1340
i915_pm_prepare(struct device * kdev)1341 static int i915_pm_prepare(struct device *kdev)
1342 {
1343 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1344
1345 if (!i915) {
1346 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1347 return -ENODEV;
1348 }
1349
1350 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1351 return 0;
1352
1353 return i915_drm_prepare(&i915->drm);
1354 }
1355
i915_pm_suspend(struct device * kdev)1356 static int i915_pm_suspend(struct device *kdev)
1357 {
1358 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1359
1360 if (!i915) {
1361 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1362 return -ENODEV;
1363 }
1364
1365 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1366 return 0;
1367
1368 return i915_drm_suspend(&i915->drm);
1369 }
1370
i915_pm_suspend_late(struct device * kdev)1371 static int i915_pm_suspend_late(struct device *kdev)
1372 {
1373 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1374
1375 /*
1376 * We have a suspend ordering issue with the snd-hda driver also
1377 * requiring our device to be power up. Due to the lack of a
1378 * parent/child relationship we currently solve this with an late
1379 * suspend hook.
1380 *
1381 * FIXME: This should be solved with a special hdmi sink device or
1382 * similar so that power domains can be employed.
1383 */
1384 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1385 return 0;
1386
1387 return i915_drm_suspend_late(&i915->drm, false);
1388 }
1389
i915_pm_poweroff_late(struct device * kdev)1390 static int i915_pm_poweroff_late(struct device *kdev)
1391 {
1392 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1393
1394 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1395 return 0;
1396
1397 return i915_drm_suspend_late(&i915->drm, true);
1398 }
1399
i915_pm_resume_early(struct device * kdev)1400 static int i915_pm_resume_early(struct device *kdev)
1401 {
1402 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1403
1404 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1405 return 0;
1406
1407 return i915_drm_resume_early(&i915->drm);
1408 }
1409
i915_pm_resume(struct device * kdev)1410 static int i915_pm_resume(struct device *kdev)
1411 {
1412 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1413
1414 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1415 return 0;
1416
1417 return i915_drm_resume(&i915->drm);
1418 }
1419
i915_pm_complete(struct device * kdev)1420 static void i915_pm_complete(struct device *kdev)
1421 {
1422 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1423
1424 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1425 return;
1426
1427 i915_drm_complete(&i915->drm);
1428 }
1429
1430 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)1431 static int i915_pm_freeze(struct device *kdev)
1432 {
1433 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1434 int ret;
1435
1436 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1437 ret = i915_drm_suspend(&i915->drm);
1438 if (ret)
1439 return ret;
1440 }
1441
1442 ret = i915_gem_freeze(i915);
1443 if (ret)
1444 return ret;
1445
1446 return 0;
1447 }
1448
i915_pm_freeze_late(struct device * kdev)1449 static int i915_pm_freeze_late(struct device *kdev)
1450 {
1451 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1452 int ret;
1453
1454 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1455 ret = i915_drm_suspend_late(&i915->drm, true);
1456 if (ret)
1457 return ret;
1458 }
1459
1460 ret = i915_gem_freeze_late(i915);
1461 if (ret)
1462 return ret;
1463
1464 return 0;
1465 }
1466
1467 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)1468 static int i915_pm_thaw_early(struct device *kdev)
1469 {
1470 return i915_pm_resume_early(kdev);
1471 }
1472
i915_pm_thaw(struct device * kdev)1473 static int i915_pm_thaw(struct device *kdev)
1474 {
1475 return i915_pm_resume(kdev);
1476 }
1477
1478 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)1479 static int i915_pm_restore_early(struct device *kdev)
1480 {
1481 return i915_pm_resume_early(kdev);
1482 }
1483
i915_pm_restore(struct device * kdev)1484 static int i915_pm_restore(struct device *kdev)
1485 {
1486 return i915_pm_resume(kdev);
1487 }
1488
intel_runtime_suspend(struct device * kdev)1489 static int intel_runtime_suspend(struct device *kdev)
1490 {
1491 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1492 struct intel_display *display = dev_priv->display;
1493 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1494 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1495 struct pci_dev *root_pdev;
1496 struct intel_gt *gt;
1497 int ret, i;
1498
1499 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1500 return -ENODEV;
1501
1502 drm_dbg(&dev_priv->drm, "Suspending device\n");
1503
1504 disable_rpm_wakeref_asserts(rpm);
1505
1506 /*
1507 * We are safe here against re-faults, since the fault handler takes
1508 * an RPM reference.
1509 */
1510 i915_gem_runtime_suspend(dev_priv);
1511
1512 intel_pxp_runtime_suspend(dev_priv->pxp);
1513
1514 for_each_gt(gt, dev_priv, i)
1515 intel_gt_runtime_suspend(gt);
1516
1517 intel_irq_suspend(dev_priv);
1518
1519 for_each_gt(gt, dev_priv, i)
1520 intel_uncore_suspend(gt->uncore);
1521
1522 intel_display_power_suspend(display);
1523
1524 ret = vlv_suspend_complete(dev_priv);
1525 if (ret) {
1526 drm_err(&dev_priv->drm,
1527 "Runtime suspend failed, disabling it (%d)\n", ret);
1528 intel_uncore_runtime_resume(&dev_priv->uncore);
1529
1530 intel_irq_resume(dev_priv);
1531
1532 for_each_gt(gt, dev_priv, i)
1533 intel_gt_runtime_resume(gt);
1534
1535 enable_rpm_wakeref_asserts(rpm);
1536
1537 return ret;
1538 }
1539
1540 enable_rpm_wakeref_asserts(rpm);
1541 intel_runtime_pm_driver_release(rpm);
1542
1543 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1544 drm_err(&dev_priv->drm,
1545 "Unclaimed access detected prior to suspending\n");
1546
1547 /*
1548 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1549 * This should be totally removed when we handle the pci states properly
1550 * on runtime PM.
1551 */
1552 root_pdev = pcie_find_root_port(pdev);
1553 if (root_pdev)
1554 pci_d3cold_disable(root_pdev);
1555
1556 /*
1557 * FIXME: We really should find a document that references the arguments
1558 * used below!
1559 */
1560 if (IS_BROADWELL(dev_priv)) {
1561 /*
1562 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1563 * being detected, and the call we do at intel_runtime_resume()
1564 * won't be able to restore them. Since PCI_D3hot matches the
1565 * actual specification and appears to be working, use it.
1566 */
1567 intel_opregion_notify_adapter(display, PCI_D3hot);
1568 } else {
1569 /*
1570 * current versions of firmware which depend on this opregion
1571 * notification have repurposed the D1 definition to mean
1572 * "runtime suspended" vs. what you would normally expect (D3)
1573 * to distinguish it from notifications that might be sent via
1574 * the suspend path.
1575 */
1576 intel_opregion_notify_adapter(display, PCI_D1);
1577 }
1578
1579 assert_forcewakes_inactive(&dev_priv->uncore);
1580
1581 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1582 intel_hpd_poll_enable(display);
1583
1584 drm_dbg(&dev_priv->drm, "Device suspended\n");
1585 return 0;
1586 }
1587
intel_runtime_resume(struct device * kdev)1588 static int intel_runtime_resume(struct device *kdev)
1589 {
1590 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1591 struct intel_display *display = dev_priv->display;
1592 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1593 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1594 struct pci_dev *root_pdev;
1595 struct intel_gt *gt;
1596 int ret, i;
1597
1598 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1599 return -ENODEV;
1600
1601 drm_dbg(&dev_priv->drm, "Resuming device\n");
1602
1603 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1604 disable_rpm_wakeref_asserts(rpm);
1605
1606 intel_opregion_notify_adapter(display, PCI_D0);
1607
1608 root_pdev = pcie_find_root_port(pdev);
1609 if (root_pdev)
1610 pci_d3cold_enable(root_pdev);
1611
1612 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1613 drm_dbg(&dev_priv->drm,
1614 "Unclaimed access during suspend, bios?\n");
1615
1616 intel_display_power_resume(display);
1617
1618 ret = vlv_resume_prepare(dev_priv, true);
1619
1620 for_each_gt(gt, dev_priv, i)
1621 intel_uncore_runtime_resume(gt->uncore);
1622
1623 intel_irq_resume(dev_priv);
1624
1625 /*
1626 * No point of rolling back things in case of an error, as the best
1627 * we can do is to hope that things will still work (and disable RPM).
1628 */
1629 for_each_gt(gt, dev_priv, i)
1630 intel_gt_runtime_resume(gt);
1631
1632 intel_pxp_runtime_resume(dev_priv->pxp);
1633
1634 /*
1635 * On VLV/CHV display interrupts are part of the display
1636 * power well, so hpd is reinitialized from there. For
1637 * everyone else do it here.
1638 */
1639 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1640 intel_hpd_init(display);
1641 intel_hpd_poll_disable(display);
1642 }
1643
1644 skl_watermark_ipc_update(display);
1645
1646 enable_rpm_wakeref_asserts(rpm);
1647
1648 if (ret)
1649 drm_err(&dev_priv->drm,
1650 "Runtime resume failed, disabling it (%d)\n", ret);
1651 else
1652 drm_dbg(&dev_priv->drm, "Device resumed\n");
1653
1654 return ret;
1655 }
1656
1657 const struct dev_pm_ops i915_pm_ops = {
1658 /*
1659 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1660 * PMSG_RESUME]
1661 */
1662 .prepare = i915_pm_prepare,
1663 .suspend = i915_pm_suspend,
1664 .suspend_late = i915_pm_suspend_late,
1665 .resume_early = i915_pm_resume_early,
1666 .resume = i915_pm_resume,
1667 .complete = i915_pm_complete,
1668
1669 /*
1670 * S4 event handlers
1671 * @freeze, @freeze_late : called (1) before creating the
1672 * hibernation image [PMSG_FREEZE] and
1673 * (2) after rebooting, before restoring
1674 * the image [PMSG_QUIESCE]
1675 * @thaw, @thaw_early : called (1) after creating the hibernation
1676 * image, before writing it [PMSG_THAW]
1677 * and (2) after failing to create or
1678 * restore the image [PMSG_RECOVER]
1679 * @poweroff, @poweroff_late: called after writing the hibernation
1680 * image, before rebooting [PMSG_HIBERNATE]
1681 * @restore, @restore_early : called after rebooting and restoring the
1682 * hibernation image [PMSG_RESTORE]
1683 */
1684 .freeze = i915_pm_freeze,
1685 .freeze_late = i915_pm_freeze_late,
1686 .thaw_early = i915_pm_thaw_early,
1687 .thaw = i915_pm_thaw,
1688 .poweroff = i915_pm_suspend,
1689 .poweroff_late = i915_pm_poweroff_late,
1690 .restore_early = i915_pm_restore_early,
1691 .restore = i915_pm_restore,
1692
1693 /* S0ix (via runtime suspend) event handlers */
1694 .runtime_suspend = intel_runtime_suspend,
1695 .runtime_resume = intel_runtime_resume,
1696 };
1697
1698 static const struct file_operations i915_driver_fops = {
1699 .owner = THIS_MODULE,
1700 .open = drm_open,
1701 .release = drm_release_noglobal,
1702 .unlocked_ioctl = drm_ioctl,
1703 .mmap = i915_gem_mmap,
1704 .poll = drm_poll,
1705 .read = drm_read,
1706 .compat_ioctl = i915_ioc32_compat_ioctl,
1707 .llseek = noop_llseek,
1708 #ifdef CONFIG_PROC_FS
1709 .show_fdinfo = drm_show_fdinfo,
1710 #endif
1711 .fop_flags = FOP_UNSIGNED_OFFSET,
1712 };
1713
1714 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1715 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1716 struct drm_file *file)
1717 {
1718 return -ENODEV;
1719 }
1720
1721 static const struct drm_ioctl_desc i915_ioctls[] = {
1722 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1723 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1724 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1725 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1726 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1727 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1728 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1729 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1730 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1731 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1732 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1733 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1734 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1735 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1736 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1737 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1738 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1739 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1740 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1741 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1742 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1743 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1744 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1745 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1746 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1747 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1748 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1749 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1750 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1751 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1752 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1753 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1754 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1755 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1756 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1757 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1758 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1759 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1760 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1761 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0),
1762 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1763 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1764 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1765 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1766 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1767 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1768 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1769 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1770 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1771 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1772 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1773 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1774 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1775 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1776 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1777 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1778 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1779 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1780 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1781 };
1782
1783 /*
1784 * Interface history:
1785 *
1786 * 1.1: Original.
1787 * 1.2: Add Power Management
1788 * 1.3: Add vblank support
1789 * 1.4: Fix cmdbuffer path, add heap destroy
1790 * 1.5: Add vblank pipe configuration
1791 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1792 * - Support vertical blank on secondary display pipe
1793 */
1794 #define DRIVER_MAJOR 1
1795 #define DRIVER_MINOR 6
1796 #define DRIVER_PATCHLEVEL 0
1797
1798 static const struct drm_driver i915_drm_driver = {
1799 /* Don't use MTRRs here; the Xserver or userspace app should
1800 * deal with them for Intel hardware.
1801 */
1802 .driver_features =
1803 DRIVER_GEM |
1804 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1805 DRIVER_SYNCOBJ_TIMELINE,
1806 .release = i915_driver_release,
1807 .open = i915_driver_open,
1808 .postclose = i915_driver_postclose,
1809 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo),
1810
1811 .gem_prime_import = i915_gem_prime_import,
1812
1813 .dumb_create = i915_gem_dumb_create,
1814 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1815
1816 INTEL_FBDEV_DRIVER_OPS,
1817
1818 .ioctls = i915_ioctls,
1819 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1820 .fops = &i915_driver_fops,
1821 .name = DRIVER_NAME,
1822 .desc = DRIVER_DESC,
1823 .major = DRIVER_MAJOR,
1824 .minor = DRIVER_MINOR,
1825 .patchlevel = DRIVER_PATCHLEVEL,
1826 };
1827