1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4 #include <generated/utsrelease.h>
5 #include <linux/crash_dump.h>
6 #include <linux/if_bridge.h>
7 #include <linux/if_macvlan.h>
8 #include <linux/module.h>
9 #include <net/pkt_cls.h>
10 #include <net/xdp_sock_drv.h>
11
12 /* Local includes */
13 #include "i40e.h"
14 #include "i40e_devids.h"
15 #include "i40e_diag.h"
16 #include "i40e_lan_hmc.h"
17 #include "i40e_virtchnl_pf.h"
18 #include "i40e_xsk.h"
19
20 /* All i40e tracepoints are defined by the include below, which
21 * must be included exactly once across the whole kernel with
22 * CREATE_TRACE_POINTS defined
23 */
24 #define CREATE_TRACE_POINTS
25 #include "i40e_trace.h"
26
27 const char i40e_driver_name[] = "i40e";
28 static const char i40e_driver_string[] =
29 "Intel(R) Ethernet Connection XL710 Network Driver";
30
31 static const char i40e_copyright[] = "Copyright (c) 2013 - 2019 Intel Corporation.";
32
33 /* a bit of forward declarations */
34 static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
35 static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired);
36 static int i40e_add_vsi(struct i40e_vsi *vsi);
37 static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
38 static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acquired);
39 static int i40e_setup_misc_vector(struct i40e_pf *pf);
40 static void i40e_determine_queue_usage(struct i40e_pf *pf);
41 static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
42 static void i40e_prep_for_reset(struct i40e_pf *pf);
43 static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit,
44 bool lock_acquired);
45 static int i40e_reset(struct i40e_pf *pf);
46 static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired);
47 static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf);
48 static int i40e_restore_interrupt_scheme(struct i40e_pf *pf);
49 static bool i40e_check_recovery_mode(struct i40e_pf *pf);
50 static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw);
51 static void i40e_fdir_sb_setup(struct i40e_pf *pf);
52 static int i40e_veb_get_bw_info(struct i40e_veb *veb);
53 static int i40e_get_capabilities(struct i40e_pf *pf,
54 enum i40e_admin_queue_opc list_type);
55 static bool i40e_is_total_port_shutdown_enabled(struct i40e_pf *pf);
56
57 /* i40e_pci_tbl - PCI Device ID Table
58 *
59 * Last entry must be all 0s
60 *
61 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
62 * Class, Class Mask, private data (not used) }
63 */
64 static const struct pci_device_id i40e_pci_tbl[] = {
65 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
66 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
67 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
68 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_BC), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_BC), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_SFP), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722_A), 0},
85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_X710_N3000), 0},
88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_XXV710_N3000), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0},
90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0},
91 /* required last entry */
92 {0, }
93 };
94 MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
95
96 #define I40E_MAX_VF_COUNT 128
97 static int debug = -1;
98 module_param(debug, uint, 0);
99 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX)");
100
101 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
102 MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
103 MODULE_LICENSE("GPL v2");
104
105 static struct workqueue_struct *i40e_wq;
106
netdev_hw_addr_refcnt(struct i40e_mac_filter * f,struct net_device * netdev,int delta)107 static void netdev_hw_addr_refcnt(struct i40e_mac_filter *f,
108 struct net_device *netdev, int delta)
109 {
110 struct netdev_hw_addr_list *ha_list;
111 struct netdev_hw_addr *ha;
112
113 if (!f || !netdev)
114 return;
115
116 if (is_unicast_ether_addr(f->macaddr) || is_link_local_ether_addr(f->macaddr))
117 ha_list = &netdev->uc;
118 else
119 ha_list = &netdev->mc;
120
121 netdev_hw_addr_list_for_each(ha, ha_list) {
122 if (ether_addr_equal(ha->addr, f->macaddr)) {
123 ha->refcount += delta;
124 if (ha->refcount <= 0)
125 ha->refcount = 1;
126 break;
127 }
128 }
129 }
130
131 /**
132 * i40e_hw_to_dev - get device pointer from the hardware structure
133 * @hw: pointer to the device HW structure
134 **/
i40e_hw_to_dev(struct i40e_hw * hw)135 struct device *i40e_hw_to_dev(struct i40e_hw *hw)
136 {
137 struct i40e_pf *pf = i40e_hw_to_pf(hw);
138
139 return &pf->pdev->dev;
140 }
141
142 /**
143 * i40e_allocate_dma_mem - OS specific memory alloc for shared code
144 * @hw: pointer to the HW structure
145 * @mem: ptr to mem struct to fill out
146 * @size: size of memory requested
147 * @alignment: what to align the allocation to
148 **/
i40e_allocate_dma_mem(struct i40e_hw * hw,struct i40e_dma_mem * mem,u64 size,u32 alignment)149 int i40e_allocate_dma_mem(struct i40e_hw *hw, struct i40e_dma_mem *mem,
150 u64 size, u32 alignment)
151 {
152 struct i40e_pf *pf = i40e_hw_to_pf(hw);
153
154 mem->size = ALIGN(size, alignment);
155 mem->va = dma_alloc_coherent(&pf->pdev->dev, mem->size, &mem->pa,
156 GFP_KERNEL);
157 if (!mem->va)
158 return -ENOMEM;
159
160 return 0;
161 }
162
163 /**
164 * i40e_free_dma_mem - OS specific memory free for shared code
165 * @hw: pointer to the HW structure
166 * @mem: ptr to mem struct to free
167 **/
i40e_free_dma_mem(struct i40e_hw * hw,struct i40e_dma_mem * mem)168 int i40e_free_dma_mem(struct i40e_hw *hw, struct i40e_dma_mem *mem)
169 {
170 struct i40e_pf *pf = i40e_hw_to_pf(hw);
171
172 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
173 mem->va = NULL;
174 mem->pa = 0;
175 mem->size = 0;
176
177 return 0;
178 }
179
180 /**
181 * i40e_allocate_virt_mem - OS specific memory alloc for shared code
182 * @hw: pointer to the HW structure
183 * @mem: ptr to mem struct to fill out
184 * @size: size of memory requested
185 **/
i40e_allocate_virt_mem(struct i40e_hw * hw,struct i40e_virt_mem * mem,u32 size)186 int i40e_allocate_virt_mem(struct i40e_hw *hw, struct i40e_virt_mem *mem,
187 u32 size)
188 {
189 mem->size = size;
190 mem->va = kzalloc(size, GFP_KERNEL);
191
192 if (!mem->va)
193 return -ENOMEM;
194
195 return 0;
196 }
197
198 /**
199 * i40e_free_virt_mem - OS specific memory free for shared code
200 * @hw: pointer to the HW structure
201 * @mem: ptr to mem struct to free
202 **/
i40e_free_virt_mem(struct i40e_hw * hw,struct i40e_virt_mem * mem)203 int i40e_free_virt_mem(struct i40e_hw *hw, struct i40e_virt_mem *mem)
204 {
205 /* it's ok to kfree a NULL pointer */
206 kfree(mem->va);
207 mem->va = NULL;
208 mem->size = 0;
209
210 return 0;
211 }
212
213 /**
214 * i40e_get_lump - find a lump of free generic resource
215 * @pf: board private structure
216 * @pile: the pile of resource to search
217 * @needed: the number of items needed
218 * @id: an owner id to stick on the items assigned
219 *
220 * Returns the base item index of the lump, or negative for error
221 **/
i40e_get_lump(struct i40e_pf * pf,struct i40e_lump_tracking * pile,u16 needed,u16 id)222 static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
223 u16 needed, u16 id)
224 {
225 int ret = -ENOMEM;
226 int i, j;
227
228 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
229 dev_info(&pf->pdev->dev,
230 "param err: pile=%s needed=%d id=0x%04x\n",
231 pile ? "<valid>" : "<null>", needed, id);
232 return -EINVAL;
233 }
234
235 /* Allocate last queue in the pile for FDIR VSI queue
236 * so it doesn't fragment the qp_pile
237 */
238 if (pile == pf->qp_pile && pf->vsi[id]->type == I40E_VSI_FDIR) {
239 if (pile->list[pile->num_entries - 1] & I40E_PILE_VALID_BIT) {
240 dev_err(&pf->pdev->dev,
241 "Cannot allocate queue %d for I40E_VSI_FDIR\n",
242 pile->num_entries - 1);
243 return -ENOMEM;
244 }
245 pile->list[pile->num_entries - 1] = id | I40E_PILE_VALID_BIT;
246 return pile->num_entries - 1;
247 }
248
249 i = 0;
250 while (i < pile->num_entries) {
251 /* skip already allocated entries */
252 if (pile->list[i] & I40E_PILE_VALID_BIT) {
253 i++;
254 continue;
255 }
256
257 /* do we have enough in this lump? */
258 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
259 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
260 break;
261 }
262
263 if (j == needed) {
264 /* there was enough, so assign it to the requestor */
265 for (j = 0; j < needed; j++)
266 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
267 ret = i;
268 break;
269 }
270
271 /* not enough, so skip over it and continue looking */
272 i += j;
273 }
274
275 return ret;
276 }
277
278 /**
279 * i40e_put_lump - return a lump of generic resource
280 * @pile: the pile of resource to search
281 * @index: the base item index
282 * @id: the owner id of the items assigned
283 *
284 * Returns the count of items in the lump
285 **/
i40e_put_lump(struct i40e_lump_tracking * pile,u16 index,u16 id)286 static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
287 {
288 int valid_id = (id | I40E_PILE_VALID_BIT);
289 int count = 0;
290 u16 i;
291
292 if (!pile || index >= pile->num_entries)
293 return -EINVAL;
294
295 for (i = index;
296 i < pile->num_entries && pile->list[i] == valid_id;
297 i++) {
298 pile->list[i] = 0;
299 count++;
300 }
301
302
303 return count;
304 }
305
306 /**
307 * i40e_find_vsi_from_id - searches for the vsi with the given id
308 * @pf: the pf structure to search for the vsi
309 * @id: id of the vsi it is searching for
310 **/
i40e_find_vsi_from_id(struct i40e_pf * pf,u16 id)311 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
312 {
313 int i;
314
315 for (i = 0; i < pf->num_alloc_vsi; i++)
316 if (pf->vsi[i] && (pf->vsi[i]->id == id))
317 return pf->vsi[i];
318
319 return NULL;
320 }
321
322 /**
323 * i40e_service_event_schedule - Schedule the service task to wake up
324 * @pf: board private structure
325 *
326 * If not already scheduled, this puts the task into the work queue
327 **/
i40e_service_event_schedule(struct i40e_pf * pf)328 void i40e_service_event_schedule(struct i40e_pf *pf)
329 {
330 if ((!test_bit(__I40E_DOWN, pf->state) &&
331 !test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) ||
332 test_bit(__I40E_RECOVERY_MODE, pf->state))
333 queue_work(i40e_wq, &pf->service_task);
334 }
335
336 /**
337 * i40e_tx_timeout - Respond to a Tx Hang
338 * @netdev: network interface device structure
339 * @txqueue: queue number timing out
340 *
341 * If any port has noticed a Tx timeout, it is likely that the whole
342 * device is munged, not just the one netdev port, so go for the full
343 * reset.
344 **/
i40e_tx_timeout(struct net_device * netdev,unsigned int txqueue)345 static void i40e_tx_timeout(struct net_device *netdev, unsigned int txqueue)
346 {
347 struct i40e_netdev_priv *np = netdev_priv(netdev);
348 struct i40e_vsi *vsi = np->vsi;
349 struct i40e_pf *pf = vsi->back;
350 struct i40e_ring *tx_ring = NULL;
351 unsigned int i;
352 u32 head, val;
353
354 pf->tx_timeout_count++;
355
356 /* with txqueue index, find the tx_ring struct */
357 for (i = 0; i < vsi->num_queue_pairs; i++) {
358 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
359 if (txqueue ==
360 vsi->tx_rings[i]->queue_index) {
361 tx_ring = vsi->tx_rings[i];
362 break;
363 }
364 }
365 }
366
367 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
368 pf->tx_timeout_recovery_level = 1; /* reset after some time */
369 else if (time_before(jiffies,
370 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
371 return; /* don't do any new action before the next timeout */
372
373 /* don't kick off another recovery if one is already pending */
374 if (test_and_set_bit(__I40E_TIMEOUT_RECOVERY_PENDING, pf->state))
375 return;
376
377 if (tx_ring) {
378 head = i40e_get_head(tx_ring);
379 /* Read interrupt register */
380 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
381 val = rd32(&pf->hw,
382 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
383 tx_ring->vsi->base_vector - 1));
384 else
385 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
386
387 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
388 vsi->seid, txqueue, tx_ring->next_to_clean,
389 head, tx_ring->next_to_use,
390 readl(tx_ring->tail), val);
391 }
392
393 pf->tx_timeout_last_recovery = jiffies;
394 netdev_info(netdev, "tx_timeout recovery level %d, txqueue %d\n",
395 pf->tx_timeout_recovery_level, txqueue);
396
397 switch (pf->tx_timeout_recovery_level) {
398 case 1:
399 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
400 break;
401 case 2:
402 set_bit(__I40E_CORE_RESET_REQUESTED, pf->state);
403 break;
404 case 3:
405 set_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state);
406 break;
407 default:
408 netdev_err(netdev, "tx_timeout recovery unsuccessful, device is in non-recoverable state.\n");
409 set_bit(__I40E_DOWN_REQUESTED, pf->state);
410 set_bit(__I40E_VSI_DOWN_REQUESTED, vsi->state);
411 break;
412 }
413
414 i40e_service_event_schedule(pf);
415 pf->tx_timeout_recovery_level++;
416 }
417
418 /**
419 * i40e_get_vsi_stats_struct - Get System Network Statistics
420 * @vsi: the VSI we care about
421 *
422 * Returns the address of the device statistics structure.
423 * The statistics are actually updated from the service task.
424 **/
i40e_get_vsi_stats_struct(struct i40e_vsi * vsi)425 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
426 {
427 return &vsi->net_stats;
428 }
429
430 /**
431 * i40e_get_netdev_stats_struct_tx - populate stats from a Tx ring
432 * @ring: Tx ring to get statistics from
433 * @stats: statistics entry to be updated
434 **/
i40e_get_netdev_stats_struct_tx(struct i40e_ring * ring,struct rtnl_link_stats64 * stats)435 static void i40e_get_netdev_stats_struct_tx(struct i40e_ring *ring,
436 struct rtnl_link_stats64 *stats)
437 {
438 u64 bytes, packets;
439 unsigned int start;
440
441 do {
442 start = u64_stats_fetch_begin(&ring->syncp);
443 packets = ring->stats.packets;
444 bytes = ring->stats.bytes;
445 } while (u64_stats_fetch_retry(&ring->syncp, start));
446
447 stats->tx_packets += packets;
448 stats->tx_bytes += bytes;
449 }
450
451 /**
452 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
453 * @netdev: network interface device structure
454 * @stats: data structure to store statistics
455 *
456 * Returns the address of the device statistics structure.
457 * The statistics are actually updated from the service task.
458 **/
i40e_get_netdev_stats_struct(struct net_device * netdev,struct rtnl_link_stats64 * stats)459 static void i40e_get_netdev_stats_struct(struct net_device *netdev,
460 struct rtnl_link_stats64 *stats)
461 {
462 struct i40e_netdev_priv *np = netdev_priv(netdev);
463 struct i40e_vsi *vsi = np->vsi;
464 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
465 struct i40e_ring *ring;
466 int i;
467
468 if (test_bit(__I40E_VSI_DOWN, vsi->state))
469 return;
470
471 if (!vsi->tx_rings)
472 return;
473
474 rcu_read_lock();
475 for (i = 0; i < vsi->num_queue_pairs; i++) {
476 u64 bytes, packets;
477 unsigned int start;
478
479 ring = READ_ONCE(vsi->tx_rings[i]);
480 if (!ring)
481 continue;
482 i40e_get_netdev_stats_struct_tx(ring, stats);
483
484 if (i40e_enabled_xdp_vsi(vsi)) {
485 ring = READ_ONCE(vsi->xdp_rings[i]);
486 if (!ring)
487 continue;
488 i40e_get_netdev_stats_struct_tx(ring, stats);
489 }
490
491 ring = READ_ONCE(vsi->rx_rings[i]);
492 if (!ring)
493 continue;
494 do {
495 start = u64_stats_fetch_begin(&ring->syncp);
496 packets = ring->stats.packets;
497 bytes = ring->stats.bytes;
498 } while (u64_stats_fetch_retry(&ring->syncp, start));
499
500 stats->rx_packets += packets;
501 stats->rx_bytes += bytes;
502
503 }
504 rcu_read_unlock();
505
506 /* following stats updated by i40e_watchdog_subtask() */
507 stats->multicast = vsi_stats->multicast;
508 stats->tx_errors = vsi_stats->tx_errors;
509 stats->tx_dropped = vsi_stats->tx_dropped;
510 stats->rx_errors = vsi_stats->rx_errors;
511 stats->rx_dropped = vsi_stats->rx_dropped;
512 stats->rx_missed_errors = vsi_stats->rx_missed_errors;
513 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
514 stats->rx_length_errors = vsi_stats->rx_length_errors;
515 }
516
517 /**
518 * i40e_vsi_reset_stats - Resets all stats of the given vsi
519 * @vsi: the VSI to have its stats reset
520 **/
i40e_vsi_reset_stats(struct i40e_vsi * vsi)521 void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
522 {
523 struct rtnl_link_stats64 *ns;
524 int i;
525
526 if (!vsi)
527 return;
528
529 ns = i40e_get_vsi_stats_struct(vsi);
530 memset(ns, 0, sizeof(*ns));
531 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
532 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
533 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
534 if (vsi->rx_rings && vsi->rx_rings[0]) {
535 for (i = 0; i < vsi->num_queue_pairs; i++) {
536 memset(&vsi->rx_rings[i]->stats, 0,
537 sizeof(vsi->rx_rings[i]->stats));
538 memset(&vsi->rx_rings[i]->rx_stats, 0,
539 sizeof(vsi->rx_rings[i]->rx_stats));
540 memset(&vsi->tx_rings[i]->stats, 0,
541 sizeof(vsi->tx_rings[i]->stats));
542 memset(&vsi->tx_rings[i]->tx_stats, 0,
543 sizeof(vsi->tx_rings[i]->tx_stats));
544 }
545 }
546 vsi->stat_offsets_loaded = false;
547 }
548
549 /**
550 * i40e_pf_reset_stats - Reset all of the stats for the given PF
551 * @pf: the PF to be reset
552 **/
i40e_pf_reset_stats(struct i40e_pf * pf)553 void i40e_pf_reset_stats(struct i40e_pf *pf)
554 {
555 int i;
556
557 memset(&pf->stats, 0, sizeof(pf->stats));
558 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
559 pf->stat_offsets_loaded = false;
560
561 for (i = 0; i < I40E_MAX_VEB; i++) {
562 if (pf->veb[i]) {
563 memset(&pf->veb[i]->stats, 0,
564 sizeof(pf->veb[i]->stats));
565 memset(&pf->veb[i]->stats_offsets, 0,
566 sizeof(pf->veb[i]->stats_offsets));
567 memset(&pf->veb[i]->tc_stats, 0,
568 sizeof(pf->veb[i]->tc_stats));
569 memset(&pf->veb[i]->tc_stats_offsets, 0,
570 sizeof(pf->veb[i]->tc_stats_offsets));
571 pf->veb[i]->stat_offsets_loaded = false;
572 }
573 }
574 pf->hw_csum_rx_error = 0;
575 }
576
577 /**
578 * i40e_compute_pci_to_hw_id - compute index form PCI function.
579 * @vsi: ptr to the VSI to read from.
580 * @hw: ptr to the hardware info.
581 **/
i40e_compute_pci_to_hw_id(struct i40e_vsi * vsi,struct i40e_hw * hw)582 static u32 i40e_compute_pci_to_hw_id(struct i40e_vsi *vsi, struct i40e_hw *hw)
583 {
584 int pf_count = i40e_get_pf_count(hw);
585
586 if (vsi->type == I40E_VSI_SRIOV)
587 return (hw->port * BIT(7)) / pf_count + vsi->vf_id;
588
589 return hw->port + BIT(7);
590 }
591
592 /**
593 * i40e_stat_update64 - read and update a 64 bit stat from the chip.
594 * @hw: ptr to the hardware info.
595 * @hireg: the high 32 bit reg to read.
596 * @loreg: the low 32 bit reg to read.
597 * @offset_loaded: has the initial offset been loaded yet.
598 * @offset: ptr to current offset value.
599 * @stat: ptr to the stat.
600 *
601 * Since the device stats are not reset at PFReset, they will not
602 * be zeroed when the driver starts. We'll save the first values read
603 * and use them as offsets to be subtracted from the raw values in order
604 * to report stats that count from zero.
605 **/
i40e_stat_update64(struct i40e_hw * hw,u32 hireg,u32 loreg,bool offset_loaded,u64 * offset,u64 * stat)606 static void i40e_stat_update64(struct i40e_hw *hw, u32 hireg, u32 loreg,
607 bool offset_loaded, u64 *offset, u64 *stat)
608 {
609 u64 new_data;
610
611 new_data = rd64(hw, loreg);
612
613 if (!offset_loaded || new_data < *offset)
614 *offset = new_data;
615 *stat = new_data - *offset;
616 }
617
618 /**
619 * i40e_stat_update48 - read and update a 48 bit stat from the chip
620 * @hw: ptr to the hardware info
621 * @hireg: the high 32 bit reg to read
622 * @loreg: the low 32 bit reg to read
623 * @offset_loaded: has the initial offset been loaded yet
624 * @offset: ptr to current offset value
625 * @stat: ptr to the stat
626 *
627 * Since the device stats are not reset at PFReset, they likely will not
628 * be zeroed when the driver starts. We'll save the first values read
629 * and use them as offsets to be subtracted from the raw values in order
630 * to report stats that count from zero. In the process, we also manage
631 * the potential roll-over.
632 **/
i40e_stat_update48(struct i40e_hw * hw,u32 hireg,u32 loreg,bool offset_loaded,u64 * offset,u64 * stat)633 static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
634 bool offset_loaded, u64 *offset, u64 *stat)
635 {
636 u64 new_data;
637
638 if (hw->device_id == I40E_DEV_ID_QEMU) {
639 new_data = rd32(hw, loreg);
640 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
641 } else {
642 new_data = rd64(hw, loreg);
643 }
644 if (!offset_loaded)
645 *offset = new_data;
646 if (likely(new_data >= *offset))
647 *stat = new_data - *offset;
648 else
649 *stat = (new_data + BIT_ULL(48)) - *offset;
650 *stat &= 0xFFFFFFFFFFFFULL;
651 }
652
653 /**
654 * i40e_stat_update32 - read and update a 32 bit stat from the chip
655 * @hw: ptr to the hardware info
656 * @reg: the hw reg to read
657 * @offset_loaded: has the initial offset been loaded yet
658 * @offset: ptr to current offset value
659 * @stat: ptr to the stat
660 **/
i40e_stat_update32(struct i40e_hw * hw,u32 reg,bool offset_loaded,u64 * offset,u64 * stat)661 static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
662 bool offset_loaded, u64 *offset, u64 *stat)
663 {
664 u32 new_data;
665
666 new_data = rd32(hw, reg);
667 if (!offset_loaded)
668 *offset = new_data;
669 if (likely(new_data >= *offset))
670 *stat = (u32)(new_data - *offset);
671 else
672 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
673 }
674
675 /**
676 * i40e_stat_update_and_clear32 - read and clear hw reg, update a 32 bit stat
677 * @hw: ptr to the hardware info
678 * @reg: the hw reg to read and clear
679 * @stat: ptr to the stat
680 **/
i40e_stat_update_and_clear32(struct i40e_hw * hw,u32 reg,u64 * stat)681 static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat)
682 {
683 u32 new_data = rd32(hw, reg);
684
685 wr32(hw, reg, 1); /* must write a nonzero value to clear register */
686 *stat += new_data;
687 }
688
689 /**
690 * i40e_stats_update_rx_discards - update rx_discards.
691 * @vsi: ptr to the VSI to be updated.
692 * @hw: ptr to the hardware info.
693 * @stat_idx: VSI's stat_counter_idx.
694 * @offset_loaded: ptr to the VSI's stat_offsets_loaded.
695 * @stat_offset: ptr to stat_offset to store first read of specific register.
696 * @stat: ptr to VSI's stat to be updated.
697 **/
698 static void
i40e_stats_update_rx_discards(struct i40e_vsi * vsi,struct i40e_hw * hw,int stat_idx,bool offset_loaded,struct i40e_eth_stats * stat_offset,struct i40e_eth_stats * stat)699 i40e_stats_update_rx_discards(struct i40e_vsi *vsi, struct i40e_hw *hw,
700 int stat_idx, bool offset_loaded,
701 struct i40e_eth_stats *stat_offset,
702 struct i40e_eth_stats *stat)
703 {
704 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), offset_loaded,
705 &stat_offset->rx_discards, &stat->rx_discards);
706 i40e_stat_update64(hw,
707 I40E_GL_RXERR1H(i40e_compute_pci_to_hw_id(vsi, hw)),
708 I40E_GL_RXERR1L(i40e_compute_pci_to_hw_id(vsi, hw)),
709 offset_loaded, &stat_offset->rx_discards_other,
710 &stat->rx_discards_other);
711 }
712
713 /**
714 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
715 * @vsi: the VSI to be updated
716 **/
i40e_update_eth_stats(struct i40e_vsi * vsi)717 void i40e_update_eth_stats(struct i40e_vsi *vsi)
718 {
719 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
720 struct i40e_pf *pf = vsi->back;
721 struct i40e_hw *hw = &pf->hw;
722 struct i40e_eth_stats *oes;
723 struct i40e_eth_stats *es; /* device's eth stats */
724
725 es = &vsi->eth_stats;
726 oes = &vsi->eth_stats_offsets;
727
728 /* Gather up the stats that the hw collects */
729 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
730 vsi->stat_offsets_loaded,
731 &oes->tx_errors, &es->tx_errors);
732 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
733 vsi->stat_offsets_loaded,
734 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
735
736 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
737 I40E_GLV_GORCL(stat_idx),
738 vsi->stat_offsets_loaded,
739 &oes->rx_bytes, &es->rx_bytes);
740 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
741 I40E_GLV_UPRCL(stat_idx),
742 vsi->stat_offsets_loaded,
743 &oes->rx_unicast, &es->rx_unicast);
744 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
745 I40E_GLV_MPRCL(stat_idx),
746 vsi->stat_offsets_loaded,
747 &oes->rx_multicast, &es->rx_multicast);
748 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
749 I40E_GLV_BPRCL(stat_idx),
750 vsi->stat_offsets_loaded,
751 &oes->rx_broadcast, &es->rx_broadcast);
752
753 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
754 I40E_GLV_GOTCL(stat_idx),
755 vsi->stat_offsets_loaded,
756 &oes->tx_bytes, &es->tx_bytes);
757 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
758 I40E_GLV_UPTCL(stat_idx),
759 vsi->stat_offsets_loaded,
760 &oes->tx_unicast, &es->tx_unicast);
761 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
762 I40E_GLV_MPTCL(stat_idx),
763 vsi->stat_offsets_loaded,
764 &oes->tx_multicast, &es->tx_multicast);
765 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
766 I40E_GLV_BPTCL(stat_idx),
767 vsi->stat_offsets_loaded,
768 &oes->tx_broadcast, &es->tx_broadcast);
769
770 i40e_stats_update_rx_discards(vsi, hw, stat_idx,
771 vsi->stat_offsets_loaded, oes, es);
772
773 vsi->stat_offsets_loaded = true;
774 }
775
776 /**
777 * i40e_update_veb_stats - Update Switch component statistics
778 * @veb: the VEB being updated
779 **/
i40e_update_veb_stats(struct i40e_veb * veb)780 void i40e_update_veb_stats(struct i40e_veb *veb)
781 {
782 struct i40e_pf *pf = veb->pf;
783 struct i40e_hw *hw = &pf->hw;
784 struct i40e_eth_stats *oes;
785 struct i40e_eth_stats *es; /* device's eth stats */
786 struct i40e_veb_tc_stats *veb_oes;
787 struct i40e_veb_tc_stats *veb_es;
788 int i, idx = 0;
789
790 idx = veb->stats_idx;
791 es = &veb->stats;
792 oes = &veb->stats_offsets;
793 veb_es = &veb->tc_stats;
794 veb_oes = &veb->tc_stats_offsets;
795
796 /* Gather up the stats that the hw collects */
797 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
798 veb->stat_offsets_loaded,
799 &oes->tx_discards, &es->tx_discards);
800 if (hw->revision_id > 0)
801 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
802 veb->stat_offsets_loaded,
803 &oes->rx_unknown_protocol,
804 &es->rx_unknown_protocol);
805 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
806 veb->stat_offsets_loaded,
807 &oes->rx_bytes, &es->rx_bytes);
808 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
809 veb->stat_offsets_loaded,
810 &oes->rx_unicast, &es->rx_unicast);
811 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
812 veb->stat_offsets_loaded,
813 &oes->rx_multicast, &es->rx_multicast);
814 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
815 veb->stat_offsets_loaded,
816 &oes->rx_broadcast, &es->rx_broadcast);
817
818 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
819 veb->stat_offsets_loaded,
820 &oes->tx_bytes, &es->tx_bytes);
821 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
822 veb->stat_offsets_loaded,
823 &oes->tx_unicast, &es->tx_unicast);
824 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
825 veb->stat_offsets_loaded,
826 &oes->tx_multicast, &es->tx_multicast);
827 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
828 veb->stat_offsets_loaded,
829 &oes->tx_broadcast, &es->tx_broadcast);
830 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
831 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
832 I40E_GLVEBTC_RPCL(i, idx),
833 veb->stat_offsets_loaded,
834 &veb_oes->tc_rx_packets[i],
835 &veb_es->tc_rx_packets[i]);
836 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
837 I40E_GLVEBTC_RBCL(i, idx),
838 veb->stat_offsets_loaded,
839 &veb_oes->tc_rx_bytes[i],
840 &veb_es->tc_rx_bytes[i]);
841 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
842 I40E_GLVEBTC_TPCL(i, idx),
843 veb->stat_offsets_loaded,
844 &veb_oes->tc_tx_packets[i],
845 &veb_es->tc_tx_packets[i]);
846 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
847 I40E_GLVEBTC_TBCL(i, idx),
848 veb->stat_offsets_loaded,
849 &veb_oes->tc_tx_bytes[i],
850 &veb_es->tc_tx_bytes[i]);
851 }
852 veb->stat_offsets_loaded = true;
853 }
854
855 /**
856 * i40e_update_vsi_stats - Update the vsi statistics counters.
857 * @vsi: the VSI to be updated
858 *
859 * There are a few instances where we store the same stat in a
860 * couple of different structs. This is partly because we have
861 * the netdev stats that need to be filled out, which is slightly
862 * different from the "eth_stats" defined by the chip and used in
863 * VF communications. We sort it out here.
864 **/
i40e_update_vsi_stats(struct i40e_vsi * vsi)865 static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
866 {
867 u64 rx_page, rx_buf, rx_reuse, rx_alloc, rx_waive, rx_busy;
868 struct i40e_pf *pf = vsi->back;
869 struct rtnl_link_stats64 *ons;
870 struct rtnl_link_stats64 *ns; /* netdev stats */
871 struct i40e_eth_stats *oes;
872 struct i40e_eth_stats *es; /* device's eth stats */
873 u64 tx_restart, tx_busy;
874 struct i40e_ring *p;
875 u64 bytes, packets;
876 unsigned int start;
877 u64 tx_linearize;
878 u64 tx_force_wb;
879 u64 tx_stopped;
880 u64 rx_p, rx_b;
881 u64 tx_p, tx_b;
882 u16 q;
883
884 if (test_bit(__I40E_VSI_DOWN, vsi->state) ||
885 test_bit(__I40E_CONFIG_BUSY, pf->state))
886 return;
887
888 ns = i40e_get_vsi_stats_struct(vsi);
889 ons = &vsi->net_stats_offsets;
890 es = &vsi->eth_stats;
891 oes = &vsi->eth_stats_offsets;
892
893 /* Gather up the netdev and vsi stats that the driver collects
894 * on the fly during packet processing
895 */
896 rx_b = rx_p = 0;
897 tx_b = tx_p = 0;
898 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
899 tx_stopped = 0;
900 rx_page = 0;
901 rx_buf = 0;
902 rx_reuse = 0;
903 rx_alloc = 0;
904 rx_waive = 0;
905 rx_busy = 0;
906 rcu_read_lock();
907 for (q = 0; q < vsi->num_queue_pairs; q++) {
908 /* locate Tx ring */
909 p = READ_ONCE(vsi->tx_rings[q]);
910 if (!p)
911 continue;
912
913 do {
914 start = u64_stats_fetch_begin(&p->syncp);
915 packets = p->stats.packets;
916 bytes = p->stats.bytes;
917 } while (u64_stats_fetch_retry(&p->syncp, start));
918 tx_b += bytes;
919 tx_p += packets;
920 tx_restart += p->tx_stats.restart_queue;
921 tx_busy += p->tx_stats.tx_busy;
922 tx_linearize += p->tx_stats.tx_linearize;
923 tx_force_wb += p->tx_stats.tx_force_wb;
924 tx_stopped += p->tx_stats.tx_stopped;
925
926 /* locate Rx ring */
927 p = READ_ONCE(vsi->rx_rings[q]);
928 if (!p)
929 continue;
930
931 do {
932 start = u64_stats_fetch_begin(&p->syncp);
933 packets = p->stats.packets;
934 bytes = p->stats.bytes;
935 } while (u64_stats_fetch_retry(&p->syncp, start));
936 rx_b += bytes;
937 rx_p += packets;
938 rx_buf += p->rx_stats.alloc_buff_failed;
939 rx_page += p->rx_stats.alloc_page_failed;
940 rx_reuse += p->rx_stats.page_reuse_count;
941 rx_alloc += p->rx_stats.page_alloc_count;
942 rx_waive += p->rx_stats.page_waive_count;
943 rx_busy += p->rx_stats.page_busy_count;
944
945 if (i40e_enabled_xdp_vsi(vsi)) {
946 /* locate XDP ring */
947 p = READ_ONCE(vsi->xdp_rings[q]);
948 if (!p)
949 continue;
950
951 do {
952 start = u64_stats_fetch_begin(&p->syncp);
953 packets = p->stats.packets;
954 bytes = p->stats.bytes;
955 } while (u64_stats_fetch_retry(&p->syncp, start));
956 tx_b += bytes;
957 tx_p += packets;
958 tx_restart += p->tx_stats.restart_queue;
959 tx_busy += p->tx_stats.tx_busy;
960 tx_linearize += p->tx_stats.tx_linearize;
961 tx_force_wb += p->tx_stats.tx_force_wb;
962 }
963 }
964 rcu_read_unlock();
965 vsi->tx_restart = tx_restart;
966 vsi->tx_busy = tx_busy;
967 vsi->tx_linearize = tx_linearize;
968 vsi->tx_force_wb = tx_force_wb;
969 vsi->tx_stopped = tx_stopped;
970 vsi->rx_page_failed = rx_page;
971 vsi->rx_buf_failed = rx_buf;
972 vsi->rx_page_reuse = rx_reuse;
973 vsi->rx_page_alloc = rx_alloc;
974 vsi->rx_page_waive = rx_waive;
975 vsi->rx_page_busy = rx_busy;
976
977 ns->rx_packets = rx_p;
978 ns->rx_bytes = rx_b;
979 ns->tx_packets = tx_p;
980 ns->tx_bytes = tx_b;
981
982 /* update netdev stats from eth stats */
983 i40e_update_eth_stats(vsi);
984 ons->tx_errors = oes->tx_errors;
985 ns->tx_errors = es->tx_errors;
986 ons->multicast = oes->rx_multicast;
987 ns->multicast = es->rx_multicast;
988 ons->rx_dropped = oes->rx_discards_other;
989 ns->rx_dropped = es->rx_discards_other;
990 ons->rx_missed_errors = oes->rx_discards;
991 ns->rx_missed_errors = es->rx_discards;
992 ons->tx_dropped = oes->tx_discards;
993 ns->tx_dropped = es->tx_discards;
994
995 /* pull in a couple PF stats if this is the main vsi */
996 if (vsi == pf->vsi[pf->lan_vsi]) {
997 ns->rx_crc_errors = pf->stats.crc_errors;
998 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
999 ns->rx_length_errors = pf->stats.rx_length_errors;
1000 }
1001 }
1002
1003 /**
1004 * i40e_update_pf_stats - Update the PF statistics counters.
1005 * @pf: the PF to be updated
1006 **/
i40e_update_pf_stats(struct i40e_pf * pf)1007 static void i40e_update_pf_stats(struct i40e_pf *pf)
1008 {
1009 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
1010 struct i40e_hw_port_stats *nsd = &pf->stats;
1011 struct i40e_hw *hw = &pf->hw;
1012 u32 val;
1013 int i;
1014
1015 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
1016 I40E_GLPRT_GORCL(hw->port),
1017 pf->stat_offsets_loaded,
1018 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
1019 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
1020 I40E_GLPRT_GOTCL(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
1023 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
1024 pf->stat_offsets_loaded,
1025 &osd->eth.rx_discards,
1026 &nsd->eth.rx_discards);
1027 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
1028 I40E_GLPRT_UPRCL(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->eth.rx_unicast,
1031 &nsd->eth.rx_unicast);
1032 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
1033 I40E_GLPRT_MPRCL(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->eth.rx_multicast,
1036 &nsd->eth.rx_multicast);
1037 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
1038 I40E_GLPRT_BPRCL(hw->port),
1039 pf->stat_offsets_loaded,
1040 &osd->eth.rx_broadcast,
1041 &nsd->eth.rx_broadcast);
1042 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1043 I40E_GLPRT_UPTCL(hw->port),
1044 pf->stat_offsets_loaded,
1045 &osd->eth.tx_unicast,
1046 &nsd->eth.tx_unicast);
1047 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1048 I40E_GLPRT_MPTCL(hw->port),
1049 pf->stat_offsets_loaded,
1050 &osd->eth.tx_multicast,
1051 &nsd->eth.tx_multicast);
1052 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1053 I40E_GLPRT_BPTCL(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->eth.tx_broadcast,
1056 &nsd->eth.tx_broadcast);
1057
1058 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_dropped_link_down,
1061 &nsd->tx_dropped_link_down);
1062
1063 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1064 pf->stat_offsets_loaded,
1065 &osd->crc_errors, &nsd->crc_errors);
1066
1067 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1068 pf->stat_offsets_loaded,
1069 &osd->illegal_bytes, &nsd->illegal_bytes);
1070
1071 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1072 pf->stat_offsets_loaded,
1073 &osd->mac_local_faults,
1074 &nsd->mac_local_faults);
1075 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->mac_remote_faults,
1078 &nsd->mac_remote_faults);
1079
1080 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_length_errors,
1083 &nsd->rx_length_errors);
1084
1085 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1086 pf->stat_offsets_loaded,
1087 &osd->link_xon_rx, &nsd->link_xon_rx);
1088 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1089 pf->stat_offsets_loaded,
1090 &osd->link_xon_tx, &nsd->link_xon_tx);
1091 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1092 pf->stat_offsets_loaded,
1093 &osd->link_xoff_rx, &nsd->link_xoff_rx);
1094 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1095 pf->stat_offsets_loaded,
1096 &osd->link_xoff_tx, &nsd->link_xoff_tx);
1097
1098 for (i = 0; i < 8; i++) {
1099 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1100 pf->stat_offsets_loaded,
1101 &osd->priority_xoff_rx[i],
1102 &nsd->priority_xoff_rx[i]);
1103 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1104 pf->stat_offsets_loaded,
1105 &osd->priority_xon_rx[i],
1106 &nsd->priority_xon_rx[i]);
1107 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1108 pf->stat_offsets_loaded,
1109 &osd->priority_xon_tx[i],
1110 &nsd->priority_xon_tx[i]);
1111 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1112 pf->stat_offsets_loaded,
1113 &osd->priority_xoff_tx[i],
1114 &nsd->priority_xoff_tx[i]);
1115 i40e_stat_update32(hw,
1116 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1117 pf->stat_offsets_loaded,
1118 &osd->priority_xon_2_xoff[i],
1119 &nsd->priority_xon_2_xoff[i]);
1120 }
1121
1122 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1123 I40E_GLPRT_PRC64L(hw->port),
1124 pf->stat_offsets_loaded,
1125 &osd->rx_size_64, &nsd->rx_size_64);
1126 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1127 I40E_GLPRT_PRC127L(hw->port),
1128 pf->stat_offsets_loaded,
1129 &osd->rx_size_127, &nsd->rx_size_127);
1130 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1131 I40E_GLPRT_PRC255L(hw->port),
1132 pf->stat_offsets_loaded,
1133 &osd->rx_size_255, &nsd->rx_size_255);
1134 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1135 I40E_GLPRT_PRC511L(hw->port),
1136 pf->stat_offsets_loaded,
1137 &osd->rx_size_511, &nsd->rx_size_511);
1138 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1139 I40E_GLPRT_PRC1023L(hw->port),
1140 pf->stat_offsets_loaded,
1141 &osd->rx_size_1023, &nsd->rx_size_1023);
1142 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1143 I40E_GLPRT_PRC1522L(hw->port),
1144 pf->stat_offsets_loaded,
1145 &osd->rx_size_1522, &nsd->rx_size_1522);
1146 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1147 I40E_GLPRT_PRC9522L(hw->port),
1148 pf->stat_offsets_loaded,
1149 &osd->rx_size_big, &nsd->rx_size_big);
1150
1151 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1152 I40E_GLPRT_PTC64L(hw->port),
1153 pf->stat_offsets_loaded,
1154 &osd->tx_size_64, &nsd->tx_size_64);
1155 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1156 I40E_GLPRT_PTC127L(hw->port),
1157 pf->stat_offsets_loaded,
1158 &osd->tx_size_127, &nsd->tx_size_127);
1159 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1160 I40E_GLPRT_PTC255L(hw->port),
1161 pf->stat_offsets_loaded,
1162 &osd->tx_size_255, &nsd->tx_size_255);
1163 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1164 I40E_GLPRT_PTC511L(hw->port),
1165 pf->stat_offsets_loaded,
1166 &osd->tx_size_511, &nsd->tx_size_511);
1167 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1168 I40E_GLPRT_PTC1023L(hw->port),
1169 pf->stat_offsets_loaded,
1170 &osd->tx_size_1023, &nsd->tx_size_1023);
1171 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1172 I40E_GLPRT_PTC1522L(hw->port),
1173 pf->stat_offsets_loaded,
1174 &osd->tx_size_1522, &nsd->tx_size_1522);
1175 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1176 I40E_GLPRT_PTC9522L(hw->port),
1177 pf->stat_offsets_loaded,
1178 &osd->tx_size_big, &nsd->tx_size_big);
1179
1180 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1181 pf->stat_offsets_loaded,
1182 &osd->rx_undersize, &nsd->rx_undersize);
1183 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1184 pf->stat_offsets_loaded,
1185 &osd->rx_fragments, &nsd->rx_fragments);
1186 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1187 pf->stat_offsets_loaded,
1188 &osd->rx_oversize, &nsd->rx_oversize);
1189 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1190 pf->stat_offsets_loaded,
1191 &osd->rx_jabber, &nsd->rx_jabber);
1192
1193 /* FDIR stats */
1194 i40e_stat_update_and_clear32(hw,
1195 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(hw->pf_id)),
1196 &nsd->fd_atr_match);
1197 i40e_stat_update_and_clear32(hw,
1198 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(hw->pf_id)),
1199 &nsd->fd_sb_match);
1200 i40e_stat_update_and_clear32(hw,
1201 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(hw->pf_id)),
1202 &nsd->fd_atr_tunnel_match);
1203
1204 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1205 nsd->tx_lpi_status =
1206 FIELD_GET(I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK, val);
1207 nsd->rx_lpi_status =
1208 FIELD_GET(I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK, val);
1209 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1210 pf->stat_offsets_loaded,
1211 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1212 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1213 pf->stat_offsets_loaded,
1214 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1215
1216 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) &&
1217 !test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
1218 nsd->fd_sb_status = true;
1219 else
1220 nsd->fd_sb_status = false;
1221
1222 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) &&
1223 !test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
1224 nsd->fd_atr_status = true;
1225 else
1226 nsd->fd_atr_status = false;
1227
1228 pf->stat_offsets_loaded = true;
1229 }
1230
1231 /**
1232 * i40e_update_stats - Update the various statistics counters.
1233 * @vsi: the VSI to be updated
1234 *
1235 * Update the various stats for this VSI and its related entities.
1236 **/
i40e_update_stats(struct i40e_vsi * vsi)1237 void i40e_update_stats(struct i40e_vsi *vsi)
1238 {
1239 struct i40e_pf *pf = vsi->back;
1240
1241 if (vsi == pf->vsi[pf->lan_vsi])
1242 i40e_update_pf_stats(pf);
1243
1244 i40e_update_vsi_stats(vsi);
1245 }
1246
1247 /**
1248 * i40e_count_filters - counts VSI mac filters
1249 * @vsi: the VSI to be searched
1250 *
1251 * Returns count of mac filters
1252 **/
i40e_count_filters(struct i40e_vsi * vsi)1253 int i40e_count_filters(struct i40e_vsi *vsi)
1254 {
1255 struct i40e_mac_filter *f;
1256 struct hlist_node *h;
1257 int bkt;
1258 int cnt = 0;
1259
1260 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist)
1261 ++cnt;
1262
1263 return cnt;
1264 }
1265
1266 /**
1267 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1268 * @vsi: the VSI to be searched
1269 * @macaddr: the MAC address
1270 * @vlan: the vlan
1271 *
1272 * Returns ptr to the filter object or NULL
1273 **/
i40e_find_filter(struct i40e_vsi * vsi,const u8 * macaddr,s16 vlan)1274 static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1275 const u8 *macaddr, s16 vlan)
1276 {
1277 struct i40e_mac_filter *f;
1278 u64 key;
1279
1280 if (!vsi || !macaddr)
1281 return NULL;
1282
1283 key = i40e_addr_to_hkey(macaddr);
1284 hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) {
1285 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1286 (vlan == f->vlan))
1287 return f;
1288 }
1289 return NULL;
1290 }
1291
1292 /**
1293 * i40e_find_mac - Find a mac addr in the macvlan filters list
1294 * @vsi: the VSI to be searched
1295 * @macaddr: the MAC address we are searching for
1296 *
1297 * Returns the first filter with the provided MAC address or NULL if
1298 * MAC address was not found
1299 **/
i40e_find_mac(struct i40e_vsi * vsi,const u8 * macaddr)1300 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr)
1301 {
1302 struct i40e_mac_filter *f;
1303 u64 key;
1304
1305 if (!vsi || !macaddr)
1306 return NULL;
1307
1308 key = i40e_addr_to_hkey(macaddr);
1309 hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) {
1310 if ((ether_addr_equal(macaddr, f->macaddr)))
1311 return f;
1312 }
1313 return NULL;
1314 }
1315
1316 /**
1317 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1318 * @vsi: the VSI to be searched
1319 *
1320 * Returns true if VSI is in vlan mode or false otherwise
1321 **/
i40e_is_vsi_in_vlan(struct i40e_vsi * vsi)1322 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1323 {
1324 /* If we have a PVID, always operate in VLAN mode */
1325 if (vsi->info.pvid)
1326 return true;
1327
1328 /* We need to operate in VLAN mode whenever we have any filters with
1329 * a VLAN other than I40E_VLAN_ALL. We could check the table each
1330 * time, incurring search cost repeatedly. However, we can notice two
1331 * things:
1332 *
1333 * 1) the only place where we can gain a VLAN filter is in
1334 * i40e_add_filter.
1335 *
1336 * 2) the only place where filters are actually removed is in
1337 * i40e_sync_filters_subtask.
1338 *
1339 * Thus, we can simply use a boolean value, has_vlan_filters which we
1340 * will set to true when we add a VLAN filter in i40e_add_filter. Then
1341 * we have to perform the full search after deleting filters in
1342 * i40e_sync_filters_subtask, but we already have to search
1343 * filters here and can perform the check at the same time. This
1344 * results in avoiding embedding a loop for VLAN mode inside another
1345 * loop over all the filters, and should maintain correctness as noted
1346 * above.
1347 */
1348 return vsi->has_vlan_filter;
1349 }
1350
1351 /**
1352 * i40e_correct_mac_vlan_filters - Correct non-VLAN filters if necessary
1353 * @vsi: the VSI to configure
1354 * @tmp_add_list: list of filters ready to be added
1355 * @tmp_del_list: list of filters ready to be deleted
1356 * @vlan_filters: the number of active VLAN filters
1357 *
1358 * Update VLAN=0 and VLAN=-1 (I40E_VLAN_ANY) filters properly so that they
1359 * behave as expected. If we have any active VLAN filters remaining or about
1360 * to be added then we need to update non-VLAN filters to be marked as VLAN=0
1361 * so that they only match against untagged traffic. If we no longer have any
1362 * active VLAN filters, we need to make all non-VLAN filters marked as VLAN=-1
1363 * so that they match against both tagged and untagged traffic. In this way,
1364 * we ensure that we correctly receive the desired traffic. This ensures that
1365 * when we have an active VLAN we will receive only untagged traffic and
1366 * traffic matching active VLANs. If we have no active VLANs then we will
1367 * operate in non-VLAN mode and receive all traffic, tagged or untagged.
1368 *
1369 * Finally, in a similar fashion, this function also corrects filters when
1370 * there is an active PVID assigned to this VSI.
1371 *
1372 * In case of memory allocation failure return -ENOMEM. Otherwise, return 0.
1373 *
1374 * This function is only expected to be called from within
1375 * i40e_sync_vsi_filters.
1376 *
1377 * NOTE: This function expects to be called while under the
1378 * mac_filter_hash_lock
1379 */
i40e_correct_mac_vlan_filters(struct i40e_vsi * vsi,struct hlist_head * tmp_add_list,struct hlist_head * tmp_del_list,int vlan_filters)1380 static int i40e_correct_mac_vlan_filters(struct i40e_vsi *vsi,
1381 struct hlist_head *tmp_add_list,
1382 struct hlist_head *tmp_del_list,
1383 int vlan_filters)
1384 {
1385 s16 pvid = le16_to_cpu(vsi->info.pvid);
1386 struct i40e_mac_filter *f, *add_head;
1387 struct i40e_new_mac_filter *new;
1388 struct hlist_node *h;
1389 int bkt, new_vlan;
1390
1391 /* To determine if a particular filter needs to be replaced we
1392 * have the three following conditions:
1393 *
1394 * a) if we have a PVID assigned, then all filters which are
1395 * not marked as VLAN=PVID must be replaced with filters that
1396 * are.
1397 * b) otherwise, if we have any active VLANS, all filters
1398 * which are marked as VLAN=-1 must be replaced with
1399 * filters marked as VLAN=0
1400 * c) finally, if we do not have any active VLANS, all filters
1401 * which are marked as VLAN=0 must be replaced with filters
1402 * marked as VLAN=-1
1403 */
1404
1405 /* Update the filters about to be added in place */
1406 hlist_for_each_entry(new, tmp_add_list, hlist) {
1407 if (pvid && new->f->vlan != pvid)
1408 new->f->vlan = pvid;
1409 else if (vlan_filters && new->f->vlan == I40E_VLAN_ANY)
1410 new->f->vlan = 0;
1411 else if (!vlan_filters && new->f->vlan == 0)
1412 new->f->vlan = I40E_VLAN_ANY;
1413 }
1414
1415 /* Update the remaining active filters */
1416 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
1417 /* Combine the checks for whether a filter needs to be changed
1418 * and then determine the new VLAN inside the if block, in
1419 * order to avoid duplicating code for adding the new filter
1420 * then deleting the old filter.
1421 */
1422 if ((pvid && f->vlan != pvid) ||
1423 (vlan_filters && f->vlan == I40E_VLAN_ANY) ||
1424 (!vlan_filters && f->vlan == 0)) {
1425 /* Determine the new vlan we will be adding */
1426 if (pvid)
1427 new_vlan = pvid;
1428 else if (vlan_filters)
1429 new_vlan = 0;
1430 else
1431 new_vlan = I40E_VLAN_ANY;
1432
1433 /* Create the new filter */
1434 add_head = i40e_add_filter(vsi, f->macaddr, new_vlan);
1435 if (!add_head)
1436 return -ENOMEM;
1437
1438 /* Create a temporary i40e_new_mac_filter */
1439 new = kzalloc(sizeof(*new), GFP_ATOMIC);
1440 if (!new)
1441 return -ENOMEM;
1442
1443 new->f = add_head;
1444 new->state = add_head->state;
1445
1446 /* Add the new filter to the tmp list */
1447 hlist_add_head(&new->hlist, tmp_add_list);
1448
1449 /* Put the original filter into the delete list */
1450 f->state = I40E_FILTER_REMOVE;
1451 hash_del(&f->hlist);
1452 hlist_add_head(&f->hlist, tmp_del_list);
1453 }
1454 }
1455
1456 vsi->has_vlan_filter = !!vlan_filters;
1457
1458 return 0;
1459 }
1460
1461 /**
1462 * i40e_get_vf_new_vlan - Get new vlan id on a vf
1463 * @vsi: the vsi to configure
1464 * @new_mac: new mac filter to be added
1465 * @f: existing mac filter, replaced with new_mac->f if new_mac is not NULL
1466 * @vlan_filters: the number of active VLAN filters
1467 * @trusted: flag if the VF is trusted
1468 *
1469 * Get new VLAN id based on current VLAN filters, trust, PVID
1470 * and vf-vlan-prune-disable flag.
1471 *
1472 * Returns the value of the new vlan filter or
1473 * the old value if no new filter is needed.
1474 */
i40e_get_vf_new_vlan(struct i40e_vsi * vsi,struct i40e_new_mac_filter * new_mac,struct i40e_mac_filter * f,int vlan_filters,bool trusted)1475 static s16 i40e_get_vf_new_vlan(struct i40e_vsi *vsi,
1476 struct i40e_new_mac_filter *new_mac,
1477 struct i40e_mac_filter *f,
1478 int vlan_filters,
1479 bool trusted)
1480 {
1481 s16 pvid = le16_to_cpu(vsi->info.pvid);
1482 struct i40e_pf *pf = vsi->back;
1483 bool is_any;
1484
1485 if (new_mac)
1486 f = new_mac->f;
1487
1488 if (pvid && f->vlan != pvid)
1489 return pvid;
1490
1491 is_any = (trusted ||
1492 !test_bit(I40E_FLAG_VF_VLAN_PRUNING_ENA, pf->flags));
1493
1494 if ((vlan_filters && f->vlan == I40E_VLAN_ANY) ||
1495 (!is_any && !vlan_filters && f->vlan == I40E_VLAN_ANY) ||
1496 (is_any && !vlan_filters && f->vlan == 0)) {
1497 if (is_any)
1498 return I40E_VLAN_ANY;
1499 else
1500 return 0;
1501 }
1502
1503 return f->vlan;
1504 }
1505
1506 /**
1507 * i40e_correct_vf_mac_vlan_filters - Correct non-VLAN VF filters if necessary
1508 * @vsi: the vsi to configure
1509 * @tmp_add_list: list of filters ready to be added
1510 * @tmp_del_list: list of filters ready to be deleted
1511 * @vlan_filters: the number of active VLAN filters
1512 * @trusted: flag if the VF is trusted
1513 *
1514 * Correct VF VLAN filters based on current VLAN filters, trust, PVID
1515 * and vf-vlan-prune-disable flag.
1516 *
1517 * In case of memory allocation failure return -ENOMEM. Otherwise, return 0.
1518 *
1519 * This function is only expected to be called from within
1520 * i40e_sync_vsi_filters.
1521 *
1522 * NOTE: This function expects to be called while under the
1523 * mac_filter_hash_lock
1524 */
i40e_correct_vf_mac_vlan_filters(struct i40e_vsi * vsi,struct hlist_head * tmp_add_list,struct hlist_head * tmp_del_list,int vlan_filters,bool trusted)1525 static int i40e_correct_vf_mac_vlan_filters(struct i40e_vsi *vsi,
1526 struct hlist_head *tmp_add_list,
1527 struct hlist_head *tmp_del_list,
1528 int vlan_filters,
1529 bool trusted)
1530 {
1531 struct i40e_mac_filter *f, *add_head;
1532 struct i40e_new_mac_filter *new_mac;
1533 struct hlist_node *h;
1534 int bkt, new_vlan;
1535
1536 hlist_for_each_entry(new_mac, tmp_add_list, hlist) {
1537 new_mac->f->vlan = i40e_get_vf_new_vlan(vsi, new_mac, NULL,
1538 vlan_filters, trusted);
1539 }
1540
1541 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
1542 new_vlan = i40e_get_vf_new_vlan(vsi, NULL, f, vlan_filters,
1543 trusted);
1544 if (new_vlan != f->vlan) {
1545 add_head = i40e_add_filter(vsi, f->macaddr, new_vlan);
1546 if (!add_head)
1547 return -ENOMEM;
1548 /* Create a temporary i40e_new_mac_filter */
1549 new_mac = kzalloc(sizeof(*new_mac), GFP_ATOMIC);
1550 if (!new_mac)
1551 return -ENOMEM;
1552 new_mac->f = add_head;
1553 new_mac->state = add_head->state;
1554
1555 /* Add the new filter to the tmp list */
1556 hlist_add_head(&new_mac->hlist, tmp_add_list);
1557
1558 /* Put the original filter into the delete list */
1559 f->state = I40E_FILTER_REMOVE;
1560 hash_del(&f->hlist);
1561 hlist_add_head(&f->hlist, tmp_del_list);
1562 }
1563 }
1564
1565 vsi->has_vlan_filter = !!vlan_filters;
1566 return 0;
1567 }
1568
1569 /**
1570 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1571 * @vsi: the PF Main VSI - inappropriate for any other VSI
1572 * @macaddr: the MAC address
1573 *
1574 * Remove whatever filter the firmware set up so the driver can manage
1575 * its own filtering intelligently.
1576 **/
i40e_rm_default_mac_filter(struct i40e_vsi * vsi,u8 * macaddr)1577 static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
1578 {
1579 struct i40e_aqc_remove_macvlan_element_data element;
1580 struct i40e_pf *pf = vsi->back;
1581
1582 /* Only appropriate for the PF main VSI */
1583 if (vsi->type != I40E_VSI_MAIN)
1584 return;
1585
1586 memset(&element, 0, sizeof(element));
1587 ether_addr_copy(element.mac_addr, macaddr);
1588 element.vlan_tag = 0;
1589 /* Ignore error returns, some firmware does it this way... */
1590 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1591 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1592
1593 memset(&element, 0, sizeof(element));
1594 ether_addr_copy(element.mac_addr, macaddr);
1595 element.vlan_tag = 0;
1596 /* ...and some firmware does it this way. */
1597 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1598 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1599 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1600 }
1601
1602 /**
1603 * i40e_add_filter - Add a mac/vlan filter to the VSI
1604 * @vsi: the VSI to be searched
1605 * @macaddr: the MAC address
1606 * @vlan: the vlan
1607 *
1608 * Returns ptr to the filter object or NULL when no memory available.
1609 *
1610 * NOTE: This function is expected to be called with mac_filter_hash_lock
1611 * being held.
1612 **/
i40e_add_filter(struct i40e_vsi * vsi,const u8 * macaddr,s16 vlan)1613 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1614 const u8 *macaddr, s16 vlan)
1615 {
1616 struct i40e_mac_filter *f;
1617 u64 key;
1618
1619 if (!vsi || !macaddr)
1620 return NULL;
1621
1622 f = i40e_find_filter(vsi, macaddr, vlan);
1623 if (!f) {
1624 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1625 if (!f)
1626 return NULL;
1627
1628 /* Update the boolean indicating if we need to function in
1629 * VLAN mode.
1630 */
1631 if (vlan >= 0)
1632 vsi->has_vlan_filter = true;
1633
1634 ether_addr_copy(f->macaddr, macaddr);
1635 f->vlan = vlan;
1636 f->state = I40E_FILTER_NEW;
1637 INIT_HLIST_NODE(&f->hlist);
1638
1639 key = i40e_addr_to_hkey(macaddr);
1640 hash_add(vsi->mac_filter_hash, &f->hlist, key);
1641
1642 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1643 set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state);
1644 }
1645
1646 /* If we're asked to add a filter that has been marked for removal, it
1647 * is safe to simply restore it to active state. __i40e_del_filter
1648 * will have simply deleted any filters which were previously marked
1649 * NEW or FAILED, so if it is currently marked REMOVE it must have
1650 * previously been ACTIVE. Since we haven't yet run the sync filters
1651 * task, just restore this filter to the ACTIVE state so that the
1652 * sync task leaves it in place
1653 */
1654 if (f->state == I40E_FILTER_REMOVE)
1655 f->state = I40E_FILTER_ACTIVE;
1656
1657 return f;
1658 }
1659
1660 /**
1661 * __i40e_del_filter - Remove a specific filter from the VSI
1662 * @vsi: VSI to remove from
1663 * @f: the filter to remove from the list
1664 *
1665 * This function should be called instead of i40e_del_filter only if you know
1666 * the exact filter you will remove already, such as via i40e_find_filter or
1667 * i40e_find_mac.
1668 *
1669 * NOTE: This function is expected to be called with mac_filter_hash_lock
1670 * being held.
1671 * ANOTHER NOTE: This function MUST be called from within the context of
1672 * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe()
1673 * instead of list_for_each_entry().
1674 **/
__i40e_del_filter(struct i40e_vsi * vsi,struct i40e_mac_filter * f)1675 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f)
1676 {
1677 if (!f)
1678 return;
1679
1680 /* If the filter was never added to firmware then we can just delete it
1681 * directly and we don't want to set the status to remove or else an
1682 * admin queue command will unnecessarily fire.
1683 */
1684 if ((f->state == I40E_FILTER_FAILED) ||
1685 (f->state == I40E_FILTER_NEW)) {
1686 hash_del(&f->hlist);
1687 kfree(f);
1688 } else {
1689 f->state = I40E_FILTER_REMOVE;
1690 }
1691
1692 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1693 set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state);
1694 }
1695
1696 /**
1697 * i40e_del_filter - Remove a MAC/VLAN filter from the VSI
1698 * @vsi: the VSI to be searched
1699 * @macaddr: the MAC address
1700 * @vlan: the VLAN
1701 *
1702 * NOTE: This function is expected to be called with mac_filter_hash_lock
1703 * being held.
1704 * ANOTHER NOTE: This function MUST be called from within the context of
1705 * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe()
1706 * instead of list_for_each_entry().
1707 **/
i40e_del_filter(struct i40e_vsi * vsi,const u8 * macaddr,s16 vlan)1708 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan)
1709 {
1710 struct i40e_mac_filter *f;
1711
1712 if (!vsi || !macaddr)
1713 return;
1714
1715 f = i40e_find_filter(vsi, macaddr, vlan);
1716 __i40e_del_filter(vsi, f);
1717 }
1718
1719 /**
1720 * i40e_add_mac_filter - Add a MAC filter for all active VLANs
1721 * @vsi: the VSI to be searched
1722 * @macaddr: the mac address to be filtered
1723 *
1724 * If we're not in VLAN mode, just add the filter to I40E_VLAN_ANY. Otherwise,
1725 * go through all the macvlan filters and add a macvlan filter for each
1726 * unique vlan that already exists. If a PVID has been assigned, instead only
1727 * add the macaddr to that VLAN.
1728 *
1729 * Returns last filter added on success, else NULL
1730 **/
i40e_add_mac_filter(struct i40e_vsi * vsi,const u8 * macaddr)1731 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1732 const u8 *macaddr)
1733 {
1734 struct i40e_mac_filter *f, *add = NULL;
1735 struct hlist_node *h;
1736 int bkt;
1737
1738 if (vsi->info.pvid)
1739 return i40e_add_filter(vsi, macaddr,
1740 le16_to_cpu(vsi->info.pvid));
1741
1742 if (!i40e_is_vsi_in_vlan(vsi))
1743 return i40e_add_filter(vsi, macaddr, I40E_VLAN_ANY);
1744
1745 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
1746 if (f->state == I40E_FILTER_REMOVE)
1747 continue;
1748 add = i40e_add_filter(vsi, macaddr, f->vlan);
1749 if (!add)
1750 return NULL;
1751 }
1752
1753 return add;
1754 }
1755
1756 /**
1757 * i40e_del_mac_filter - Remove a MAC filter from all VLANs
1758 * @vsi: the VSI to be searched
1759 * @macaddr: the mac address to be removed
1760 *
1761 * Removes a given MAC address from a VSI regardless of what VLAN it has been
1762 * associated with.
1763 *
1764 * Returns 0 for success, or error
1765 **/
i40e_del_mac_filter(struct i40e_vsi * vsi,const u8 * macaddr)1766 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr)
1767 {
1768 struct i40e_mac_filter *f;
1769 struct hlist_node *h;
1770 bool found = false;
1771 int bkt;
1772
1773 lockdep_assert_held(&vsi->mac_filter_hash_lock);
1774 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
1775 if (ether_addr_equal(macaddr, f->macaddr)) {
1776 __i40e_del_filter(vsi, f);
1777 found = true;
1778 }
1779 }
1780
1781 if (found)
1782 return 0;
1783 else
1784 return -ENOENT;
1785 }
1786
1787 /**
1788 * i40e_set_mac - NDO callback to set mac address
1789 * @netdev: network interface device structure
1790 * @p: pointer to an address structure
1791 *
1792 * Returns 0 on success, negative on failure
1793 **/
i40e_set_mac(struct net_device * netdev,void * p)1794 static int i40e_set_mac(struct net_device *netdev, void *p)
1795 {
1796 struct i40e_netdev_priv *np = netdev_priv(netdev);
1797 struct i40e_vsi *vsi = np->vsi;
1798 struct i40e_pf *pf = vsi->back;
1799 struct i40e_hw *hw = &pf->hw;
1800 struct sockaddr *addr = p;
1801
1802 if (!is_valid_ether_addr(addr->sa_data))
1803 return -EADDRNOTAVAIL;
1804
1805 if (test_bit(__I40E_DOWN, pf->state) ||
1806 test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
1807 return -EADDRNOTAVAIL;
1808
1809 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1810 netdev_info(netdev, "returning to hw mac address %pM\n",
1811 hw->mac.addr);
1812 else
1813 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1814
1815 /* Copy the address first, so that we avoid a possible race with
1816 * .set_rx_mode().
1817 * - Remove old address from MAC filter
1818 * - Copy new address
1819 * - Add new address to MAC filter
1820 */
1821 spin_lock_bh(&vsi->mac_filter_hash_lock);
1822 i40e_del_mac_filter(vsi, netdev->dev_addr);
1823 eth_hw_addr_set(netdev, addr->sa_data);
1824 i40e_add_mac_filter(vsi, netdev->dev_addr);
1825 spin_unlock_bh(&vsi->mac_filter_hash_lock);
1826
1827 if (vsi->type == I40E_VSI_MAIN) {
1828 int ret;
1829
1830 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
1831 addr->sa_data, NULL);
1832 if (ret)
1833 netdev_info(netdev, "Ignoring error from firmware on LAA update, status %pe, AQ ret %s\n",
1834 ERR_PTR(ret),
1835 i40e_aq_str(hw, hw->aq.asq_last_status));
1836 }
1837
1838 /* schedule our worker thread which will take care of
1839 * applying the new filter changes
1840 */
1841 i40e_service_event_schedule(pf);
1842 return 0;
1843 }
1844
1845 /**
1846 * i40e_config_rss_aq - Prepare for RSS using AQ commands
1847 * @vsi: vsi structure
1848 * @seed: RSS hash seed
1849 * @lut: pointer to lookup table of lut_size
1850 * @lut_size: size of the lookup table
1851 **/
i40e_config_rss_aq(struct i40e_vsi * vsi,const u8 * seed,u8 * lut,u16 lut_size)1852 static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
1853 u8 *lut, u16 lut_size)
1854 {
1855 struct i40e_pf *pf = vsi->back;
1856 struct i40e_hw *hw = &pf->hw;
1857 int ret = 0;
1858
1859 if (seed) {
1860 struct i40e_aqc_get_set_rss_key_data *seed_dw =
1861 (struct i40e_aqc_get_set_rss_key_data *)seed;
1862 ret = i40e_aq_set_rss_key(hw, vsi->id, seed_dw);
1863 if (ret) {
1864 dev_info(&pf->pdev->dev,
1865 "Cannot set RSS key, err %pe aq_err %s\n",
1866 ERR_PTR(ret),
1867 i40e_aq_str(hw, hw->aq.asq_last_status));
1868 return ret;
1869 }
1870 }
1871 if (lut) {
1872 bool pf_lut = vsi->type == I40E_VSI_MAIN;
1873
1874 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
1875 if (ret) {
1876 dev_info(&pf->pdev->dev,
1877 "Cannot set RSS lut, err %pe aq_err %s\n",
1878 ERR_PTR(ret),
1879 i40e_aq_str(hw, hw->aq.asq_last_status));
1880 return ret;
1881 }
1882 }
1883 return ret;
1884 }
1885
1886 /**
1887 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
1888 * @vsi: VSI structure
1889 **/
i40e_vsi_config_rss(struct i40e_vsi * vsi)1890 static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
1891 {
1892 struct i40e_pf *pf = vsi->back;
1893 u8 seed[I40E_HKEY_ARRAY_SIZE];
1894 u8 *lut;
1895 int ret;
1896
1897 if (!test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps))
1898 return 0;
1899 if (!vsi->rss_size)
1900 vsi->rss_size = min_t(int, pf->alloc_rss_size,
1901 vsi->num_queue_pairs);
1902 if (!vsi->rss_size)
1903 return -EINVAL;
1904 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
1905 if (!lut)
1906 return -ENOMEM;
1907
1908 /* Use the user configured hash keys and lookup table if there is one,
1909 * otherwise use default
1910 */
1911 if (vsi->rss_lut_user)
1912 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1913 else
1914 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
1915 if (vsi->rss_hkey_user)
1916 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
1917 else
1918 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
1919 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
1920 kfree(lut);
1921 return ret;
1922 }
1923
1924 /**
1925 * i40e_vsi_setup_queue_map_mqprio - Prepares mqprio based tc_config
1926 * @vsi: the VSI being configured,
1927 * @ctxt: VSI context structure
1928 * @enabled_tc: number of traffic classes to enable
1929 *
1930 * Prepares VSI tc_config to have queue configurations based on MQPRIO options.
1931 **/
i40e_vsi_setup_queue_map_mqprio(struct i40e_vsi * vsi,struct i40e_vsi_context * ctxt,u8 enabled_tc)1932 static int i40e_vsi_setup_queue_map_mqprio(struct i40e_vsi *vsi,
1933 struct i40e_vsi_context *ctxt,
1934 u8 enabled_tc)
1935 {
1936 u16 qcount = 0, max_qcount, qmap, sections = 0;
1937 int i, override_q, pow, num_qps, ret;
1938 u8 netdev_tc = 0, offset = 0;
1939
1940 if (vsi->type != I40E_VSI_MAIN)
1941 return -EINVAL;
1942 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1943 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1944 vsi->tc_config.numtc = vsi->mqprio_qopt.qopt.num_tc;
1945 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1946 num_qps = vsi->mqprio_qopt.qopt.count[0];
1947
1948 /* find the next higher power-of-2 of num queue pairs */
1949 pow = ilog2(num_qps);
1950 if (!is_power_of_2(num_qps))
1951 pow++;
1952 qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1953 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1954
1955 /* Setup queue offset/count for all TCs for given VSI */
1956 max_qcount = vsi->mqprio_qopt.qopt.count[0];
1957 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1958 /* See if the given TC is enabled for the given VSI */
1959 if (vsi->tc_config.enabled_tc & BIT(i)) {
1960 offset = vsi->mqprio_qopt.qopt.offset[i];
1961 qcount = vsi->mqprio_qopt.qopt.count[i];
1962 if (qcount > max_qcount)
1963 max_qcount = qcount;
1964 vsi->tc_config.tc_info[i].qoffset = offset;
1965 vsi->tc_config.tc_info[i].qcount = qcount;
1966 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1967 } else {
1968 /* TC is not enabled so set the offset to
1969 * default queue and allocate one queue
1970 * for the given TC.
1971 */
1972 vsi->tc_config.tc_info[i].qoffset = 0;
1973 vsi->tc_config.tc_info[i].qcount = 1;
1974 vsi->tc_config.tc_info[i].netdev_tc = 0;
1975 }
1976 }
1977
1978 /* Set actual Tx/Rx queue pairs */
1979 vsi->num_queue_pairs = offset + qcount;
1980
1981 /* Setup queue TC[0].qmap for given VSI context */
1982 ctxt->info.tc_mapping[0] = cpu_to_le16(qmap);
1983 ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1984 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1985 ctxt->info.valid_sections |= cpu_to_le16(sections);
1986
1987 /* Reconfigure RSS for main VSI with max queue count */
1988 vsi->rss_size = max_qcount;
1989 ret = i40e_vsi_config_rss(vsi);
1990 if (ret) {
1991 dev_info(&vsi->back->pdev->dev,
1992 "Failed to reconfig rss for num_queues (%u)\n",
1993 max_qcount);
1994 return ret;
1995 }
1996 vsi->reconfig_rss = true;
1997 dev_dbg(&vsi->back->pdev->dev,
1998 "Reconfigured rss with num_queues (%u)\n", max_qcount);
1999
2000 /* Find queue count available for channel VSIs and starting offset
2001 * for channel VSIs
2002 */
2003 override_q = vsi->mqprio_qopt.qopt.count[0];
2004 if (override_q && override_q < vsi->num_queue_pairs) {
2005 vsi->cnt_q_avail = vsi->num_queue_pairs - override_q;
2006 vsi->next_base_queue = override_q;
2007 }
2008 return 0;
2009 }
2010
2011 /**
2012 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
2013 * @vsi: the VSI being setup
2014 * @ctxt: VSI context structure
2015 * @enabled_tc: Enabled TCs bitmap
2016 * @is_add: True if called before Add VSI
2017 *
2018 * Setup VSI queue mapping for enabled traffic classes.
2019 **/
i40e_vsi_setup_queue_map(struct i40e_vsi * vsi,struct i40e_vsi_context * ctxt,u8 enabled_tc,bool is_add)2020 static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
2021 struct i40e_vsi_context *ctxt,
2022 u8 enabled_tc,
2023 bool is_add)
2024 {
2025 struct i40e_pf *pf = vsi->back;
2026 u16 num_tc_qps = 0;
2027 u16 sections = 0;
2028 u8 netdev_tc = 0;
2029 u16 numtc = 1;
2030 u16 qcount;
2031 u8 offset;
2032 u16 qmap;
2033 int i;
2034
2035 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
2036 offset = 0;
2037 /* zero out queue mapping, it will get updated on the end of the function */
2038 memset(ctxt->info.queue_mapping, 0, sizeof(ctxt->info.queue_mapping));
2039
2040 if (vsi->type == I40E_VSI_MAIN) {
2041 /* This code helps add more queue to the VSI if we have
2042 * more cores than RSS can support, the higher cores will
2043 * be served by ATR or other filters. Furthermore, the
2044 * non-zero req_queue_pairs says that user requested a new
2045 * queue count via ethtool's set_channels, so use this
2046 * value for queues distribution across traffic classes
2047 * We need at least one queue pair for the interface
2048 * to be usable as we see in else statement.
2049 */
2050 if (vsi->req_queue_pairs > 0)
2051 vsi->num_queue_pairs = vsi->req_queue_pairs;
2052 else if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
2053 vsi->num_queue_pairs = pf->num_lan_msix;
2054 else
2055 vsi->num_queue_pairs = 1;
2056 }
2057
2058 /* Number of queues per enabled TC */
2059 if (vsi->type == I40E_VSI_MAIN ||
2060 (vsi->type == I40E_VSI_SRIOV && vsi->num_queue_pairs != 0))
2061 num_tc_qps = vsi->num_queue_pairs;
2062 else
2063 num_tc_qps = vsi->alloc_queue_pairs;
2064
2065 if (enabled_tc && test_bit(I40E_FLAG_DCB_ENA, vsi->back->flags)) {
2066 /* Find numtc from enabled TC bitmap */
2067 for (i = 0, numtc = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2068 if (enabled_tc & BIT(i)) /* TC is enabled */
2069 numtc++;
2070 }
2071 if (!numtc) {
2072 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
2073 numtc = 1;
2074 }
2075 num_tc_qps = num_tc_qps / numtc;
2076 num_tc_qps = min_t(int, num_tc_qps,
2077 i40e_pf_get_max_q_per_tc(pf));
2078 }
2079
2080 vsi->tc_config.numtc = numtc;
2081 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
2082
2083 /* Do not allow use more TC queue pairs than MSI-X vectors exist */
2084 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
2085 num_tc_qps = min_t(int, num_tc_qps, pf->num_lan_msix);
2086
2087 /* Setup queue offset/count for all TCs for given VSI */
2088 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2089 /* See if the given TC is enabled for the given VSI */
2090 if (vsi->tc_config.enabled_tc & BIT(i)) {
2091 /* TC is enabled */
2092 int pow, num_qps;
2093
2094 switch (vsi->type) {
2095 case I40E_VSI_MAIN:
2096 if ((!test_bit(I40E_FLAG_FD_SB_ENA,
2097 pf->flags) &&
2098 !test_bit(I40E_FLAG_FD_ATR_ENA,
2099 pf->flags)) ||
2100 vsi->tc_config.enabled_tc != 1) {
2101 qcount = min_t(int, pf->alloc_rss_size,
2102 num_tc_qps);
2103 break;
2104 }
2105 fallthrough;
2106 case I40E_VSI_FDIR:
2107 case I40E_VSI_SRIOV:
2108 case I40E_VSI_VMDQ2:
2109 default:
2110 qcount = num_tc_qps;
2111 WARN_ON(i != 0);
2112 break;
2113 }
2114 vsi->tc_config.tc_info[i].qoffset = offset;
2115 vsi->tc_config.tc_info[i].qcount = qcount;
2116
2117 /* find the next higher power-of-2 of num queue pairs */
2118 num_qps = qcount;
2119 pow = 0;
2120 while (num_qps && (BIT_ULL(pow) < qcount)) {
2121 pow++;
2122 num_qps >>= 1;
2123 }
2124
2125 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
2126 qmap =
2127 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2128 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
2129
2130 offset += qcount;
2131 } else {
2132 /* TC is not enabled so set the offset to
2133 * default queue and allocate one queue
2134 * for the given TC.
2135 */
2136 vsi->tc_config.tc_info[i].qoffset = 0;
2137 vsi->tc_config.tc_info[i].qcount = 1;
2138 vsi->tc_config.tc_info[i].netdev_tc = 0;
2139
2140 qmap = 0;
2141 }
2142 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
2143 }
2144 /* Do not change previously set num_queue_pairs for PFs and VFs*/
2145 if ((vsi->type == I40E_VSI_MAIN && numtc != 1) ||
2146 (vsi->type == I40E_VSI_SRIOV && vsi->num_queue_pairs == 0) ||
2147 (vsi->type != I40E_VSI_MAIN && vsi->type != I40E_VSI_SRIOV))
2148 vsi->num_queue_pairs = offset;
2149
2150 /* Scheduler section valid can only be set for ADD VSI */
2151 if (is_add) {
2152 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
2153
2154 ctxt->info.up_enable_bits = enabled_tc;
2155 }
2156 if (vsi->type == I40E_VSI_SRIOV) {
2157 ctxt->info.mapping_flags |=
2158 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2159 for (i = 0; i < vsi->num_queue_pairs; i++)
2160 ctxt->info.queue_mapping[i] =
2161 cpu_to_le16(vsi->base_queue + i);
2162 } else {
2163 ctxt->info.mapping_flags |=
2164 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2165 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
2166 }
2167 ctxt->info.valid_sections |= cpu_to_le16(sections);
2168 }
2169
2170 /**
2171 * i40e_addr_sync - Callback for dev_(mc|uc)_sync to add address
2172 * @netdev: the netdevice
2173 * @addr: address to add
2174 *
2175 * Called by __dev_(mc|uc)_sync when an address needs to be added. We call
2176 * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock.
2177 */
i40e_addr_sync(struct net_device * netdev,const u8 * addr)2178 static int i40e_addr_sync(struct net_device *netdev, const u8 *addr)
2179 {
2180 struct i40e_netdev_priv *np = netdev_priv(netdev);
2181 struct i40e_vsi *vsi = np->vsi;
2182
2183 if (i40e_add_mac_filter(vsi, addr))
2184 return 0;
2185 else
2186 return -ENOMEM;
2187 }
2188
2189 /**
2190 * i40e_addr_unsync - Callback for dev_(mc|uc)_sync to remove address
2191 * @netdev: the netdevice
2192 * @addr: address to add
2193 *
2194 * Called by __dev_(mc|uc)_sync when an address needs to be removed. We call
2195 * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock.
2196 */
i40e_addr_unsync(struct net_device * netdev,const u8 * addr)2197 static int i40e_addr_unsync(struct net_device *netdev, const u8 *addr)
2198 {
2199 struct i40e_netdev_priv *np = netdev_priv(netdev);
2200 struct i40e_vsi *vsi = np->vsi;
2201
2202 /* Under some circumstances, we might receive a request to delete
2203 * our own device address from our uc list. Because we store the
2204 * device address in the VSI's MAC/VLAN filter list, we need to ignore
2205 * such requests and not delete our device address from this list.
2206 */
2207 if (ether_addr_equal(addr, netdev->dev_addr))
2208 return 0;
2209
2210 i40e_del_mac_filter(vsi, addr);
2211
2212 return 0;
2213 }
2214
2215 /**
2216 * i40e_set_rx_mode - NDO callback to set the netdev filters
2217 * @netdev: network interface device structure
2218 **/
i40e_set_rx_mode(struct net_device * netdev)2219 static void i40e_set_rx_mode(struct net_device *netdev)
2220 {
2221 struct i40e_netdev_priv *np = netdev_priv(netdev);
2222 struct i40e_vsi *vsi = np->vsi;
2223
2224 spin_lock_bh(&vsi->mac_filter_hash_lock);
2225
2226 __dev_uc_sync(netdev, i40e_addr_sync, i40e_addr_unsync);
2227 __dev_mc_sync(netdev, i40e_addr_sync, i40e_addr_unsync);
2228
2229 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2230
2231 /* check for other flag changes */
2232 if (vsi->current_netdev_flags != vsi->netdev->flags) {
2233 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2234 set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state);
2235 }
2236 }
2237
2238 /**
2239 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
2240 * @vsi: Pointer to VSI struct
2241 * @from: Pointer to list which contains MAC filter entries - changes to
2242 * those entries needs to be undone.
2243 *
2244 * MAC filter entries from this list were slated for deletion.
2245 **/
i40e_undo_del_filter_entries(struct i40e_vsi * vsi,struct hlist_head * from)2246 static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
2247 struct hlist_head *from)
2248 {
2249 struct i40e_mac_filter *f;
2250 struct hlist_node *h;
2251
2252 hlist_for_each_entry_safe(f, h, from, hlist) {
2253 u64 key = i40e_addr_to_hkey(f->macaddr);
2254
2255 /* Move the element back into MAC filter list*/
2256 hlist_del(&f->hlist);
2257 hash_add(vsi->mac_filter_hash, &f->hlist, key);
2258 }
2259 }
2260
2261 /**
2262 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
2263 * @vsi: Pointer to vsi struct
2264 * @from: Pointer to list which contains MAC filter entries - changes to
2265 * those entries needs to be undone.
2266 *
2267 * MAC filter entries from this list were slated for addition.
2268 **/
i40e_undo_add_filter_entries(struct i40e_vsi * vsi,struct hlist_head * from)2269 static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi,
2270 struct hlist_head *from)
2271 {
2272 struct i40e_new_mac_filter *new;
2273 struct hlist_node *h;
2274
2275 hlist_for_each_entry_safe(new, h, from, hlist) {
2276 /* We can simply free the wrapper structure */
2277 hlist_del(&new->hlist);
2278 netdev_hw_addr_refcnt(new->f, vsi->netdev, -1);
2279 kfree(new);
2280 }
2281 }
2282
2283 /**
2284 * i40e_next_filter - Get the next non-broadcast filter from a list
2285 * @next: pointer to filter in list
2286 *
2287 * Returns the next non-broadcast filter in the list. Required so that we
2288 * ignore broadcast filters within the list, since these are not handled via
2289 * the normal firmware update path.
2290 */
2291 static
i40e_next_filter(struct i40e_new_mac_filter * next)2292 struct i40e_new_mac_filter *i40e_next_filter(struct i40e_new_mac_filter *next)
2293 {
2294 hlist_for_each_entry_continue(next, hlist) {
2295 if (!is_broadcast_ether_addr(next->f->macaddr))
2296 return next;
2297 }
2298
2299 return NULL;
2300 }
2301
2302 /**
2303 * i40e_update_filter_state - Update filter state based on return data
2304 * from firmware
2305 * @count: Number of filters added
2306 * @add_list: return data from fw
2307 * @add_head: pointer to first filter in current batch
2308 *
2309 * MAC filter entries from list were slated to be added to device. Returns
2310 * number of successful filters. Note that 0 does NOT mean success!
2311 **/
2312 static int
i40e_update_filter_state(int count,struct i40e_aqc_add_macvlan_element_data * add_list,struct i40e_new_mac_filter * add_head)2313 i40e_update_filter_state(int count,
2314 struct i40e_aqc_add_macvlan_element_data *add_list,
2315 struct i40e_new_mac_filter *add_head)
2316 {
2317 int retval = 0;
2318 int i;
2319
2320 for (i = 0; i < count; i++) {
2321 /* Always check status of each filter. We don't need to check
2322 * the firmware return status because we pre-set the filter
2323 * status to I40E_AQC_MM_ERR_NO_RES when sending the filter
2324 * request to the adminq. Thus, if it no longer matches then
2325 * we know the filter is active.
2326 */
2327 if (add_list[i].match_method == I40E_AQC_MM_ERR_NO_RES) {
2328 add_head->state = I40E_FILTER_FAILED;
2329 } else {
2330 add_head->state = I40E_FILTER_ACTIVE;
2331 retval++;
2332 }
2333
2334 add_head = i40e_next_filter(add_head);
2335 if (!add_head)
2336 break;
2337 }
2338
2339 return retval;
2340 }
2341
2342 /**
2343 * i40e_aqc_del_filters - Request firmware to delete a set of filters
2344 * @vsi: ptr to the VSI
2345 * @vsi_name: name to display in messages
2346 * @list: the list of filters to send to firmware
2347 * @num_del: the number of filters to delete
2348 * @retval: Set to -EIO on failure to delete
2349 *
2350 * Send a request to firmware via AdminQ to delete a set of filters. Uses
2351 * *retval instead of a return value so that success does not force ret_val to
2352 * be set to 0. This ensures that a sequence of calls to this function
2353 * preserve the previous value of *retval on successful delete.
2354 */
2355 static
i40e_aqc_del_filters(struct i40e_vsi * vsi,const char * vsi_name,struct i40e_aqc_remove_macvlan_element_data * list,int num_del,int * retval)2356 void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name,
2357 struct i40e_aqc_remove_macvlan_element_data *list,
2358 int num_del, int *retval)
2359 {
2360 struct i40e_hw *hw = &vsi->back->hw;
2361 enum i40e_admin_queue_err aq_status;
2362 int aq_ret;
2363
2364 aq_ret = i40e_aq_remove_macvlan_v2(hw, vsi->seid, list, num_del, NULL,
2365 &aq_status);
2366
2367 /* Explicitly ignore and do not report when firmware returns ENOENT */
2368 if (aq_ret && !(aq_status == I40E_AQ_RC_ENOENT)) {
2369 *retval = -EIO;
2370 dev_info(&vsi->back->pdev->dev,
2371 "ignoring delete macvlan error on %s, err %pe, aq_err %s\n",
2372 vsi_name, ERR_PTR(aq_ret),
2373 i40e_aq_str(hw, aq_status));
2374 }
2375 }
2376
2377 /**
2378 * i40e_aqc_add_filters - Request firmware to add a set of filters
2379 * @vsi: ptr to the VSI
2380 * @vsi_name: name to display in messages
2381 * @list: the list of filters to send to firmware
2382 * @add_head: Position in the add hlist
2383 * @num_add: the number of filters to add
2384 *
2385 * Send a request to firmware via AdminQ to add a chunk of filters. Will set
2386 * __I40E_VSI_OVERFLOW_PROMISC bit in vsi->state if the firmware has run out of
2387 * space for more filters.
2388 */
2389 static
i40e_aqc_add_filters(struct i40e_vsi * vsi,const char * vsi_name,struct i40e_aqc_add_macvlan_element_data * list,struct i40e_new_mac_filter * add_head,int num_add)2390 void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name,
2391 struct i40e_aqc_add_macvlan_element_data *list,
2392 struct i40e_new_mac_filter *add_head,
2393 int num_add)
2394 {
2395 struct i40e_hw *hw = &vsi->back->hw;
2396 enum i40e_admin_queue_err aq_status;
2397 int fcnt;
2398
2399 i40e_aq_add_macvlan_v2(hw, vsi->seid, list, num_add, NULL, &aq_status);
2400 fcnt = i40e_update_filter_state(num_add, list, add_head);
2401
2402 if (fcnt != num_add) {
2403 if (vsi->type == I40E_VSI_MAIN) {
2404 set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2405 dev_warn(&vsi->back->pdev->dev,
2406 "Error %s adding RX filters on %s, promiscuous mode forced on\n",
2407 i40e_aq_str(hw, aq_status), vsi_name);
2408 } else if (vsi->type == I40E_VSI_SRIOV ||
2409 vsi->type == I40E_VSI_VMDQ1 ||
2410 vsi->type == I40E_VSI_VMDQ2) {
2411 dev_warn(&vsi->back->pdev->dev,
2412 "Error %s adding RX filters on %s, please set promiscuous on manually for %s\n",
2413 i40e_aq_str(hw, aq_status), vsi_name,
2414 vsi_name);
2415 } else {
2416 dev_warn(&vsi->back->pdev->dev,
2417 "Error %s adding RX filters on %s, incorrect VSI type: %i.\n",
2418 i40e_aq_str(hw, aq_status), vsi_name,
2419 vsi->type);
2420 }
2421 }
2422 }
2423
2424 /**
2425 * i40e_aqc_broadcast_filter - Set promiscuous broadcast flags
2426 * @vsi: pointer to the VSI
2427 * @vsi_name: the VSI name
2428 * @f: filter data
2429 *
2430 * This function sets or clears the promiscuous broadcast flags for VLAN
2431 * filters in order to properly receive broadcast frames. Assumes that only
2432 * broadcast filters are passed.
2433 *
2434 * Returns status indicating success or failure;
2435 **/
2436 static int
i40e_aqc_broadcast_filter(struct i40e_vsi * vsi,const char * vsi_name,struct i40e_mac_filter * f)2437 i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name,
2438 struct i40e_mac_filter *f)
2439 {
2440 bool enable = f->state == I40E_FILTER_NEW;
2441 struct i40e_hw *hw = &vsi->back->hw;
2442 int aq_ret;
2443
2444 if (f->vlan == I40E_VLAN_ANY) {
2445 aq_ret = i40e_aq_set_vsi_broadcast(hw,
2446 vsi->seid,
2447 enable,
2448 NULL);
2449 } else {
2450 aq_ret = i40e_aq_set_vsi_bc_promisc_on_vlan(hw,
2451 vsi->seid,
2452 enable,
2453 f->vlan,
2454 NULL);
2455 }
2456
2457 if (aq_ret) {
2458 set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2459 dev_warn(&vsi->back->pdev->dev,
2460 "Error %s, forcing overflow promiscuous on %s\n",
2461 i40e_aq_str(hw, hw->aq.asq_last_status),
2462 vsi_name);
2463 }
2464
2465 return aq_ret;
2466 }
2467
2468 /**
2469 * i40e_set_promiscuous - set promiscuous mode
2470 * @pf: board private structure
2471 * @promisc: promisc on or off
2472 *
2473 * There are different ways of setting promiscuous mode on a PF depending on
2474 * what state/environment we're in. This identifies and sets it appropriately.
2475 * Returns 0 on success.
2476 **/
i40e_set_promiscuous(struct i40e_pf * pf,bool promisc)2477 static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc)
2478 {
2479 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
2480 struct i40e_hw *hw = &pf->hw;
2481 int aq_ret;
2482
2483 if (vsi->type == I40E_VSI_MAIN &&
2484 pf->lan_veb != I40E_NO_VEB &&
2485 !test_bit(I40E_FLAG_MFP_ENA, pf->flags)) {
2486 /* set defport ON for Main VSI instead of true promisc
2487 * this way we will get all unicast/multicast and VLAN
2488 * promisc behavior but will not get VF or VMDq traffic
2489 * replicated on the Main VSI.
2490 */
2491 if (promisc)
2492 aq_ret = i40e_aq_set_default_vsi(hw,
2493 vsi->seid,
2494 NULL);
2495 else
2496 aq_ret = i40e_aq_clear_default_vsi(hw,
2497 vsi->seid,
2498 NULL);
2499 if (aq_ret) {
2500 dev_info(&pf->pdev->dev,
2501 "Set default VSI failed, err %pe, aq_err %s\n",
2502 ERR_PTR(aq_ret),
2503 i40e_aq_str(hw, hw->aq.asq_last_status));
2504 }
2505 } else {
2506 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
2507 hw,
2508 vsi->seid,
2509 promisc, NULL,
2510 true);
2511 if (aq_ret) {
2512 dev_info(&pf->pdev->dev,
2513 "set unicast promisc failed, err %pe, aq_err %s\n",
2514 ERR_PTR(aq_ret),
2515 i40e_aq_str(hw, hw->aq.asq_last_status));
2516 }
2517 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
2518 hw,
2519 vsi->seid,
2520 promisc, NULL);
2521 if (aq_ret) {
2522 dev_info(&pf->pdev->dev,
2523 "set multicast promisc failed, err %pe, aq_err %s\n",
2524 ERR_PTR(aq_ret),
2525 i40e_aq_str(hw, hw->aq.asq_last_status));
2526 }
2527 }
2528
2529 if (!aq_ret)
2530 pf->cur_promisc = promisc;
2531
2532 return aq_ret;
2533 }
2534
2535 /**
2536 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
2537 * @vsi: ptr to the VSI
2538 *
2539 * Push any outstanding VSI filter changes through the AdminQ.
2540 *
2541 * Returns 0 or error value
2542 **/
i40e_sync_vsi_filters(struct i40e_vsi * vsi)2543 int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
2544 {
2545 struct hlist_head tmp_add_list, tmp_del_list;
2546 struct i40e_mac_filter *f;
2547 struct i40e_new_mac_filter *new, *add_head = NULL;
2548 struct i40e_hw *hw = &vsi->back->hw;
2549 bool old_overflow, new_overflow;
2550 unsigned int failed_filters = 0;
2551 unsigned int vlan_filters = 0;
2552 char vsi_name[16] = "PF";
2553 int filter_list_len = 0;
2554 u32 changed_flags = 0;
2555 struct hlist_node *h;
2556 struct i40e_pf *pf;
2557 int num_add = 0;
2558 int num_del = 0;
2559 int aq_ret = 0;
2560 int retval = 0;
2561 u16 cmd_flags;
2562 int list_size;
2563 int bkt;
2564
2565 /* empty array typed pointers, kcalloc later */
2566 struct i40e_aqc_add_macvlan_element_data *add_list;
2567 struct i40e_aqc_remove_macvlan_element_data *del_list;
2568
2569 while (test_and_set_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state))
2570 usleep_range(1000, 2000);
2571 pf = vsi->back;
2572
2573 old_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2574
2575 if (vsi->netdev) {
2576 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
2577 vsi->current_netdev_flags = vsi->netdev->flags;
2578 }
2579
2580 INIT_HLIST_HEAD(&tmp_add_list);
2581 INIT_HLIST_HEAD(&tmp_del_list);
2582
2583 if (vsi->type == I40E_VSI_SRIOV)
2584 snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id);
2585 else if (vsi->type != I40E_VSI_MAIN)
2586 snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid);
2587
2588 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
2589 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
2590
2591 spin_lock_bh(&vsi->mac_filter_hash_lock);
2592 /* Create a list of filters to delete. */
2593 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
2594 if (f->state == I40E_FILTER_REMOVE) {
2595 /* Move the element into temporary del_list */
2596 hash_del(&f->hlist);
2597 hlist_add_head(&f->hlist, &tmp_del_list);
2598
2599 /* Avoid counting removed filters */
2600 continue;
2601 }
2602 if (f->state == I40E_FILTER_NEW) {
2603 /* Create a temporary i40e_new_mac_filter */
2604 new = kzalloc(sizeof(*new), GFP_ATOMIC);
2605 if (!new)
2606 goto err_no_memory_locked;
2607
2608 /* Store pointer to the real filter */
2609 new->f = f;
2610 new->state = f->state;
2611
2612 /* Add it to the hash list */
2613 hlist_add_head(&new->hlist, &tmp_add_list);
2614 }
2615
2616 /* Count the number of active (current and new) VLAN
2617 * filters we have now. Does not count filters which
2618 * are marked for deletion.
2619 */
2620 if (f->vlan > 0)
2621 vlan_filters++;
2622 }
2623
2624 if (vsi->type != I40E_VSI_SRIOV)
2625 retval = i40e_correct_mac_vlan_filters
2626 (vsi, &tmp_add_list, &tmp_del_list,
2627 vlan_filters);
2628 else if (pf->vf)
2629 retval = i40e_correct_vf_mac_vlan_filters
2630 (vsi, &tmp_add_list, &tmp_del_list,
2631 vlan_filters, pf->vf[vsi->vf_id].trusted);
2632
2633 hlist_for_each_entry(new, &tmp_add_list, hlist)
2634 netdev_hw_addr_refcnt(new->f, vsi->netdev, 1);
2635
2636 if (retval)
2637 goto err_no_memory_locked;
2638
2639 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2640 }
2641
2642 /* Now process 'del_list' outside the lock */
2643 if (!hlist_empty(&tmp_del_list)) {
2644 filter_list_len = hw->aq.asq_buf_size /
2645 sizeof(struct i40e_aqc_remove_macvlan_element_data);
2646 list_size = filter_list_len *
2647 sizeof(struct i40e_aqc_remove_macvlan_element_data);
2648 del_list = kzalloc(list_size, GFP_ATOMIC);
2649 if (!del_list)
2650 goto err_no_memory;
2651
2652 hlist_for_each_entry_safe(f, h, &tmp_del_list, hlist) {
2653 cmd_flags = 0;
2654
2655 /* handle broadcast filters by updating the broadcast
2656 * promiscuous flag and release filter list.
2657 */
2658 if (is_broadcast_ether_addr(f->macaddr)) {
2659 i40e_aqc_broadcast_filter(vsi, vsi_name, f);
2660
2661 hlist_del(&f->hlist);
2662 kfree(f);
2663 continue;
2664 }
2665
2666 /* add to delete list */
2667 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
2668 if (f->vlan == I40E_VLAN_ANY) {
2669 del_list[num_del].vlan_tag = 0;
2670 cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2671 } else {
2672 del_list[num_del].vlan_tag =
2673 cpu_to_le16((u16)(f->vlan));
2674 }
2675
2676 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
2677 del_list[num_del].flags = cmd_flags;
2678 num_del++;
2679
2680 /* flush a full buffer */
2681 if (num_del == filter_list_len) {
2682 i40e_aqc_del_filters(vsi, vsi_name, del_list,
2683 num_del, &retval);
2684 memset(del_list, 0, list_size);
2685 num_del = 0;
2686 }
2687 /* Release memory for MAC filter entries which were
2688 * synced up with HW.
2689 */
2690 hlist_del(&f->hlist);
2691 kfree(f);
2692 }
2693
2694 if (num_del) {
2695 i40e_aqc_del_filters(vsi, vsi_name, del_list,
2696 num_del, &retval);
2697 }
2698
2699 kfree(del_list);
2700 del_list = NULL;
2701 }
2702
2703 if (!hlist_empty(&tmp_add_list)) {
2704 /* Do all the adds now. */
2705 filter_list_len = hw->aq.asq_buf_size /
2706 sizeof(struct i40e_aqc_add_macvlan_element_data);
2707 list_size = filter_list_len *
2708 sizeof(struct i40e_aqc_add_macvlan_element_data);
2709 add_list = kzalloc(list_size, GFP_ATOMIC);
2710 if (!add_list)
2711 goto err_no_memory;
2712
2713 num_add = 0;
2714 hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) {
2715 /* handle broadcast filters by updating the broadcast
2716 * promiscuous flag instead of adding a MAC filter.
2717 */
2718 if (is_broadcast_ether_addr(new->f->macaddr)) {
2719 if (i40e_aqc_broadcast_filter(vsi, vsi_name,
2720 new->f))
2721 new->state = I40E_FILTER_FAILED;
2722 else
2723 new->state = I40E_FILTER_ACTIVE;
2724 continue;
2725 }
2726
2727 /* add to add array */
2728 if (num_add == 0)
2729 add_head = new;
2730 cmd_flags = 0;
2731 ether_addr_copy(add_list[num_add].mac_addr,
2732 new->f->macaddr);
2733 if (new->f->vlan == I40E_VLAN_ANY) {
2734 add_list[num_add].vlan_tag = 0;
2735 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
2736 } else {
2737 add_list[num_add].vlan_tag =
2738 cpu_to_le16((u16)(new->f->vlan));
2739 }
2740 add_list[num_add].queue_number = 0;
2741 /* set invalid match method for later detection */
2742 add_list[num_add].match_method = I40E_AQC_MM_ERR_NO_RES;
2743 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
2744 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2745 num_add++;
2746
2747 /* flush a full buffer */
2748 if (num_add == filter_list_len) {
2749 i40e_aqc_add_filters(vsi, vsi_name, add_list,
2750 add_head, num_add);
2751 memset(add_list, 0, list_size);
2752 num_add = 0;
2753 }
2754 }
2755 if (num_add) {
2756 i40e_aqc_add_filters(vsi, vsi_name, add_list, add_head,
2757 num_add);
2758 }
2759 /* Now move all of the filters from the temp add list back to
2760 * the VSI's list.
2761 */
2762 spin_lock_bh(&vsi->mac_filter_hash_lock);
2763 hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) {
2764 /* Only update the state if we're still NEW */
2765 if (new->f->state == I40E_FILTER_NEW)
2766 new->f->state = new->state;
2767 hlist_del(&new->hlist);
2768 netdev_hw_addr_refcnt(new->f, vsi->netdev, -1);
2769 kfree(new);
2770 }
2771 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2772 kfree(add_list);
2773 add_list = NULL;
2774 }
2775
2776 /* Determine the number of active and failed filters. */
2777 spin_lock_bh(&vsi->mac_filter_hash_lock);
2778 vsi->active_filters = 0;
2779 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) {
2780 if (f->state == I40E_FILTER_ACTIVE)
2781 vsi->active_filters++;
2782 else if (f->state == I40E_FILTER_FAILED)
2783 failed_filters++;
2784 }
2785 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2786
2787 /* Check if we are able to exit overflow promiscuous mode. We can
2788 * safely exit if we didn't just enter, we no longer have any failed
2789 * filters, and we have reduced filters below the threshold value.
2790 */
2791 if (old_overflow && !failed_filters &&
2792 vsi->active_filters < vsi->promisc_threshold) {
2793 dev_info(&pf->pdev->dev,
2794 "filter logjam cleared on %s, leaving overflow promiscuous mode\n",
2795 vsi_name);
2796 clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2797 vsi->promisc_threshold = 0;
2798 }
2799
2800 /* if the VF is not trusted do not do promisc */
2801 if (vsi->type == I40E_VSI_SRIOV && pf->vf &&
2802 !pf->vf[vsi->vf_id].trusted) {
2803 clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2804 goto out;
2805 }
2806
2807 new_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2808
2809 /* If we are entering overflow promiscuous, we need to calculate a new
2810 * threshold for when we are safe to exit
2811 */
2812 if (!old_overflow && new_overflow)
2813 vsi->promisc_threshold = (vsi->active_filters * 3) / 4;
2814
2815 /* check for changes in promiscuous modes */
2816 if (changed_flags & IFF_ALLMULTI) {
2817 bool cur_multipromisc;
2818
2819 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
2820 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2821 vsi->seid,
2822 cur_multipromisc,
2823 NULL);
2824 if (aq_ret) {
2825 retval = i40e_aq_rc_to_posix(aq_ret,
2826 hw->aq.asq_last_status);
2827 dev_info(&pf->pdev->dev,
2828 "set multi promisc failed on %s, err %pe aq_err %s\n",
2829 vsi_name,
2830 ERR_PTR(aq_ret),
2831 i40e_aq_str(hw, hw->aq.asq_last_status));
2832 } else {
2833 dev_info(&pf->pdev->dev, "%s allmulti mode.\n",
2834 cur_multipromisc ? "entering" : "leaving");
2835 }
2836 }
2837
2838 if ((changed_flags & IFF_PROMISC) || old_overflow != new_overflow) {
2839 bool cur_promisc;
2840
2841 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2842 new_overflow);
2843 aq_ret = i40e_set_promiscuous(pf, cur_promisc);
2844 if (aq_ret) {
2845 retval = i40e_aq_rc_to_posix(aq_ret,
2846 hw->aq.asq_last_status);
2847 dev_info(&pf->pdev->dev,
2848 "Setting promiscuous %s failed on %s, err %pe aq_err %s\n",
2849 cur_promisc ? "on" : "off",
2850 vsi_name,
2851 ERR_PTR(aq_ret),
2852 i40e_aq_str(hw, hw->aq.asq_last_status));
2853 }
2854 }
2855 out:
2856 /* if something went wrong then set the changed flag so we try again */
2857 if (retval)
2858 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2859
2860 clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state);
2861 return retval;
2862
2863 err_no_memory:
2864 /* Restore elements on the temporary add and delete lists */
2865 spin_lock_bh(&vsi->mac_filter_hash_lock);
2866 err_no_memory_locked:
2867 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
2868 i40e_undo_add_filter_entries(vsi, &tmp_add_list);
2869 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2870
2871 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2872 clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state);
2873 return -ENOMEM;
2874 }
2875
2876 /**
2877 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2878 * @pf: board private structure
2879 **/
i40e_sync_filters_subtask(struct i40e_pf * pf)2880 static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2881 {
2882 int v;
2883
2884 if (!pf)
2885 return;
2886 if (!test_and_clear_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state))
2887 return;
2888 if (test_bit(__I40E_VF_DISABLE, pf->state)) {
2889 set_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state);
2890 return;
2891 }
2892
2893 for (v = 0; v < pf->num_alloc_vsi; v++) {
2894 if (pf->vsi[v] &&
2895 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED) &&
2896 !test_bit(__I40E_VSI_RELEASING, pf->vsi[v]->state)) {
2897 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2898
2899 if (ret) {
2900 /* come back and try again later */
2901 set_bit(__I40E_MACVLAN_SYNC_PENDING,
2902 pf->state);
2903 break;
2904 }
2905 }
2906 }
2907 }
2908
2909 /**
2910 * i40e_calculate_vsi_rx_buf_len - Calculates buffer length
2911 *
2912 * @vsi: VSI to calculate rx_buf_len from
2913 */
i40e_calculate_vsi_rx_buf_len(struct i40e_vsi * vsi)2914 static u16 i40e_calculate_vsi_rx_buf_len(struct i40e_vsi *vsi)
2915 {
2916 if (!vsi->netdev || test_bit(I40E_FLAG_LEGACY_RX_ENA, vsi->back->flags))
2917 return SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048);
2918
2919 return PAGE_SIZE < 8192 ? I40E_RXBUFFER_3072 : I40E_RXBUFFER_2048;
2920 }
2921
2922 /**
2923 * i40e_max_vsi_frame_size - returns the maximum allowed frame size for VSI
2924 * @vsi: the vsi
2925 * @xdp_prog: XDP program
2926 **/
i40e_max_vsi_frame_size(struct i40e_vsi * vsi,struct bpf_prog * xdp_prog)2927 static int i40e_max_vsi_frame_size(struct i40e_vsi *vsi,
2928 struct bpf_prog *xdp_prog)
2929 {
2930 u16 rx_buf_len = i40e_calculate_vsi_rx_buf_len(vsi);
2931 u16 chain_len;
2932
2933 if (xdp_prog && !xdp_prog->aux->xdp_has_frags)
2934 chain_len = 1;
2935 else
2936 chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2937
2938 return min_t(u16, rx_buf_len * chain_len, I40E_MAX_RXBUFFER);
2939 }
2940
2941 /**
2942 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2943 * @netdev: network interface device structure
2944 * @new_mtu: new value for maximum frame size
2945 *
2946 * Returns 0 on success, negative on failure
2947 **/
i40e_change_mtu(struct net_device * netdev,int new_mtu)2948 static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2949 {
2950 struct i40e_netdev_priv *np = netdev_priv(netdev);
2951 struct i40e_vsi *vsi = np->vsi;
2952 struct i40e_pf *pf = vsi->back;
2953 int frame_size;
2954
2955 frame_size = i40e_max_vsi_frame_size(vsi, vsi->xdp_prog);
2956 if (new_mtu > frame_size - I40E_PACKET_HDR_PAD) {
2957 netdev_err(netdev, "Error changing mtu to %d, Max is %d\n",
2958 new_mtu, frame_size - I40E_PACKET_HDR_PAD);
2959 return -EINVAL;
2960 }
2961
2962 netdev_dbg(netdev, "changing MTU from %d to %d\n",
2963 netdev->mtu, new_mtu);
2964 netdev->mtu = new_mtu;
2965 if (netif_running(netdev))
2966 i40e_vsi_reinit_locked(vsi);
2967 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
2968 set_bit(__I40E_CLIENT_L2_CHANGE, pf->state);
2969 return 0;
2970 }
2971
2972 /**
2973 * i40e_ioctl - Access the hwtstamp interface
2974 * @netdev: network interface device structure
2975 * @ifr: interface request data
2976 * @cmd: ioctl command
2977 **/
i40e_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2978 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2979 {
2980 struct i40e_netdev_priv *np = netdev_priv(netdev);
2981 struct i40e_pf *pf = np->vsi->back;
2982
2983 switch (cmd) {
2984 case SIOCGHWTSTAMP:
2985 return i40e_ptp_get_ts_config(pf, ifr);
2986 case SIOCSHWTSTAMP:
2987 return i40e_ptp_set_ts_config(pf, ifr);
2988 default:
2989 return -EOPNOTSUPP;
2990 }
2991 }
2992
2993 /**
2994 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2995 * @vsi: the vsi being adjusted
2996 **/
i40e_vlan_stripping_enable(struct i40e_vsi * vsi)2997 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2998 {
2999 struct i40e_vsi_context ctxt;
3000 int ret;
3001
3002 /* Don't modify stripping options if a port VLAN is active */
3003 if (vsi->info.pvid)
3004 return;
3005
3006 if ((vsi->info.valid_sections &
3007 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
3008 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
3009 return; /* already enabled */
3010
3011 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
3012 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3013 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3014
3015 ctxt.seid = vsi->seid;
3016 ctxt.info = vsi->info;
3017 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3018 if (ret) {
3019 dev_info(&vsi->back->pdev->dev,
3020 "update vlan stripping failed, err %pe aq_err %s\n",
3021 ERR_PTR(ret),
3022 i40e_aq_str(&vsi->back->hw,
3023 vsi->back->hw.aq.asq_last_status));
3024 }
3025 }
3026
3027 /**
3028 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
3029 * @vsi: the vsi being adjusted
3030 **/
i40e_vlan_stripping_disable(struct i40e_vsi * vsi)3031 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
3032 {
3033 struct i40e_vsi_context ctxt;
3034 int ret;
3035
3036 /* Don't modify stripping options if a port VLAN is active */
3037 if (vsi->info.pvid)
3038 return;
3039
3040 if ((vsi->info.valid_sections &
3041 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
3042 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3043 I40E_AQ_VSI_PVLAN_EMOD_MASK))
3044 return; /* already disabled */
3045
3046 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
3047 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3048 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3049
3050 ctxt.seid = vsi->seid;
3051 ctxt.info = vsi->info;
3052 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3053 if (ret) {
3054 dev_info(&vsi->back->pdev->dev,
3055 "update vlan stripping failed, err %pe aq_err %s\n",
3056 ERR_PTR(ret),
3057 i40e_aq_str(&vsi->back->hw,
3058 vsi->back->hw.aq.asq_last_status));
3059 }
3060 }
3061
3062 /**
3063 * i40e_add_vlan_all_mac - Add a MAC/VLAN filter for each existing MAC address
3064 * @vsi: the vsi being configured
3065 * @vid: vlan id to be added (0 = untagged only , -1 = any)
3066 *
3067 * This is a helper function for adding a new MAC/VLAN filter with the
3068 * specified VLAN for each existing MAC address already in the hash table.
3069 * This function does *not* perform any accounting to update filters based on
3070 * VLAN mode.
3071 *
3072 * NOTE: this function expects to be called while under the
3073 * mac_filter_hash_lock
3074 **/
i40e_add_vlan_all_mac(struct i40e_vsi * vsi,s16 vid)3075 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid)
3076 {
3077 struct i40e_mac_filter *f, *add_f;
3078 struct hlist_node *h;
3079 int bkt;
3080
3081 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
3082 /* If we're asked to add a filter that has been marked for
3083 * removal, it is safe to simply restore it to active state.
3084 * __i40e_del_filter will have simply deleted any filters which
3085 * were previously marked NEW or FAILED, so if it is currently
3086 * marked REMOVE it must have previously been ACTIVE. Since we
3087 * haven't yet run the sync filters task, just restore this
3088 * filter to the ACTIVE state so that the sync task leaves it
3089 * in place.
3090 */
3091 if (f->state == I40E_FILTER_REMOVE && f->vlan == vid) {
3092 f->state = I40E_FILTER_ACTIVE;
3093 continue;
3094 } else if (f->state == I40E_FILTER_REMOVE) {
3095 continue;
3096 }
3097 add_f = i40e_add_filter(vsi, f->macaddr, vid);
3098 if (!add_f) {
3099 dev_info(&vsi->back->pdev->dev,
3100 "Could not add vlan filter %d for %pM\n",
3101 vid, f->macaddr);
3102 return -ENOMEM;
3103 }
3104 }
3105
3106 return 0;
3107 }
3108
3109 /**
3110 * i40e_vsi_add_vlan - Add VSI membership for given VLAN
3111 * @vsi: the VSI being configured
3112 * @vid: VLAN id to be added
3113 **/
i40e_vsi_add_vlan(struct i40e_vsi * vsi,u16 vid)3114 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid)
3115 {
3116 int err;
3117
3118 if (vsi->info.pvid)
3119 return -EINVAL;
3120
3121 /* The network stack will attempt to add VID=0, with the intention to
3122 * receive priority tagged packets with a VLAN of 0. Our HW receives
3123 * these packets by default when configured to receive untagged
3124 * packets, so we don't need to add a filter for this case.
3125 * Additionally, HW interprets adding a VID=0 filter as meaning to
3126 * receive *only* tagged traffic and stops receiving untagged traffic.
3127 * Thus, we do not want to actually add a filter for VID=0
3128 */
3129 if (!vid)
3130 return 0;
3131
3132 /* Locked once because all functions invoked below iterates list*/
3133 spin_lock_bh(&vsi->mac_filter_hash_lock);
3134 err = i40e_add_vlan_all_mac(vsi, vid);
3135 spin_unlock_bh(&vsi->mac_filter_hash_lock);
3136 if (err)
3137 return err;
3138
3139 /* schedule our worker thread which will take care of
3140 * applying the new filter changes
3141 */
3142 i40e_service_event_schedule(vsi->back);
3143 return 0;
3144 }
3145
3146 /**
3147 * i40e_rm_vlan_all_mac - Remove MAC/VLAN pair for all MAC with the given VLAN
3148 * @vsi: the vsi being configured
3149 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
3150 *
3151 * This function should be used to remove all VLAN filters which match the
3152 * given VID. It does not schedule the service event and does not take the
3153 * mac_filter_hash_lock so it may be combined with other operations under
3154 * a single invocation of the mac_filter_hash_lock.
3155 *
3156 * NOTE: this function expects to be called while under the
3157 * mac_filter_hash_lock
3158 */
i40e_rm_vlan_all_mac(struct i40e_vsi * vsi,s16 vid)3159 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid)
3160 {
3161 struct i40e_mac_filter *f;
3162 struct hlist_node *h;
3163 int bkt;
3164
3165 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
3166 if (f->vlan == vid)
3167 __i40e_del_filter(vsi, f);
3168 }
3169 }
3170
3171 /**
3172 * i40e_vsi_kill_vlan - Remove VSI membership for given VLAN
3173 * @vsi: the VSI being configured
3174 * @vid: VLAN id to be removed
3175 **/
i40e_vsi_kill_vlan(struct i40e_vsi * vsi,u16 vid)3176 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid)
3177 {
3178 if (!vid || vsi->info.pvid)
3179 return;
3180
3181 spin_lock_bh(&vsi->mac_filter_hash_lock);
3182 i40e_rm_vlan_all_mac(vsi, vid);
3183 spin_unlock_bh(&vsi->mac_filter_hash_lock);
3184
3185 /* schedule our worker thread which will take care of
3186 * applying the new filter changes
3187 */
3188 i40e_service_event_schedule(vsi->back);
3189 }
3190
3191 /**
3192 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
3193 * @netdev: network interface to be adjusted
3194 * @proto: unused protocol value
3195 * @vid: vlan id to be added
3196 *
3197 * net_device_ops implementation for adding vlan ids
3198 **/
i40e_vlan_rx_add_vid(struct net_device * netdev,__always_unused __be16 proto,u16 vid)3199 static int i40e_vlan_rx_add_vid(struct net_device *netdev,
3200 __always_unused __be16 proto, u16 vid)
3201 {
3202 struct i40e_netdev_priv *np = netdev_priv(netdev);
3203 struct i40e_vsi *vsi = np->vsi;
3204 int ret = 0;
3205
3206 if (vid >= VLAN_N_VID)
3207 return -EINVAL;
3208
3209 ret = i40e_vsi_add_vlan(vsi, vid);
3210 if (!ret)
3211 set_bit(vid, vsi->active_vlans);
3212
3213 return ret;
3214 }
3215
3216 /**
3217 * i40e_vlan_rx_add_vid_up - Add a vlan id filter to HW offload in UP path
3218 * @netdev: network interface to be adjusted
3219 * @proto: unused protocol value
3220 * @vid: vlan id to be added
3221 **/
i40e_vlan_rx_add_vid_up(struct net_device * netdev,__always_unused __be16 proto,u16 vid)3222 static void i40e_vlan_rx_add_vid_up(struct net_device *netdev,
3223 __always_unused __be16 proto, u16 vid)
3224 {
3225 struct i40e_netdev_priv *np = netdev_priv(netdev);
3226 struct i40e_vsi *vsi = np->vsi;
3227
3228 if (vid >= VLAN_N_VID)
3229 return;
3230 set_bit(vid, vsi->active_vlans);
3231 }
3232
3233 /**
3234 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
3235 * @netdev: network interface to be adjusted
3236 * @proto: unused protocol value
3237 * @vid: vlan id to be removed
3238 *
3239 * net_device_ops implementation for removing vlan ids
3240 **/
i40e_vlan_rx_kill_vid(struct net_device * netdev,__always_unused __be16 proto,u16 vid)3241 static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
3242 __always_unused __be16 proto, u16 vid)
3243 {
3244 struct i40e_netdev_priv *np = netdev_priv(netdev);
3245 struct i40e_vsi *vsi = np->vsi;
3246
3247 /* return code is ignored as there is nothing a user
3248 * can do about failure to remove and a log message was
3249 * already printed from the other function
3250 */
3251 i40e_vsi_kill_vlan(vsi, vid);
3252
3253 clear_bit(vid, vsi->active_vlans);
3254
3255 return 0;
3256 }
3257
3258 /**
3259 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
3260 * @vsi: the vsi being brought back up
3261 **/
i40e_restore_vlan(struct i40e_vsi * vsi)3262 static void i40e_restore_vlan(struct i40e_vsi *vsi)
3263 {
3264 u16 vid;
3265
3266 if (!vsi->netdev)
3267 return;
3268
3269 if (vsi->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3270 i40e_vlan_stripping_enable(vsi);
3271 else
3272 i40e_vlan_stripping_disable(vsi);
3273
3274 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
3275 i40e_vlan_rx_add_vid_up(vsi->netdev, htons(ETH_P_8021Q),
3276 vid);
3277 }
3278
3279 /**
3280 * i40e_vsi_add_pvid - Add pvid for the VSI
3281 * @vsi: the vsi being adjusted
3282 * @vid: the vlan id to set as a PVID
3283 **/
i40e_vsi_add_pvid(struct i40e_vsi * vsi,u16 vid)3284 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
3285 {
3286 struct i40e_vsi_context ctxt;
3287 int ret;
3288
3289 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
3290 vsi->info.pvid = cpu_to_le16(vid);
3291 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
3292 I40E_AQ_VSI_PVLAN_INSERT_PVID |
3293 I40E_AQ_VSI_PVLAN_EMOD_STR;
3294
3295 ctxt.seid = vsi->seid;
3296 ctxt.info = vsi->info;
3297 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3298 if (ret) {
3299 dev_info(&vsi->back->pdev->dev,
3300 "add pvid failed, err %pe aq_err %s\n",
3301 ERR_PTR(ret),
3302 i40e_aq_str(&vsi->back->hw,
3303 vsi->back->hw.aq.asq_last_status));
3304 return -ENOENT;
3305 }
3306
3307 return 0;
3308 }
3309
3310 /**
3311 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
3312 * @vsi: the vsi being adjusted
3313 *
3314 * Just use the vlan_rx_register() service to put it back to normal
3315 **/
i40e_vsi_remove_pvid(struct i40e_vsi * vsi)3316 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
3317 {
3318 vsi->info.pvid = 0;
3319
3320 i40e_vlan_stripping_disable(vsi);
3321 }
3322
3323 /**
3324 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
3325 * @vsi: ptr to the VSI
3326 *
3327 * If this function returns with an error, then it's possible one or
3328 * more of the rings is populated (while the rest are not). It is the
3329 * callers duty to clean those orphaned rings.
3330 *
3331 * Return 0 on success, negative on failure
3332 **/
i40e_vsi_setup_tx_resources(struct i40e_vsi * vsi)3333 static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
3334 {
3335 int i, err = 0;
3336
3337 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
3338 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
3339
3340 if (!i40e_enabled_xdp_vsi(vsi))
3341 return err;
3342
3343 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
3344 err = i40e_setup_tx_descriptors(vsi->xdp_rings[i]);
3345
3346 return err;
3347 }
3348
3349 /**
3350 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
3351 * @vsi: ptr to the VSI
3352 *
3353 * Free VSI's transmit software resources
3354 **/
i40e_vsi_free_tx_resources(struct i40e_vsi * vsi)3355 static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
3356 {
3357 int i;
3358
3359 if (vsi->tx_rings) {
3360 for (i = 0; i < vsi->num_queue_pairs; i++)
3361 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
3362 i40e_free_tx_resources(vsi->tx_rings[i]);
3363 }
3364
3365 if (vsi->xdp_rings) {
3366 for (i = 0; i < vsi->num_queue_pairs; i++)
3367 if (vsi->xdp_rings[i] && vsi->xdp_rings[i]->desc)
3368 i40e_free_tx_resources(vsi->xdp_rings[i]);
3369 }
3370 }
3371
3372 /**
3373 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
3374 * @vsi: ptr to the VSI
3375 *
3376 * If this function returns with an error, then it's possible one or
3377 * more of the rings is populated (while the rest are not). It is the
3378 * callers duty to clean those orphaned rings.
3379 *
3380 * Return 0 on success, negative on failure
3381 **/
i40e_vsi_setup_rx_resources(struct i40e_vsi * vsi)3382 static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
3383 {
3384 int i, err = 0;
3385
3386 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
3387 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
3388 return err;
3389 }
3390
3391 /**
3392 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
3393 * @vsi: ptr to the VSI
3394 *
3395 * Free all receive software resources
3396 **/
i40e_vsi_free_rx_resources(struct i40e_vsi * vsi)3397 static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
3398 {
3399 int i;
3400
3401 if (!vsi->rx_rings)
3402 return;
3403
3404 for (i = 0; i < vsi->num_queue_pairs; i++)
3405 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
3406 i40e_free_rx_resources(vsi->rx_rings[i]);
3407 }
3408
3409 /**
3410 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
3411 * @ring: The Tx ring to configure
3412 *
3413 * This enables/disables XPS for a given Tx descriptor ring
3414 * based on the TCs enabled for the VSI that ring belongs to.
3415 **/
i40e_config_xps_tx_ring(struct i40e_ring * ring)3416 static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
3417 {
3418 int cpu;
3419
3420 if (!ring->q_vector || !ring->netdev || ring->ch)
3421 return;
3422
3423 /* We only initialize XPS once, so as not to overwrite user settings */
3424 if (test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state))
3425 return;
3426
3427 cpu = cpumask_local_spread(ring->q_vector->v_idx, -1);
3428 netif_set_xps_queue(ring->netdev, get_cpu_mask(cpu),
3429 ring->queue_index);
3430 }
3431
3432 /**
3433 * i40e_xsk_pool - Retrieve the AF_XDP buffer pool if XDP and ZC is enabled
3434 * @ring: The Tx or Rx ring
3435 *
3436 * Returns the AF_XDP buffer pool or NULL.
3437 **/
i40e_xsk_pool(struct i40e_ring * ring)3438 static struct xsk_buff_pool *i40e_xsk_pool(struct i40e_ring *ring)
3439 {
3440 bool xdp_on = i40e_enabled_xdp_vsi(ring->vsi);
3441 int qid = ring->queue_index;
3442
3443 if (ring_is_xdp(ring))
3444 qid -= ring->vsi->alloc_queue_pairs;
3445
3446 if (!xdp_on || !test_bit(qid, ring->vsi->af_xdp_zc_qps))
3447 return NULL;
3448
3449 return xsk_get_pool_from_qid(ring->vsi->netdev, qid);
3450 }
3451
3452 /**
3453 * i40e_configure_tx_ring - Configure a transmit ring context and rest
3454 * @ring: The Tx ring to configure
3455 *
3456 * Configure the Tx descriptor ring in the HMC context.
3457 **/
i40e_configure_tx_ring(struct i40e_ring * ring)3458 static int i40e_configure_tx_ring(struct i40e_ring *ring)
3459 {
3460 struct i40e_vsi *vsi = ring->vsi;
3461 u16 pf_q = vsi->base_queue + ring->queue_index;
3462 struct i40e_hw *hw = &vsi->back->hw;
3463 struct i40e_hmc_obj_txq tx_ctx;
3464 u32 qtx_ctl = 0;
3465 int err = 0;
3466
3467 if (ring_is_xdp(ring))
3468 ring->xsk_pool = i40e_xsk_pool(ring);
3469
3470 /* some ATR related tx ring init */
3471 if (test_bit(I40E_FLAG_FD_ATR_ENA, vsi->back->flags)) {
3472 ring->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
3473 ring->atr_count = 0;
3474 } else {
3475 ring->atr_sample_rate = 0;
3476 }
3477
3478 /* configure XPS */
3479 i40e_config_xps_tx_ring(ring);
3480
3481 /* clear the context structure first */
3482 memset(&tx_ctx, 0, sizeof(tx_ctx));
3483
3484 tx_ctx.new_context = 1;
3485 tx_ctx.base = (ring->dma / 128);
3486 tx_ctx.qlen = ring->count;
3487 if (test_bit(I40E_FLAG_FD_SB_ENA, vsi->back->flags) ||
3488 test_bit(I40E_FLAG_FD_ATR_ENA, vsi->back->flags))
3489 tx_ctx.fd_ena = 1;
3490 if (test_bit(I40E_FLAG_PTP_ENA, vsi->back->flags))
3491 tx_ctx.timesync_ena = 1;
3492 /* FDIR VSI tx ring can still use RS bit and writebacks */
3493 if (vsi->type != I40E_VSI_FDIR)
3494 tx_ctx.head_wb_ena = 1;
3495 tx_ctx.head_wb_addr = ring->dma +
3496 (ring->count * sizeof(struct i40e_tx_desc));
3497
3498 /* As part of VSI creation/update, FW allocates certain
3499 * Tx arbitration queue sets for each TC enabled for
3500 * the VSI. The FW returns the handles to these queue
3501 * sets as part of the response buffer to Add VSI,
3502 * Update VSI, etc. AQ commands. It is expected that
3503 * these queue set handles be associated with the Tx
3504 * queues by the driver as part of the TX queue context
3505 * initialization. This has to be done regardless of
3506 * DCB as by default everything is mapped to TC0.
3507 */
3508
3509 if (ring->ch)
3510 tx_ctx.rdylist =
3511 le16_to_cpu(ring->ch->info.qs_handle[ring->dcb_tc]);
3512
3513 else
3514 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
3515
3516 tx_ctx.rdylist_act = 0;
3517
3518 /* clear the context in the HMC */
3519 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
3520 if (err) {
3521 dev_info(&vsi->back->pdev->dev,
3522 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
3523 ring->queue_index, pf_q, err);
3524 return -ENOMEM;
3525 }
3526
3527 /* set the context in the HMC */
3528 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
3529 if (err) {
3530 dev_info(&vsi->back->pdev->dev,
3531 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
3532 ring->queue_index, pf_q, err);
3533 return -ENOMEM;
3534 }
3535
3536 /* Now associate this queue with this PCI function */
3537 if (ring->ch) {
3538 if (ring->ch->type == I40E_VSI_VMDQ2)
3539 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
3540 else
3541 return -EINVAL;
3542
3543 qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK,
3544 ring->ch->vsi_number);
3545 } else {
3546 if (vsi->type == I40E_VSI_VMDQ2) {
3547 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
3548 qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK,
3549 vsi->id);
3550 } else {
3551 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
3552 }
3553 }
3554
3555 qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_PF_INDX_MASK, hw->pf_id);
3556 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
3557 i40e_flush(hw);
3558
3559 /* cache tail off for easier writes later */
3560 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
3561
3562 return 0;
3563 }
3564
3565 /**
3566 * i40e_rx_offset - Return expected offset into page to access data
3567 * @rx_ring: Ring we are requesting offset of
3568 *
3569 * Returns the offset value for ring into the data buffer.
3570 */
i40e_rx_offset(struct i40e_ring * rx_ring)3571 static unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
3572 {
3573 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
3574 }
3575
3576 /**
3577 * i40e_configure_rx_ring - Configure a receive ring context
3578 * @ring: The Rx ring to configure
3579 *
3580 * Configure the Rx descriptor ring in the HMC context.
3581 **/
i40e_configure_rx_ring(struct i40e_ring * ring)3582 static int i40e_configure_rx_ring(struct i40e_ring *ring)
3583 {
3584 struct i40e_vsi *vsi = ring->vsi;
3585 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
3586 u16 pf_q = vsi->base_queue + ring->queue_index;
3587 struct i40e_hw *hw = &vsi->back->hw;
3588 struct i40e_hmc_obj_rxq rx_ctx;
3589 int err = 0;
3590 bool ok;
3591
3592 bitmap_zero(ring->state, __I40E_RING_STATE_NBITS);
3593
3594 /* clear the context structure first */
3595 memset(&rx_ctx, 0, sizeof(rx_ctx));
3596
3597 ring->rx_buf_len = vsi->rx_buf_len;
3598
3599 /* XDP RX-queue info only needed for RX rings exposed to XDP */
3600 if (ring->vsi->type != I40E_VSI_MAIN)
3601 goto skip;
3602
3603 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) {
3604 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
3605 ring->queue_index,
3606 ring->q_vector->napi.napi_id,
3607 ring->rx_buf_len);
3608 if (err)
3609 return err;
3610 }
3611
3612 ring->xsk_pool = i40e_xsk_pool(ring);
3613 if (ring->xsk_pool) {
3614 xdp_rxq_info_unreg(&ring->xdp_rxq);
3615 ring->rx_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool);
3616 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
3617 ring->queue_index,
3618 ring->q_vector->napi.napi_id,
3619 ring->rx_buf_len);
3620 if (err)
3621 return err;
3622 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
3623 MEM_TYPE_XSK_BUFF_POOL,
3624 NULL);
3625 if (err)
3626 return err;
3627 dev_info(&vsi->back->pdev->dev,
3628 "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n",
3629 ring->queue_index);
3630
3631 } else {
3632 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
3633 MEM_TYPE_PAGE_SHARED,
3634 NULL);
3635 if (err)
3636 return err;
3637 }
3638
3639 skip:
3640 xdp_init_buff(&ring->xdp, i40e_rx_pg_size(ring) / 2, &ring->xdp_rxq);
3641
3642 rx_ctx.dbuff = DIV_ROUND_UP(ring->rx_buf_len,
3643 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
3644
3645 rx_ctx.base = (ring->dma / 128);
3646 rx_ctx.qlen = ring->count;
3647
3648 /* use 16 byte descriptors */
3649 rx_ctx.dsize = 0;
3650
3651 /* descriptor type is always zero
3652 * rx_ctx.dtype = 0;
3653 */
3654 rx_ctx.hsplit_0 = 0;
3655
3656 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
3657 if (hw->revision_id == 0)
3658 rx_ctx.lrxqthresh = 0;
3659 else
3660 rx_ctx.lrxqthresh = 1;
3661 rx_ctx.crcstrip = 1;
3662 rx_ctx.l2tsel = 1;
3663 /* this controls whether VLAN is stripped from inner headers */
3664 rx_ctx.showiv = 0;
3665 /* set the prefena field to 1 because the manual says to */
3666 rx_ctx.prefena = 1;
3667
3668 /* clear the context in the HMC */
3669 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
3670 if (err) {
3671 dev_info(&vsi->back->pdev->dev,
3672 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
3673 ring->queue_index, pf_q, err);
3674 return -ENOMEM;
3675 }
3676
3677 /* set the context in the HMC */
3678 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
3679 if (err) {
3680 dev_info(&vsi->back->pdev->dev,
3681 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
3682 ring->queue_index, pf_q, err);
3683 return -ENOMEM;
3684 }
3685
3686 /* configure Rx buffer alignment */
3687 if (!vsi->netdev || test_bit(I40E_FLAG_LEGACY_RX_ENA, vsi->back->flags)) {
3688 if (I40E_2K_TOO_SMALL_WITH_PADDING) {
3689 dev_info(&vsi->back->pdev->dev,
3690 "2k Rx buffer is too small to fit standard MTU and skb_shared_info\n");
3691 return -EOPNOTSUPP;
3692 }
3693 clear_ring_build_skb_enabled(ring);
3694 } else {
3695 set_ring_build_skb_enabled(ring);
3696 }
3697
3698 ring->rx_offset = i40e_rx_offset(ring);
3699
3700 /* cache tail for quicker writes, and clear the reg before use */
3701 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
3702 writel(0, ring->tail);
3703
3704 if (ring->xsk_pool) {
3705 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
3706 ok = i40e_alloc_rx_buffers_zc(ring, I40E_DESC_UNUSED(ring));
3707 } else {
3708 ok = !i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
3709 }
3710 if (!ok) {
3711 /* Log this in case the user has forgotten to give the kernel
3712 * any buffers, even later in the application.
3713 */
3714 dev_info(&vsi->back->pdev->dev,
3715 "Failed to allocate some buffers on %sRx ring %d (pf_q %d)\n",
3716 ring->xsk_pool ? "AF_XDP ZC enabled " : "",
3717 ring->queue_index, pf_q);
3718 }
3719
3720 return 0;
3721 }
3722
3723 /**
3724 * i40e_vsi_configure_tx - Configure the VSI for Tx
3725 * @vsi: VSI structure describing this set of rings and resources
3726 *
3727 * Configure the Tx VSI for operation.
3728 **/
i40e_vsi_configure_tx(struct i40e_vsi * vsi)3729 static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
3730 {
3731 int err = 0;
3732 u16 i;
3733
3734 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
3735 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
3736
3737 if (err || !i40e_enabled_xdp_vsi(vsi))
3738 return err;
3739
3740 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
3741 err = i40e_configure_tx_ring(vsi->xdp_rings[i]);
3742
3743 return err;
3744 }
3745
3746 /**
3747 * i40e_vsi_configure_rx - Configure the VSI for Rx
3748 * @vsi: the VSI being configured
3749 *
3750 * Configure the Rx VSI for operation.
3751 **/
i40e_vsi_configure_rx(struct i40e_vsi * vsi)3752 static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
3753 {
3754 int err = 0;
3755 u16 i;
3756
3757 vsi->max_frame = i40e_max_vsi_frame_size(vsi, vsi->xdp_prog);
3758 vsi->rx_buf_len = i40e_calculate_vsi_rx_buf_len(vsi);
3759
3760 #if (PAGE_SIZE < 8192)
3761 if (vsi->netdev && !I40E_2K_TOO_SMALL_WITH_PADDING &&
3762 vsi->netdev->mtu <= ETH_DATA_LEN) {
3763 vsi->rx_buf_len = I40E_RXBUFFER_1536 - NET_IP_ALIGN;
3764 vsi->max_frame = vsi->rx_buf_len;
3765 }
3766 #endif
3767
3768 /* set up individual rings */
3769 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
3770 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
3771
3772 return err;
3773 }
3774
3775 /**
3776 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
3777 * @vsi: ptr to the VSI
3778 **/
i40e_vsi_config_dcb_rings(struct i40e_vsi * vsi)3779 static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
3780 {
3781 struct i40e_ring *tx_ring, *rx_ring;
3782 u16 qoffset, qcount;
3783 int i, n;
3784
3785 if (!test_bit(I40E_FLAG_DCB_ENA, vsi->back->flags)) {
3786 /* Reset the TC information */
3787 for (i = 0; i < vsi->num_queue_pairs; i++) {
3788 rx_ring = vsi->rx_rings[i];
3789 tx_ring = vsi->tx_rings[i];
3790 rx_ring->dcb_tc = 0;
3791 tx_ring->dcb_tc = 0;
3792 }
3793 return;
3794 }
3795
3796 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
3797 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
3798 continue;
3799
3800 qoffset = vsi->tc_config.tc_info[n].qoffset;
3801 qcount = vsi->tc_config.tc_info[n].qcount;
3802 for (i = qoffset; i < (qoffset + qcount); i++) {
3803 rx_ring = vsi->rx_rings[i];
3804 tx_ring = vsi->tx_rings[i];
3805 rx_ring->dcb_tc = n;
3806 tx_ring->dcb_tc = n;
3807 }
3808 }
3809 }
3810
3811 /**
3812 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3813 * @vsi: ptr to the VSI
3814 **/
i40e_set_vsi_rx_mode(struct i40e_vsi * vsi)3815 static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3816 {
3817 if (vsi->netdev)
3818 i40e_set_rx_mode(vsi->netdev);
3819 }
3820
3821 /**
3822 * i40e_reset_fdir_filter_cnt - Reset flow director filter counters
3823 * @pf: Pointer to the targeted PF
3824 *
3825 * Set all flow director counters to 0.
3826 */
i40e_reset_fdir_filter_cnt(struct i40e_pf * pf)3827 static void i40e_reset_fdir_filter_cnt(struct i40e_pf *pf)
3828 {
3829 pf->fd_tcp4_filter_cnt = 0;
3830 pf->fd_udp4_filter_cnt = 0;
3831 pf->fd_sctp4_filter_cnt = 0;
3832 pf->fd_ip4_filter_cnt = 0;
3833 pf->fd_tcp6_filter_cnt = 0;
3834 pf->fd_udp6_filter_cnt = 0;
3835 pf->fd_sctp6_filter_cnt = 0;
3836 pf->fd_ip6_filter_cnt = 0;
3837 }
3838
3839 /**
3840 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3841 * @vsi: Pointer to the targeted VSI
3842 *
3843 * This function replays the hlist on the hw where all the SB Flow Director
3844 * filters were saved.
3845 **/
i40e_fdir_filter_restore(struct i40e_vsi * vsi)3846 static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3847 {
3848 struct i40e_fdir_filter *filter;
3849 struct i40e_pf *pf = vsi->back;
3850 struct hlist_node *node;
3851
3852 if (!test_bit(I40E_FLAG_FD_SB_ENA, pf->flags))
3853 return;
3854
3855 /* Reset FDir counters as we're replaying all existing filters */
3856 i40e_reset_fdir_filter_cnt(pf);
3857
3858 hlist_for_each_entry_safe(filter, node,
3859 &pf->fdir_filter_list, fdir_node) {
3860 i40e_add_del_fdir(vsi, filter, true);
3861 }
3862 }
3863
3864 /**
3865 * i40e_vsi_configure - Set up the VSI for action
3866 * @vsi: the VSI being configured
3867 **/
i40e_vsi_configure(struct i40e_vsi * vsi)3868 static int i40e_vsi_configure(struct i40e_vsi *vsi)
3869 {
3870 int err;
3871
3872 i40e_set_vsi_rx_mode(vsi);
3873 i40e_restore_vlan(vsi);
3874 i40e_vsi_config_dcb_rings(vsi);
3875 err = i40e_vsi_configure_tx(vsi);
3876 if (!err)
3877 err = i40e_vsi_configure_rx(vsi);
3878
3879 return err;
3880 }
3881
3882 /**
3883 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3884 * @vsi: the VSI being configured
3885 **/
i40e_vsi_configure_msix(struct i40e_vsi * vsi)3886 static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3887 {
3888 bool has_xdp = i40e_enabled_xdp_vsi(vsi);
3889 struct i40e_pf *pf = vsi->back;
3890 struct i40e_hw *hw = &pf->hw;
3891 u16 vector;
3892 int i, q;
3893 u32 qp;
3894
3895 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3896 * and PFINT_LNKLSTn registers, e.g.:
3897 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3898 */
3899 qp = vsi->base_queue;
3900 vector = vsi->base_vector;
3901 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
3902 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3903
3904 q_vector->rx.next_update = jiffies + 1;
3905 q_vector->rx.target_itr =
3906 ITR_TO_REG(vsi->rx_rings[i]->itr_setting);
3907 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3908 q_vector->rx.target_itr >> 1);
3909 q_vector->rx.current_itr = q_vector->rx.target_itr;
3910
3911 q_vector->tx.next_update = jiffies + 1;
3912 q_vector->tx.target_itr =
3913 ITR_TO_REG(vsi->tx_rings[i]->itr_setting);
3914 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3915 q_vector->tx.target_itr >> 1);
3916 q_vector->tx.current_itr = q_vector->tx.target_itr;
3917
3918 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3919 i40e_intrl_usec_to_reg(vsi->int_rate_limit));
3920
3921 /* begin of linked list for RX queue assigned to this vector */
3922 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3923 for (q = 0; q < q_vector->num_ringpairs; q++) {
3924 u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp;
3925 u32 val;
3926
3927 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3928 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3929 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3930 (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
3931 (I40E_QUEUE_TYPE_TX <<
3932 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3933
3934 wr32(hw, I40E_QINT_RQCTL(qp), val);
3935
3936 if (has_xdp) {
3937 /* TX queue with next queue set to TX */
3938 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3939 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3940 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3941 (qp << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
3942 (I40E_QUEUE_TYPE_TX <<
3943 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3944
3945 wr32(hw, I40E_QINT_TQCTL(nextqp), val);
3946 }
3947 /* TX queue with next RX or end of linked list */
3948 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3949 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3950 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3951 ((qp + 1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
3952 (I40E_QUEUE_TYPE_RX <<
3953 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3954
3955 /* Terminate the linked list */
3956 if (q == (q_vector->num_ringpairs - 1))
3957 val |= (I40E_QUEUE_END_OF_LIST <<
3958 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3959
3960 wr32(hw, I40E_QINT_TQCTL(qp), val);
3961 qp++;
3962 }
3963 }
3964
3965 i40e_flush(hw);
3966 }
3967
3968 /**
3969 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3970 * @pf: pointer to private device data structure
3971 **/
i40e_enable_misc_int_causes(struct i40e_pf * pf)3972 static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
3973 {
3974 struct i40e_hw *hw = &pf->hw;
3975 u32 val;
3976
3977 /* clear things first */
3978 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3979 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3980
3981 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3982 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3983 I40E_PFINT_ICR0_ENA_GRST_MASK |
3984 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3985 I40E_PFINT_ICR0_ENA_GPIO_MASK |
3986 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3987 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3988 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3989
3990 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags))
3991 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3992
3993 if (test_bit(I40E_FLAG_PTP_ENA, pf->flags))
3994 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3995
3996 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3997
3998 /* SW_ITR_IDX = 0, but don't change INTENA */
3999 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
4000 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
4001
4002 /* OTHER_ITR_IDX = 0 */
4003 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
4004 }
4005
4006 /**
4007 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
4008 * @vsi: the VSI being configured
4009 **/
i40e_configure_msi_and_legacy(struct i40e_vsi * vsi)4010 static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
4011 {
4012 u32 nextqp = i40e_enabled_xdp_vsi(vsi) ? vsi->alloc_queue_pairs : 0;
4013 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
4014 struct i40e_pf *pf = vsi->back;
4015 struct i40e_hw *hw = &pf->hw;
4016
4017 /* set the ITR configuration */
4018 q_vector->rx.next_update = jiffies + 1;
4019 q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting);
4020 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr >> 1);
4021 q_vector->rx.current_itr = q_vector->rx.target_itr;
4022 q_vector->tx.next_update = jiffies + 1;
4023 q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting);
4024 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.target_itr >> 1);
4025 q_vector->tx.current_itr = q_vector->tx.target_itr;
4026
4027 i40e_enable_misc_int_causes(pf);
4028
4029 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
4030 wr32(hw, I40E_PFINT_LNKLST0, 0);
4031
4032 /* Associate the queue pair to the vector and enable the queue
4033 * interrupt RX queue in linked list with next queue set to TX
4034 */
4035 wr32(hw, I40E_QINT_RQCTL(0), I40E_QINT_RQCTL_VAL(nextqp, 0, TX));
4036
4037 if (i40e_enabled_xdp_vsi(vsi)) {
4038 /* TX queue in linked list with next queue set to TX */
4039 wr32(hw, I40E_QINT_TQCTL(nextqp),
4040 I40E_QINT_TQCTL_VAL(nextqp, 0, TX));
4041 }
4042
4043 /* last TX queue so the next RX queue doesn't matter */
4044 wr32(hw, I40E_QINT_TQCTL(0),
4045 I40E_QINT_TQCTL_VAL(I40E_QUEUE_END_OF_LIST, 0, RX));
4046 i40e_flush(hw);
4047 }
4048
4049 /**
4050 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
4051 * @pf: board private structure
4052 **/
i40e_irq_dynamic_disable_icr0(struct i40e_pf * pf)4053 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
4054 {
4055 struct i40e_hw *hw = &pf->hw;
4056
4057 wr32(hw, I40E_PFINT_DYN_CTL0,
4058 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
4059 i40e_flush(hw);
4060 }
4061
4062 /**
4063 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
4064 * @pf: board private structure
4065 **/
i40e_irq_dynamic_enable_icr0(struct i40e_pf * pf)4066 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
4067 {
4068 struct i40e_hw *hw = &pf->hw;
4069 u32 val;
4070
4071 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
4072 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4073 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
4074
4075 wr32(hw, I40E_PFINT_DYN_CTL0, val);
4076 i40e_flush(hw);
4077 }
4078
4079 /**
4080 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
4081 * @irq: interrupt number
4082 * @data: pointer to a q_vector
4083 **/
i40e_msix_clean_rings(int irq,void * data)4084 static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
4085 {
4086 struct i40e_q_vector *q_vector = data;
4087
4088 if (!q_vector->tx.ring && !q_vector->rx.ring)
4089 return IRQ_HANDLED;
4090
4091 napi_schedule_irqoff(&q_vector->napi);
4092
4093 return IRQ_HANDLED;
4094 }
4095
4096 /**
4097 * i40e_irq_affinity_notify - Callback for affinity changes
4098 * @notify: context as to what irq was changed
4099 * @mask: the new affinity mask
4100 *
4101 * This is a callback function used by the irq_set_affinity_notifier function
4102 * so that we may register to receive changes to the irq affinity masks.
4103 **/
i40e_irq_affinity_notify(struct irq_affinity_notify * notify,const cpumask_t * mask)4104 static void i40e_irq_affinity_notify(struct irq_affinity_notify *notify,
4105 const cpumask_t *mask)
4106 {
4107 struct i40e_q_vector *q_vector =
4108 container_of(notify, struct i40e_q_vector, affinity_notify);
4109
4110 cpumask_copy(&q_vector->affinity_mask, mask);
4111 }
4112
4113 /**
4114 * i40e_irq_affinity_release - Callback for affinity notifier release
4115 * @ref: internal core kernel usage
4116 *
4117 * This is a callback function used by the irq_set_affinity_notifier function
4118 * to inform the current notification subscriber that they will no longer
4119 * receive notifications.
4120 **/
i40e_irq_affinity_release(struct kref * ref)4121 static void i40e_irq_affinity_release(struct kref *ref) {}
4122
4123 /**
4124 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
4125 * @vsi: the VSI being configured
4126 * @basename: name for the vector
4127 *
4128 * Allocates MSI-X vectors and requests interrupts from the kernel.
4129 **/
i40e_vsi_request_irq_msix(struct i40e_vsi * vsi,char * basename)4130 static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
4131 {
4132 int q_vectors = vsi->num_q_vectors;
4133 struct i40e_pf *pf = vsi->back;
4134 int base = vsi->base_vector;
4135 int rx_int_idx = 0;
4136 int tx_int_idx = 0;
4137 int vector, err;
4138 int irq_num;
4139 int cpu;
4140
4141 for (vector = 0; vector < q_vectors; vector++) {
4142 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
4143
4144 irq_num = pf->msix_entries[base + vector].vector;
4145
4146 if (q_vector->tx.ring && q_vector->rx.ring) {
4147 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4148 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
4149 tx_int_idx++;
4150 } else if (q_vector->rx.ring) {
4151 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4152 "%s-%s-%d", basename, "rx", rx_int_idx++);
4153 } else if (q_vector->tx.ring) {
4154 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4155 "%s-%s-%d", basename, "tx", tx_int_idx++);
4156 } else {
4157 /* skip this unused q_vector */
4158 continue;
4159 }
4160 err = request_irq(irq_num,
4161 vsi->irq_handler,
4162 0,
4163 q_vector->name,
4164 q_vector);
4165 if (err) {
4166 dev_info(&pf->pdev->dev,
4167 "MSIX request_irq failed, error: %d\n", err);
4168 goto free_queue_irqs;
4169 }
4170
4171 /* register for affinity change notifications */
4172 q_vector->irq_num = irq_num;
4173 q_vector->affinity_notify.notify = i40e_irq_affinity_notify;
4174 q_vector->affinity_notify.release = i40e_irq_affinity_release;
4175 irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify);
4176 /* Spread affinity hints out across online CPUs.
4177 *
4178 * get_cpu_mask returns a static constant mask with
4179 * a permanent lifetime so it's ok to pass to
4180 * irq_update_affinity_hint without making a copy.
4181 */
4182 cpu = cpumask_local_spread(q_vector->v_idx, -1);
4183 irq_update_affinity_hint(irq_num, get_cpu_mask(cpu));
4184 }
4185
4186 vsi->irqs_ready = true;
4187 return 0;
4188
4189 free_queue_irqs:
4190 while (vector) {
4191 vector--;
4192 irq_num = pf->msix_entries[base + vector].vector;
4193 irq_set_affinity_notifier(irq_num, NULL);
4194 irq_update_affinity_hint(irq_num, NULL);
4195 free_irq(irq_num, &vsi->q_vectors[vector]);
4196 }
4197 return err;
4198 }
4199
4200 /**
4201 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
4202 * @vsi: the VSI being un-configured
4203 **/
i40e_vsi_disable_irq(struct i40e_vsi * vsi)4204 static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
4205 {
4206 struct i40e_pf *pf = vsi->back;
4207 struct i40e_hw *hw = &pf->hw;
4208 int base = vsi->base_vector;
4209 int i;
4210
4211 /* disable interrupt causation from each queue */
4212 for (i = 0; i < vsi->num_queue_pairs; i++) {
4213 u32 val;
4214
4215 val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx));
4216 val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
4217 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val);
4218
4219 val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx));
4220 val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
4221 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val);
4222
4223 if (!i40e_enabled_xdp_vsi(vsi))
4224 continue;
4225 wr32(hw, I40E_QINT_TQCTL(vsi->xdp_rings[i]->reg_idx), 0);
4226 }
4227
4228 /* disable each interrupt */
4229 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
4230 for (i = vsi->base_vector;
4231 i < (vsi->num_q_vectors + vsi->base_vector); i++)
4232 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
4233
4234 i40e_flush(hw);
4235 for (i = 0; i < vsi->num_q_vectors; i++)
4236 synchronize_irq(pf->msix_entries[i + base].vector);
4237 } else {
4238 /* Legacy and MSI mode - this stops all interrupt handling */
4239 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
4240 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
4241 i40e_flush(hw);
4242 synchronize_irq(pf->pdev->irq);
4243 }
4244 }
4245
4246 /**
4247 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
4248 * @vsi: the VSI being configured
4249 **/
i40e_vsi_enable_irq(struct i40e_vsi * vsi)4250 static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
4251 {
4252 struct i40e_pf *pf = vsi->back;
4253 int i;
4254
4255 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
4256 for (i = 0; i < vsi->num_q_vectors; i++)
4257 i40e_irq_dynamic_enable(vsi, i);
4258 } else {
4259 i40e_irq_dynamic_enable_icr0(pf);
4260 }
4261
4262 i40e_flush(&pf->hw);
4263 return 0;
4264 }
4265
4266 /**
4267 * i40e_free_misc_vector - Free the vector that handles non-queue events
4268 * @pf: board private structure
4269 **/
i40e_free_misc_vector(struct i40e_pf * pf)4270 static void i40e_free_misc_vector(struct i40e_pf *pf)
4271 {
4272 /* Disable ICR 0 */
4273 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
4274 i40e_flush(&pf->hw);
4275
4276 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags) && pf->msix_entries) {
4277 free_irq(pf->msix_entries[0].vector, pf);
4278 clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state);
4279 }
4280 }
4281
4282 /**
4283 * i40e_intr - MSI/Legacy and non-queue interrupt handler
4284 * @irq: interrupt number
4285 * @data: pointer to a q_vector
4286 *
4287 * This is the handler used for all MSI/Legacy interrupts, and deals
4288 * with both queue and non-queue interrupts. This is also used in
4289 * MSIX mode to handle the non-queue interrupts.
4290 **/
i40e_intr(int irq,void * data)4291 static irqreturn_t i40e_intr(int irq, void *data)
4292 {
4293 struct i40e_pf *pf = (struct i40e_pf *)data;
4294 struct i40e_hw *hw = &pf->hw;
4295 irqreturn_t ret = IRQ_NONE;
4296 u32 icr0, icr0_remaining;
4297 u32 val, ena_mask;
4298
4299 icr0 = rd32(hw, I40E_PFINT_ICR0);
4300 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
4301
4302 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
4303 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
4304 goto enable_intr;
4305
4306 /* if interrupt but no bits showing, must be SWINT */
4307 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
4308 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
4309 pf->sw_int_count++;
4310
4311 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags) &&
4312 (icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
4313 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
4314 dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n");
4315 set_bit(__I40E_CORE_RESET_REQUESTED, pf->state);
4316 }
4317
4318 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
4319 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
4320 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4321 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
4322
4323 /* We do not have a way to disarm Queue causes while leaving
4324 * interrupt enabled for all other causes, ideally
4325 * interrupt should be disabled while we are in NAPI but
4326 * this is not a performance path and napi_schedule()
4327 * can deal with rescheduling.
4328 */
4329 if (!test_bit(__I40E_DOWN, pf->state))
4330 napi_schedule_irqoff(&q_vector->napi);
4331 }
4332
4333 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4334 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4335 set_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state);
4336 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
4337 }
4338
4339 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
4340 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
4341 set_bit(__I40E_MDD_EVENT_PENDING, pf->state);
4342 }
4343
4344 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4345 /* disable any further VFLR event notifications */
4346 if (test_bit(__I40E_VF_RESETS_DISABLED, pf->state)) {
4347 u32 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
4348
4349 reg &= ~I40E_PFINT_ICR0_VFLR_MASK;
4350 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
4351 } else {
4352 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
4353 set_bit(__I40E_VFLR_EVENT_PENDING, pf->state);
4354 }
4355 }
4356
4357 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
4358 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
4359 set_bit(__I40E_RESET_INTR_RECEIVED, pf->state);
4360 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
4361 val = rd32(hw, I40E_GLGEN_RSTAT);
4362 val = FIELD_GET(I40E_GLGEN_RSTAT_RESET_TYPE_MASK, val);
4363 if (val == I40E_RESET_CORER) {
4364 pf->corer_count++;
4365 } else if (val == I40E_RESET_GLOBR) {
4366 pf->globr_count++;
4367 } else if (val == I40E_RESET_EMPR) {
4368 pf->empr_count++;
4369 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state);
4370 }
4371 }
4372
4373 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
4374 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
4375 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
4376 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
4377 rd32(hw, I40E_PFHMC_ERRORINFO),
4378 rd32(hw, I40E_PFHMC_ERRORDATA));
4379 }
4380
4381 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
4382 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
4383
4384 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_EVENT0_MASK)
4385 schedule_work(&pf->ptp_extts0_work);
4386
4387 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK)
4388 i40e_ptp_tx_hwtstamp(pf);
4389
4390 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
4391 }
4392
4393 /* If a critical error is pending we have no choice but to reset the
4394 * device.
4395 * Report and mask out any remaining unexpected interrupts.
4396 */
4397 icr0_remaining = icr0 & ena_mask;
4398 if (icr0_remaining) {
4399 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
4400 icr0_remaining);
4401 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
4402 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
4403 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
4404 dev_info(&pf->pdev->dev, "device will be reset\n");
4405 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
4406 i40e_service_event_schedule(pf);
4407 }
4408 ena_mask &= ~icr0_remaining;
4409 }
4410 ret = IRQ_HANDLED;
4411
4412 enable_intr:
4413 /* re-enable interrupt causes */
4414 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
4415 if (!test_bit(__I40E_DOWN, pf->state) ||
4416 test_bit(__I40E_RECOVERY_MODE, pf->state)) {
4417 i40e_service_event_schedule(pf);
4418 i40e_irq_dynamic_enable_icr0(pf);
4419 }
4420
4421 return ret;
4422 }
4423
4424 /**
4425 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
4426 * @tx_ring: tx ring to clean
4427 * @budget: how many cleans we're allowed
4428 *
4429 * Returns true if there's any budget left (e.g. the clean is finished)
4430 **/
i40e_clean_fdir_tx_irq(struct i40e_ring * tx_ring,int budget)4431 static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
4432 {
4433 struct i40e_vsi *vsi = tx_ring->vsi;
4434 u16 i = tx_ring->next_to_clean;
4435 struct i40e_tx_buffer *tx_buf;
4436 struct i40e_tx_desc *tx_desc;
4437
4438 tx_buf = &tx_ring->tx_bi[i];
4439 tx_desc = I40E_TX_DESC(tx_ring, i);
4440 i -= tx_ring->count;
4441
4442 do {
4443 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
4444
4445 /* if next_to_watch is not set then there is no work pending */
4446 if (!eop_desc)
4447 break;
4448
4449 /* prevent any other reads prior to eop_desc */
4450 smp_rmb();
4451
4452 /* if the descriptor isn't done, no work yet to do */
4453 if (!(eop_desc->cmd_type_offset_bsz &
4454 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
4455 break;
4456
4457 /* clear next_to_watch to prevent false hangs */
4458 tx_buf->next_to_watch = NULL;
4459
4460 tx_desc->buffer_addr = 0;
4461 tx_desc->cmd_type_offset_bsz = 0;
4462 /* move past filter desc */
4463 tx_buf++;
4464 tx_desc++;
4465 i++;
4466 if (unlikely(!i)) {
4467 i -= tx_ring->count;
4468 tx_buf = tx_ring->tx_bi;
4469 tx_desc = I40E_TX_DESC(tx_ring, 0);
4470 }
4471 /* unmap skb header data */
4472 dma_unmap_single(tx_ring->dev,
4473 dma_unmap_addr(tx_buf, dma),
4474 dma_unmap_len(tx_buf, len),
4475 DMA_TO_DEVICE);
4476 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
4477 kfree(tx_buf->raw_buf);
4478
4479 tx_buf->raw_buf = NULL;
4480 tx_buf->tx_flags = 0;
4481 tx_buf->next_to_watch = NULL;
4482 dma_unmap_len_set(tx_buf, len, 0);
4483 tx_desc->buffer_addr = 0;
4484 tx_desc->cmd_type_offset_bsz = 0;
4485
4486 /* move us past the eop_desc for start of next FD desc */
4487 tx_buf++;
4488 tx_desc++;
4489 i++;
4490 if (unlikely(!i)) {
4491 i -= tx_ring->count;
4492 tx_buf = tx_ring->tx_bi;
4493 tx_desc = I40E_TX_DESC(tx_ring, 0);
4494 }
4495
4496 /* update budget accounting */
4497 budget--;
4498 } while (likely(budget));
4499
4500 i += tx_ring->count;
4501 tx_ring->next_to_clean = i;
4502
4503 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags))
4504 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
4505
4506 return budget > 0;
4507 }
4508
4509 /**
4510 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
4511 * @irq: interrupt number
4512 * @data: pointer to a q_vector
4513 **/
i40e_fdir_clean_ring(int irq,void * data)4514 static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
4515 {
4516 struct i40e_q_vector *q_vector = data;
4517 struct i40e_vsi *vsi;
4518
4519 if (!q_vector->tx.ring)
4520 return IRQ_HANDLED;
4521
4522 vsi = q_vector->tx.ring->vsi;
4523 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
4524
4525 return IRQ_HANDLED;
4526 }
4527
4528 /**
4529 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
4530 * @vsi: the VSI being configured
4531 * @v_idx: vector index
4532 * @qp_idx: queue pair index
4533 **/
i40e_map_vector_to_qp(struct i40e_vsi * vsi,int v_idx,int qp_idx)4534 static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
4535 {
4536 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
4537 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
4538 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
4539
4540 tx_ring->q_vector = q_vector;
4541 tx_ring->next = q_vector->tx.ring;
4542 q_vector->tx.ring = tx_ring;
4543 q_vector->tx.count++;
4544
4545 /* Place XDP Tx ring in the same q_vector ring list as regular Tx */
4546 if (i40e_enabled_xdp_vsi(vsi)) {
4547 struct i40e_ring *xdp_ring = vsi->xdp_rings[qp_idx];
4548
4549 xdp_ring->q_vector = q_vector;
4550 xdp_ring->next = q_vector->tx.ring;
4551 q_vector->tx.ring = xdp_ring;
4552 q_vector->tx.count++;
4553 }
4554
4555 rx_ring->q_vector = q_vector;
4556 rx_ring->next = q_vector->rx.ring;
4557 q_vector->rx.ring = rx_ring;
4558 q_vector->rx.count++;
4559 }
4560
4561 /**
4562 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
4563 * @vsi: the VSI being configured
4564 *
4565 * This function maps descriptor rings to the queue-specific vectors
4566 * we were allotted through the MSI-X enabling code. Ideally, we'd have
4567 * one vector per queue pair, but on a constrained vector budget, we
4568 * group the queue pairs as "efficiently" as possible.
4569 **/
i40e_vsi_map_rings_to_vectors(struct i40e_vsi * vsi)4570 static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
4571 {
4572 int qp_remaining = vsi->num_queue_pairs;
4573 int q_vectors = vsi->num_q_vectors;
4574 int num_ringpairs;
4575 int v_start = 0;
4576 int qp_idx = 0;
4577
4578 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
4579 * group them so there are multiple queues per vector.
4580 * It is also important to go through all the vectors available to be
4581 * sure that if we don't use all the vectors, that the remaining vectors
4582 * are cleared. This is especially important when decreasing the
4583 * number of queues in use.
4584 */
4585 for (; v_start < q_vectors; v_start++) {
4586 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
4587
4588 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
4589
4590 q_vector->num_ringpairs = num_ringpairs;
4591 q_vector->reg_idx = q_vector->v_idx + vsi->base_vector - 1;
4592
4593 q_vector->rx.count = 0;
4594 q_vector->tx.count = 0;
4595 q_vector->rx.ring = NULL;
4596 q_vector->tx.ring = NULL;
4597
4598 while (num_ringpairs--) {
4599 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
4600 qp_idx++;
4601 qp_remaining--;
4602 }
4603 }
4604 }
4605
4606 /**
4607 * i40e_vsi_request_irq - Request IRQ from the OS
4608 * @vsi: the VSI being configured
4609 * @basename: name for the vector
4610 **/
i40e_vsi_request_irq(struct i40e_vsi * vsi,char * basename)4611 static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
4612 {
4613 struct i40e_pf *pf = vsi->back;
4614 int err;
4615
4616 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
4617 err = i40e_vsi_request_irq_msix(vsi, basename);
4618 else if (test_bit(I40E_FLAG_MSI_ENA, pf->flags))
4619 err = request_irq(pf->pdev->irq, i40e_intr, 0,
4620 pf->int_name, pf);
4621 else
4622 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
4623 pf->int_name, pf);
4624
4625 if (err)
4626 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
4627
4628 return err;
4629 }
4630
4631 #ifdef CONFIG_NET_POLL_CONTROLLER
4632 /**
4633 * i40e_netpoll - A Polling 'interrupt' handler
4634 * @netdev: network interface device structure
4635 *
4636 * This is used by netconsole to send skbs without having to re-enable
4637 * interrupts. It's not called while the normal interrupt routine is executing.
4638 **/
i40e_netpoll(struct net_device * netdev)4639 static void i40e_netpoll(struct net_device *netdev)
4640 {
4641 struct i40e_netdev_priv *np = netdev_priv(netdev);
4642 struct i40e_vsi *vsi = np->vsi;
4643 struct i40e_pf *pf = vsi->back;
4644 int i;
4645
4646 /* if interface is down do nothing */
4647 if (test_bit(__I40E_VSI_DOWN, vsi->state))
4648 return;
4649
4650 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
4651 for (i = 0; i < vsi->num_q_vectors; i++)
4652 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
4653 } else {
4654 i40e_intr(pf->pdev->irq, netdev);
4655 }
4656 }
4657 #endif
4658
4659 #define I40E_QTX_ENA_WAIT_COUNT 50
4660
4661 /**
4662 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
4663 * @pf: the PF being configured
4664 * @pf_q: the PF queue
4665 * @enable: enable or disable state of the queue
4666 *
4667 * This routine will wait for the given Tx queue of the PF to reach the
4668 * enabled or disabled state.
4669 * Returns -ETIMEDOUT in case of failing to reach the requested state after
4670 * multiple retries; else will return 0 in case of success.
4671 **/
i40e_pf_txq_wait(struct i40e_pf * pf,int pf_q,bool enable)4672 static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
4673 {
4674 int i;
4675 u32 tx_reg;
4676
4677 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
4678 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
4679 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
4680 break;
4681
4682 usleep_range(10, 20);
4683 }
4684 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
4685 return -ETIMEDOUT;
4686
4687 return 0;
4688 }
4689
4690 /**
4691 * i40e_control_tx_q - Start or stop a particular Tx queue
4692 * @pf: the PF structure
4693 * @pf_q: the PF queue to configure
4694 * @enable: start or stop the queue
4695 *
4696 * This function enables or disables a single queue. Note that any delay
4697 * required after the operation is expected to be handled by the caller of
4698 * this function.
4699 **/
i40e_control_tx_q(struct i40e_pf * pf,int pf_q,bool enable)4700 static void i40e_control_tx_q(struct i40e_pf *pf, int pf_q, bool enable)
4701 {
4702 struct i40e_hw *hw = &pf->hw;
4703 u32 tx_reg;
4704 int i;
4705
4706 /* warn the TX unit of coming changes */
4707 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
4708 if (!enable)
4709 usleep_range(10, 20);
4710
4711 for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) {
4712 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
4713 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
4714 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
4715 break;
4716 usleep_range(1000, 2000);
4717 }
4718
4719 /* Skip if the queue is already in the requested state */
4720 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
4721 return;
4722
4723 /* turn on/off the queue */
4724 if (enable) {
4725 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
4726 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4727 } else {
4728 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4729 }
4730
4731 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
4732 }
4733
4734 /**
4735 * i40e_control_wait_tx_q - Start/stop Tx queue and wait for completion
4736 * @seid: VSI SEID
4737 * @pf: the PF structure
4738 * @pf_q: the PF queue to configure
4739 * @is_xdp: true if the queue is used for XDP
4740 * @enable: start or stop the queue
4741 **/
i40e_control_wait_tx_q(int seid,struct i40e_pf * pf,int pf_q,bool is_xdp,bool enable)4742 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q,
4743 bool is_xdp, bool enable)
4744 {
4745 int ret;
4746
4747 i40e_control_tx_q(pf, pf_q, enable);
4748
4749 /* wait for the change to finish */
4750 ret = i40e_pf_txq_wait(pf, pf_q, enable);
4751 if (ret) {
4752 dev_info(&pf->pdev->dev,
4753 "VSI seid %d %sTx ring %d %sable timeout\n",
4754 seid, (is_xdp ? "XDP " : ""), pf_q,
4755 (enable ? "en" : "dis"));
4756 }
4757
4758 return ret;
4759 }
4760
4761 /**
4762 * i40e_vsi_enable_tx - Start a VSI's rings
4763 * @vsi: the VSI being configured
4764 **/
i40e_vsi_enable_tx(struct i40e_vsi * vsi)4765 static int i40e_vsi_enable_tx(struct i40e_vsi *vsi)
4766 {
4767 struct i40e_pf *pf = vsi->back;
4768 int i, pf_q, ret = 0;
4769
4770 pf_q = vsi->base_queue;
4771 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4772 ret = i40e_control_wait_tx_q(vsi->seid, pf,
4773 pf_q,
4774 false /*is xdp*/, true);
4775 if (ret)
4776 break;
4777
4778 if (!i40e_enabled_xdp_vsi(vsi))
4779 continue;
4780
4781 ret = i40e_control_wait_tx_q(vsi->seid, pf,
4782 pf_q + vsi->alloc_queue_pairs,
4783 true /*is xdp*/, true);
4784 if (ret)
4785 break;
4786 }
4787 return ret;
4788 }
4789
4790 /**
4791 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
4792 * @pf: the PF being configured
4793 * @pf_q: the PF queue
4794 * @enable: enable or disable state of the queue
4795 *
4796 * This routine will wait for the given Rx queue of the PF to reach the
4797 * enabled or disabled state.
4798 * Returns -ETIMEDOUT in case of failing to reach the requested state after
4799 * multiple retries; else will return 0 in case of success.
4800 **/
i40e_pf_rxq_wait(struct i40e_pf * pf,int pf_q,bool enable)4801 static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
4802 {
4803 int i;
4804 u32 rx_reg;
4805
4806 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
4807 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
4808 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
4809 break;
4810
4811 usleep_range(10, 20);
4812 }
4813 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
4814 return -ETIMEDOUT;
4815
4816 return 0;
4817 }
4818
4819 /**
4820 * i40e_control_rx_q - Start or stop a particular Rx queue
4821 * @pf: the PF structure
4822 * @pf_q: the PF queue to configure
4823 * @enable: start or stop the queue
4824 *
4825 * This function enables or disables a single queue. Note that
4826 * any delay required after the operation is expected to be
4827 * handled by the caller of this function.
4828 **/
i40e_control_rx_q(struct i40e_pf * pf,int pf_q,bool enable)4829 static void i40e_control_rx_q(struct i40e_pf *pf, int pf_q, bool enable)
4830 {
4831 struct i40e_hw *hw = &pf->hw;
4832 u32 rx_reg;
4833 int i;
4834
4835 for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) {
4836 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
4837 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
4838 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
4839 break;
4840 usleep_range(1000, 2000);
4841 }
4842
4843 /* Skip if the queue is already in the requested state */
4844 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
4845 return;
4846
4847 /* turn on/off the queue */
4848 if (enable)
4849 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4850 else
4851 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4852
4853 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
4854 }
4855
4856 /**
4857 * i40e_control_wait_rx_q
4858 * @pf: the PF structure
4859 * @pf_q: queue being configured
4860 * @enable: start or stop the rings
4861 *
4862 * This function enables or disables a single queue along with waiting
4863 * for the change to finish. The caller of this function should handle
4864 * the delays needed in the case of disabling queues.
4865 **/
i40e_control_wait_rx_q(struct i40e_pf * pf,int pf_q,bool enable)4866 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable)
4867 {
4868 int ret = 0;
4869
4870 i40e_control_rx_q(pf, pf_q, enable);
4871
4872 /* wait for the change to finish */
4873 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
4874 if (ret)
4875 return ret;
4876
4877 return ret;
4878 }
4879
4880 /**
4881 * i40e_vsi_enable_rx - Start a VSI's rings
4882 * @vsi: the VSI being configured
4883 **/
i40e_vsi_enable_rx(struct i40e_vsi * vsi)4884 static int i40e_vsi_enable_rx(struct i40e_vsi *vsi)
4885 {
4886 struct i40e_pf *pf = vsi->back;
4887 int i, pf_q, ret = 0;
4888
4889 pf_q = vsi->base_queue;
4890 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4891 ret = i40e_control_wait_rx_q(pf, pf_q, true);
4892 if (ret) {
4893 dev_info(&pf->pdev->dev,
4894 "VSI seid %d Rx ring %d enable timeout\n",
4895 vsi->seid, pf_q);
4896 break;
4897 }
4898 }
4899
4900 return ret;
4901 }
4902
4903 /**
4904 * i40e_vsi_start_rings - Start a VSI's rings
4905 * @vsi: the VSI being configured
4906 **/
i40e_vsi_start_rings(struct i40e_vsi * vsi)4907 int i40e_vsi_start_rings(struct i40e_vsi *vsi)
4908 {
4909 int ret = 0;
4910
4911 /* do rx first for enable and last for disable */
4912 ret = i40e_vsi_enable_rx(vsi);
4913 if (ret)
4914 return ret;
4915 ret = i40e_vsi_enable_tx(vsi);
4916
4917 return ret;
4918 }
4919
4920 #define I40E_DISABLE_TX_GAP_MSEC 50
4921
4922 /**
4923 * i40e_vsi_stop_rings - Stop a VSI's rings
4924 * @vsi: the VSI being configured
4925 **/
i40e_vsi_stop_rings(struct i40e_vsi * vsi)4926 void i40e_vsi_stop_rings(struct i40e_vsi *vsi)
4927 {
4928 struct i40e_pf *pf = vsi->back;
4929 u32 pf_q, tx_q_end, rx_q_end;
4930
4931 /* When port TX is suspended, don't wait */
4932 if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state))
4933 return i40e_vsi_stop_rings_no_wait(vsi);
4934
4935 tx_q_end = vsi->base_queue +
4936 vsi->alloc_queue_pairs * (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
4937 for (pf_q = vsi->base_queue; pf_q < tx_q_end; pf_q++)
4938 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, false);
4939
4940 rx_q_end = vsi->base_queue + vsi->num_queue_pairs;
4941 for (pf_q = vsi->base_queue; pf_q < rx_q_end; pf_q++)
4942 i40e_control_rx_q(pf, pf_q, false);
4943
4944 msleep(I40E_DISABLE_TX_GAP_MSEC);
4945 for (pf_q = vsi->base_queue; pf_q < tx_q_end; pf_q++)
4946 wr32(&pf->hw, I40E_QTX_ENA(pf_q), 0);
4947
4948 i40e_vsi_wait_queues_disabled(vsi);
4949 }
4950
4951 /**
4952 * i40e_vsi_stop_rings_no_wait - Stop a VSI's rings and do not delay
4953 * @vsi: the VSI being shutdown
4954 *
4955 * This function stops all the rings for a VSI but does not delay to verify
4956 * that rings have been disabled. It is expected that the caller is shutting
4957 * down multiple VSIs at once and will delay together for all the VSIs after
4958 * initiating the shutdown. This is particularly useful for shutting down lots
4959 * of VFs together. Otherwise, a large delay can be incurred while configuring
4960 * each VSI in serial.
4961 **/
i40e_vsi_stop_rings_no_wait(struct i40e_vsi * vsi)4962 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi)
4963 {
4964 struct i40e_pf *pf = vsi->back;
4965 int i, pf_q;
4966
4967 pf_q = vsi->base_queue;
4968 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4969 i40e_control_tx_q(pf, pf_q, false);
4970 i40e_control_rx_q(pf, pf_q, false);
4971 }
4972 }
4973
4974 /**
4975 * i40e_vsi_free_irq - Free the irq association with the OS
4976 * @vsi: the VSI being configured
4977 **/
i40e_vsi_free_irq(struct i40e_vsi * vsi)4978 static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
4979 {
4980 struct i40e_pf *pf = vsi->back;
4981 struct i40e_hw *hw = &pf->hw;
4982 int base = vsi->base_vector;
4983 u32 val, qp;
4984 int i;
4985
4986 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
4987 if (!vsi->q_vectors)
4988 return;
4989
4990 if (!vsi->irqs_ready)
4991 return;
4992
4993 vsi->irqs_ready = false;
4994 for (i = 0; i < vsi->num_q_vectors; i++) {
4995 int irq_num;
4996 u16 vector;
4997
4998 vector = i + base;
4999 irq_num = pf->msix_entries[vector].vector;
5000
5001 /* free only the irqs that were actually requested */
5002 if (!vsi->q_vectors[i] ||
5003 !vsi->q_vectors[i]->num_ringpairs)
5004 continue;
5005
5006 /* clear the affinity notifier in the IRQ descriptor */
5007 irq_set_affinity_notifier(irq_num, NULL);
5008 /* remove our suggested affinity mask for this IRQ */
5009 irq_update_affinity_hint(irq_num, NULL);
5010 free_irq(irq_num, vsi->q_vectors[i]);
5011
5012 /* Tear down the interrupt queue link list
5013 *
5014 * We know that they come in pairs and always
5015 * the Rx first, then the Tx. To clear the
5016 * link list, stick the EOL value into the
5017 * next_q field of the registers.
5018 */
5019 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
5020 qp = FIELD_GET(I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK,
5021 val);
5022 val |= I40E_QUEUE_END_OF_LIST
5023 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
5024 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
5025
5026 while (qp != I40E_QUEUE_END_OF_LIST) {
5027 u32 next;
5028
5029 val = rd32(hw, I40E_QINT_RQCTL(qp));
5030
5031 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
5032 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
5033 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
5034 I40E_QINT_RQCTL_INTEVENT_MASK);
5035
5036 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
5037 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
5038
5039 wr32(hw, I40E_QINT_RQCTL(qp), val);
5040
5041 val = rd32(hw, I40E_QINT_TQCTL(qp));
5042
5043 next = FIELD_GET(I40E_QINT_TQCTL_NEXTQ_INDX_MASK,
5044 val);
5045
5046 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
5047 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
5048 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
5049 I40E_QINT_TQCTL_INTEVENT_MASK);
5050
5051 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
5052 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
5053
5054 wr32(hw, I40E_QINT_TQCTL(qp), val);
5055 qp = next;
5056 }
5057 }
5058 } else {
5059 free_irq(pf->pdev->irq, pf);
5060
5061 val = rd32(hw, I40E_PFINT_LNKLST0);
5062 qp = FIELD_GET(I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK, val);
5063 val |= I40E_QUEUE_END_OF_LIST
5064 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
5065 wr32(hw, I40E_PFINT_LNKLST0, val);
5066
5067 val = rd32(hw, I40E_QINT_RQCTL(qp));
5068 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
5069 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
5070 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
5071 I40E_QINT_RQCTL_INTEVENT_MASK);
5072
5073 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
5074 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
5075
5076 wr32(hw, I40E_QINT_RQCTL(qp), val);
5077
5078 val = rd32(hw, I40E_QINT_TQCTL(qp));
5079
5080 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
5081 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
5082 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
5083 I40E_QINT_TQCTL_INTEVENT_MASK);
5084
5085 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
5086 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
5087
5088 wr32(hw, I40E_QINT_TQCTL(qp), val);
5089 }
5090 }
5091
5092 /**
5093 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
5094 * @vsi: the VSI being configured
5095 * @v_idx: Index of vector to be freed
5096 *
5097 * This function frees the memory allocated to the q_vector. In addition if
5098 * NAPI is enabled it will delete any references to the NAPI struct prior
5099 * to freeing the q_vector.
5100 **/
i40e_free_q_vector(struct i40e_vsi * vsi,int v_idx)5101 static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
5102 {
5103 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
5104 struct i40e_ring *ring;
5105
5106 if (!q_vector)
5107 return;
5108
5109 /* disassociate q_vector from rings */
5110 i40e_for_each_ring(ring, q_vector->tx)
5111 ring->q_vector = NULL;
5112
5113 i40e_for_each_ring(ring, q_vector->rx)
5114 ring->q_vector = NULL;
5115
5116 /* only VSI w/ an associated netdev is set up w/ NAPI */
5117 if (vsi->netdev)
5118 netif_napi_del(&q_vector->napi);
5119
5120 vsi->q_vectors[v_idx] = NULL;
5121
5122 kfree_rcu(q_vector, rcu);
5123 }
5124
5125 /**
5126 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
5127 * @vsi: the VSI being un-configured
5128 *
5129 * This frees the memory allocated to the q_vectors and
5130 * deletes references to the NAPI struct.
5131 **/
i40e_vsi_free_q_vectors(struct i40e_vsi * vsi)5132 static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
5133 {
5134 int v_idx;
5135
5136 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
5137 i40e_free_q_vector(vsi, v_idx);
5138 }
5139
5140 /**
5141 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
5142 * @pf: board private structure
5143 **/
i40e_reset_interrupt_capability(struct i40e_pf * pf)5144 static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
5145 {
5146 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
5147 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
5148 pci_disable_msix(pf->pdev);
5149 kfree(pf->msix_entries);
5150 pf->msix_entries = NULL;
5151 kfree(pf->irq_pile);
5152 pf->irq_pile = NULL;
5153 } else if (test_bit(I40E_FLAG_MSI_ENA, pf->flags)) {
5154 pci_disable_msi(pf->pdev);
5155 }
5156 clear_bit(I40E_FLAG_MSI_ENA, pf->flags);
5157 clear_bit(I40E_FLAG_MSIX_ENA, pf->flags);
5158 }
5159
5160 /**
5161 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
5162 * @pf: board private structure
5163 *
5164 * We go through and clear interrupt specific resources and reset the structure
5165 * to pre-load conditions
5166 **/
i40e_clear_interrupt_scheme(struct i40e_pf * pf)5167 static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
5168 {
5169 int i;
5170
5171 if (test_bit(__I40E_MISC_IRQ_REQUESTED, pf->state))
5172 i40e_free_misc_vector(pf);
5173
5174 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
5175 I40E_IWARP_IRQ_PILE_ID);
5176
5177 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
5178 for (i = 0; i < pf->num_alloc_vsi; i++)
5179 if (pf->vsi[i])
5180 i40e_vsi_free_q_vectors(pf->vsi[i]);
5181 i40e_reset_interrupt_capability(pf);
5182 }
5183
5184 /**
5185 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
5186 * @vsi: the VSI being configured
5187 **/
i40e_napi_enable_all(struct i40e_vsi * vsi)5188 static void i40e_napi_enable_all(struct i40e_vsi *vsi)
5189 {
5190 int q_idx;
5191
5192 if (!vsi->netdev)
5193 return;
5194
5195 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) {
5196 struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx];
5197
5198 if (q_vector->rx.ring || q_vector->tx.ring)
5199 napi_enable(&q_vector->napi);
5200 }
5201 }
5202
5203 /**
5204 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
5205 * @vsi: the VSI being configured
5206 **/
i40e_napi_disable_all(struct i40e_vsi * vsi)5207 static void i40e_napi_disable_all(struct i40e_vsi *vsi)
5208 {
5209 int q_idx;
5210
5211 if (!vsi->netdev)
5212 return;
5213
5214 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) {
5215 struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx];
5216
5217 if (q_vector->rx.ring || q_vector->tx.ring)
5218 napi_disable(&q_vector->napi);
5219 }
5220 }
5221
5222 /**
5223 * i40e_vsi_close - Shut down a VSI
5224 * @vsi: the vsi to be quelled
5225 **/
i40e_vsi_close(struct i40e_vsi * vsi)5226 static void i40e_vsi_close(struct i40e_vsi *vsi)
5227 {
5228 struct i40e_pf *pf = vsi->back;
5229 if (!test_and_set_bit(__I40E_VSI_DOWN, vsi->state))
5230 i40e_down(vsi);
5231 i40e_vsi_free_irq(vsi);
5232 i40e_vsi_free_tx_resources(vsi);
5233 i40e_vsi_free_rx_resources(vsi);
5234 vsi->current_netdev_flags = 0;
5235 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
5236 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
5237 set_bit(__I40E_CLIENT_RESET, pf->state);
5238 }
5239
5240 /**
5241 * i40e_quiesce_vsi - Pause a given VSI
5242 * @vsi: the VSI being paused
5243 **/
i40e_quiesce_vsi(struct i40e_vsi * vsi)5244 static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
5245 {
5246 if (test_bit(__I40E_VSI_DOWN, vsi->state))
5247 return;
5248
5249 set_bit(__I40E_VSI_NEEDS_RESTART, vsi->state);
5250 if (vsi->netdev && netif_running(vsi->netdev))
5251 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
5252 else
5253 i40e_vsi_close(vsi);
5254 }
5255
5256 /**
5257 * i40e_unquiesce_vsi - Resume a given VSI
5258 * @vsi: the VSI being resumed
5259 **/
i40e_unquiesce_vsi(struct i40e_vsi * vsi)5260 static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
5261 {
5262 if (!test_and_clear_bit(__I40E_VSI_NEEDS_RESTART, vsi->state))
5263 return;
5264
5265 if (vsi->netdev && netif_running(vsi->netdev))
5266 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
5267 else
5268 i40e_vsi_open(vsi); /* this clears the DOWN bit */
5269 }
5270
5271 /**
5272 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
5273 * @pf: the PF
5274 **/
i40e_pf_quiesce_all_vsi(struct i40e_pf * pf)5275 static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
5276 {
5277 int v;
5278
5279 for (v = 0; v < pf->num_alloc_vsi; v++) {
5280 if (pf->vsi[v])
5281 i40e_quiesce_vsi(pf->vsi[v]);
5282 }
5283 }
5284
5285 /**
5286 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
5287 * @pf: the PF
5288 **/
i40e_pf_unquiesce_all_vsi(struct i40e_pf * pf)5289 static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
5290 {
5291 int v;
5292
5293 for (v = 0; v < pf->num_alloc_vsi; v++) {
5294 if (pf->vsi[v])
5295 i40e_unquiesce_vsi(pf->vsi[v]);
5296 }
5297 }
5298
5299 /**
5300 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled
5301 * @vsi: the VSI being configured
5302 *
5303 * Wait until all queues on a given VSI have been disabled.
5304 **/
i40e_vsi_wait_queues_disabled(struct i40e_vsi * vsi)5305 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
5306 {
5307 struct i40e_pf *pf = vsi->back;
5308 int i, pf_q, ret;
5309
5310 pf_q = vsi->base_queue;
5311 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
5312 /* Check and wait for the Tx queue */
5313 ret = i40e_pf_txq_wait(pf, pf_q, false);
5314 if (ret) {
5315 dev_info(&pf->pdev->dev,
5316 "VSI seid %d Tx ring %d disable timeout\n",
5317 vsi->seid, pf_q);
5318 return ret;
5319 }
5320
5321 if (!i40e_enabled_xdp_vsi(vsi))
5322 goto wait_rx;
5323
5324 /* Check and wait for the XDP Tx queue */
5325 ret = i40e_pf_txq_wait(pf, pf_q + vsi->alloc_queue_pairs,
5326 false);
5327 if (ret) {
5328 dev_info(&pf->pdev->dev,
5329 "VSI seid %d XDP Tx ring %d disable timeout\n",
5330 vsi->seid, pf_q);
5331 return ret;
5332 }
5333 wait_rx:
5334 /* Check and wait for the Rx queue */
5335 ret = i40e_pf_rxq_wait(pf, pf_q, false);
5336 if (ret) {
5337 dev_info(&pf->pdev->dev,
5338 "VSI seid %d Rx ring %d disable timeout\n",
5339 vsi->seid, pf_q);
5340 return ret;
5341 }
5342 }
5343
5344 return 0;
5345 }
5346
5347 #ifdef CONFIG_I40E_DCB
5348 /**
5349 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled
5350 * @pf: the PF
5351 *
5352 * This function waits for the queues to be in disabled state for all the
5353 * VSIs that are managed by this PF.
5354 **/
i40e_pf_wait_queues_disabled(struct i40e_pf * pf)5355 static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
5356 {
5357 int v, ret = 0;
5358
5359 for (v = 0; v < pf->num_alloc_vsi; v++) {
5360 if (pf->vsi[v]) {
5361 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
5362 if (ret)
5363 break;
5364 }
5365 }
5366
5367 return ret;
5368 }
5369
5370 #endif
5371
5372 /**
5373 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
5374 * @pf: pointer to PF
5375 *
5376 * Get TC map for ISCSI PF type that will include iSCSI TC
5377 * and LAN TC.
5378 **/
i40e_get_iscsi_tc_map(struct i40e_pf * pf)5379 static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
5380 {
5381 struct i40e_dcb_app_priority_table app;
5382 struct i40e_hw *hw = &pf->hw;
5383 u8 enabled_tc = 1; /* TC0 is always enabled */
5384 u8 tc, i;
5385 /* Get the iSCSI APP TLV */
5386 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
5387
5388 for (i = 0; i < dcbcfg->numapps; i++) {
5389 app = dcbcfg->app[i];
5390 if (app.selector == I40E_APP_SEL_TCPIP &&
5391 app.protocolid == I40E_APP_PROTOID_ISCSI) {
5392 tc = dcbcfg->etscfg.prioritytable[app.priority];
5393 enabled_tc |= BIT(tc);
5394 break;
5395 }
5396 }
5397
5398 return enabled_tc;
5399 }
5400
5401 /**
5402 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
5403 * @dcbcfg: the corresponding DCBx configuration structure
5404 *
5405 * Return the number of TCs from given DCBx configuration
5406 **/
i40e_dcb_get_num_tc(struct i40e_dcbx_config * dcbcfg)5407 static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
5408 {
5409 int i, tc_unused = 0;
5410 u8 num_tc = 0;
5411 u8 ret = 0;
5412
5413 /* Scan the ETS Config Priority Table to find
5414 * traffic class enabled for a given priority
5415 * and create a bitmask of enabled TCs
5416 */
5417 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
5418 num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]);
5419
5420 /* Now scan the bitmask to check for
5421 * contiguous TCs starting with TC0
5422 */
5423 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5424 if (num_tc & BIT(i)) {
5425 if (!tc_unused) {
5426 ret++;
5427 } else {
5428 pr_err("Non-contiguous TC - Disabling DCB\n");
5429 return 1;
5430 }
5431 } else {
5432 tc_unused = 1;
5433 }
5434 }
5435
5436 /* There is always at least TC0 */
5437 if (!ret)
5438 ret = 1;
5439
5440 return ret;
5441 }
5442
5443 /**
5444 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
5445 * @dcbcfg: the corresponding DCBx configuration structure
5446 *
5447 * Query the current DCB configuration and return the number of
5448 * traffic classes enabled from the given DCBX config
5449 **/
i40e_dcb_get_enabled_tc(struct i40e_dcbx_config * dcbcfg)5450 static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
5451 {
5452 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
5453 u8 enabled_tc = 1;
5454 u8 i;
5455
5456 for (i = 0; i < num_tc; i++)
5457 enabled_tc |= BIT(i);
5458
5459 return enabled_tc;
5460 }
5461
5462 /**
5463 * i40e_mqprio_get_enabled_tc - Get enabled traffic classes
5464 * @pf: PF being queried
5465 *
5466 * Query the current MQPRIO configuration and return the number of
5467 * traffic classes enabled.
5468 **/
i40e_mqprio_get_enabled_tc(struct i40e_pf * pf)5469 static u8 i40e_mqprio_get_enabled_tc(struct i40e_pf *pf)
5470 {
5471 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
5472 u8 num_tc = vsi->mqprio_qopt.qopt.num_tc;
5473 u8 enabled_tc = 1, i;
5474
5475 for (i = 1; i < num_tc; i++)
5476 enabled_tc |= BIT(i);
5477 return enabled_tc;
5478 }
5479
5480 /**
5481 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
5482 * @pf: PF being queried
5483 *
5484 * Return number of traffic classes enabled for the given PF
5485 **/
i40e_pf_get_num_tc(struct i40e_pf * pf)5486 static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
5487 {
5488 struct i40e_hw *hw = &pf->hw;
5489 u8 i, enabled_tc = 1;
5490 u8 num_tc = 0;
5491 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
5492
5493 if (i40e_is_tc_mqprio_enabled(pf))
5494 return pf->vsi[pf->lan_vsi]->mqprio_qopt.qopt.num_tc;
5495
5496 /* If neither MQPRIO nor DCB is enabled, then always use single TC */
5497 if (!test_bit(I40E_FLAG_DCB_ENA, pf->flags))
5498 return 1;
5499
5500 /* SFP mode will be enabled for all TCs on port */
5501 if (!test_bit(I40E_FLAG_MFP_ENA, pf->flags))
5502 return i40e_dcb_get_num_tc(dcbcfg);
5503
5504 /* MFP mode return count of enabled TCs for this PF */
5505 if (pf->hw.func_caps.iscsi)
5506 enabled_tc = i40e_get_iscsi_tc_map(pf);
5507 else
5508 return 1; /* Only TC0 */
5509
5510 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5511 if (enabled_tc & BIT(i))
5512 num_tc++;
5513 }
5514 return num_tc;
5515 }
5516
5517 /**
5518 * i40e_pf_get_tc_map - Get bitmap for enabled traffic classes
5519 * @pf: PF being queried
5520 *
5521 * Return a bitmap for enabled traffic classes for this PF.
5522 **/
i40e_pf_get_tc_map(struct i40e_pf * pf)5523 static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
5524 {
5525 if (i40e_is_tc_mqprio_enabled(pf))
5526 return i40e_mqprio_get_enabled_tc(pf);
5527
5528 /* If neither MQPRIO nor DCB is enabled for this PF then just return
5529 * default TC
5530 */
5531 if (!test_bit(I40E_FLAG_DCB_ENA, pf->flags))
5532 return I40E_DEFAULT_TRAFFIC_CLASS;
5533
5534 /* SFP mode we want PF to be enabled for all TCs */
5535 if (!test_bit(I40E_FLAG_MFP_ENA, pf->flags))
5536 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
5537
5538 /* MFP enabled and iSCSI PF type */
5539 if (pf->hw.func_caps.iscsi)
5540 return i40e_get_iscsi_tc_map(pf);
5541 else
5542 return I40E_DEFAULT_TRAFFIC_CLASS;
5543 }
5544
5545 /**
5546 * i40e_vsi_get_bw_info - Query VSI BW Information
5547 * @vsi: the VSI being queried
5548 *
5549 * Returns 0 on success, negative value on failure
5550 **/
i40e_vsi_get_bw_info(struct i40e_vsi * vsi)5551 static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
5552 {
5553 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
5554 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
5555 struct i40e_pf *pf = vsi->back;
5556 struct i40e_hw *hw = &pf->hw;
5557 u32 tc_bw_max;
5558 int ret;
5559 int i;
5560
5561 /* Get the VSI level BW configuration */
5562 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5563 if (ret) {
5564 dev_info(&pf->pdev->dev,
5565 "couldn't get PF vsi bw config, err %pe aq_err %s\n",
5566 ERR_PTR(ret),
5567 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
5568 return -EINVAL;
5569 }
5570
5571 /* Get the VSI level BW configuration per TC */
5572 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
5573 NULL);
5574 if (ret) {
5575 dev_info(&pf->pdev->dev,
5576 "couldn't get PF vsi ets bw config, err %pe aq_err %s\n",
5577 ERR_PTR(ret),
5578 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
5579 return -EINVAL;
5580 }
5581
5582 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
5583 dev_info(&pf->pdev->dev,
5584 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
5585 bw_config.tc_valid_bits,
5586 bw_ets_config.tc_valid_bits);
5587 /* Still continuing */
5588 }
5589
5590 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
5591 vsi->bw_max_quanta = bw_config.max_bw;
5592 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
5593 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
5594 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5595 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
5596 vsi->bw_ets_limit_credits[i] =
5597 le16_to_cpu(bw_ets_config.credits[i]);
5598 /* 3 bits out of 4 for each TC */
5599 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
5600 }
5601
5602 return 0;
5603 }
5604
5605 /**
5606 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
5607 * @vsi: the VSI being configured
5608 * @enabled_tc: TC bitmap
5609 * @bw_share: BW shared credits per TC
5610 *
5611 * Returns 0 on success, negative value on failure
5612 **/
i40e_vsi_configure_bw_alloc(struct i40e_vsi * vsi,u8 enabled_tc,u8 * bw_share)5613 static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
5614 u8 *bw_share)
5615 {
5616 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
5617 struct i40e_pf *pf = vsi->back;
5618 int ret;
5619 int i;
5620
5621 /* There is no need to reset BW when mqprio mode is on. */
5622 if (i40e_is_tc_mqprio_enabled(pf))
5623 return 0;
5624 if (!vsi->mqprio_qopt.qopt.hw && !test_bit(I40E_FLAG_DCB_ENA, pf->flags)) {
5625 ret = i40e_set_bw_limit(vsi, vsi->seid, 0);
5626 if (ret)
5627 dev_info(&pf->pdev->dev,
5628 "Failed to reset tx rate for vsi->seid %u\n",
5629 vsi->seid);
5630 return ret;
5631 }
5632 memset(&bw_data, 0, sizeof(bw_data));
5633 bw_data.tc_valid_bits = enabled_tc;
5634 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5635 bw_data.tc_bw_credits[i] = bw_share[i];
5636
5637 ret = i40e_aq_config_vsi_tc_bw(&pf->hw, vsi->seid, &bw_data, NULL);
5638 if (ret) {
5639 dev_info(&pf->pdev->dev,
5640 "AQ command Config VSI BW allocation per TC failed = %d\n",
5641 pf->hw.aq.asq_last_status);
5642 return -EINVAL;
5643 }
5644
5645 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5646 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
5647
5648 return 0;
5649 }
5650
5651 /**
5652 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
5653 * @vsi: the VSI being configured
5654 * @enabled_tc: TC map to be enabled
5655 *
5656 **/
i40e_vsi_config_netdev_tc(struct i40e_vsi * vsi,u8 enabled_tc)5657 static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
5658 {
5659 struct net_device *netdev = vsi->netdev;
5660 struct i40e_pf *pf = vsi->back;
5661 struct i40e_hw *hw = &pf->hw;
5662 u8 netdev_tc = 0;
5663 int i;
5664 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
5665
5666 if (!netdev)
5667 return;
5668
5669 if (!enabled_tc) {
5670 netdev_reset_tc(netdev);
5671 return;
5672 }
5673
5674 /* Set up actual enabled TCs on the VSI */
5675 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
5676 return;
5677
5678 /* set per TC queues for the VSI */
5679 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5680 /* Only set TC queues for enabled tcs
5681 *
5682 * e.g. For a VSI that has TC0 and TC3 enabled the
5683 * enabled_tc bitmap would be 0x00001001; the driver
5684 * will set the numtc for netdev as 2 that will be
5685 * referenced by the netdev layer as TC 0 and 1.
5686 */
5687 if (vsi->tc_config.enabled_tc & BIT(i))
5688 netdev_set_tc_queue(netdev,
5689 vsi->tc_config.tc_info[i].netdev_tc,
5690 vsi->tc_config.tc_info[i].qcount,
5691 vsi->tc_config.tc_info[i].qoffset);
5692 }
5693
5694 if (i40e_is_tc_mqprio_enabled(pf))
5695 return;
5696
5697 /* Assign UP2TC map for the VSI */
5698 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
5699 /* Get the actual TC# for the UP */
5700 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
5701 /* Get the mapped netdev TC# for the UP */
5702 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
5703 netdev_set_prio_tc_map(netdev, i, netdev_tc);
5704 }
5705 }
5706
5707 /**
5708 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
5709 * @vsi: the VSI being configured
5710 * @ctxt: the ctxt buffer returned from AQ VSI update param command
5711 **/
i40e_vsi_update_queue_map(struct i40e_vsi * vsi,struct i40e_vsi_context * ctxt)5712 static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
5713 struct i40e_vsi_context *ctxt)
5714 {
5715 /* copy just the sections touched not the entire info
5716 * since not all sections are valid as returned by
5717 * update vsi params
5718 */
5719 vsi->info.mapping_flags = ctxt->info.mapping_flags;
5720 memcpy(&vsi->info.queue_mapping,
5721 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
5722 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
5723 sizeof(vsi->info.tc_mapping));
5724 }
5725
5726 /**
5727 * i40e_update_adq_vsi_queues - update queue mapping for ADq VSI
5728 * @vsi: the VSI being reconfigured
5729 * @vsi_offset: offset from main VF VSI
5730 */
i40e_update_adq_vsi_queues(struct i40e_vsi * vsi,int vsi_offset)5731 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset)
5732 {
5733 struct i40e_vsi_context ctxt = {};
5734 struct i40e_pf *pf;
5735 struct i40e_hw *hw;
5736 int ret;
5737
5738 if (!vsi)
5739 return -EINVAL;
5740 pf = vsi->back;
5741 hw = &pf->hw;
5742
5743 ctxt.seid = vsi->seid;
5744 ctxt.pf_num = hw->pf_id;
5745 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id + vsi_offset;
5746 ctxt.uplink_seid = vsi->uplink_seid;
5747 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
5748 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5749 ctxt.info = vsi->info;
5750
5751 i40e_vsi_setup_queue_map(vsi, &ctxt, vsi->tc_config.enabled_tc,
5752 false);
5753 if (vsi->reconfig_rss) {
5754 vsi->rss_size = min_t(int, pf->alloc_rss_size,
5755 vsi->num_queue_pairs);
5756 ret = i40e_vsi_config_rss(vsi);
5757 if (ret) {
5758 dev_info(&pf->pdev->dev, "Failed to reconfig rss for num_queues\n");
5759 return ret;
5760 }
5761 vsi->reconfig_rss = false;
5762 }
5763
5764 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5765 if (ret) {
5766 dev_info(&pf->pdev->dev, "Update vsi config failed, err %pe aq_err %s\n",
5767 ERR_PTR(ret),
5768 i40e_aq_str(hw, hw->aq.asq_last_status));
5769 return ret;
5770 }
5771 /* update the local VSI info with updated queue map */
5772 i40e_vsi_update_queue_map(vsi, &ctxt);
5773 vsi->info.valid_sections = 0;
5774
5775 return ret;
5776 }
5777
5778 /**
5779 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
5780 * @vsi: VSI to be configured
5781 * @enabled_tc: TC bitmap
5782 *
5783 * This configures a particular VSI for TCs that are mapped to the
5784 * given TC bitmap. It uses default bandwidth share for TCs across
5785 * VSIs to configure TC for a particular VSI.
5786 *
5787 * NOTE:
5788 * It is expected that the VSI queues have been quisced before calling
5789 * this function.
5790 **/
i40e_vsi_config_tc(struct i40e_vsi * vsi,u8 enabled_tc)5791 static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
5792 {
5793 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
5794 struct i40e_pf *pf = vsi->back;
5795 struct i40e_hw *hw = &pf->hw;
5796 struct i40e_vsi_context ctxt;
5797 int ret = 0;
5798 int i;
5799
5800 /* Check if enabled_tc is same as existing or new TCs */
5801 if (vsi->tc_config.enabled_tc == enabled_tc &&
5802 vsi->mqprio_qopt.mode != TC_MQPRIO_MODE_CHANNEL)
5803 return ret;
5804
5805 /* Enable ETS TCs with equal BW Share for now across all VSIs */
5806 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5807 if (enabled_tc & BIT(i))
5808 bw_share[i] = 1;
5809 }
5810
5811 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
5812 if (ret) {
5813 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
5814
5815 dev_info(&pf->pdev->dev,
5816 "Failed configuring TC map %d for VSI %d\n",
5817 enabled_tc, vsi->seid);
5818 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid,
5819 &bw_config, NULL);
5820 if (ret) {
5821 dev_info(&pf->pdev->dev,
5822 "Failed querying vsi bw info, err %pe aq_err %s\n",
5823 ERR_PTR(ret),
5824 i40e_aq_str(hw, hw->aq.asq_last_status));
5825 goto out;
5826 }
5827 if ((bw_config.tc_valid_bits & enabled_tc) != enabled_tc) {
5828 u8 valid_tc = bw_config.tc_valid_bits & enabled_tc;
5829
5830 if (!valid_tc)
5831 valid_tc = bw_config.tc_valid_bits;
5832 /* Always enable TC0, no matter what */
5833 valid_tc |= 1;
5834 dev_info(&pf->pdev->dev,
5835 "Requested tc 0x%x, but FW reports 0x%x as valid. Attempting to use 0x%x.\n",
5836 enabled_tc, bw_config.tc_valid_bits, valid_tc);
5837 enabled_tc = valid_tc;
5838 }
5839
5840 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
5841 if (ret) {
5842 dev_err(&pf->pdev->dev,
5843 "Unable to configure TC map %d for VSI %d\n",
5844 enabled_tc, vsi->seid);
5845 goto out;
5846 }
5847 }
5848
5849 /* Update Queue Pairs Mapping for currently enabled UPs */
5850 ctxt.seid = vsi->seid;
5851 ctxt.pf_num = vsi->back->hw.pf_id;
5852 ctxt.vf_num = 0;
5853 ctxt.uplink_seid = vsi->uplink_seid;
5854 ctxt.info = vsi->info;
5855 if (i40e_is_tc_mqprio_enabled(pf)) {
5856 ret = i40e_vsi_setup_queue_map_mqprio(vsi, &ctxt, enabled_tc);
5857 if (ret)
5858 goto out;
5859 } else {
5860 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
5861 }
5862
5863 /* On destroying the qdisc, reset vsi->rss_size, as number of enabled
5864 * queues changed.
5865 */
5866 if (!vsi->mqprio_qopt.qopt.hw && vsi->reconfig_rss) {
5867 vsi->rss_size = min_t(int, vsi->back->alloc_rss_size,
5868 vsi->num_queue_pairs);
5869 ret = i40e_vsi_config_rss(vsi);
5870 if (ret) {
5871 dev_info(&vsi->back->pdev->dev,
5872 "Failed to reconfig rss for num_queues\n");
5873 return ret;
5874 }
5875 vsi->reconfig_rss = false;
5876 }
5877 if (test_bit(I40E_FLAG_IWARP_ENA, vsi->back->flags)) {
5878 ctxt.info.valid_sections |=
5879 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
5880 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
5881 }
5882
5883 /* Update the VSI after updating the VSI queue-mapping
5884 * information
5885 */
5886 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5887 if (ret) {
5888 dev_info(&pf->pdev->dev,
5889 "Update vsi tc config failed, err %pe aq_err %s\n",
5890 ERR_PTR(ret),
5891 i40e_aq_str(hw, hw->aq.asq_last_status));
5892 goto out;
5893 }
5894 /* update the local VSI info with updated queue map */
5895 i40e_vsi_update_queue_map(vsi, &ctxt);
5896 vsi->info.valid_sections = 0;
5897
5898 /* Update current VSI BW information */
5899 ret = i40e_vsi_get_bw_info(vsi);
5900 if (ret) {
5901 dev_info(&pf->pdev->dev,
5902 "Failed updating vsi bw info, err %pe aq_err %s\n",
5903 ERR_PTR(ret),
5904 i40e_aq_str(hw, hw->aq.asq_last_status));
5905 goto out;
5906 }
5907
5908 /* Update the netdev TC setup */
5909 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
5910 out:
5911 return ret;
5912 }
5913
5914 /**
5915 * i40e_get_link_speed - Returns link speed for the interface
5916 * @vsi: VSI to be configured
5917 *
5918 **/
i40e_get_link_speed(struct i40e_vsi * vsi)5919 static int i40e_get_link_speed(struct i40e_vsi *vsi)
5920 {
5921 struct i40e_pf *pf = vsi->back;
5922
5923 switch (pf->hw.phy.link_info.link_speed) {
5924 case I40E_LINK_SPEED_40GB:
5925 return 40000;
5926 case I40E_LINK_SPEED_25GB:
5927 return 25000;
5928 case I40E_LINK_SPEED_20GB:
5929 return 20000;
5930 case I40E_LINK_SPEED_10GB:
5931 return 10000;
5932 case I40E_LINK_SPEED_1GB:
5933 return 1000;
5934 default:
5935 return -EINVAL;
5936 }
5937 }
5938
5939 /**
5940 * i40e_bw_bytes_to_mbits - Convert max_tx_rate from bytes to mbits
5941 * @vsi: Pointer to vsi structure
5942 * @max_tx_rate: max TX rate in bytes to be converted into Mbits
5943 *
5944 * Helper function to convert units before send to set BW limit
5945 **/
i40e_bw_bytes_to_mbits(struct i40e_vsi * vsi,u64 max_tx_rate)5946 static u64 i40e_bw_bytes_to_mbits(struct i40e_vsi *vsi, u64 max_tx_rate)
5947 {
5948 if (max_tx_rate < I40E_BW_MBPS_DIVISOR) {
5949 dev_warn(&vsi->back->pdev->dev,
5950 "Setting max tx rate to minimum usable value of 50Mbps.\n");
5951 max_tx_rate = I40E_BW_CREDIT_DIVISOR;
5952 } else {
5953 do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR);
5954 }
5955
5956 return max_tx_rate;
5957 }
5958
5959 /**
5960 * i40e_set_bw_limit - setup BW limit for Tx traffic based on max_tx_rate
5961 * @vsi: VSI to be configured
5962 * @seid: seid of the channel/VSI
5963 * @max_tx_rate: max TX rate to be configured as BW limit
5964 *
5965 * Helper function to set BW limit for a given VSI
5966 **/
i40e_set_bw_limit(struct i40e_vsi * vsi,u16 seid,u64 max_tx_rate)5967 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate)
5968 {
5969 struct i40e_pf *pf = vsi->back;
5970 u64 credits = 0;
5971 int speed = 0;
5972 int ret = 0;
5973
5974 speed = i40e_get_link_speed(vsi);
5975 if (max_tx_rate > speed) {
5976 dev_err(&pf->pdev->dev,
5977 "Invalid max tx rate %llu specified for VSI seid %d.",
5978 max_tx_rate, seid);
5979 return -EINVAL;
5980 }
5981 if (max_tx_rate && max_tx_rate < I40E_BW_CREDIT_DIVISOR) {
5982 dev_warn(&pf->pdev->dev,
5983 "Setting max tx rate to minimum usable value of 50Mbps.\n");
5984 max_tx_rate = I40E_BW_CREDIT_DIVISOR;
5985 }
5986
5987 /* Tx rate credits are in values of 50Mbps, 0 is disabled */
5988 credits = max_tx_rate;
5989 do_div(credits, I40E_BW_CREDIT_DIVISOR);
5990 ret = i40e_aq_config_vsi_bw_limit(&pf->hw, seid, credits,
5991 I40E_MAX_BW_INACTIVE_ACCUM, NULL);
5992 if (ret)
5993 dev_err(&pf->pdev->dev,
5994 "Failed set tx rate (%llu Mbps) for vsi->seid %u, err %pe aq_err %s\n",
5995 max_tx_rate, seid, ERR_PTR(ret),
5996 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
5997 return ret;
5998 }
5999
6000 /**
6001 * i40e_remove_queue_channels - Remove queue channels for the TCs
6002 * @vsi: VSI to be configured
6003 *
6004 * Remove queue channels for the TCs
6005 **/
i40e_remove_queue_channels(struct i40e_vsi * vsi)6006 static void i40e_remove_queue_channels(struct i40e_vsi *vsi)
6007 {
6008 enum i40e_admin_queue_err last_aq_status;
6009 struct i40e_cloud_filter *cfilter;
6010 struct i40e_channel *ch, *ch_tmp;
6011 struct i40e_pf *pf = vsi->back;
6012 struct hlist_node *node;
6013 int ret, i;
6014
6015 /* Reset rss size that was stored when reconfiguring rss for
6016 * channel VSIs with non-power-of-2 queue count.
6017 */
6018 vsi->current_rss_size = 0;
6019
6020 /* perform cleanup for channels if they exist */
6021 if (list_empty(&vsi->ch_list))
6022 return;
6023
6024 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) {
6025 struct i40e_vsi *p_vsi;
6026
6027 list_del(&ch->list);
6028 p_vsi = ch->parent_vsi;
6029 if (!p_vsi || !ch->initialized) {
6030 kfree(ch);
6031 continue;
6032 }
6033 /* Reset queue contexts */
6034 for (i = 0; i < ch->num_queue_pairs; i++) {
6035 struct i40e_ring *tx_ring, *rx_ring;
6036 u16 pf_q;
6037
6038 pf_q = ch->base_queue + i;
6039 tx_ring = vsi->tx_rings[pf_q];
6040 tx_ring->ch = NULL;
6041
6042 rx_ring = vsi->rx_rings[pf_q];
6043 rx_ring->ch = NULL;
6044 }
6045
6046 /* Reset BW configured for this VSI via mqprio */
6047 ret = i40e_set_bw_limit(vsi, ch->seid, 0);
6048 if (ret)
6049 dev_info(&vsi->back->pdev->dev,
6050 "Failed to reset tx rate for ch->seid %u\n",
6051 ch->seid);
6052
6053 /* delete cloud filters associated with this channel */
6054 hlist_for_each_entry_safe(cfilter, node,
6055 &pf->cloud_filter_list, cloud_node) {
6056 if (cfilter->seid != ch->seid)
6057 continue;
6058
6059 hash_del(&cfilter->cloud_node);
6060 if (cfilter->dst_port)
6061 ret = i40e_add_del_cloud_filter_big_buf(vsi,
6062 cfilter,
6063 false);
6064 else
6065 ret = i40e_add_del_cloud_filter(vsi, cfilter,
6066 false);
6067 last_aq_status = pf->hw.aq.asq_last_status;
6068 if (ret)
6069 dev_info(&pf->pdev->dev,
6070 "Failed to delete cloud filter, err %pe aq_err %s\n",
6071 ERR_PTR(ret),
6072 i40e_aq_str(&pf->hw, last_aq_status));
6073 kfree(cfilter);
6074 }
6075
6076 /* delete VSI from FW */
6077 ret = i40e_aq_delete_element(&vsi->back->hw, ch->seid,
6078 NULL);
6079 if (ret)
6080 dev_err(&vsi->back->pdev->dev,
6081 "unable to remove channel (%d) for parent VSI(%d)\n",
6082 ch->seid, p_vsi->seid);
6083 kfree(ch);
6084 }
6085 INIT_LIST_HEAD(&vsi->ch_list);
6086 }
6087
6088 /**
6089 * i40e_get_max_queues_for_channel
6090 * @vsi: ptr to VSI to which channels are associated with
6091 *
6092 * Helper function which returns max value among the queue counts set on the
6093 * channels/TCs created.
6094 **/
i40e_get_max_queues_for_channel(struct i40e_vsi * vsi)6095 static int i40e_get_max_queues_for_channel(struct i40e_vsi *vsi)
6096 {
6097 struct i40e_channel *ch, *ch_tmp;
6098 int max = 0;
6099
6100 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) {
6101 if (!ch->initialized)
6102 continue;
6103 if (ch->num_queue_pairs > max)
6104 max = ch->num_queue_pairs;
6105 }
6106
6107 return max;
6108 }
6109
6110 /**
6111 * i40e_validate_num_queues - validate num_queues w.r.t channel
6112 * @pf: ptr to PF device
6113 * @num_queues: number of queues
6114 * @vsi: the parent VSI
6115 * @reconfig_rss: indicates should the RSS be reconfigured or not
6116 *
6117 * This function validates number of queues in the context of new channel
6118 * which is being established and determines if RSS should be reconfigured
6119 * or not for parent VSI.
6120 **/
i40e_validate_num_queues(struct i40e_pf * pf,int num_queues,struct i40e_vsi * vsi,bool * reconfig_rss)6121 static int i40e_validate_num_queues(struct i40e_pf *pf, int num_queues,
6122 struct i40e_vsi *vsi, bool *reconfig_rss)
6123 {
6124 int max_ch_queues;
6125
6126 if (!reconfig_rss)
6127 return -EINVAL;
6128
6129 *reconfig_rss = false;
6130 if (vsi->current_rss_size) {
6131 if (num_queues > vsi->current_rss_size) {
6132 dev_dbg(&pf->pdev->dev,
6133 "Error: num_queues (%d) > vsi's current_size(%d)\n",
6134 num_queues, vsi->current_rss_size);
6135 return -EINVAL;
6136 } else if ((num_queues < vsi->current_rss_size) &&
6137 (!is_power_of_2(num_queues))) {
6138 dev_dbg(&pf->pdev->dev,
6139 "Error: num_queues (%d) < vsi's current_size(%d), but not power of 2\n",
6140 num_queues, vsi->current_rss_size);
6141 return -EINVAL;
6142 }
6143 }
6144
6145 if (!is_power_of_2(num_queues)) {
6146 /* Find the max num_queues configured for channel if channel
6147 * exist.
6148 * if channel exist, then enforce 'num_queues' to be more than
6149 * max ever queues configured for channel.
6150 */
6151 max_ch_queues = i40e_get_max_queues_for_channel(vsi);
6152 if (num_queues < max_ch_queues) {
6153 dev_dbg(&pf->pdev->dev,
6154 "Error: num_queues (%d) < max queues configured for channel(%d)\n",
6155 num_queues, max_ch_queues);
6156 return -EINVAL;
6157 }
6158 *reconfig_rss = true;
6159 }
6160
6161 return 0;
6162 }
6163
6164 /**
6165 * i40e_vsi_reconfig_rss - reconfig RSS based on specified rss_size
6166 * @vsi: the VSI being setup
6167 * @rss_size: size of RSS, accordingly LUT gets reprogrammed
6168 *
6169 * This function reconfigures RSS by reprogramming LUTs using 'rss_size'
6170 **/
i40e_vsi_reconfig_rss(struct i40e_vsi * vsi,u16 rss_size)6171 static int i40e_vsi_reconfig_rss(struct i40e_vsi *vsi, u16 rss_size)
6172 {
6173 struct i40e_pf *pf = vsi->back;
6174 u8 seed[I40E_HKEY_ARRAY_SIZE];
6175 struct i40e_hw *hw = &pf->hw;
6176 int local_rss_size;
6177 u8 *lut;
6178 int ret;
6179
6180 if (!vsi->rss_size)
6181 return -EINVAL;
6182
6183 if (rss_size > vsi->rss_size)
6184 return -EINVAL;
6185
6186 local_rss_size = min_t(int, vsi->rss_size, rss_size);
6187 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
6188 if (!lut)
6189 return -ENOMEM;
6190
6191 /* Ignoring user configured lut if there is one */
6192 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, local_rss_size);
6193
6194 /* Use user configured hash key if there is one, otherwise
6195 * use default.
6196 */
6197 if (vsi->rss_hkey_user)
6198 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
6199 else
6200 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
6201
6202 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
6203 if (ret) {
6204 dev_info(&pf->pdev->dev,
6205 "Cannot set RSS lut, err %pe aq_err %s\n",
6206 ERR_PTR(ret),
6207 i40e_aq_str(hw, hw->aq.asq_last_status));
6208 kfree(lut);
6209 return ret;
6210 }
6211 kfree(lut);
6212
6213 /* Do the update w.r.t. storing rss_size */
6214 if (!vsi->orig_rss_size)
6215 vsi->orig_rss_size = vsi->rss_size;
6216 vsi->current_rss_size = local_rss_size;
6217
6218 return ret;
6219 }
6220
6221 /**
6222 * i40e_channel_setup_queue_map - Setup a channel queue map
6223 * @pf: ptr to PF device
6224 * @ctxt: VSI context structure
6225 * @ch: ptr to channel structure
6226 *
6227 * Setup queue map for a specific channel
6228 **/
i40e_channel_setup_queue_map(struct i40e_pf * pf,struct i40e_vsi_context * ctxt,struct i40e_channel * ch)6229 static void i40e_channel_setup_queue_map(struct i40e_pf *pf,
6230 struct i40e_vsi_context *ctxt,
6231 struct i40e_channel *ch)
6232 {
6233 u16 qcount, qmap, sections = 0;
6234 u8 offset = 0;
6235 int pow;
6236
6237 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
6238 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
6239
6240 qcount = min_t(int, ch->num_queue_pairs, pf->num_lan_msix);
6241 ch->num_queue_pairs = qcount;
6242
6243 /* find the next higher power-of-2 of num queue pairs */
6244 pow = ilog2(qcount);
6245 if (!is_power_of_2(qcount))
6246 pow++;
6247
6248 qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
6249 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
6250
6251 /* Setup queue TC[0].qmap for given VSI context */
6252 ctxt->info.tc_mapping[0] = cpu_to_le16(qmap);
6253
6254 ctxt->info.up_enable_bits = 0x1; /* TC0 enabled */
6255 ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
6256 ctxt->info.queue_mapping[0] = cpu_to_le16(ch->base_queue);
6257 ctxt->info.valid_sections |= cpu_to_le16(sections);
6258 }
6259
6260 /**
6261 * i40e_add_channel - add a channel by adding VSI
6262 * @pf: ptr to PF device
6263 * @uplink_seid: underlying HW switching element (VEB) ID
6264 * @ch: ptr to channel structure
6265 *
6266 * Add a channel (VSI) using add_vsi and queue_map
6267 **/
i40e_add_channel(struct i40e_pf * pf,u16 uplink_seid,struct i40e_channel * ch)6268 static int i40e_add_channel(struct i40e_pf *pf, u16 uplink_seid,
6269 struct i40e_channel *ch)
6270 {
6271 struct i40e_hw *hw = &pf->hw;
6272 struct i40e_vsi_context ctxt;
6273 u8 enabled_tc = 0x1; /* TC0 enabled */
6274 int ret;
6275
6276 if (ch->type != I40E_VSI_VMDQ2) {
6277 dev_info(&pf->pdev->dev,
6278 "add new vsi failed, ch->type %d\n", ch->type);
6279 return -EINVAL;
6280 }
6281
6282 memset(&ctxt, 0, sizeof(ctxt));
6283 ctxt.pf_num = hw->pf_id;
6284 ctxt.vf_num = 0;
6285 ctxt.uplink_seid = uplink_seid;
6286 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
6287 if (ch->type == I40E_VSI_VMDQ2)
6288 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6289
6290 if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags)) {
6291 ctxt.info.valid_sections |=
6292 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6293 ctxt.info.switch_id =
6294 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6295 }
6296
6297 /* Set queue map for a given VSI context */
6298 i40e_channel_setup_queue_map(pf, &ctxt, ch);
6299
6300 /* Now time to create VSI */
6301 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6302 if (ret) {
6303 dev_info(&pf->pdev->dev,
6304 "add new vsi failed, err %pe aq_err %s\n",
6305 ERR_PTR(ret),
6306 i40e_aq_str(&pf->hw,
6307 pf->hw.aq.asq_last_status));
6308 return -ENOENT;
6309 }
6310
6311 /* Success, update channel, set enabled_tc only if the channel
6312 * is not a macvlan
6313 */
6314 ch->enabled_tc = !i40e_is_channel_macvlan(ch) && enabled_tc;
6315 ch->seid = ctxt.seid;
6316 ch->vsi_number = ctxt.vsi_number;
6317 ch->stat_counter_idx = le16_to_cpu(ctxt.info.stat_counter_idx);
6318
6319 /* copy just the sections touched not the entire info
6320 * since not all sections are valid as returned by
6321 * update vsi params
6322 */
6323 ch->info.mapping_flags = ctxt.info.mapping_flags;
6324 memcpy(&ch->info.queue_mapping,
6325 &ctxt.info.queue_mapping, sizeof(ctxt.info.queue_mapping));
6326 memcpy(&ch->info.tc_mapping, ctxt.info.tc_mapping,
6327 sizeof(ctxt.info.tc_mapping));
6328
6329 return 0;
6330 }
6331
i40e_channel_config_bw(struct i40e_vsi * vsi,struct i40e_channel * ch,u8 * bw_share)6332 static int i40e_channel_config_bw(struct i40e_vsi *vsi, struct i40e_channel *ch,
6333 u8 *bw_share)
6334 {
6335 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
6336 int ret;
6337 int i;
6338
6339 memset(&bw_data, 0, sizeof(bw_data));
6340 bw_data.tc_valid_bits = ch->enabled_tc;
6341 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
6342 bw_data.tc_bw_credits[i] = bw_share[i];
6343
6344 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, ch->seid,
6345 &bw_data, NULL);
6346 if (ret) {
6347 dev_info(&vsi->back->pdev->dev,
6348 "Config VSI BW allocation per TC failed, aq_err: %d for new_vsi->seid %u\n",
6349 vsi->back->hw.aq.asq_last_status, ch->seid);
6350 return -EINVAL;
6351 }
6352
6353 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
6354 ch->info.qs_handle[i] = bw_data.qs_handles[i];
6355
6356 return 0;
6357 }
6358
6359 /**
6360 * i40e_channel_config_tx_ring - config TX ring associated with new channel
6361 * @pf: ptr to PF device
6362 * @vsi: the VSI being setup
6363 * @ch: ptr to channel structure
6364 *
6365 * Configure TX rings associated with channel (VSI) since queues are being
6366 * from parent VSI.
6367 **/
i40e_channel_config_tx_ring(struct i40e_pf * pf,struct i40e_vsi * vsi,struct i40e_channel * ch)6368 static int i40e_channel_config_tx_ring(struct i40e_pf *pf,
6369 struct i40e_vsi *vsi,
6370 struct i40e_channel *ch)
6371 {
6372 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
6373 int ret;
6374 int i;
6375
6376 /* Enable ETS TCs with equal BW Share for now across all VSIs */
6377 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6378 if (ch->enabled_tc & BIT(i))
6379 bw_share[i] = 1;
6380 }
6381
6382 /* configure BW for new VSI */
6383 ret = i40e_channel_config_bw(vsi, ch, bw_share);
6384 if (ret) {
6385 dev_info(&vsi->back->pdev->dev,
6386 "Failed configuring TC map %d for channel (seid %u)\n",
6387 ch->enabled_tc, ch->seid);
6388 return ret;
6389 }
6390
6391 for (i = 0; i < ch->num_queue_pairs; i++) {
6392 struct i40e_ring *tx_ring, *rx_ring;
6393 u16 pf_q;
6394
6395 pf_q = ch->base_queue + i;
6396
6397 /* Get to TX ring ptr of main VSI, for re-setup TX queue
6398 * context
6399 */
6400 tx_ring = vsi->tx_rings[pf_q];
6401 tx_ring->ch = ch;
6402
6403 /* Get the RX ring ptr */
6404 rx_ring = vsi->rx_rings[pf_q];
6405 rx_ring->ch = ch;
6406 }
6407
6408 return 0;
6409 }
6410
6411 /**
6412 * i40e_setup_hw_channel - setup new channel
6413 * @pf: ptr to PF device
6414 * @vsi: the VSI being setup
6415 * @ch: ptr to channel structure
6416 * @uplink_seid: underlying HW switching element (VEB) ID
6417 * @type: type of channel to be created (VMDq2/VF)
6418 *
6419 * Setup new channel (VSI) based on specified type (VMDq2/VF)
6420 * and configures TX rings accordingly
6421 **/
i40e_setup_hw_channel(struct i40e_pf * pf,struct i40e_vsi * vsi,struct i40e_channel * ch,u16 uplink_seid,u8 type)6422 static inline int i40e_setup_hw_channel(struct i40e_pf *pf,
6423 struct i40e_vsi *vsi,
6424 struct i40e_channel *ch,
6425 u16 uplink_seid, u8 type)
6426 {
6427 int ret;
6428
6429 ch->initialized = false;
6430 ch->base_queue = vsi->next_base_queue;
6431 ch->type = type;
6432
6433 /* Proceed with creation of channel (VMDq2) VSI */
6434 ret = i40e_add_channel(pf, uplink_seid, ch);
6435 if (ret) {
6436 dev_info(&pf->pdev->dev,
6437 "failed to add_channel using uplink_seid %u\n",
6438 uplink_seid);
6439 return ret;
6440 }
6441
6442 /* Mark the successful creation of channel */
6443 ch->initialized = true;
6444
6445 /* Reconfigure TX queues using QTX_CTL register */
6446 ret = i40e_channel_config_tx_ring(pf, vsi, ch);
6447 if (ret) {
6448 dev_info(&pf->pdev->dev,
6449 "failed to configure TX rings for channel %u\n",
6450 ch->seid);
6451 return ret;
6452 }
6453
6454 /* update 'next_base_queue' */
6455 vsi->next_base_queue = vsi->next_base_queue + ch->num_queue_pairs;
6456 dev_dbg(&pf->pdev->dev,
6457 "Added channel: vsi_seid %u, vsi_number %u, stat_counter_idx %u, num_queue_pairs %u, pf->next_base_queue %d\n",
6458 ch->seid, ch->vsi_number, ch->stat_counter_idx,
6459 ch->num_queue_pairs,
6460 vsi->next_base_queue);
6461 return ret;
6462 }
6463
6464 /**
6465 * i40e_setup_channel - setup new channel using uplink element
6466 * @pf: ptr to PF device
6467 * @vsi: pointer to the VSI to set up the channel within
6468 * @ch: ptr to channel structure
6469 *
6470 * Setup new channel (VSI) based on specified type (VMDq2/VF)
6471 * and uplink switching element (uplink_seid)
6472 **/
i40e_setup_channel(struct i40e_pf * pf,struct i40e_vsi * vsi,struct i40e_channel * ch)6473 static bool i40e_setup_channel(struct i40e_pf *pf, struct i40e_vsi *vsi,
6474 struct i40e_channel *ch)
6475 {
6476 u8 vsi_type;
6477 u16 seid;
6478 int ret;
6479
6480 if (vsi->type == I40E_VSI_MAIN) {
6481 vsi_type = I40E_VSI_VMDQ2;
6482 } else {
6483 dev_err(&pf->pdev->dev, "unsupported parent vsi type(%d)\n",
6484 vsi->type);
6485 return false;
6486 }
6487
6488 /* underlying switching element */
6489 seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6490
6491 /* create channel (VSI), configure TX rings */
6492 ret = i40e_setup_hw_channel(pf, vsi, ch, seid, vsi_type);
6493 if (ret) {
6494 dev_err(&pf->pdev->dev, "failed to setup hw_channel\n");
6495 return false;
6496 }
6497
6498 return ch->initialized ? true : false;
6499 }
6500
6501 /**
6502 * i40e_validate_and_set_switch_mode - sets up switch mode correctly
6503 * @vsi: ptr to VSI which has PF backing
6504 *
6505 * Sets up switch mode correctly if it needs to be changed and perform
6506 * what are allowed modes.
6507 **/
i40e_validate_and_set_switch_mode(struct i40e_vsi * vsi)6508 static int i40e_validate_and_set_switch_mode(struct i40e_vsi *vsi)
6509 {
6510 u8 mode;
6511 struct i40e_pf *pf = vsi->back;
6512 struct i40e_hw *hw = &pf->hw;
6513 int ret;
6514
6515 ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_dev_capabilities);
6516 if (ret)
6517 return -EINVAL;
6518
6519 if (hw->dev_caps.switch_mode) {
6520 /* if switch mode is set, support mode2 (non-tunneled for
6521 * cloud filter) for now
6522 */
6523 u32 switch_mode = hw->dev_caps.switch_mode &
6524 I40E_SWITCH_MODE_MASK;
6525 if (switch_mode >= I40E_CLOUD_FILTER_MODE1) {
6526 if (switch_mode == I40E_CLOUD_FILTER_MODE2)
6527 return 0;
6528 dev_err(&pf->pdev->dev,
6529 "Invalid switch_mode (%d), only non-tunneled mode for cloud filter is supported\n",
6530 hw->dev_caps.switch_mode);
6531 return -EINVAL;
6532 }
6533 }
6534
6535 /* Set Bit 7 to be valid */
6536 mode = I40E_AQ_SET_SWITCH_BIT7_VALID;
6537
6538 /* Set L4type for TCP support */
6539 mode |= I40E_AQ_SET_SWITCH_L4_TYPE_TCP;
6540
6541 /* Set cloud filter mode */
6542 mode |= I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL;
6543
6544 /* Prep mode field for set_switch_config */
6545 ret = i40e_aq_set_switch_config(hw, pf->last_sw_conf_flags,
6546 pf->last_sw_conf_valid_flags,
6547 mode, NULL);
6548 if (ret && hw->aq.asq_last_status != I40E_AQ_RC_ESRCH)
6549 dev_err(&pf->pdev->dev,
6550 "couldn't set switch config bits, err %pe aq_err %s\n",
6551 ERR_PTR(ret),
6552 i40e_aq_str(hw,
6553 hw->aq.asq_last_status));
6554
6555 return ret;
6556 }
6557
6558 /**
6559 * i40e_create_queue_channel - function to create channel
6560 * @vsi: VSI to be configured
6561 * @ch: ptr to channel (it contains channel specific params)
6562 *
6563 * This function creates channel (VSI) using num_queues specified by user,
6564 * reconfigs RSS if needed.
6565 **/
i40e_create_queue_channel(struct i40e_vsi * vsi,struct i40e_channel * ch)6566 int i40e_create_queue_channel(struct i40e_vsi *vsi,
6567 struct i40e_channel *ch)
6568 {
6569 struct i40e_pf *pf = vsi->back;
6570 bool reconfig_rss;
6571 int err;
6572
6573 if (!ch)
6574 return -EINVAL;
6575
6576 if (!ch->num_queue_pairs) {
6577 dev_err(&pf->pdev->dev, "Invalid num_queues requested: %d\n",
6578 ch->num_queue_pairs);
6579 return -EINVAL;
6580 }
6581
6582 /* validate user requested num_queues for channel */
6583 err = i40e_validate_num_queues(pf, ch->num_queue_pairs, vsi,
6584 &reconfig_rss);
6585 if (err) {
6586 dev_info(&pf->pdev->dev, "Failed to validate num_queues (%d)\n",
6587 ch->num_queue_pairs);
6588 return -EINVAL;
6589 }
6590
6591 /* By default we are in VEPA mode, if this is the first VF/VMDq
6592 * VSI to be added switch to VEB mode.
6593 */
6594
6595 if (!test_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags)) {
6596 set_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
6597
6598 if (vsi->type == I40E_VSI_MAIN) {
6599 if (i40e_is_tc_mqprio_enabled(pf))
6600 i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);
6601 else
6602 i40e_do_reset_safe(pf, I40E_PF_RESET_FLAG);
6603 }
6604 /* now onwards for main VSI, number of queues will be value
6605 * of TC0's queue count
6606 */
6607 }
6608
6609 /* By this time, vsi->cnt_q_avail shall be set to non-zero and
6610 * it should be more than num_queues
6611 */
6612 if (!vsi->cnt_q_avail || vsi->cnt_q_avail < ch->num_queue_pairs) {
6613 dev_dbg(&pf->pdev->dev,
6614 "Error: cnt_q_avail (%u) less than num_queues %d\n",
6615 vsi->cnt_q_avail, ch->num_queue_pairs);
6616 return -EINVAL;
6617 }
6618
6619 /* reconfig_rss only if vsi type is MAIN_VSI */
6620 if (reconfig_rss && (vsi->type == I40E_VSI_MAIN)) {
6621 err = i40e_vsi_reconfig_rss(vsi, ch->num_queue_pairs);
6622 if (err) {
6623 dev_info(&pf->pdev->dev,
6624 "Error: unable to reconfig rss for num_queues (%u)\n",
6625 ch->num_queue_pairs);
6626 return -EINVAL;
6627 }
6628 }
6629
6630 if (!i40e_setup_channel(pf, vsi, ch)) {
6631 dev_info(&pf->pdev->dev, "Failed to setup channel\n");
6632 return -EINVAL;
6633 }
6634
6635 dev_info(&pf->pdev->dev,
6636 "Setup channel (id:%u) utilizing num_queues %d\n",
6637 ch->seid, ch->num_queue_pairs);
6638
6639 /* configure VSI for BW limit */
6640 if (ch->max_tx_rate) {
6641 u64 credits = ch->max_tx_rate;
6642
6643 if (i40e_set_bw_limit(vsi, ch->seid, ch->max_tx_rate))
6644 return -EINVAL;
6645
6646 do_div(credits, I40E_BW_CREDIT_DIVISOR);
6647 dev_dbg(&pf->pdev->dev,
6648 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
6649 ch->max_tx_rate,
6650 credits,
6651 ch->seid);
6652 }
6653
6654 /* in case of VF, this will be main SRIOV VSI */
6655 ch->parent_vsi = vsi;
6656
6657 /* and update main_vsi's count for queue_available to use */
6658 vsi->cnt_q_avail -= ch->num_queue_pairs;
6659
6660 return 0;
6661 }
6662
6663 /**
6664 * i40e_configure_queue_channels - Add queue channel for the given TCs
6665 * @vsi: VSI to be configured
6666 *
6667 * Configures queue channel mapping to the given TCs
6668 **/
i40e_configure_queue_channels(struct i40e_vsi * vsi)6669 static int i40e_configure_queue_channels(struct i40e_vsi *vsi)
6670 {
6671 struct i40e_channel *ch;
6672 u64 max_rate = 0;
6673 int ret = 0, i;
6674
6675 /* Create app vsi with the TCs. Main VSI with TC0 is already set up */
6676 vsi->tc_seid_map[0] = vsi->seid;
6677 for (i = 1; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6678 if (vsi->tc_config.enabled_tc & BIT(i)) {
6679 ch = kzalloc(sizeof(*ch), GFP_KERNEL);
6680 if (!ch) {
6681 ret = -ENOMEM;
6682 goto err_free;
6683 }
6684
6685 INIT_LIST_HEAD(&ch->list);
6686 ch->num_queue_pairs =
6687 vsi->tc_config.tc_info[i].qcount;
6688 ch->base_queue =
6689 vsi->tc_config.tc_info[i].qoffset;
6690
6691 /* Bandwidth limit through tc interface is in bytes/s,
6692 * change to Mbit/s
6693 */
6694 max_rate = vsi->mqprio_qopt.max_rate[i];
6695 do_div(max_rate, I40E_BW_MBPS_DIVISOR);
6696 ch->max_tx_rate = max_rate;
6697
6698 list_add_tail(&ch->list, &vsi->ch_list);
6699
6700 ret = i40e_create_queue_channel(vsi, ch);
6701 if (ret) {
6702 dev_err(&vsi->back->pdev->dev,
6703 "Failed creating queue channel with TC%d: queues %d\n",
6704 i, ch->num_queue_pairs);
6705 goto err_free;
6706 }
6707 vsi->tc_seid_map[i] = ch->seid;
6708 }
6709 }
6710
6711 /* reset to reconfigure TX queue contexts */
6712 i40e_do_reset(vsi->back, I40E_PF_RESET_FLAG, true);
6713 return ret;
6714
6715 err_free:
6716 i40e_remove_queue_channels(vsi);
6717 return ret;
6718 }
6719
6720 /**
6721 * i40e_veb_config_tc - Configure TCs for given VEB
6722 * @veb: given VEB
6723 * @enabled_tc: TC bitmap
6724 *
6725 * Configures given TC bitmap for VEB (switching) element
6726 **/
i40e_veb_config_tc(struct i40e_veb * veb,u8 enabled_tc)6727 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
6728 {
6729 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
6730 struct i40e_pf *pf = veb->pf;
6731 int ret = 0;
6732 int i;
6733
6734 /* No TCs or already enabled TCs just return */
6735 if (!enabled_tc || veb->enabled_tc == enabled_tc)
6736 return ret;
6737
6738 bw_data.tc_valid_bits = enabled_tc;
6739 /* bw_data.absolute_credits is not set (relative) */
6740
6741 /* Enable ETS TCs with equal BW Share for now */
6742 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6743 if (enabled_tc & BIT(i))
6744 bw_data.tc_bw_share_credits[i] = 1;
6745 }
6746
6747 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
6748 &bw_data, NULL);
6749 if (ret) {
6750 dev_info(&pf->pdev->dev,
6751 "VEB bw config failed, err %pe aq_err %s\n",
6752 ERR_PTR(ret),
6753 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6754 goto out;
6755 }
6756
6757 /* Update the BW information */
6758 ret = i40e_veb_get_bw_info(veb);
6759 if (ret) {
6760 dev_info(&pf->pdev->dev,
6761 "Failed getting veb bw config, err %pe aq_err %s\n",
6762 ERR_PTR(ret),
6763 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6764 }
6765
6766 out:
6767 return ret;
6768 }
6769
6770 #ifdef CONFIG_I40E_DCB
6771 /**
6772 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
6773 * @pf: PF struct
6774 *
6775 * Reconfigure VEB/VSIs on a given PF; it is assumed that
6776 * the caller would've quiesce all the VSIs before calling
6777 * this function
6778 **/
i40e_dcb_reconfigure(struct i40e_pf * pf)6779 static void i40e_dcb_reconfigure(struct i40e_pf *pf)
6780 {
6781 u8 tc_map = 0;
6782 int ret;
6783 u8 v;
6784
6785 /* Enable the TCs available on PF to all VEBs */
6786 tc_map = i40e_pf_get_tc_map(pf);
6787 if (tc_map == I40E_DEFAULT_TRAFFIC_CLASS)
6788 return;
6789
6790 for (v = 0; v < I40E_MAX_VEB; v++) {
6791 if (!pf->veb[v])
6792 continue;
6793 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
6794 if (ret) {
6795 dev_info(&pf->pdev->dev,
6796 "Failed configuring TC for VEB seid=%d\n",
6797 pf->veb[v]->seid);
6798 /* Will try to configure as many components */
6799 }
6800 }
6801
6802 /* Update each VSI */
6803 for (v = 0; v < pf->num_alloc_vsi; v++) {
6804 if (!pf->vsi[v])
6805 continue;
6806
6807 /* - Enable all TCs for the LAN VSI
6808 * - For all others keep them at TC0 for now
6809 */
6810 if (v == pf->lan_vsi)
6811 tc_map = i40e_pf_get_tc_map(pf);
6812 else
6813 tc_map = I40E_DEFAULT_TRAFFIC_CLASS;
6814
6815 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
6816 if (ret) {
6817 dev_info(&pf->pdev->dev,
6818 "Failed configuring TC for VSI seid=%d\n",
6819 pf->vsi[v]->seid);
6820 /* Will try to configure as many components */
6821 } else {
6822 /* Re-configure VSI vectors based on updated TC map */
6823 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
6824 if (pf->vsi[v]->netdev)
6825 i40e_dcbnl_set_all(pf->vsi[v]);
6826 }
6827 }
6828 }
6829
6830 /**
6831 * i40e_resume_port_tx - Resume port Tx
6832 * @pf: PF struct
6833 *
6834 * Resume a port's Tx and issue a PF reset in case of failure to
6835 * resume.
6836 **/
i40e_resume_port_tx(struct i40e_pf * pf)6837 static int i40e_resume_port_tx(struct i40e_pf *pf)
6838 {
6839 struct i40e_hw *hw = &pf->hw;
6840 int ret;
6841
6842 ret = i40e_aq_resume_port_tx(hw, NULL);
6843 if (ret) {
6844 dev_info(&pf->pdev->dev,
6845 "Resume Port Tx failed, err %pe aq_err %s\n",
6846 ERR_PTR(ret),
6847 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6848 /* Schedule PF reset to recover */
6849 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
6850 i40e_service_event_schedule(pf);
6851 }
6852
6853 return ret;
6854 }
6855
6856 /**
6857 * i40e_suspend_port_tx - Suspend port Tx
6858 * @pf: PF struct
6859 *
6860 * Suspend a port's Tx and issue a PF reset in case of failure.
6861 **/
i40e_suspend_port_tx(struct i40e_pf * pf)6862 static int i40e_suspend_port_tx(struct i40e_pf *pf)
6863 {
6864 struct i40e_hw *hw = &pf->hw;
6865 int ret;
6866
6867 ret = i40e_aq_suspend_port_tx(hw, pf->mac_seid, NULL);
6868 if (ret) {
6869 dev_info(&pf->pdev->dev,
6870 "Suspend Port Tx failed, err %pe aq_err %s\n",
6871 ERR_PTR(ret),
6872 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6873 /* Schedule PF reset to recover */
6874 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
6875 i40e_service_event_schedule(pf);
6876 }
6877
6878 return ret;
6879 }
6880
6881 /**
6882 * i40e_hw_set_dcb_config - Program new DCBX settings into HW
6883 * @pf: PF being configured
6884 * @new_cfg: New DCBX configuration
6885 *
6886 * Program DCB settings into HW and reconfigure VEB/VSIs on
6887 * given PF. Uses "Set LLDP MIB" AQC to program the hardware.
6888 **/
i40e_hw_set_dcb_config(struct i40e_pf * pf,struct i40e_dcbx_config * new_cfg)6889 static int i40e_hw_set_dcb_config(struct i40e_pf *pf,
6890 struct i40e_dcbx_config *new_cfg)
6891 {
6892 struct i40e_dcbx_config *old_cfg = &pf->hw.local_dcbx_config;
6893 int ret;
6894
6895 /* Check if need reconfiguration */
6896 if (!memcmp(&new_cfg, &old_cfg, sizeof(new_cfg))) {
6897 dev_dbg(&pf->pdev->dev, "No Change in DCB Config required.\n");
6898 return 0;
6899 }
6900
6901 /* Config change disable all VSIs */
6902 i40e_pf_quiesce_all_vsi(pf);
6903
6904 /* Copy the new config to the current config */
6905 *old_cfg = *new_cfg;
6906 old_cfg->etsrec = old_cfg->etscfg;
6907 ret = i40e_set_dcb_config(&pf->hw);
6908 if (ret) {
6909 dev_info(&pf->pdev->dev,
6910 "Set DCB Config failed, err %pe aq_err %s\n",
6911 ERR_PTR(ret),
6912 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6913 goto out;
6914 }
6915
6916 /* Changes in configuration update VEB/VSI */
6917 i40e_dcb_reconfigure(pf);
6918 out:
6919 /* In case of reset do not try to resume anything */
6920 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) {
6921 /* Re-start the VSIs if disabled */
6922 ret = i40e_resume_port_tx(pf);
6923 /* In case of error no point in resuming VSIs */
6924 if (ret)
6925 goto err;
6926 i40e_pf_unquiesce_all_vsi(pf);
6927 }
6928 err:
6929 return ret;
6930 }
6931
6932 /**
6933 * i40e_hw_dcb_config - Program new DCBX settings into HW
6934 * @pf: PF being configured
6935 * @new_cfg: New DCBX configuration
6936 *
6937 * Program DCB settings into HW and reconfigure VEB/VSIs on
6938 * given PF
6939 **/
i40e_hw_dcb_config(struct i40e_pf * pf,struct i40e_dcbx_config * new_cfg)6940 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg)
6941 {
6942 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
6943 u8 prio_type[I40E_MAX_TRAFFIC_CLASS] = {0};
6944 u32 mfs_tc[I40E_MAX_TRAFFIC_CLASS];
6945 struct i40e_dcbx_config *old_cfg;
6946 u8 mode[I40E_MAX_TRAFFIC_CLASS];
6947 struct i40e_rx_pb_config pb_cfg;
6948 struct i40e_hw *hw = &pf->hw;
6949 u8 num_ports = hw->num_ports;
6950 bool need_reconfig;
6951 int ret = -EINVAL;
6952 u8 lltc_map = 0;
6953 u8 tc_map = 0;
6954 u8 new_numtc;
6955 u8 i;
6956
6957 dev_dbg(&pf->pdev->dev, "Configuring DCB registers directly\n");
6958 /* Un-pack information to Program ETS HW via shared API
6959 * numtc, tcmap
6960 * LLTC map
6961 * ETS/NON-ETS arbiter mode
6962 * max exponent (credit refills)
6963 * Total number of ports
6964 * PFC priority bit-map
6965 * Priority Table
6966 * BW % per TC
6967 * Arbiter mode between UPs sharing same TC
6968 * TSA table (ETS or non-ETS)
6969 * EEE enabled or not
6970 * MFS TC table
6971 */
6972
6973 new_numtc = i40e_dcb_get_num_tc(new_cfg);
6974
6975 memset(&ets_data, 0, sizeof(ets_data));
6976 for (i = 0; i < new_numtc; i++) {
6977 tc_map |= BIT(i);
6978 switch (new_cfg->etscfg.tsatable[i]) {
6979 case I40E_IEEE_TSA_ETS:
6980 prio_type[i] = I40E_DCB_PRIO_TYPE_ETS;
6981 ets_data.tc_bw_share_credits[i] =
6982 new_cfg->etscfg.tcbwtable[i];
6983 break;
6984 case I40E_IEEE_TSA_STRICT:
6985 prio_type[i] = I40E_DCB_PRIO_TYPE_STRICT;
6986 lltc_map |= BIT(i);
6987 ets_data.tc_bw_share_credits[i] =
6988 I40E_DCB_STRICT_PRIO_CREDITS;
6989 break;
6990 default:
6991 /* Invalid TSA type */
6992 need_reconfig = false;
6993 goto out;
6994 }
6995 }
6996
6997 old_cfg = &hw->local_dcbx_config;
6998 /* Check if need reconfiguration */
6999 need_reconfig = i40e_dcb_need_reconfig(pf, old_cfg, new_cfg);
7000
7001 /* If needed, enable/disable frame tagging, disable all VSIs
7002 * and suspend port tx
7003 */
7004 if (need_reconfig) {
7005 /* Enable DCB tagging only when more than one TC */
7006 if (new_numtc > 1)
7007 set_bit(I40E_FLAG_DCB_ENA, pf->flags);
7008 else
7009 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
7010
7011 set_bit(__I40E_PORT_SUSPENDED, pf->state);
7012 /* Reconfiguration needed quiesce all VSIs */
7013 i40e_pf_quiesce_all_vsi(pf);
7014 ret = i40e_suspend_port_tx(pf);
7015 if (ret)
7016 goto err;
7017 }
7018
7019 /* Configure Port ETS Tx Scheduler */
7020 ets_data.tc_valid_bits = tc_map;
7021 ets_data.tc_strict_priority_flags = lltc_map;
7022 ret = i40e_aq_config_switch_comp_ets
7023 (hw, pf->mac_seid, &ets_data,
7024 i40e_aqc_opc_modify_switching_comp_ets, NULL);
7025 if (ret) {
7026 dev_info(&pf->pdev->dev,
7027 "Modify Port ETS failed, err %pe aq_err %s\n",
7028 ERR_PTR(ret),
7029 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7030 goto out;
7031 }
7032
7033 /* Configure Rx ETS HW */
7034 memset(&mode, I40E_DCB_ARB_MODE_ROUND_ROBIN, sizeof(mode));
7035 i40e_dcb_hw_set_num_tc(hw, new_numtc);
7036 i40e_dcb_hw_rx_fifo_config(hw, I40E_DCB_ARB_MODE_ROUND_ROBIN,
7037 I40E_DCB_ARB_MODE_STRICT_PRIORITY,
7038 I40E_DCB_DEFAULT_MAX_EXPONENT,
7039 lltc_map);
7040 i40e_dcb_hw_rx_cmd_monitor_config(hw, new_numtc, num_ports);
7041 i40e_dcb_hw_rx_ets_bw_config(hw, new_cfg->etscfg.tcbwtable, mode,
7042 prio_type);
7043 i40e_dcb_hw_pfc_config(hw, new_cfg->pfc.pfcenable,
7044 new_cfg->etscfg.prioritytable);
7045 i40e_dcb_hw_rx_up2tc_config(hw, new_cfg->etscfg.prioritytable);
7046
7047 /* Configure Rx Packet Buffers in HW */
7048 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7049 mfs_tc[i] = pf->vsi[pf->lan_vsi]->netdev->mtu;
7050 mfs_tc[i] += I40E_PACKET_HDR_PAD;
7051 }
7052
7053 i40e_dcb_hw_calculate_pool_sizes(hw, num_ports,
7054 false, new_cfg->pfc.pfcenable,
7055 mfs_tc, &pb_cfg);
7056 i40e_dcb_hw_rx_pb_config(hw, &pf->pb_cfg, &pb_cfg);
7057
7058 /* Update the local Rx Packet buffer config */
7059 pf->pb_cfg = pb_cfg;
7060
7061 /* Inform the FW about changes to DCB configuration */
7062 ret = i40e_aq_dcb_updated(&pf->hw, NULL);
7063 if (ret) {
7064 dev_info(&pf->pdev->dev,
7065 "DCB Updated failed, err %pe aq_err %s\n",
7066 ERR_PTR(ret),
7067 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7068 goto out;
7069 }
7070
7071 /* Update the port DCBx configuration */
7072 *old_cfg = *new_cfg;
7073
7074 /* Changes in configuration update VEB/VSI */
7075 i40e_dcb_reconfigure(pf);
7076 out:
7077 /* Re-start the VSIs if disabled */
7078 if (need_reconfig) {
7079 ret = i40e_resume_port_tx(pf);
7080
7081 clear_bit(__I40E_PORT_SUSPENDED, pf->state);
7082 /* In case of error no point in resuming VSIs */
7083 if (ret)
7084 goto err;
7085
7086 /* Wait for the PF's queues to be disabled */
7087 ret = i40e_pf_wait_queues_disabled(pf);
7088 if (ret) {
7089 /* Schedule PF reset to recover */
7090 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
7091 i40e_service_event_schedule(pf);
7092 goto err;
7093 } else {
7094 i40e_pf_unquiesce_all_vsi(pf);
7095 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
7096 set_bit(__I40E_CLIENT_L2_CHANGE, pf->state);
7097 }
7098 /* registers are set, lets apply */
7099 if (test_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf->hw.caps))
7100 ret = i40e_hw_set_dcb_config(pf, new_cfg);
7101 }
7102
7103 err:
7104 return ret;
7105 }
7106
7107 /**
7108 * i40e_dcb_sw_default_config - Set default DCB configuration when DCB in SW
7109 * @pf: PF being queried
7110 *
7111 * Set default DCB configuration in case DCB is to be done in SW.
7112 **/
i40e_dcb_sw_default_config(struct i40e_pf * pf)7113 int i40e_dcb_sw_default_config(struct i40e_pf *pf)
7114 {
7115 struct i40e_dcbx_config *dcb_cfg = &pf->hw.local_dcbx_config;
7116 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
7117 struct i40e_hw *hw = &pf->hw;
7118 int err;
7119
7120 if (test_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf->hw.caps)) {
7121 /* Update the local cached instance with TC0 ETS */
7122 memset(&pf->tmp_cfg, 0, sizeof(struct i40e_dcbx_config));
7123 pf->tmp_cfg.etscfg.willing = I40E_IEEE_DEFAULT_ETS_WILLING;
7124 pf->tmp_cfg.etscfg.maxtcs = 0;
7125 pf->tmp_cfg.etscfg.tcbwtable[0] = I40E_IEEE_DEFAULT_ETS_TCBW;
7126 pf->tmp_cfg.etscfg.tsatable[0] = I40E_IEEE_TSA_ETS;
7127 pf->tmp_cfg.pfc.willing = I40E_IEEE_DEFAULT_PFC_WILLING;
7128 pf->tmp_cfg.pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7129 /* FW needs one App to configure HW */
7130 pf->tmp_cfg.numapps = I40E_IEEE_DEFAULT_NUM_APPS;
7131 pf->tmp_cfg.app[0].selector = I40E_APP_SEL_ETHTYPE;
7132 pf->tmp_cfg.app[0].priority = I40E_IEEE_DEFAULT_APP_PRIO;
7133 pf->tmp_cfg.app[0].protocolid = I40E_APP_PROTOID_FCOE;
7134
7135 return i40e_hw_set_dcb_config(pf, &pf->tmp_cfg);
7136 }
7137
7138 memset(&ets_data, 0, sizeof(ets_data));
7139 ets_data.tc_valid_bits = I40E_DEFAULT_TRAFFIC_CLASS; /* TC0 only */
7140 ets_data.tc_strict_priority_flags = 0; /* ETS */
7141 ets_data.tc_bw_share_credits[0] = I40E_IEEE_DEFAULT_ETS_TCBW; /* 100% to TC0 */
7142
7143 /* Enable ETS on the Physical port */
7144 err = i40e_aq_config_switch_comp_ets
7145 (hw, pf->mac_seid, &ets_data,
7146 i40e_aqc_opc_enable_switching_comp_ets, NULL);
7147 if (err) {
7148 dev_info(&pf->pdev->dev,
7149 "Enable Port ETS failed, err %pe aq_err %s\n",
7150 ERR_PTR(err),
7151 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7152 err = -ENOENT;
7153 goto out;
7154 }
7155
7156 /* Update the local cached instance with TC0 ETS */
7157 dcb_cfg->etscfg.willing = I40E_IEEE_DEFAULT_ETS_WILLING;
7158 dcb_cfg->etscfg.cbs = 0;
7159 dcb_cfg->etscfg.maxtcs = I40E_MAX_TRAFFIC_CLASS;
7160 dcb_cfg->etscfg.tcbwtable[0] = I40E_IEEE_DEFAULT_ETS_TCBW;
7161
7162 out:
7163 return err;
7164 }
7165
7166 /**
7167 * i40e_init_pf_dcb - Initialize DCB configuration
7168 * @pf: PF being configured
7169 *
7170 * Query the current DCB configuration and cache it
7171 * in the hardware structure
7172 **/
i40e_init_pf_dcb(struct i40e_pf * pf)7173 static int i40e_init_pf_dcb(struct i40e_pf *pf)
7174 {
7175 struct i40e_hw *hw = &pf->hw;
7176 int err;
7177
7178 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable
7179 * Also do not enable DCBx if FW LLDP agent is disabled
7180 */
7181 if (test_bit(I40E_HW_CAP_NO_DCB_SUPPORT, pf->hw.caps)) {
7182 dev_info(&pf->pdev->dev, "DCB is not supported.\n");
7183 err = -EOPNOTSUPP;
7184 goto out;
7185 }
7186 if (test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags)) {
7187 dev_info(&pf->pdev->dev, "FW LLDP is disabled, attempting SW DCB\n");
7188 err = i40e_dcb_sw_default_config(pf);
7189 if (err) {
7190 dev_info(&pf->pdev->dev, "Could not initialize SW DCB\n");
7191 goto out;
7192 }
7193 dev_info(&pf->pdev->dev, "SW DCB initialization succeeded.\n");
7194 pf->dcbx_cap = DCB_CAP_DCBX_HOST |
7195 DCB_CAP_DCBX_VER_IEEE;
7196 /* at init capable but disabled */
7197 set_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
7198 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
7199 goto out;
7200 }
7201 err = i40e_init_dcb(hw, true);
7202 if (!err) {
7203 /* Device/Function is not DCBX capable */
7204 if ((!hw->func_caps.dcb) ||
7205 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
7206 dev_info(&pf->pdev->dev,
7207 "DCBX offload is not supported or is disabled for this PF.\n");
7208 } else {
7209 /* When status is not DISABLED then DCBX in FW */
7210 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
7211 DCB_CAP_DCBX_VER_IEEE;
7212
7213 set_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
7214 /* Enable DCB tagging only when more than one TC
7215 * or explicitly disable if only one TC
7216 */
7217 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
7218 set_bit(I40E_FLAG_DCB_ENA, pf->flags);
7219 else
7220 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
7221 dev_dbg(&pf->pdev->dev,
7222 "DCBX offload is supported for this PF.\n");
7223 }
7224 } else if (pf->hw.aq.asq_last_status == I40E_AQ_RC_EPERM) {
7225 dev_info(&pf->pdev->dev, "FW LLDP disabled for this PF.\n");
7226 set_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags);
7227 } else {
7228 dev_info(&pf->pdev->dev,
7229 "Query for DCB configuration failed, err %pe aq_err %s\n",
7230 ERR_PTR(err),
7231 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7232 }
7233
7234 out:
7235 return err;
7236 }
7237 #endif /* CONFIG_I40E_DCB */
7238
7239 /**
7240 * i40e_print_link_message - print link up or down
7241 * @vsi: the VSI for which link needs a message
7242 * @isup: true of link is up, false otherwise
7243 */
i40e_print_link_message(struct i40e_vsi * vsi,bool isup)7244 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
7245 {
7246 enum i40e_aq_link_speed new_speed;
7247 struct i40e_pf *pf = vsi->back;
7248 char *speed = "Unknown";
7249 char *fc = "Unknown";
7250 char *fec = "";
7251 char *req_fec = "";
7252 char *an = "";
7253
7254 if (isup)
7255 new_speed = pf->hw.phy.link_info.link_speed;
7256 else
7257 new_speed = I40E_LINK_SPEED_UNKNOWN;
7258
7259 if ((vsi->current_isup == isup) && (vsi->current_speed == new_speed))
7260 return;
7261 vsi->current_isup = isup;
7262 vsi->current_speed = new_speed;
7263 if (!isup) {
7264 netdev_info(vsi->netdev, "NIC Link is Down\n");
7265 return;
7266 }
7267
7268 /* Warn user if link speed on NPAR enabled partition is not at
7269 * least 10GB
7270 */
7271 if (pf->hw.func_caps.npar_enable &&
7272 (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
7273 pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
7274 netdev_warn(vsi->netdev,
7275 "The partition detected link speed that is less than 10Gbps\n");
7276
7277 switch (pf->hw.phy.link_info.link_speed) {
7278 case I40E_LINK_SPEED_40GB:
7279 speed = "40 G";
7280 break;
7281 case I40E_LINK_SPEED_20GB:
7282 speed = "20 G";
7283 break;
7284 case I40E_LINK_SPEED_25GB:
7285 speed = "25 G";
7286 break;
7287 case I40E_LINK_SPEED_10GB:
7288 speed = "10 G";
7289 break;
7290 case I40E_LINK_SPEED_5GB:
7291 speed = "5 G";
7292 break;
7293 case I40E_LINK_SPEED_2_5GB:
7294 speed = "2.5 G";
7295 break;
7296 case I40E_LINK_SPEED_1GB:
7297 speed = "1000 M";
7298 break;
7299 case I40E_LINK_SPEED_100MB:
7300 speed = "100 M";
7301 break;
7302 default:
7303 break;
7304 }
7305
7306 switch (pf->hw.fc.current_mode) {
7307 case I40E_FC_FULL:
7308 fc = "RX/TX";
7309 break;
7310 case I40E_FC_TX_PAUSE:
7311 fc = "TX";
7312 break;
7313 case I40E_FC_RX_PAUSE:
7314 fc = "RX";
7315 break;
7316 default:
7317 fc = "None";
7318 break;
7319 }
7320
7321 if (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_25GB) {
7322 req_fec = "None";
7323 fec = "None";
7324 an = "False";
7325
7326 if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED)
7327 an = "True";
7328
7329 if (pf->hw.phy.link_info.fec_info &
7330 I40E_AQ_CONFIG_FEC_KR_ENA)
7331 fec = "CL74 FC-FEC/BASE-R";
7332 else if (pf->hw.phy.link_info.fec_info &
7333 I40E_AQ_CONFIG_FEC_RS_ENA)
7334 fec = "CL108 RS-FEC";
7335
7336 /* 'CL108 RS-FEC' should be displayed when RS is requested, or
7337 * both RS and FC are requested
7338 */
7339 if (vsi->back->hw.phy.link_info.req_fec_info &
7340 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS)) {
7341 if (vsi->back->hw.phy.link_info.req_fec_info &
7342 I40E_AQ_REQUEST_FEC_RS)
7343 req_fec = "CL108 RS-FEC";
7344 else
7345 req_fec = "CL74 FC-FEC/BASE-R";
7346 }
7347 netdev_info(vsi->netdev,
7348 "NIC Link is Up, %sbps Full Duplex, Requested FEC: %s, Negotiated FEC: %s, Autoneg: %s, Flow Control: %s\n",
7349 speed, req_fec, fec, an, fc);
7350 } else if (pf->hw.device_id == I40E_DEV_ID_KX_X722) {
7351 req_fec = "None";
7352 fec = "None";
7353 an = "False";
7354
7355 if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED)
7356 an = "True";
7357
7358 if (pf->hw.phy.link_info.fec_info &
7359 I40E_AQ_CONFIG_FEC_KR_ENA)
7360 fec = "CL74 FC-FEC/BASE-R";
7361
7362 if (pf->hw.phy.link_info.req_fec_info &
7363 I40E_AQ_REQUEST_FEC_KR)
7364 req_fec = "CL74 FC-FEC/BASE-R";
7365
7366 netdev_info(vsi->netdev,
7367 "NIC Link is Up, %sbps Full Duplex, Requested FEC: %s, Negotiated FEC: %s, Autoneg: %s, Flow Control: %s\n",
7368 speed, req_fec, fec, an, fc);
7369 } else {
7370 netdev_info(vsi->netdev,
7371 "NIC Link is Up, %sbps Full Duplex, Flow Control: %s\n",
7372 speed, fc);
7373 }
7374
7375 }
7376
7377 /**
7378 * i40e_up_complete - Finish the last steps of bringing up a connection
7379 * @vsi: the VSI being configured
7380 **/
i40e_up_complete(struct i40e_vsi * vsi)7381 static int i40e_up_complete(struct i40e_vsi *vsi)
7382 {
7383 struct i40e_pf *pf = vsi->back;
7384 int err;
7385
7386 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
7387 i40e_vsi_configure_msix(vsi);
7388 else
7389 i40e_configure_msi_and_legacy(vsi);
7390
7391 /* start rings */
7392 err = i40e_vsi_start_rings(vsi);
7393 if (err)
7394 return err;
7395
7396 clear_bit(__I40E_VSI_DOWN, vsi->state);
7397 i40e_napi_enable_all(vsi);
7398 i40e_vsi_enable_irq(vsi);
7399
7400 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
7401 (vsi->netdev)) {
7402 i40e_print_link_message(vsi, true);
7403 netif_tx_start_all_queues(vsi->netdev);
7404 netif_carrier_on(vsi->netdev);
7405 }
7406
7407 /* replay FDIR SB filters */
7408 if (vsi->type == I40E_VSI_FDIR) {
7409 /* reset fd counters */
7410 pf->fd_add_err = 0;
7411 pf->fd_atr_cnt = 0;
7412 i40e_fdir_filter_restore(vsi);
7413 }
7414
7415 /* On the next run of the service_task, notify any clients of the new
7416 * opened netdev
7417 */
7418 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
7419 i40e_service_event_schedule(pf);
7420
7421 return 0;
7422 }
7423
7424 /**
7425 * i40e_vsi_reinit_locked - Reset the VSI
7426 * @vsi: the VSI being configured
7427 *
7428 * Rebuild the ring structs after some configuration
7429 * has changed, e.g. MTU size.
7430 **/
i40e_vsi_reinit_locked(struct i40e_vsi * vsi)7431 static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
7432 {
7433 struct i40e_pf *pf = vsi->back;
7434
7435 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state))
7436 usleep_range(1000, 2000);
7437 i40e_down(vsi);
7438
7439 i40e_up(vsi);
7440 clear_bit(__I40E_CONFIG_BUSY, pf->state);
7441 }
7442
7443 /**
7444 * i40e_force_link_state - Force the link status
7445 * @pf: board private structure
7446 * @is_up: whether the link state should be forced up or down
7447 **/
i40e_force_link_state(struct i40e_pf * pf,bool is_up)7448 static int i40e_force_link_state(struct i40e_pf *pf, bool is_up)
7449 {
7450 struct i40e_aq_get_phy_abilities_resp abilities;
7451 struct i40e_aq_set_phy_config config = {0};
7452 bool non_zero_phy_type = is_up;
7453 struct i40e_hw *hw = &pf->hw;
7454 u64 mask;
7455 u8 speed;
7456 int err;
7457
7458 /* Card might've been put in an unstable state by other drivers
7459 * and applications, which causes incorrect speed values being
7460 * set on startup. In order to clear speed registers, we call
7461 * get_phy_capabilities twice, once to get initial state of
7462 * available speeds, and once to get current PHY config.
7463 */
7464 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
7465 NULL);
7466 if (err) {
7467 dev_err(&pf->pdev->dev,
7468 "failed to get phy cap., ret = %pe last_status = %s\n",
7469 ERR_PTR(err),
7470 i40e_aq_str(hw, hw->aq.asq_last_status));
7471 return err;
7472 }
7473 speed = abilities.link_speed;
7474
7475 /* Get the current phy config */
7476 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
7477 NULL);
7478 if (err) {
7479 dev_err(&pf->pdev->dev,
7480 "failed to get phy cap., ret = %pe last_status = %s\n",
7481 ERR_PTR(err),
7482 i40e_aq_str(hw, hw->aq.asq_last_status));
7483 return err;
7484 }
7485
7486 /* If link needs to go up, but was not forced to go down,
7487 * and its speed values are OK, no need for a flap
7488 * if non_zero_phy_type was set, still need to force up
7489 */
7490 if (test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, pf->flags))
7491 non_zero_phy_type = true;
7492 else if (is_up && abilities.phy_type != 0 && abilities.link_speed != 0)
7493 return 0;
7494
7495 /* To force link we need to set bits for all supported PHY types,
7496 * but there are now more than 32, so we need to split the bitmap
7497 * across two fields.
7498 */
7499 mask = I40E_PHY_TYPES_BITMASK;
7500 config.phy_type =
7501 non_zero_phy_type ? cpu_to_le32((u32)(mask & 0xffffffff)) : 0;
7502 config.phy_type_ext =
7503 non_zero_phy_type ? (u8)((mask >> 32) & 0xff) : 0;
7504 /* Copy the old settings, except of phy_type */
7505 config.abilities = abilities.abilities;
7506 if (test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, pf->flags)) {
7507 if (is_up)
7508 config.abilities |= I40E_AQ_PHY_ENABLE_LINK;
7509 else
7510 config.abilities &= ~(I40E_AQ_PHY_ENABLE_LINK);
7511 }
7512 if (abilities.link_speed != 0)
7513 config.link_speed = abilities.link_speed;
7514 else
7515 config.link_speed = speed;
7516 config.eee_capability = abilities.eee_capability;
7517 config.eeer = abilities.eeer_val;
7518 config.low_power_ctrl = abilities.d3_lpan;
7519 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
7520 I40E_AQ_PHY_FEC_CONFIG_MASK;
7521 err = i40e_aq_set_phy_config(hw, &config, NULL);
7522
7523 if (err) {
7524 dev_err(&pf->pdev->dev,
7525 "set phy config ret = %pe last_status = %s\n",
7526 ERR_PTR(err),
7527 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7528 return err;
7529 }
7530
7531 /* Update the link info */
7532 err = i40e_update_link_info(hw);
7533 if (err) {
7534 /* Wait a little bit (on 40G cards it sometimes takes a really
7535 * long time for link to come back from the atomic reset)
7536 * and try once more
7537 */
7538 msleep(1000);
7539 i40e_update_link_info(hw);
7540 }
7541
7542 i40e_aq_set_link_restart_an(hw, is_up, NULL);
7543
7544 return 0;
7545 }
7546
7547 /**
7548 * i40e_up - Bring the connection back up after being down
7549 * @vsi: the VSI being configured
7550 **/
i40e_up(struct i40e_vsi * vsi)7551 int i40e_up(struct i40e_vsi *vsi)
7552 {
7553 int err;
7554
7555 if (vsi->type == I40E_VSI_MAIN &&
7556 (test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, vsi->back->flags) ||
7557 test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, vsi->back->flags)))
7558 i40e_force_link_state(vsi->back, true);
7559
7560 err = i40e_vsi_configure(vsi);
7561 if (!err)
7562 err = i40e_up_complete(vsi);
7563
7564 return err;
7565 }
7566
7567 /**
7568 * i40e_down - Shutdown the connection processing
7569 * @vsi: the VSI being stopped
7570 **/
i40e_down(struct i40e_vsi * vsi)7571 void i40e_down(struct i40e_vsi *vsi)
7572 {
7573 int i;
7574
7575 /* It is assumed that the caller of this function
7576 * sets the vsi->state __I40E_VSI_DOWN bit.
7577 */
7578 if (vsi->netdev) {
7579 netif_carrier_off(vsi->netdev);
7580 netif_tx_disable(vsi->netdev);
7581 }
7582 i40e_vsi_disable_irq(vsi);
7583 i40e_vsi_stop_rings(vsi);
7584 if (vsi->type == I40E_VSI_MAIN &&
7585 (test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, vsi->back->flags) ||
7586 test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, vsi->back->flags)))
7587 i40e_force_link_state(vsi->back, false);
7588 i40e_napi_disable_all(vsi);
7589
7590 for (i = 0; i < vsi->num_queue_pairs; i++) {
7591 i40e_clean_tx_ring(vsi->tx_rings[i]);
7592 if (i40e_enabled_xdp_vsi(vsi)) {
7593 /* Make sure that in-progress ndo_xdp_xmit and
7594 * ndo_xsk_wakeup calls are completed.
7595 */
7596 synchronize_rcu();
7597 i40e_clean_tx_ring(vsi->xdp_rings[i]);
7598 }
7599 i40e_clean_rx_ring(vsi->rx_rings[i]);
7600 }
7601
7602 }
7603
7604 /**
7605 * i40e_validate_mqprio_qopt- validate queue mapping info
7606 * @vsi: the VSI being configured
7607 * @mqprio_qopt: queue parametrs
7608 **/
i40e_validate_mqprio_qopt(struct i40e_vsi * vsi,struct tc_mqprio_qopt_offload * mqprio_qopt)7609 static int i40e_validate_mqprio_qopt(struct i40e_vsi *vsi,
7610 struct tc_mqprio_qopt_offload *mqprio_qopt)
7611 {
7612 u64 sum_max_rate = 0;
7613 u64 max_rate = 0;
7614 int i;
7615
7616 if (mqprio_qopt->qopt.offset[0] != 0 ||
7617 mqprio_qopt->qopt.num_tc < 1 ||
7618 mqprio_qopt->qopt.num_tc > I40E_MAX_TRAFFIC_CLASS)
7619 return -EINVAL;
7620 for (i = 0; ; i++) {
7621 if (!mqprio_qopt->qopt.count[i])
7622 return -EINVAL;
7623 if (mqprio_qopt->min_rate[i]) {
7624 dev_err(&vsi->back->pdev->dev,
7625 "Invalid min tx rate (greater than 0) specified\n");
7626 return -EINVAL;
7627 }
7628 max_rate = mqprio_qopt->max_rate[i];
7629 do_div(max_rate, I40E_BW_MBPS_DIVISOR);
7630 sum_max_rate += max_rate;
7631
7632 if (i >= mqprio_qopt->qopt.num_tc - 1)
7633 break;
7634 if (mqprio_qopt->qopt.offset[i + 1] !=
7635 (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i]))
7636 return -EINVAL;
7637 }
7638 if (vsi->num_queue_pairs <
7639 (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) {
7640 dev_err(&vsi->back->pdev->dev,
7641 "Failed to create traffic channel, insufficient number of queues.\n");
7642 return -EINVAL;
7643 }
7644 if (sum_max_rate > i40e_get_link_speed(vsi)) {
7645 dev_err(&vsi->back->pdev->dev,
7646 "Invalid max tx rate specified\n");
7647 return -EINVAL;
7648 }
7649 return 0;
7650 }
7651
7652 /**
7653 * i40e_vsi_set_default_tc_config - set default values for tc configuration
7654 * @vsi: the VSI being configured
7655 **/
i40e_vsi_set_default_tc_config(struct i40e_vsi * vsi)7656 static void i40e_vsi_set_default_tc_config(struct i40e_vsi *vsi)
7657 {
7658 u16 qcount;
7659 int i;
7660
7661 /* Only TC0 is enabled */
7662 vsi->tc_config.numtc = 1;
7663 vsi->tc_config.enabled_tc = 1;
7664 qcount = min_t(int, vsi->alloc_queue_pairs,
7665 i40e_pf_get_max_q_per_tc(vsi->back));
7666 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7667 /* For the TC that is not enabled set the offset to default
7668 * queue and allocate one queue for the given TC.
7669 */
7670 vsi->tc_config.tc_info[i].qoffset = 0;
7671 if (i == 0)
7672 vsi->tc_config.tc_info[i].qcount = qcount;
7673 else
7674 vsi->tc_config.tc_info[i].qcount = 1;
7675 vsi->tc_config.tc_info[i].netdev_tc = 0;
7676 }
7677 }
7678
7679 /**
7680 * i40e_del_macvlan_filter
7681 * @hw: pointer to the HW structure
7682 * @seid: seid of the channel VSI
7683 * @macaddr: the mac address to apply as a filter
7684 * @aq_err: store the admin Q error
7685 *
7686 * This function deletes a mac filter on the channel VSI which serves as the
7687 * macvlan. Returns 0 on success.
7688 **/
i40e_del_macvlan_filter(struct i40e_hw * hw,u16 seid,const u8 * macaddr,int * aq_err)7689 static int i40e_del_macvlan_filter(struct i40e_hw *hw, u16 seid,
7690 const u8 *macaddr, int *aq_err)
7691 {
7692 struct i40e_aqc_remove_macvlan_element_data element;
7693 int status;
7694
7695 memset(&element, 0, sizeof(element));
7696 ether_addr_copy(element.mac_addr, macaddr);
7697 element.vlan_tag = 0;
7698 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7699 status = i40e_aq_remove_macvlan(hw, seid, &element, 1, NULL);
7700 *aq_err = hw->aq.asq_last_status;
7701
7702 return status;
7703 }
7704
7705 /**
7706 * i40e_add_macvlan_filter
7707 * @hw: pointer to the HW structure
7708 * @seid: seid of the channel VSI
7709 * @macaddr: the mac address to apply as a filter
7710 * @aq_err: store the admin Q error
7711 *
7712 * This function adds a mac filter on the channel VSI which serves as the
7713 * macvlan. Returns 0 on success.
7714 **/
i40e_add_macvlan_filter(struct i40e_hw * hw,u16 seid,const u8 * macaddr,int * aq_err)7715 static int i40e_add_macvlan_filter(struct i40e_hw *hw, u16 seid,
7716 const u8 *macaddr, int *aq_err)
7717 {
7718 struct i40e_aqc_add_macvlan_element_data element;
7719 u16 cmd_flags = 0;
7720 int status;
7721
7722 ether_addr_copy(element.mac_addr, macaddr);
7723 element.vlan_tag = 0;
7724 element.queue_number = 0;
7725 element.match_method = I40E_AQC_MM_ERR_NO_RES;
7726 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7727 element.flags = cpu_to_le16(cmd_flags);
7728 status = i40e_aq_add_macvlan(hw, seid, &element, 1, NULL);
7729 *aq_err = hw->aq.asq_last_status;
7730
7731 return status;
7732 }
7733
7734 /**
7735 * i40e_reset_ch_rings - Reset the queue contexts in a channel
7736 * @vsi: the VSI we want to access
7737 * @ch: the channel we want to access
7738 */
i40e_reset_ch_rings(struct i40e_vsi * vsi,struct i40e_channel * ch)7739 static void i40e_reset_ch_rings(struct i40e_vsi *vsi, struct i40e_channel *ch)
7740 {
7741 struct i40e_ring *tx_ring, *rx_ring;
7742 u16 pf_q;
7743 int i;
7744
7745 for (i = 0; i < ch->num_queue_pairs; i++) {
7746 pf_q = ch->base_queue + i;
7747 tx_ring = vsi->tx_rings[pf_q];
7748 tx_ring->ch = NULL;
7749 rx_ring = vsi->rx_rings[pf_q];
7750 rx_ring->ch = NULL;
7751 }
7752 }
7753
7754 /**
7755 * i40e_free_macvlan_channels
7756 * @vsi: the VSI we want to access
7757 *
7758 * This function frees the Qs of the channel VSI from
7759 * the stack and also deletes the channel VSIs which
7760 * serve as macvlans.
7761 */
i40e_free_macvlan_channels(struct i40e_vsi * vsi)7762 static void i40e_free_macvlan_channels(struct i40e_vsi *vsi)
7763 {
7764 struct i40e_channel *ch, *ch_tmp;
7765 int ret;
7766
7767 if (list_empty(&vsi->macvlan_list))
7768 return;
7769
7770 list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) {
7771 struct i40e_vsi *parent_vsi;
7772
7773 if (i40e_is_channel_macvlan(ch)) {
7774 i40e_reset_ch_rings(vsi, ch);
7775 clear_bit(ch->fwd->bit_no, vsi->fwd_bitmask);
7776 netdev_unbind_sb_channel(vsi->netdev, ch->fwd->netdev);
7777 netdev_set_sb_channel(ch->fwd->netdev, 0);
7778 kfree(ch->fwd);
7779 ch->fwd = NULL;
7780 }
7781
7782 list_del(&ch->list);
7783 parent_vsi = ch->parent_vsi;
7784 if (!parent_vsi || !ch->initialized) {
7785 kfree(ch);
7786 continue;
7787 }
7788
7789 /* remove the VSI */
7790 ret = i40e_aq_delete_element(&vsi->back->hw, ch->seid,
7791 NULL);
7792 if (ret)
7793 dev_err(&vsi->back->pdev->dev,
7794 "unable to remove channel (%d) for parent VSI(%d)\n",
7795 ch->seid, parent_vsi->seid);
7796 kfree(ch);
7797 }
7798 vsi->macvlan_cnt = 0;
7799 }
7800
7801 /**
7802 * i40e_fwd_ring_up - bring the macvlan device up
7803 * @vsi: the VSI we want to access
7804 * @vdev: macvlan netdevice
7805 * @fwd: the private fwd structure
7806 */
i40e_fwd_ring_up(struct i40e_vsi * vsi,struct net_device * vdev,struct i40e_fwd_adapter * fwd)7807 static int i40e_fwd_ring_up(struct i40e_vsi *vsi, struct net_device *vdev,
7808 struct i40e_fwd_adapter *fwd)
7809 {
7810 struct i40e_channel *ch = NULL, *ch_tmp, *iter;
7811 int ret = 0, num_tc = 1, i, aq_err;
7812 struct i40e_pf *pf = vsi->back;
7813 struct i40e_hw *hw = &pf->hw;
7814
7815 /* Go through the list and find an available channel */
7816 list_for_each_entry_safe(iter, ch_tmp, &vsi->macvlan_list, list) {
7817 if (!i40e_is_channel_macvlan(iter)) {
7818 iter->fwd = fwd;
7819 /* record configuration for macvlan interface in vdev */
7820 for (i = 0; i < num_tc; i++)
7821 netdev_bind_sb_channel_queue(vsi->netdev, vdev,
7822 i,
7823 iter->num_queue_pairs,
7824 iter->base_queue);
7825 for (i = 0; i < iter->num_queue_pairs; i++) {
7826 struct i40e_ring *tx_ring, *rx_ring;
7827 u16 pf_q;
7828
7829 pf_q = iter->base_queue + i;
7830
7831 /* Get to TX ring ptr */
7832 tx_ring = vsi->tx_rings[pf_q];
7833 tx_ring->ch = iter;
7834
7835 /* Get the RX ring ptr */
7836 rx_ring = vsi->rx_rings[pf_q];
7837 rx_ring->ch = iter;
7838 }
7839 ch = iter;
7840 break;
7841 }
7842 }
7843
7844 if (!ch)
7845 return -EINVAL;
7846
7847 /* Guarantee all rings are updated before we update the
7848 * MAC address filter.
7849 */
7850 wmb();
7851
7852 /* Add a mac filter */
7853 ret = i40e_add_macvlan_filter(hw, ch->seid, vdev->dev_addr, &aq_err);
7854 if (ret) {
7855 /* if we cannot add the MAC rule then disable the offload */
7856 macvlan_release_l2fw_offload(vdev);
7857 for (i = 0; i < ch->num_queue_pairs; i++) {
7858 struct i40e_ring *rx_ring;
7859 u16 pf_q;
7860
7861 pf_q = ch->base_queue + i;
7862 rx_ring = vsi->rx_rings[pf_q];
7863 rx_ring->netdev = NULL;
7864 }
7865 dev_info(&pf->pdev->dev,
7866 "Error adding mac filter on macvlan err %pe, aq_err %s\n",
7867 ERR_PTR(ret),
7868 i40e_aq_str(hw, aq_err));
7869 netdev_err(vdev, "L2fwd offload disabled to L2 filter error\n");
7870 }
7871
7872 return ret;
7873 }
7874
7875 /**
7876 * i40e_setup_macvlans - create the channels which will be macvlans
7877 * @vsi: the VSI we want to access
7878 * @macvlan_cnt: no. of macvlans to be setup
7879 * @qcnt: no. of Qs per macvlan
7880 * @vdev: macvlan netdevice
7881 */
i40e_setup_macvlans(struct i40e_vsi * vsi,u16 macvlan_cnt,u16 qcnt,struct net_device * vdev)7882 static int i40e_setup_macvlans(struct i40e_vsi *vsi, u16 macvlan_cnt, u16 qcnt,
7883 struct net_device *vdev)
7884 {
7885 struct i40e_pf *pf = vsi->back;
7886 struct i40e_hw *hw = &pf->hw;
7887 struct i40e_vsi_context ctxt;
7888 u16 sections, qmap, num_qps;
7889 struct i40e_channel *ch;
7890 int i, pow, ret = 0;
7891 u8 offset = 0;
7892
7893 if (vsi->type != I40E_VSI_MAIN || !macvlan_cnt)
7894 return -EINVAL;
7895
7896 num_qps = vsi->num_queue_pairs - (macvlan_cnt * qcnt);
7897
7898 /* find the next higher power-of-2 of num queue pairs */
7899 pow = fls(roundup_pow_of_two(num_qps) - 1);
7900
7901 qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
7902 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
7903
7904 /* Setup context bits for the main VSI */
7905 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
7906 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
7907 memset(&ctxt, 0, sizeof(ctxt));
7908 ctxt.seid = vsi->seid;
7909 ctxt.pf_num = vsi->back->hw.pf_id;
7910 ctxt.vf_num = 0;
7911 ctxt.uplink_seid = vsi->uplink_seid;
7912 ctxt.info = vsi->info;
7913 ctxt.info.tc_mapping[0] = cpu_to_le16(qmap);
7914 ctxt.info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
7915 ctxt.info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
7916 ctxt.info.valid_sections |= cpu_to_le16(sections);
7917
7918 /* Reconfigure RSS for main VSI with new max queue count */
7919 vsi->rss_size = max_t(u16, num_qps, qcnt);
7920 ret = i40e_vsi_config_rss(vsi);
7921 if (ret) {
7922 dev_info(&pf->pdev->dev,
7923 "Failed to reconfig RSS for num_queues (%u)\n",
7924 vsi->rss_size);
7925 return ret;
7926 }
7927 vsi->reconfig_rss = true;
7928 dev_dbg(&vsi->back->pdev->dev,
7929 "Reconfigured RSS with num_queues (%u)\n", vsi->rss_size);
7930 vsi->next_base_queue = num_qps;
7931 vsi->cnt_q_avail = vsi->num_queue_pairs - num_qps;
7932
7933 /* Update the VSI after updating the VSI queue-mapping
7934 * information
7935 */
7936 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7937 if (ret) {
7938 dev_info(&pf->pdev->dev,
7939 "Update vsi tc config failed, err %pe aq_err %s\n",
7940 ERR_PTR(ret),
7941 i40e_aq_str(hw, hw->aq.asq_last_status));
7942 return ret;
7943 }
7944 /* update the local VSI info with updated queue map */
7945 i40e_vsi_update_queue_map(vsi, &ctxt);
7946 vsi->info.valid_sections = 0;
7947
7948 /* Create channels for macvlans */
7949 INIT_LIST_HEAD(&vsi->macvlan_list);
7950 for (i = 0; i < macvlan_cnt; i++) {
7951 ch = kzalloc(sizeof(*ch), GFP_KERNEL);
7952 if (!ch) {
7953 ret = -ENOMEM;
7954 goto err_free;
7955 }
7956 INIT_LIST_HEAD(&ch->list);
7957 ch->num_queue_pairs = qcnt;
7958 if (!i40e_setup_channel(pf, vsi, ch)) {
7959 ret = -EINVAL;
7960 kfree(ch);
7961 goto err_free;
7962 }
7963 ch->parent_vsi = vsi;
7964 vsi->cnt_q_avail -= ch->num_queue_pairs;
7965 vsi->macvlan_cnt++;
7966 list_add_tail(&ch->list, &vsi->macvlan_list);
7967 }
7968
7969 return ret;
7970
7971 err_free:
7972 dev_info(&pf->pdev->dev, "Failed to setup macvlans\n");
7973 i40e_free_macvlan_channels(vsi);
7974
7975 return ret;
7976 }
7977
7978 /**
7979 * i40e_fwd_add - configure macvlans
7980 * @netdev: net device to configure
7981 * @vdev: macvlan netdevice
7982 **/
i40e_fwd_add(struct net_device * netdev,struct net_device * vdev)7983 static void *i40e_fwd_add(struct net_device *netdev, struct net_device *vdev)
7984 {
7985 struct i40e_netdev_priv *np = netdev_priv(netdev);
7986 u16 q_per_macvlan = 0, macvlan_cnt = 0, vectors;
7987 struct i40e_vsi *vsi = np->vsi;
7988 struct i40e_pf *pf = vsi->back;
7989 struct i40e_fwd_adapter *fwd;
7990 int avail_macvlan, ret;
7991
7992 if (test_bit(I40E_FLAG_DCB_ENA, pf->flags)) {
7993 netdev_info(netdev, "Macvlans are not supported when DCB is enabled\n");
7994 return ERR_PTR(-EINVAL);
7995 }
7996 if (i40e_is_tc_mqprio_enabled(pf)) {
7997 netdev_info(netdev, "Macvlans are not supported when HW TC offload is on\n");
7998 return ERR_PTR(-EINVAL);
7999 }
8000 if (pf->num_lan_msix < I40E_MIN_MACVLAN_VECTORS) {
8001 netdev_info(netdev, "Not enough vectors available to support macvlans\n");
8002 return ERR_PTR(-EINVAL);
8003 }
8004
8005 /* The macvlan device has to be a single Q device so that the
8006 * tc_to_txq field can be reused to pick the tx queue.
8007 */
8008 if (netif_is_multiqueue(vdev))
8009 return ERR_PTR(-ERANGE);
8010
8011 if (!vsi->macvlan_cnt) {
8012 /* reserve bit 0 for the pf device */
8013 set_bit(0, vsi->fwd_bitmask);
8014
8015 /* Try to reserve as many queues as possible for macvlans. First
8016 * reserve 3/4th of max vectors, then half, then quarter and
8017 * calculate Qs per macvlan as you go
8018 */
8019 vectors = pf->num_lan_msix;
8020 if (vectors <= I40E_MAX_MACVLANS && vectors > 64) {
8021 /* allocate 4 Qs per macvlan and 32 Qs to the PF*/
8022 q_per_macvlan = 4;
8023 macvlan_cnt = (vectors - 32) / 4;
8024 } else if (vectors <= 64 && vectors > 32) {
8025 /* allocate 2 Qs per macvlan and 16 Qs to the PF*/
8026 q_per_macvlan = 2;
8027 macvlan_cnt = (vectors - 16) / 2;
8028 } else if (vectors <= 32 && vectors > 16) {
8029 /* allocate 1 Q per macvlan and 16 Qs to the PF*/
8030 q_per_macvlan = 1;
8031 macvlan_cnt = vectors - 16;
8032 } else if (vectors <= 16 && vectors > 8) {
8033 /* allocate 1 Q per macvlan and 8 Qs to the PF */
8034 q_per_macvlan = 1;
8035 macvlan_cnt = vectors - 8;
8036 } else {
8037 /* allocate 1 Q per macvlan and 1 Q to the PF */
8038 q_per_macvlan = 1;
8039 macvlan_cnt = vectors - 1;
8040 }
8041
8042 if (macvlan_cnt == 0)
8043 return ERR_PTR(-EBUSY);
8044
8045 /* Quiesce VSI queues */
8046 i40e_quiesce_vsi(vsi);
8047
8048 /* sets up the macvlans but does not "enable" them */
8049 ret = i40e_setup_macvlans(vsi, macvlan_cnt, q_per_macvlan,
8050 vdev);
8051 if (ret)
8052 return ERR_PTR(ret);
8053
8054 /* Unquiesce VSI */
8055 i40e_unquiesce_vsi(vsi);
8056 }
8057 avail_macvlan = find_first_zero_bit(vsi->fwd_bitmask,
8058 vsi->macvlan_cnt);
8059 if (avail_macvlan >= I40E_MAX_MACVLANS)
8060 return ERR_PTR(-EBUSY);
8061
8062 /* create the fwd struct */
8063 fwd = kzalloc(sizeof(*fwd), GFP_KERNEL);
8064 if (!fwd)
8065 return ERR_PTR(-ENOMEM);
8066
8067 set_bit(avail_macvlan, vsi->fwd_bitmask);
8068 fwd->bit_no = avail_macvlan;
8069 netdev_set_sb_channel(vdev, avail_macvlan);
8070 fwd->netdev = vdev;
8071
8072 if (!netif_running(netdev))
8073 return fwd;
8074
8075 /* Set fwd ring up */
8076 ret = i40e_fwd_ring_up(vsi, vdev, fwd);
8077 if (ret) {
8078 /* unbind the queues and drop the subordinate channel config */
8079 netdev_unbind_sb_channel(netdev, vdev);
8080 netdev_set_sb_channel(vdev, 0);
8081
8082 kfree(fwd);
8083 return ERR_PTR(-EINVAL);
8084 }
8085
8086 return fwd;
8087 }
8088
8089 /**
8090 * i40e_del_all_macvlans - Delete all the mac filters on the channels
8091 * @vsi: the VSI we want to access
8092 */
i40e_del_all_macvlans(struct i40e_vsi * vsi)8093 static void i40e_del_all_macvlans(struct i40e_vsi *vsi)
8094 {
8095 struct i40e_channel *ch, *ch_tmp;
8096 struct i40e_pf *pf = vsi->back;
8097 struct i40e_hw *hw = &pf->hw;
8098 int aq_err, ret = 0;
8099
8100 if (list_empty(&vsi->macvlan_list))
8101 return;
8102
8103 list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) {
8104 if (i40e_is_channel_macvlan(ch)) {
8105 ret = i40e_del_macvlan_filter(hw, ch->seid,
8106 i40e_channel_mac(ch),
8107 &aq_err);
8108 if (!ret) {
8109 /* Reset queue contexts */
8110 i40e_reset_ch_rings(vsi, ch);
8111 clear_bit(ch->fwd->bit_no, vsi->fwd_bitmask);
8112 netdev_unbind_sb_channel(vsi->netdev,
8113 ch->fwd->netdev);
8114 netdev_set_sb_channel(ch->fwd->netdev, 0);
8115 kfree(ch->fwd);
8116 ch->fwd = NULL;
8117 }
8118 }
8119 }
8120 }
8121
8122 /**
8123 * i40e_fwd_del - delete macvlan interfaces
8124 * @netdev: net device to configure
8125 * @vdev: macvlan netdevice
8126 */
i40e_fwd_del(struct net_device * netdev,void * vdev)8127 static void i40e_fwd_del(struct net_device *netdev, void *vdev)
8128 {
8129 struct i40e_netdev_priv *np = netdev_priv(netdev);
8130 struct i40e_fwd_adapter *fwd = vdev;
8131 struct i40e_channel *ch, *ch_tmp;
8132 struct i40e_vsi *vsi = np->vsi;
8133 struct i40e_pf *pf = vsi->back;
8134 struct i40e_hw *hw = &pf->hw;
8135 int aq_err, ret = 0;
8136
8137 /* Find the channel associated with the macvlan and del mac filter */
8138 list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) {
8139 if (i40e_is_channel_macvlan(ch) &&
8140 ether_addr_equal(i40e_channel_mac(ch),
8141 fwd->netdev->dev_addr)) {
8142 ret = i40e_del_macvlan_filter(hw, ch->seid,
8143 i40e_channel_mac(ch),
8144 &aq_err);
8145 if (!ret) {
8146 /* Reset queue contexts */
8147 i40e_reset_ch_rings(vsi, ch);
8148 clear_bit(ch->fwd->bit_no, vsi->fwd_bitmask);
8149 netdev_unbind_sb_channel(netdev, fwd->netdev);
8150 netdev_set_sb_channel(fwd->netdev, 0);
8151 kfree(ch->fwd);
8152 ch->fwd = NULL;
8153 } else {
8154 dev_info(&pf->pdev->dev,
8155 "Error deleting mac filter on macvlan err %pe, aq_err %s\n",
8156 ERR_PTR(ret),
8157 i40e_aq_str(hw, aq_err));
8158 }
8159 break;
8160 }
8161 }
8162 }
8163
8164 /**
8165 * i40e_setup_tc - configure multiple traffic classes
8166 * @netdev: net device to configure
8167 * @type_data: tc offload data
8168 **/
i40e_setup_tc(struct net_device * netdev,void * type_data)8169 static int i40e_setup_tc(struct net_device *netdev, void *type_data)
8170 {
8171 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
8172 struct i40e_netdev_priv *np = netdev_priv(netdev);
8173 struct i40e_vsi *vsi = np->vsi;
8174 struct i40e_pf *pf = vsi->back;
8175 u8 enabled_tc = 0, num_tc, hw;
8176 bool need_reset = false;
8177 int old_queue_pairs;
8178 int ret = -EINVAL;
8179 u16 mode;
8180 int i;
8181
8182 old_queue_pairs = vsi->num_queue_pairs;
8183 num_tc = mqprio_qopt->qopt.num_tc;
8184 hw = mqprio_qopt->qopt.hw;
8185 mode = mqprio_qopt->mode;
8186 if (!hw) {
8187 clear_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags);
8188 memcpy(&vsi->mqprio_qopt, mqprio_qopt, sizeof(*mqprio_qopt));
8189 goto config_tc;
8190 }
8191
8192 /* Check if MFP enabled */
8193 if (test_bit(I40E_FLAG_MFP_ENA, pf->flags)) {
8194 netdev_info(netdev,
8195 "Configuring TC not supported in MFP mode\n");
8196 return ret;
8197 }
8198 switch (mode) {
8199 case TC_MQPRIO_MODE_DCB:
8200 clear_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags);
8201
8202 /* Check if DCB enabled to continue */
8203 if (!test_bit(I40E_FLAG_DCB_ENA, pf->flags)) {
8204 netdev_info(netdev,
8205 "DCB is not enabled for adapter\n");
8206 return ret;
8207 }
8208
8209 /* Check whether tc count is within enabled limit */
8210 if (num_tc > i40e_pf_get_num_tc(pf)) {
8211 netdev_info(netdev,
8212 "TC count greater than enabled on link for adapter\n");
8213 return ret;
8214 }
8215 break;
8216 case TC_MQPRIO_MODE_CHANNEL:
8217 if (test_bit(I40E_FLAG_DCB_ENA, pf->flags)) {
8218 netdev_info(netdev,
8219 "Full offload of TC Mqprio options is not supported when DCB is enabled\n");
8220 return ret;
8221 }
8222 if (!test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
8223 return ret;
8224 ret = i40e_validate_mqprio_qopt(vsi, mqprio_qopt);
8225 if (ret)
8226 return ret;
8227 memcpy(&vsi->mqprio_qopt, mqprio_qopt,
8228 sizeof(*mqprio_qopt));
8229 set_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags);
8230 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
8231 break;
8232 default:
8233 return -EINVAL;
8234 }
8235
8236 config_tc:
8237 /* Generate TC map for number of tc requested */
8238 for (i = 0; i < num_tc; i++)
8239 enabled_tc |= BIT(i);
8240
8241 /* Requesting same TC configuration as already enabled */
8242 if (enabled_tc == vsi->tc_config.enabled_tc &&
8243 mode != TC_MQPRIO_MODE_CHANNEL)
8244 return 0;
8245
8246 /* Quiesce VSI queues */
8247 i40e_quiesce_vsi(vsi);
8248
8249 if (!hw && !i40e_is_tc_mqprio_enabled(pf))
8250 i40e_remove_queue_channels(vsi);
8251
8252 /* Configure VSI for enabled TCs */
8253 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8254 if (ret) {
8255 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
8256 vsi->seid);
8257 need_reset = true;
8258 goto exit;
8259 } else if (enabled_tc &&
8260 (!is_power_of_2(vsi->tc_config.tc_info[0].qcount))) {
8261 netdev_info(netdev,
8262 "Failed to create channel. Override queues (%u) not power of 2\n",
8263 vsi->tc_config.tc_info[0].qcount);
8264 ret = -EINVAL;
8265 need_reset = true;
8266 goto exit;
8267 }
8268
8269 dev_info(&vsi->back->pdev->dev,
8270 "Setup channel (id:%u) utilizing num_queues %d\n",
8271 vsi->seid, vsi->tc_config.tc_info[0].qcount);
8272
8273 if (i40e_is_tc_mqprio_enabled(pf)) {
8274 if (vsi->mqprio_qopt.max_rate[0]) {
8275 u64 max_tx_rate = i40e_bw_bytes_to_mbits(vsi,
8276 vsi->mqprio_qopt.max_rate[0]);
8277
8278 ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate);
8279 if (!ret) {
8280 u64 credits = max_tx_rate;
8281
8282 do_div(credits, I40E_BW_CREDIT_DIVISOR);
8283 dev_dbg(&vsi->back->pdev->dev,
8284 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
8285 max_tx_rate,
8286 credits,
8287 vsi->seid);
8288 } else {
8289 need_reset = true;
8290 goto exit;
8291 }
8292 }
8293 ret = i40e_configure_queue_channels(vsi);
8294 if (ret) {
8295 vsi->num_queue_pairs = old_queue_pairs;
8296 netdev_info(netdev,
8297 "Failed configuring queue channels\n");
8298 need_reset = true;
8299 goto exit;
8300 }
8301 }
8302
8303 exit:
8304 /* Reset the configuration data to defaults, only TC0 is enabled */
8305 if (need_reset) {
8306 i40e_vsi_set_default_tc_config(vsi);
8307 need_reset = false;
8308 }
8309
8310 /* Unquiesce VSI */
8311 i40e_unquiesce_vsi(vsi);
8312 return ret;
8313 }
8314
8315 /**
8316 * i40e_set_cld_element - sets cloud filter element data
8317 * @filter: cloud filter rule
8318 * @cld: ptr to cloud filter element data
8319 *
8320 * This is helper function to copy data into cloud filter element
8321 **/
8322 static inline void
i40e_set_cld_element(struct i40e_cloud_filter * filter,struct i40e_aqc_cloud_filters_element_data * cld)8323 i40e_set_cld_element(struct i40e_cloud_filter *filter,
8324 struct i40e_aqc_cloud_filters_element_data *cld)
8325 {
8326 u32 ipa;
8327 int i;
8328
8329 memset(cld, 0, sizeof(*cld));
8330 ether_addr_copy(cld->outer_mac, filter->dst_mac);
8331 ether_addr_copy(cld->inner_mac, filter->src_mac);
8332
8333 if (filter->n_proto != ETH_P_IP && filter->n_proto != ETH_P_IPV6)
8334 return;
8335
8336 if (filter->n_proto == ETH_P_IPV6) {
8337 #define IPV6_MAX_INDEX (ARRAY_SIZE(filter->dst_ipv6) - 1)
8338 for (i = 0; i < ARRAY_SIZE(filter->dst_ipv6); i++) {
8339 ipa = be32_to_cpu(filter->dst_ipv6[IPV6_MAX_INDEX - i]);
8340
8341 *(__le32 *)&cld->ipaddr.raw_v6.data[i * 2] = cpu_to_le32(ipa);
8342 }
8343 } else {
8344 ipa = be32_to_cpu(filter->dst_ipv4);
8345
8346 memcpy(&cld->ipaddr.v4.data, &ipa, sizeof(ipa));
8347 }
8348
8349 cld->inner_vlan = cpu_to_le16(ntohs(filter->vlan_id));
8350
8351 /* tenant_id is not supported by FW now, once the support is enabled
8352 * fill the cld->tenant_id with cpu_to_le32(filter->tenant_id)
8353 */
8354 if (filter->tenant_id)
8355 return;
8356 }
8357
8358 /**
8359 * i40e_add_del_cloud_filter - Add/del cloud filter
8360 * @vsi: pointer to VSI
8361 * @filter: cloud filter rule
8362 * @add: if true, add, if false, delete
8363 *
8364 * Add or delete a cloud filter for a specific flow spec.
8365 * Returns 0 if the filter were successfully added.
8366 **/
i40e_add_del_cloud_filter(struct i40e_vsi * vsi,struct i40e_cloud_filter * filter,bool add)8367 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
8368 struct i40e_cloud_filter *filter, bool add)
8369 {
8370 struct i40e_aqc_cloud_filters_element_data cld_filter;
8371 struct i40e_pf *pf = vsi->back;
8372 int ret;
8373 static const u16 flag_table[128] = {
8374 [I40E_CLOUD_FILTER_FLAGS_OMAC] =
8375 I40E_AQC_ADD_CLOUD_FILTER_OMAC,
8376 [I40E_CLOUD_FILTER_FLAGS_IMAC] =
8377 I40E_AQC_ADD_CLOUD_FILTER_IMAC,
8378 [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN] =
8379 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN,
8380 [I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID] =
8381 I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID,
8382 [I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC] =
8383 I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC,
8384 [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID] =
8385 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID,
8386 [I40E_CLOUD_FILTER_FLAGS_IIP] =
8387 I40E_AQC_ADD_CLOUD_FILTER_IIP,
8388 };
8389
8390 if (filter->flags >= ARRAY_SIZE(flag_table))
8391 return -EIO;
8392
8393 memset(&cld_filter, 0, sizeof(cld_filter));
8394
8395 /* copy element needed to add cloud filter from filter */
8396 i40e_set_cld_element(filter, &cld_filter);
8397
8398 if (filter->tunnel_type != I40E_CLOUD_TNL_TYPE_NONE)
8399 cld_filter.flags = cpu_to_le16(filter->tunnel_type <<
8400 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
8401
8402 if (filter->n_proto == ETH_P_IPV6)
8403 cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] |
8404 I40E_AQC_ADD_CLOUD_FLAGS_IPV6);
8405 else
8406 cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] |
8407 I40E_AQC_ADD_CLOUD_FLAGS_IPV4);
8408
8409 if (add)
8410 ret = i40e_aq_add_cloud_filters(&pf->hw, filter->seid,
8411 &cld_filter, 1);
8412 else
8413 ret = i40e_aq_rem_cloud_filters(&pf->hw, filter->seid,
8414 &cld_filter, 1);
8415 if (ret)
8416 dev_dbg(&pf->pdev->dev,
8417 "Failed to %s cloud filter using l4 port %u, err %d aq_err %d\n",
8418 add ? "add" : "delete", filter->dst_port, ret,
8419 pf->hw.aq.asq_last_status);
8420 else
8421 dev_info(&pf->pdev->dev,
8422 "%s cloud filter for VSI: %d\n",
8423 add ? "Added" : "Deleted", filter->seid);
8424 return ret;
8425 }
8426
8427 /**
8428 * i40e_add_del_cloud_filter_big_buf - Add/del cloud filter using big_buf
8429 * @vsi: pointer to VSI
8430 * @filter: cloud filter rule
8431 * @add: if true, add, if false, delete
8432 *
8433 * Add or delete a cloud filter for a specific flow spec using big buffer.
8434 * Returns 0 if the filter were successfully added.
8435 **/
i40e_add_del_cloud_filter_big_buf(struct i40e_vsi * vsi,struct i40e_cloud_filter * filter,bool add)8436 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
8437 struct i40e_cloud_filter *filter,
8438 bool add)
8439 {
8440 struct i40e_aqc_cloud_filters_element_bb cld_filter;
8441 struct i40e_pf *pf = vsi->back;
8442 int ret;
8443
8444 /* Both (src/dst) valid mac_addr are not supported */
8445 if ((is_valid_ether_addr(filter->dst_mac) &&
8446 is_valid_ether_addr(filter->src_mac)) ||
8447 (is_multicast_ether_addr(filter->dst_mac) &&
8448 is_multicast_ether_addr(filter->src_mac)))
8449 return -EOPNOTSUPP;
8450
8451 /* Big buffer cloud filter needs 'L4 port' to be non-zero. Also, UDP
8452 * ports are not supported via big buffer now.
8453 */
8454 if (!filter->dst_port || filter->ip_proto == IPPROTO_UDP)
8455 return -EOPNOTSUPP;
8456
8457 /* adding filter using src_port/src_ip is not supported at this stage */
8458 if (filter->src_port ||
8459 (filter->src_ipv4 && filter->n_proto != ETH_P_IPV6) ||
8460 !ipv6_addr_any(&filter->ip.v6.src_ip6))
8461 return -EOPNOTSUPP;
8462
8463 memset(&cld_filter, 0, sizeof(cld_filter));
8464
8465 /* copy element needed to add cloud filter from filter */
8466 i40e_set_cld_element(filter, &cld_filter.element);
8467
8468 if (is_valid_ether_addr(filter->dst_mac) ||
8469 is_valid_ether_addr(filter->src_mac) ||
8470 is_multicast_ether_addr(filter->dst_mac) ||
8471 is_multicast_ether_addr(filter->src_mac)) {
8472 /* MAC + IP : unsupported mode */
8473 if (filter->dst_ipv4)
8474 return -EOPNOTSUPP;
8475
8476 /* since we validated that L4 port must be valid before
8477 * we get here, start with respective "flags" value
8478 * and update if vlan is present or not
8479 */
8480 cld_filter.element.flags =
8481 cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT);
8482
8483 if (filter->vlan_id) {
8484 cld_filter.element.flags =
8485 cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT);
8486 }
8487
8488 } else if ((filter->dst_ipv4 && filter->n_proto != ETH_P_IPV6) ||
8489 !ipv6_addr_any(&filter->ip.v6.dst_ip6)) {
8490 cld_filter.element.flags =
8491 cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_IP_PORT);
8492 if (filter->n_proto == ETH_P_IPV6)
8493 cld_filter.element.flags |=
8494 cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV6);
8495 else
8496 cld_filter.element.flags |=
8497 cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV4);
8498 } else {
8499 dev_err(&pf->pdev->dev,
8500 "either mac or ip has to be valid for cloud filter\n");
8501 return -EINVAL;
8502 }
8503
8504 /* Now copy L4 port in Byte 6..7 in general fields */
8505 cld_filter.general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0] =
8506 be16_to_cpu(filter->dst_port);
8507
8508 if (add) {
8509 /* Validate current device switch mode, change if necessary */
8510 ret = i40e_validate_and_set_switch_mode(vsi);
8511 if (ret) {
8512 dev_err(&pf->pdev->dev,
8513 "failed to set switch mode, ret %d\n",
8514 ret);
8515 return ret;
8516 }
8517
8518 ret = i40e_aq_add_cloud_filters_bb(&pf->hw, filter->seid,
8519 &cld_filter, 1);
8520 } else {
8521 ret = i40e_aq_rem_cloud_filters_bb(&pf->hw, filter->seid,
8522 &cld_filter, 1);
8523 }
8524
8525 if (ret)
8526 dev_dbg(&pf->pdev->dev,
8527 "Failed to %s cloud filter(big buffer) err %d aq_err %d\n",
8528 add ? "add" : "delete", ret, pf->hw.aq.asq_last_status);
8529 else
8530 dev_info(&pf->pdev->dev,
8531 "%s cloud filter for VSI: %d, L4 port: %d\n",
8532 add ? "add" : "delete", filter->seid,
8533 ntohs(filter->dst_port));
8534 return ret;
8535 }
8536
8537 /**
8538 * i40e_parse_cls_flower - Parse tc flower filters provided by kernel
8539 * @vsi: Pointer to VSI
8540 * @f: Pointer to struct flow_cls_offload
8541 * @filter: Pointer to cloud filter structure
8542 *
8543 **/
i40e_parse_cls_flower(struct i40e_vsi * vsi,struct flow_cls_offload * f,struct i40e_cloud_filter * filter)8544 static int i40e_parse_cls_flower(struct i40e_vsi *vsi,
8545 struct flow_cls_offload *f,
8546 struct i40e_cloud_filter *filter)
8547 {
8548 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8549 struct flow_dissector *dissector = rule->match.dissector;
8550 u16 n_proto_mask = 0, n_proto_key = 0, addr_type = 0;
8551 struct i40e_pf *pf = vsi->back;
8552 u8 field_flags = 0;
8553
8554 if (dissector->used_keys &
8555 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
8556 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
8557 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
8558 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
8559 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
8560 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
8561 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
8562 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID))) {
8563 dev_err(&pf->pdev->dev, "Unsupported key used: 0x%llx\n",
8564 dissector->used_keys);
8565 return -EOPNOTSUPP;
8566 }
8567
8568 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
8569 struct flow_match_enc_keyid match;
8570
8571 flow_rule_match_enc_keyid(rule, &match);
8572 if (match.mask->keyid != 0)
8573 field_flags |= I40E_CLOUD_FIELD_TEN_ID;
8574
8575 filter->tenant_id = be32_to_cpu(match.key->keyid);
8576 }
8577
8578 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
8579 struct flow_match_basic match;
8580
8581 flow_rule_match_basic(rule, &match);
8582 n_proto_key = ntohs(match.key->n_proto);
8583 n_proto_mask = ntohs(match.mask->n_proto);
8584
8585 if (n_proto_key == ETH_P_ALL) {
8586 n_proto_key = 0;
8587 n_proto_mask = 0;
8588 }
8589 filter->n_proto = n_proto_key & n_proto_mask;
8590 filter->ip_proto = match.key->ip_proto;
8591 }
8592
8593 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
8594 struct flow_match_eth_addrs match;
8595
8596 flow_rule_match_eth_addrs(rule, &match);
8597
8598 /* use is_broadcast and is_zero to check for all 0xf or 0 */
8599 if (!is_zero_ether_addr(match.mask->dst)) {
8600 if (is_broadcast_ether_addr(match.mask->dst)) {
8601 field_flags |= I40E_CLOUD_FIELD_OMAC;
8602 } else {
8603 dev_err(&pf->pdev->dev, "Bad ether dest mask %pM\n",
8604 match.mask->dst);
8605 return -EIO;
8606 }
8607 }
8608
8609 if (!is_zero_ether_addr(match.mask->src)) {
8610 if (is_broadcast_ether_addr(match.mask->src)) {
8611 field_flags |= I40E_CLOUD_FIELD_IMAC;
8612 } else {
8613 dev_err(&pf->pdev->dev, "Bad ether src mask %pM\n",
8614 match.mask->src);
8615 return -EIO;
8616 }
8617 }
8618 ether_addr_copy(filter->dst_mac, match.key->dst);
8619 ether_addr_copy(filter->src_mac, match.key->src);
8620 }
8621
8622 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
8623 struct flow_match_vlan match;
8624
8625 flow_rule_match_vlan(rule, &match);
8626 if (match.mask->vlan_id) {
8627 if (match.mask->vlan_id == VLAN_VID_MASK) {
8628 field_flags |= I40E_CLOUD_FIELD_IVLAN;
8629
8630 } else {
8631 dev_err(&pf->pdev->dev, "Bad vlan mask 0x%04x\n",
8632 match.mask->vlan_id);
8633 return -EIO;
8634 }
8635 }
8636
8637 filter->vlan_id = cpu_to_be16(match.key->vlan_id);
8638 }
8639
8640 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
8641 struct flow_match_control match;
8642
8643 flow_rule_match_control(rule, &match);
8644 addr_type = match.key->addr_type;
8645 }
8646
8647 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8648 struct flow_match_ipv4_addrs match;
8649
8650 flow_rule_match_ipv4_addrs(rule, &match);
8651 if (match.mask->dst) {
8652 if (match.mask->dst == cpu_to_be32(0xffffffff)) {
8653 field_flags |= I40E_CLOUD_FIELD_IIP;
8654 } else {
8655 dev_err(&pf->pdev->dev, "Bad ip dst mask %pI4b\n",
8656 &match.mask->dst);
8657 return -EIO;
8658 }
8659 }
8660
8661 if (match.mask->src) {
8662 if (match.mask->src == cpu_to_be32(0xffffffff)) {
8663 field_flags |= I40E_CLOUD_FIELD_IIP;
8664 } else {
8665 dev_err(&pf->pdev->dev, "Bad ip src mask %pI4b\n",
8666 &match.mask->src);
8667 return -EIO;
8668 }
8669 }
8670
8671 if (field_flags & I40E_CLOUD_FIELD_TEN_ID) {
8672 dev_err(&pf->pdev->dev, "Tenant id not allowed for ip filter\n");
8673 return -EIO;
8674 }
8675 filter->dst_ipv4 = match.key->dst;
8676 filter->src_ipv4 = match.key->src;
8677 }
8678
8679 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8680 struct flow_match_ipv6_addrs match;
8681
8682 flow_rule_match_ipv6_addrs(rule, &match);
8683
8684 /* src and dest IPV6 address should not be LOOPBACK
8685 * (0:0:0:0:0:0:0:1), which can be represented as ::1
8686 */
8687 if (ipv6_addr_loopback(&match.key->dst) ||
8688 ipv6_addr_loopback(&match.key->src)) {
8689 dev_err(&pf->pdev->dev,
8690 "Bad ipv6, addr is LOOPBACK\n");
8691 return -EIO;
8692 }
8693 if (!ipv6_addr_any(&match.mask->dst) ||
8694 !ipv6_addr_any(&match.mask->src))
8695 field_flags |= I40E_CLOUD_FIELD_IIP;
8696
8697 memcpy(&filter->src_ipv6, &match.key->src.s6_addr32,
8698 sizeof(filter->src_ipv6));
8699 memcpy(&filter->dst_ipv6, &match.key->dst.s6_addr32,
8700 sizeof(filter->dst_ipv6));
8701 }
8702
8703 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
8704 struct flow_match_ports match;
8705
8706 flow_rule_match_ports(rule, &match);
8707 if (match.mask->src) {
8708 if (match.mask->src == cpu_to_be16(0xffff)) {
8709 field_flags |= I40E_CLOUD_FIELD_IIP;
8710 } else {
8711 dev_err(&pf->pdev->dev, "Bad src port mask 0x%04x\n",
8712 be16_to_cpu(match.mask->src));
8713 return -EIO;
8714 }
8715 }
8716
8717 if (match.mask->dst) {
8718 if (match.mask->dst == cpu_to_be16(0xffff)) {
8719 field_flags |= I40E_CLOUD_FIELD_IIP;
8720 } else {
8721 dev_err(&pf->pdev->dev, "Bad dst port mask 0x%04x\n",
8722 be16_to_cpu(match.mask->dst));
8723 return -EIO;
8724 }
8725 }
8726
8727 filter->dst_port = match.key->dst;
8728 filter->src_port = match.key->src;
8729
8730 switch (filter->ip_proto) {
8731 case IPPROTO_TCP:
8732 case IPPROTO_UDP:
8733 break;
8734 default:
8735 dev_err(&pf->pdev->dev,
8736 "Only UDP and TCP transport are supported\n");
8737 return -EINVAL;
8738 }
8739 }
8740 filter->flags = field_flags;
8741 return 0;
8742 }
8743
8744 /**
8745 * i40e_handle_tclass: Forward to a traffic class on the device
8746 * @vsi: Pointer to VSI
8747 * @tc: traffic class index on the device
8748 * @filter: Pointer to cloud filter structure
8749 *
8750 **/
i40e_handle_tclass(struct i40e_vsi * vsi,u32 tc,struct i40e_cloud_filter * filter)8751 static int i40e_handle_tclass(struct i40e_vsi *vsi, u32 tc,
8752 struct i40e_cloud_filter *filter)
8753 {
8754 struct i40e_channel *ch, *ch_tmp;
8755
8756 /* direct to a traffic class on the same device */
8757 if (tc == 0) {
8758 filter->seid = vsi->seid;
8759 return 0;
8760 } else if (vsi->tc_config.enabled_tc & BIT(tc)) {
8761 if (!filter->dst_port) {
8762 dev_err(&vsi->back->pdev->dev,
8763 "Specify destination port to direct to traffic class that is not default\n");
8764 return -EINVAL;
8765 }
8766 if (list_empty(&vsi->ch_list))
8767 return -EINVAL;
8768 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list,
8769 list) {
8770 if (ch->seid == vsi->tc_seid_map[tc])
8771 filter->seid = ch->seid;
8772 }
8773 return 0;
8774 }
8775 dev_err(&vsi->back->pdev->dev, "TC is not enabled\n");
8776 return -EINVAL;
8777 }
8778
8779 /**
8780 * i40e_configure_clsflower - Configure tc flower filters
8781 * @vsi: Pointer to VSI
8782 * @cls_flower: Pointer to struct flow_cls_offload
8783 *
8784 **/
i40e_configure_clsflower(struct i40e_vsi * vsi,struct flow_cls_offload * cls_flower)8785 static int i40e_configure_clsflower(struct i40e_vsi *vsi,
8786 struct flow_cls_offload *cls_flower)
8787 {
8788 int tc = tc_classid_to_hwtc(vsi->netdev, cls_flower->classid);
8789 struct i40e_cloud_filter *filter = NULL;
8790 struct i40e_pf *pf = vsi->back;
8791 int err = 0;
8792
8793 if (tc < 0) {
8794 dev_err(&vsi->back->pdev->dev, "Invalid traffic class\n");
8795 return -EOPNOTSUPP;
8796 }
8797
8798 if (!tc) {
8799 dev_err(&pf->pdev->dev, "Unable to add filter because of invalid destination");
8800 return -EINVAL;
8801 }
8802
8803 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
8804 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
8805 return -EBUSY;
8806
8807 if (pf->fdir_pf_active_filters ||
8808 (!hlist_empty(&pf->fdir_filter_list))) {
8809 dev_err(&vsi->back->pdev->dev,
8810 "Flow Director Sideband filters exists, turn ntuple off to configure cloud filters\n");
8811 return -EINVAL;
8812 }
8813
8814 if (test_bit(I40E_FLAG_FD_SB_ENA, vsi->back->flags)) {
8815 dev_err(&vsi->back->pdev->dev,
8816 "Disable Flow Director Sideband, configuring Cloud filters via tc-flower\n");
8817 clear_bit(I40E_FLAG_FD_SB_ENA, vsi->back->flags);
8818 clear_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, vsi->back->flags);
8819 }
8820
8821 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
8822 if (!filter)
8823 return -ENOMEM;
8824
8825 filter->cookie = cls_flower->cookie;
8826
8827 err = i40e_parse_cls_flower(vsi, cls_flower, filter);
8828 if (err < 0)
8829 goto err;
8830
8831 err = i40e_handle_tclass(vsi, tc, filter);
8832 if (err < 0)
8833 goto err;
8834
8835 /* Add cloud filter */
8836 if (filter->dst_port)
8837 err = i40e_add_del_cloud_filter_big_buf(vsi, filter, true);
8838 else
8839 err = i40e_add_del_cloud_filter(vsi, filter, true);
8840
8841 if (err) {
8842 dev_err(&pf->pdev->dev, "Failed to add cloud filter, err %d\n",
8843 err);
8844 goto err;
8845 }
8846
8847 /* add filter to the ordered list */
8848 INIT_HLIST_NODE(&filter->cloud_node);
8849
8850 hlist_add_head(&filter->cloud_node, &pf->cloud_filter_list);
8851
8852 pf->num_cloud_filters++;
8853
8854 return err;
8855 err:
8856 kfree(filter);
8857 return err;
8858 }
8859
8860 /**
8861 * i40e_find_cloud_filter - Find the could filter in the list
8862 * @vsi: Pointer to VSI
8863 * @cookie: filter specific cookie
8864 *
8865 **/
i40e_find_cloud_filter(struct i40e_vsi * vsi,unsigned long * cookie)8866 static struct i40e_cloud_filter *i40e_find_cloud_filter(struct i40e_vsi *vsi,
8867 unsigned long *cookie)
8868 {
8869 struct i40e_cloud_filter *filter = NULL;
8870 struct hlist_node *node2;
8871
8872 hlist_for_each_entry_safe(filter, node2,
8873 &vsi->back->cloud_filter_list, cloud_node)
8874 if (!memcmp(cookie, &filter->cookie, sizeof(filter->cookie)))
8875 return filter;
8876 return NULL;
8877 }
8878
8879 /**
8880 * i40e_delete_clsflower - Remove tc flower filters
8881 * @vsi: Pointer to VSI
8882 * @cls_flower: Pointer to struct flow_cls_offload
8883 *
8884 **/
i40e_delete_clsflower(struct i40e_vsi * vsi,struct flow_cls_offload * cls_flower)8885 static int i40e_delete_clsflower(struct i40e_vsi *vsi,
8886 struct flow_cls_offload *cls_flower)
8887 {
8888 struct i40e_cloud_filter *filter = NULL;
8889 struct i40e_pf *pf = vsi->back;
8890 int err = 0;
8891
8892 filter = i40e_find_cloud_filter(vsi, &cls_flower->cookie);
8893
8894 if (!filter)
8895 return -EINVAL;
8896
8897 hash_del(&filter->cloud_node);
8898
8899 if (filter->dst_port)
8900 err = i40e_add_del_cloud_filter_big_buf(vsi, filter, false);
8901 else
8902 err = i40e_add_del_cloud_filter(vsi, filter, false);
8903
8904 kfree(filter);
8905 if (err) {
8906 dev_err(&pf->pdev->dev,
8907 "Failed to delete cloud filter, err %pe\n",
8908 ERR_PTR(err));
8909 return i40e_aq_rc_to_posix(err, pf->hw.aq.asq_last_status);
8910 }
8911
8912 pf->num_cloud_filters--;
8913 if (!pf->num_cloud_filters)
8914 if (test_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf->flags) &&
8915 !test_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags)) {
8916 set_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
8917 clear_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf->flags);
8918 clear_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
8919 }
8920 return 0;
8921 }
8922
8923 /**
8924 * i40e_setup_tc_cls_flower - flower classifier offloads
8925 * @np: net device to configure
8926 * @cls_flower: offload data
8927 **/
i40e_setup_tc_cls_flower(struct i40e_netdev_priv * np,struct flow_cls_offload * cls_flower)8928 static int i40e_setup_tc_cls_flower(struct i40e_netdev_priv *np,
8929 struct flow_cls_offload *cls_flower)
8930 {
8931 struct i40e_vsi *vsi = np->vsi;
8932
8933 switch (cls_flower->command) {
8934 case FLOW_CLS_REPLACE:
8935 return i40e_configure_clsflower(vsi, cls_flower);
8936 case FLOW_CLS_DESTROY:
8937 return i40e_delete_clsflower(vsi, cls_flower);
8938 case FLOW_CLS_STATS:
8939 return -EOPNOTSUPP;
8940 default:
8941 return -EOPNOTSUPP;
8942 }
8943 }
8944
i40e_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)8945 static int i40e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
8946 void *cb_priv)
8947 {
8948 struct i40e_netdev_priv *np = cb_priv;
8949
8950 if (!tc_cls_can_offload_and_chain0(np->vsi->netdev, type_data))
8951 return -EOPNOTSUPP;
8952
8953 switch (type) {
8954 case TC_SETUP_CLSFLOWER:
8955 return i40e_setup_tc_cls_flower(np, type_data);
8956
8957 default:
8958 return -EOPNOTSUPP;
8959 }
8960 }
8961
8962 static LIST_HEAD(i40e_block_cb_list);
8963
__i40e_setup_tc(struct net_device * netdev,enum tc_setup_type type,void * type_data)8964 static int __i40e_setup_tc(struct net_device *netdev, enum tc_setup_type type,
8965 void *type_data)
8966 {
8967 struct i40e_netdev_priv *np = netdev_priv(netdev);
8968
8969 switch (type) {
8970 case TC_SETUP_QDISC_MQPRIO:
8971 return i40e_setup_tc(netdev, type_data);
8972 case TC_SETUP_BLOCK:
8973 return flow_block_cb_setup_simple(type_data,
8974 &i40e_block_cb_list,
8975 i40e_setup_tc_block_cb,
8976 np, np, true);
8977 default:
8978 return -EOPNOTSUPP;
8979 }
8980 }
8981
8982 /**
8983 * i40e_open - Called when a network interface is made active
8984 * @netdev: network interface device structure
8985 *
8986 * The open entry point is called when a network interface is made
8987 * active by the system (IFF_UP). At this point all resources needed
8988 * for transmit and receive operations are allocated, the interrupt
8989 * handler is registered with the OS, the netdev watchdog subtask is
8990 * enabled, and the stack is notified that the interface is ready.
8991 *
8992 * Returns 0 on success, negative value on failure
8993 **/
i40e_open(struct net_device * netdev)8994 int i40e_open(struct net_device *netdev)
8995 {
8996 struct i40e_netdev_priv *np = netdev_priv(netdev);
8997 struct i40e_vsi *vsi = np->vsi;
8998 struct i40e_pf *pf = vsi->back;
8999 int err;
9000
9001 /* disallow open during test or if eeprom is broken */
9002 if (test_bit(__I40E_TESTING, pf->state) ||
9003 test_bit(__I40E_BAD_EEPROM, pf->state))
9004 return -EBUSY;
9005
9006 netif_carrier_off(netdev);
9007
9008 if (i40e_force_link_state(pf, true))
9009 return -EAGAIN;
9010
9011 err = i40e_vsi_open(vsi);
9012 if (err)
9013 return err;
9014
9015 /* configure global TSO hardware offload settings */
9016 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
9017 TCP_FLAG_FIN) >> 16);
9018 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
9019 TCP_FLAG_FIN |
9020 TCP_FLAG_CWR) >> 16);
9021 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
9022 udp_tunnel_get_rx_info(netdev);
9023
9024 return 0;
9025 }
9026
9027 /**
9028 * i40e_netif_set_realnum_tx_rx_queues - Update number of tx/rx queues
9029 * @vsi: vsi structure
9030 *
9031 * This updates netdev's number of tx/rx queues
9032 *
9033 * Returns status of setting tx/rx queues
9034 **/
i40e_netif_set_realnum_tx_rx_queues(struct i40e_vsi * vsi)9035 static int i40e_netif_set_realnum_tx_rx_queues(struct i40e_vsi *vsi)
9036 {
9037 int ret;
9038
9039 ret = netif_set_real_num_rx_queues(vsi->netdev,
9040 vsi->num_queue_pairs);
9041 if (ret)
9042 return ret;
9043
9044 return netif_set_real_num_tx_queues(vsi->netdev,
9045 vsi->num_queue_pairs);
9046 }
9047
9048 /**
9049 * i40e_vsi_open -
9050 * @vsi: the VSI to open
9051 *
9052 * Finish initialization of the VSI.
9053 *
9054 * Returns 0 on success, negative value on failure
9055 *
9056 * Note: expects to be called while under rtnl_lock()
9057 **/
i40e_vsi_open(struct i40e_vsi * vsi)9058 int i40e_vsi_open(struct i40e_vsi *vsi)
9059 {
9060 struct i40e_pf *pf = vsi->back;
9061 char int_name[I40E_INT_NAME_STR_LEN];
9062 int err;
9063
9064 /* allocate descriptors */
9065 err = i40e_vsi_setup_tx_resources(vsi);
9066 if (err)
9067 goto err_setup_tx;
9068 err = i40e_vsi_setup_rx_resources(vsi);
9069 if (err)
9070 goto err_setup_rx;
9071
9072 err = i40e_vsi_configure(vsi);
9073 if (err)
9074 goto err_setup_rx;
9075
9076 if (vsi->netdev) {
9077 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
9078 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
9079 err = i40e_vsi_request_irq(vsi, int_name);
9080 if (err)
9081 goto err_setup_rx;
9082
9083 /* Notify the stack of the actual queue counts. */
9084 err = i40e_netif_set_realnum_tx_rx_queues(vsi);
9085 if (err)
9086 goto err_set_queues;
9087
9088 } else if (vsi->type == I40E_VSI_FDIR) {
9089 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
9090 dev_driver_string(&pf->pdev->dev),
9091 dev_name(&pf->pdev->dev));
9092 err = i40e_vsi_request_irq(vsi, int_name);
9093 if (err)
9094 goto err_setup_rx;
9095
9096 } else {
9097 err = -EINVAL;
9098 goto err_setup_rx;
9099 }
9100
9101 err = i40e_up_complete(vsi);
9102 if (err)
9103 goto err_up_complete;
9104
9105 return 0;
9106
9107 err_up_complete:
9108 i40e_down(vsi);
9109 err_set_queues:
9110 i40e_vsi_free_irq(vsi);
9111 err_setup_rx:
9112 i40e_vsi_free_rx_resources(vsi);
9113 err_setup_tx:
9114 i40e_vsi_free_tx_resources(vsi);
9115 if (vsi == pf->vsi[pf->lan_vsi])
9116 i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);
9117
9118 return err;
9119 }
9120
9121 /**
9122 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
9123 * @pf: Pointer to PF
9124 *
9125 * This function destroys the hlist where all the Flow Director
9126 * filters were saved.
9127 **/
i40e_fdir_filter_exit(struct i40e_pf * pf)9128 static void i40e_fdir_filter_exit(struct i40e_pf *pf)
9129 {
9130 struct i40e_fdir_filter *filter;
9131 struct i40e_flex_pit *pit_entry, *tmp;
9132 struct hlist_node *node2;
9133
9134 hlist_for_each_entry_safe(filter, node2,
9135 &pf->fdir_filter_list, fdir_node) {
9136 hlist_del(&filter->fdir_node);
9137 kfree(filter);
9138 }
9139
9140 list_for_each_entry_safe(pit_entry, tmp, &pf->l3_flex_pit_list, list) {
9141 list_del(&pit_entry->list);
9142 kfree(pit_entry);
9143 }
9144 INIT_LIST_HEAD(&pf->l3_flex_pit_list);
9145
9146 list_for_each_entry_safe(pit_entry, tmp, &pf->l4_flex_pit_list, list) {
9147 list_del(&pit_entry->list);
9148 kfree(pit_entry);
9149 }
9150 INIT_LIST_HEAD(&pf->l4_flex_pit_list);
9151
9152 pf->fdir_pf_active_filters = 0;
9153 i40e_reset_fdir_filter_cnt(pf);
9154
9155 /* Reprogram the default input set for TCP/IPv4 */
9156 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9157 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
9158 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
9159
9160 /* Reprogram the default input set for TCP/IPv6 */
9161 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9162 I40E_L3_V6_SRC_MASK | I40E_L3_V6_DST_MASK |
9163 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
9164
9165 /* Reprogram the default input set for UDP/IPv4 */
9166 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9167 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
9168 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
9169
9170 /* Reprogram the default input set for UDP/IPv6 */
9171 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9172 I40E_L3_V6_SRC_MASK | I40E_L3_V6_DST_MASK |
9173 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
9174
9175 /* Reprogram the default input set for SCTP/IPv4 */
9176 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9177 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
9178 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
9179
9180 /* Reprogram the default input set for SCTP/IPv6 */
9181 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9182 I40E_L3_V6_SRC_MASK | I40E_L3_V6_DST_MASK |
9183 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
9184
9185 /* Reprogram the default input set for Other/IPv4 */
9186 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9187 I40E_L3_SRC_MASK | I40E_L3_DST_MASK);
9188
9189 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4,
9190 I40E_L3_SRC_MASK | I40E_L3_DST_MASK);
9191
9192 /* Reprogram the default input set for Other/IPv6 */
9193 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9194 I40E_L3_SRC_MASK | I40E_L3_DST_MASK);
9195
9196 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV6,
9197 I40E_L3_SRC_MASK | I40E_L3_DST_MASK);
9198 }
9199
9200 /**
9201 * i40e_cloud_filter_exit - Cleans up the cloud filters
9202 * @pf: Pointer to PF
9203 *
9204 * This function destroys the hlist where all the cloud filters
9205 * were saved.
9206 **/
i40e_cloud_filter_exit(struct i40e_pf * pf)9207 static void i40e_cloud_filter_exit(struct i40e_pf *pf)
9208 {
9209 struct i40e_cloud_filter *cfilter;
9210 struct hlist_node *node;
9211
9212 hlist_for_each_entry_safe(cfilter, node,
9213 &pf->cloud_filter_list, cloud_node) {
9214 hlist_del(&cfilter->cloud_node);
9215 kfree(cfilter);
9216 }
9217 pf->num_cloud_filters = 0;
9218
9219 if (test_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf->flags) &&
9220 !test_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags)) {
9221 set_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
9222 clear_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf->flags);
9223 clear_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
9224 }
9225 }
9226
9227 /**
9228 * i40e_close - Disables a network interface
9229 * @netdev: network interface device structure
9230 *
9231 * The close entry point is called when an interface is de-activated
9232 * by the OS. The hardware is still under the driver's control, but
9233 * this netdev interface is disabled.
9234 *
9235 * Returns 0, this is not allowed to fail
9236 **/
i40e_close(struct net_device * netdev)9237 int i40e_close(struct net_device *netdev)
9238 {
9239 struct i40e_netdev_priv *np = netdev_priv(netdev);
9240 struct i40e_vsi *vsi = np->vsi;
9241
9242 i40e_vsi_close(vsi);
9243
9244 return 0;
9245 }
9246
9247 /**
9248 * i40e_do_reset - Start a PF or Core Reset sequence
9249 * @pf: board private structure
9250 * @reset_flags: which reset is requested
9251 * @lock_acquired: indicates whether or not the lock has been acquired
9252 * before this function was called.
9253 *
9254 * The essential difference in resets is that the PF Reset
9255 * doesn't clear the packet buffers, doesn't reset the PE
9256 * firmware, and doesn't bother the other PFs on the chip.
9257 **/
i40e_do_reset(struct i40e_pf * pf,u32 reset_flags,bool lock_acquired)9258 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired)
9259 {
9260 u32 val;
9261
9262 /* do the biggest reset indicated */
9263 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
9264
9265 /* Request a Global Reset
9266 *
9267 * This will start the chip's countdown to the actual full
9268 * chip reset event, and a warning interrupt to be sent
9269 * to all PFs, including the requestor. Our handler
9270 * for the warning interrupt will deal with the shutdown
9271 * and recovery of the switch setup.
9272 */
9273 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
9274 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9275 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
9276 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
9277
9278 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
9279
9280 /* Request a Core Reset
9281 *
9282 * Same as Global Reset, except does *not* include the MAC/PHY
9283 */
9284 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
9285 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9286 val |= I40E_GLGEN_RTRIG_CORER_MASK;
9287 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
9288 i40e_flush(&pf->hw);
9289
9290 } else if (reset_flags & I40E_PF_RESET_FLAG) {
9291
9292 /* Request a PF Reset
9293 *
9294 * Resets only the PF-specific registers
9295 *
9296 * This goes directly to the tear-down and rebuild of
9297 * the switch, since we need to do all the recovery as
9298 * for the Core Reset.
9299 */
9300 dev_dbg(&pf->pdev->dev, "PFR requested\n");
9301 i40e_handle_reset_warning(pf, lock_acquired);
9302
9303 } else if (reset_flags & I40E_PF_RESET_AND_REBUILD_FLAG) {
9304 /* Request a PF Reset
9305 *
9306 * Resets PF and reinitializes PFs VSI.
9307 */
9308 i40e_prep_for_reset(pf);
9309 i40e_reset_and_rebuild(pf, true, lock_acquired);
9310 dev_info(&pf->pdev->dev,
9311 test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags) ?
9312 "FW LLDP is disabled\n" :
9313 "FW LLDP is enabled\n");
9314
9315 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
9316 int v;
9317
9318 /* Find the VSI(s) that requested a re-init */
9319 dev_info(&pf->pdev->dev,
9320 "VSI reinit requested\n");
9321 for (v = 0; v < pf->num_alloc_vsi; v++) {
9322 struct i40e_vsi *vsi = pf->vsi[v];
9323
9324 if (vsi != NULL &&
9325 test_and_clear_bit(__I40E_VSI_REINIT_REQUESTED,
9326 vsi->state))
9327 i40e_vsi_reinit_locked(pf->vsi[v]);
9328 }
9329 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
9330 int v;
9331
9332 /* Find the VSI(s) that needs to be brought down */
9333 dev_info(&pf->pdev->dev, "VSI down requested\n");
9334 for (v = 0; v < pf->num_alloc_vsi; v++) {
9335 struct i40e_vsi *vsi = pf->vsi[v];
9336
9337 if (vsi != NULL &&
9338 test_and_clear_bit(__I40E_VSI_DOWN_REQUESTED,
9339 vsi->state)) {
9340 set_bit(__I40E_VSI_DOWN, vsi->state);
9341 i40e_down(vsi);
9342 }
9343 }
9344 } else {
9345 dev_info(&pf->pdev->dev,
9346 "bad reset request 0x%08x\n", reset_flags);
9347 }
9348 }
9349
9350 #ifdef CONFIG_I40E_DCB
9351 /**
9352 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
9353 * @pf: board private structure
9354 * @old_cfg: current DCB config
9355 * @new_cfg: new DCB config
9356 **/
i40e_dcb_need_reconfig(struct i40e_pf * pf,struct i40e_dcbx_config * old_cfg,struct i40e_dcbx_config * new_cfg)9357 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
9358 struct i40e_dcbx_config *old_cfg,
9359 struct i40e_dcbx_config *new_cfg)
9360 {
9361 bool need_reconfig = false;
9362
9363 /* Check if ETS configuration has changed */
9364 if (memcmp(&new_cfg->etscfg,
9365 &old_cfg->etscfg,
9366 sizeof(new_cfg->etscfg))) {
9367 /* If Priority Table has changed reconfig is needed */
9368 if (memcmp(&new_cfg->etscfg.prioritytable,
9369 &old_cfg->etscfg.prioritytable,
9370 sizeof(new_cfg->etscfg.prioritytable))) {
9371 need_reconfig = true;
9372 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
9373 }
9374
9375 if (memcmp(&new_cfg->etscfg.tcbwtable,
9376 &old_cfg->etscfg.tcbwtable,
9377 sizeof(new_cfg->etscfg.tcbwtable)))
9378 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
9379
9380 if (memcmp(&new_cfg->etscfg.tsatable,
9381 &old_cfg->etscfg.tsatable,
9382 sizeof(new_cfg->etscfg.tsatable)))
9383 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
9384 }
9385
9386 /* Check if PFC configuration has changed */
9387 if (memcmp(&new_cfg->pfc,
9388 &old_cfg->pfc,
9389 sizeof(new_cfg->pfc))) {
9390 need_reconfig = true;
9391 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
9392 }
9393
9394 /* Check if APP Table has changed */
9395 if (memcmp(&new_cfg->app,
9396 &old_cfg->app,
9397 sizeof(new_cfg->app))) {
9398 need_reconfig = true;
9399 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
9400 }
9401
9402 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
9403 return need_reconfig;
9404 }
9405
9406 /**
9407 * i40e_handle_lldp_event - Handle LLDP Change MIB event
9408 * @pf: board private structure
9409 * @e: event info posted on ARQ
9410 **/
i40e_handle_lldp_event(struct i40e_pf * pf,struct i40e_arq_event_info * e)9411 static int i40e_handle_lldp_event(struct i40e_pf *pf,
9412 struct i40e_arq_event_info *e)
9413 {
9414 struct i40e_aqc_lldp_get_mib *mib =
9415 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
9416 struct i40e_hw *hw = &pf->hw;
9417 struct i40e_dcbx_config tmp_dcbx_cfg;
9418 bool need_reconfig = false;
9419 int ret = 0;
9420 u8 type;
9421
9422 /* X710-T*L 2.5G and 5G speeds don't support DCB */
9423 if (I40E_IS_X710TL_DEVICE(hw->device_id) &&
9424 (hw->phy.link_info.link_speed &
9425 ~(I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB)) &&
9426 !test_bit(I40E_FLAG_DCB_CAPABLE, pf->flags))
9427 /* let firmware decide if the DCB should be disabled */
9428 set_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
9429
9430 /* Not DCB capable or capability disabled */
9431 if (!test_bit(I40E_FLAG_DCB_CAPABLE, pf->flags))
9432 return ret;
9433
9434 /* Ignore if event is not for Nearest Bridge */
9435 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
9436 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9437 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
9438 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
9439 return ret;
9440
9441 /* Check MIB Type and return if event for Remote MIB update */
9442 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9443 dev_dbg(&pf->pdev->dev,
9444 "LLDP event mib type %s\n", type ? "remote" : "local");
9445 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
9446 /* Update the remote cached instance and return */
9447 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
9448 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
9449 &hw->remote_dcbx_config);
9450 goto exit;
9451 }
9452
9453 /* Store the old configuration */
9454 tmp_dcbx_cfg = hw->local_dcbx_config;
9455
9456 /* Reset the old DCBx configuration data */
9457 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9458 /* Get updated DCBX data from firmware */
9459 ret = i40e_get_dcb_config(&pf->hw);
9460 if (ret) {
9461 /* X710-T*L 2.5G and 5G speeds don't support DCB */
9462 if (I40E_IS_X710TL_DEVICE(hw->device_id) &&
9463 (hw->phy.link_info.link_speed &
9464 (I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB))) {
9465 dev_warn(&pf->pdev->dev,
9466 "DCB is not supported for X710-T*L 2.5/5G speeds\n");
9467 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
9468 } else {
9469 dev_info(&pf->pdev->dev,
9470 "Failed querying DCB configuration data from firmware, err %pe aq_err %s\n",
9471 ERR_PTR(ret),
9472 i40e_aq_str(&pf->hw,
9473 pf->hw.aq.asq_last_status));
9474 }
9475 goto exit;
9476 }
9477
9478 /* No change detected in DCBX configs */
9479 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
9480 sizeof(tmp_dcbx_cfg))) {
9481 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
9482 goto exit;
9483 }
9484
9485 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
9486 &hw->local_dcbx_config);
9487
9488 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
9489
9490 if (!need_reconfig)
9491 goto exit;
9492
9493 /* Enable DCB tagging only when more than one TC */
9494 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
9495 set_bit(I40E_FLAG_DCB_ENA, pf->flags);
9496 else
9497 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
9498
9499 set_bit(__I40E_PORT_SUSPENDED, pf->state);
9500 /* Reconfiguration needed quiesce all VSIs */
9501 i40e_pf_quiesce_all_vsi(pf);
9502
9503 /* Changes in configuration update VEB/VSI */
9504 i40e_dcb_reconfigure(pf);
9505
9506 ret = i40e_resume_port_tx(pf);
9507
9508 clear_bit(__I40E_PORT_SUSPENDED, pf->state);
9509 /* In case of error no point in resuming VSIs */
9510 if (ret)
9511 goto exit;
9512
9513 /* Wait for the PF's queues to be disabled */
9514 ret = i40e_pf_wait_queues_disabled(pf);
9515 if (ret) {
9516 /* Schedule PF reset to recover */
9517 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
9518 i40e_service_event_schedule(pf);
9519 } else {
9520 i40e_pf_unquiesce_all_vsi(pf);
9521 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
9522 set_bit(__I40E_CLIENT_L2_CHANGE, pf->state);
9523 }
9524
9525 exit:
9526 return ret;
9527 }
9528 #endif /* CONFIG_I40E_DCB */
9529
9530 /**
9531 * i40e_do_reset_safe - Protected reset path for userland calls.
9532 * @pf: board private structure
9533 * @reset_flags: which reset is requested
9534 *
9535 **/
i40e_do_reset_safe(struct i40e_pf * pf,u32 reset_flags)9536 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
9537 {
9538 rtnl_lock();
9539 i40e_do_reset(pf, reset_flags, true);
9540 rtnl_unlock();
9541 }
9542
9543 /**
9544 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
9545 * @pf: board private structure
9546 * @e: event info posted on ARQ
9547 *
9548 * Handler for LAN Queue Overflow Event generated by the firmware for PF
9549 * and VF queues
9550 **/
i40e_handle_lan_overflow_event(struct i40e_pf * pf,struct i40e_arq_event_info * e)9551 static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
9552 struct i40e_arq_event_info *e)
9553 {
9554 struct i40e_aqc_lan_overflow *data =
9555 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
9556 u32 queue = le32_to_cpu(data->prtdcb_rupto);
9557 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
9558 struct i40e_hw *hw = &pf->hw;
9559 struct i40e_vf *vf;
9560 u16 vf_id;
9561
9562 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
9563 queue, qtx_ctl);
9564
9565 if (FIELD_GET(I40E_QTX_CTL_PFVF_Q_MASK, qtx_ctl) !=
9566 I40E_QTX_CTL_VF_QUEUE)
9567 return;
9568
9569 /* Queue belongs to VF, find the VF and issue VF reset */
9570 vf_id = FIELD_GET(I40E_QTX_CTL_VFVM_INDX_MASK, qtx_ctl);
9571 vf_id -= hw->func_caps.vf_base_id;
9572 vf = &pf->vf[vf_id];
9573 i40e_vc_notify_vf_reset(vf);
9574 /* Allow VF to process pending reset notification */
9575 msleep(20);
9576 i40e_reset_vf(vf, false);
9577 }
9578
9579 /**
9580 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
9581 * @pf: board private structure
9582 **/
i40e_get_cur_guaranteed_fd_count(struct i40e_pf * pf)9583 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
9584 {
9585 u32 val, fcnt_prog;
9586
9587 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
9588 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
9589 return fcnt_prog;
9590 }
9591
9592 /**
9593 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
9594 * @pf: board private structure
9595 **/
i40e_get_current_fd_count(struct i40e_pf * pf)9596 u32 i40e_get_current_fd_count(struct i40e_pf *pf)
9597 {
9598 u32 val, fcnt_prog;
9599
9600 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
9601 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
9602 FIELD_GET(I40E_PFQF_FDSTAT_BEST_CNT_MASK, val);
9603 return fcnt_prog;
9604 }
9605
9606 /**
9607 * i40e_get_global_fd_count - Get total FD filters programmed on device
9608 * @pf: board private structure
9609 **/
i40e_get_global_fd_count(struct i40e_pf * pf)9610 u32 i40e_get_global_fd_count(struct i40e_pf *pf)
9611 {
9612 u32 val, fcnt_prog;
9613
9614 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
9615 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
9616 FIELD_GET(I40E_GLQF_FDCNT_0_BESTCNT_MASK, val);
9617 return fcnt_prog;
9618 }
9619
9620 /**
9621 * i40e_reenable_fdir_sb - Restore FDir SB capability
9622 * @pf: board private structure
9623 **/
i40e_reenable_fdir_sb(struct i40e_pf * pf)9624 static void i40e_reenable_fdir_sb(struct i40e_pf *pf)
9625 {
9626 if (test_and_clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
9627 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) &&
9628 (I40E_DEBUG_FD & pf->hw.debug_mask))
9629 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
9630 }
9631
9632 /**
9633 * i40e_reenable_fdir_atr - Restore FDir ATR capability
9634 * @pf: board private structure
9635 **/
i40e_reenable_fdir_atr(struct i40e_pf * pf)9636 static void i40e_reenable_fdir_atr(struct i40e_pf *pf)
9637 {
9638 if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) {
9639 /* ATR uses the same filtering logic as SB rules. It only
9640 * functions properly if the input set mask is at the default
9641 * settings. It is safe to restore the default input set
9642 * because there are no active TCPv4 filter rules.
9643 */
9644 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9645 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
9646 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
9647
9648 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) &&
9649 (I40E_DEBUG_FD & pf->hw.debug_mask))
9650 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n");
9651 }
9652 }
9653
9654 /**
9655 * i40e_delete_invalid_filter - Delete an invalid FDIR filter
9656 * @pf: board private structure
9657 * @filter: FDir filter to remove
9658 */
i40e_delete_invalid_filter(struct i40e_pf * pf,struct i40e_fdir_filter * filter)9659 static void i40e_delete_invalid_filter(struct i40e_pf *pf,
9660 struct i40e_fdir_filter *filter)
9661 {
9662 /* Update counters */
9663 pf->fdir_pf_active_filters--;
9664 pf->fd_inv = 0;
9665
9666 switch (filter->flow_type) {
9667 case TCP_V4_FLOW:
9668 pf->fd_tcp4_filter_cnt--;
9669 break;
9670 case UDP_V4_FLOW:
9671 pf->fd_udp4_filter_cnt--;
9672 break;
9673 case SCTP_V4_FLOW:
9674 pf->fd_sctp4_filter_cnt--;
9675 break;
9676 case TCP_V6_FLOW:
9677 pf->fd_tcp6_filter_cnt--;
9678 break;
9679 case UDP_V6_FLOW:
9680 pf->fd_udp6_filter_cnt--;
9681 break;
9682 case SCTP_V6_FLOW:
9683 pf->fd_udp6_filter_cnt--;
9684 break;
9685 case IP_USER_FLOW:
9686 switch (filter->ipl4_proto) {
9687 case IPPROTO_TCP:
9688 pf->fd_tcp4_filter_cnt--;
9689 break;
9690 case IPPROTO_UDP:
9691 pf->fd_udp4_filter_cnt--;
9692 break;
9693 case IPPROTO_SCTP:
9694 pf->fd_sctp4_filter_cnt--;
9695 break;
9696 case IPPROTO_IP:
9697 pf->fd_ip4_filter_cnt--;
9698 break;
9699 }
9700 break;
9701 case IPV6_USER_FLOW:
9702 switch (filter->ipl4_proto) {
9703 case IPPROTO_TCP:
9704 pf->fd_tcp6_filter_cnt--;
9705 break;
9706 case IPPROTO_UDP:
9707 pf->fd_udp6_filter_cnt--;
9708 break;
9709 case IPPROTO_SCTP:
9710 pf->fd_sctp6_filter_cnt--;
9711 break;
9712 case IPPROTO_IP:
9713 pf->fd_ip6_filter_cnt--;
9714 break;
9715 }
9716 break;
9717 }
9718
9719 /* Remove the filter from the list and free memory */
9720 hlist_del(&filter->fdir_node);
9721 kfree(filter);
9722 }
9723
9724 /**
9725 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
9726 * @pf: board private structure
9727 **/
i40e_fdir_check_and_reenable(struct i40e_pf * pf)9728 void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
9729 {
9730 struct i40e_fdir_filter *filter;
9731 u32 fcnt_prog, fcnt_avail;
9732 struct hlist_node *node;
9733
9734 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
9735 return;
9736
9737 /* Check if we have enough room to re-enable FDir SB capability. */
9738 fcnt_prog = i40e_get_global_fd_count(pf);
9739 fcnt_avail = pf->fdir_pf_filter_count;
9740 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
9741 (pf->fd_add_err == 0) ||
9742 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt))
9743 i40e_reenable_fdir_sb(pf);
9744
9745 /* We should wait for even more space before re-enabling ATR.
9746 * Additionally, we cannot enable ATR as long as we still have TCP SB
9747 * rules active.
9748 */
9749 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) &&
9750 pf->fd_tcp4_filter_cnt == 0 && pf->fd_tcp6_filter_cnt == 0)
9751 i40e_reenable_fdir_atr(pf);
9752
9753 /* if hw had a problem adding a filter, delete it */
9754 if (pf->fd_inv > 0) {
9755 hlist_for_each_entry_safe(filter, node,
9756 &pf->fdir_filter_list, fdir_node)
9757 if (filter->fd_id == pf->fd_inv)
9758 i40e_delete_invalid_filter(pf, filter);
9759 }
9760 }
9761
9762 #define I40E_MIN_FD_FLUSH_INTERVAL 10
9763 #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
9764 /**
9765 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
9766 * @pf: board private structure
9767 **/
i40e_fdir_flush_and_replay(struct i40e_pf * pf)9768 static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
9769 {
9770 unsigned long min_flush_time;
9771 int flush_wait_retry = 50;
9772 bool disable_atr = false;
9773 int fd_room;
9774 int reg;
9775
9776 if (!time_after(jiffies, pf->fd_flush_timestamp +
9777 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
9778 return;
9779
9780 /* If the flush is happening too quick and we have mostly SB rules we
9781 * should not re-enable ATR for some time.
9782 */
9783 min_flush_time = pf->fd_flush_timestamp +
9784 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
9785 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
9786
9787 if (!(time_after(jiffies, min_flush_time)) &&
9788 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
9789 if (I40E_DEBUG_FD & pf->hw.debug_mask)
9790 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
9791 disable_atr = true;
9792 }
9793
9794 pf->fd_flush_timestamp = jiffies;
9795 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
9796 /* flush all filters */
9797 wr32(&pf->hw, I40E_PFQF_CTL_1,
9798 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
9799 i40e_flush(&pf->hw);
9800 pf->fd_flush_cnt++;
9801 pf->fd_add_err = 0;
9802 do {
9803 /* Check FD flush status every 5-6msec */
9804 usleep_range(5000, 6000);
9805 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
9806 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
9807 break;
9808 } while (flush_wait_retry--);
9809 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
9810 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
9811 } else {
9812 /* replay sideband filters */
9813 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
9814 if (!disable_atr && !pf->fd_tcp4_filter_cnt)
9815 clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
9816 clear_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
9817 if (I40E_DEBUG_FD & pf->hw.debug_mask)
9818 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
9819 }
9820 }
9821
9822 /**
9823 * i40e_get_current_atr_cnt - Get the count of total FD ATR filters programmed
9824 * @pf: board private structure
9825 **/
i40e_get_current_atr_cnt(struct i40e_pf * pf)9826 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
9827 {
9828 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
9829 }
9830
9831 /**
9832 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
9833 * @pf: board private structure
9834 **/
i40e_fdir_reinit_subtask(struct i40e_pf * pf)9835 static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
9836 {
9837
9838 /* if interface is down do nothing */
9839 if (test_bit(__I40E_DOWN, pf->state))
9840 return;
9841
9842 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
9843 i40e_fdir_flush_and_replay(pf);
9844
9845 i40e_fdir_check_and_reenable(pf);
9846
9847 }
9848
9849 /**
9850 * i40e_vsi_link_event - notify VSI of a link event
9851 * @vsi: vsi to be notified
9852 * @link_up: link up or down
9853 **/
i40e_vsi_link_event(struct i40e_vsi * vsi,bool link_up)9854 static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
9855 {
9856 if (!vsi || test_bit(__I40E_VSI_DOWN, vsi->state))
9857 return;
9858
9859 switch (vsi->type) {
9860 case I40E_VSI_MAIN:
9861 if (!vsi->netdev || !vsi->netdev_registered)
9862 break;
9863
9864 if (link_up) {
9865 netif_carrier_on(vsi->netdev);
9866 netif_tx_wake_all_queues(vsi->netdev);
9867 } else {
9868 netif_carrier_off(vsi->netdev);
9869 netif_tx_stop_all_queues(vsi->netdev);
9870 }
9871 break;
9872
9873 case I40E_VSI_SRIOV:
9874 case I40E_VSI_VMDQ2:
9875 case I40E_VSI_CTRL:
9876 case I40E_VSI_IWARP:
9877 case I40E_VSI_MIRROR:
9878 default:
9879 /* there is no notification for other VSIs */
9880 break;
9881 }
9882 }
9883
9884 /**
9885 * i40e_veb_link_event - notify elements on the veb of a link event
9886 * @veb: veb to be notified
9887 * @link_up: link up or down
9888 **/
i40e_veb_link_event(struct i40e_veb * veb,bool link_up)9889 static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
9890 {
9891 struct i40e_pf *pf;
9892 int i;
9893
9894 if (!veb || !veb->pf)
9895 return;
9896 pf = veb->pf;
9897
9898 /* depth first... */
9899 for (i = 0; i < I40E_MAX_VEB; i++)
9900 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
9901 i40e_veb_link_event(pf->veb[i], link_up);
9902
9903 /* ... now the local VSIs */
9904 for (i = 0; i < pf->num_alloc_vsi; i++)
9905 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
9906 i40e_vsi_link_event(pf->vsi[i], link_up);
9907 }
9908
9909 /**
9910 * i40e_link_event - Update netif_carrier status
9911 * @pf: board private structure
9912 **/
i40e_link_event(struct i40e_pf * pf)9913 static void i40e_link_event(struct i40e_pf *pf)
9914 {
9915 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
9916 u8 new_link_speed, old_link_speed;
9917 bool new_link, old_link;
9918 int status;
9919 #ifdef CONFIG_I40E_DCB
9920 int err;
9921 #endif /* CONFIG_I40E_DCB */
9922
9923 /* set this to force the get_link_status call to refresh state */
9924 pf->hw.phy.get_link_info = true;
9925 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
9926 status = i40e_get_link_status(&pf->hw, &new_link);
9927
9928 /* On success, disable temp link polling */
9929 if (status == 0) {
9930 clear_bit(__I40E_TEMP_LINK_POLLING, pf->state);
9931 } else {
9932 /* Enable link polling temporarily until i40e_get_link_status
9933 * returns 0
9934 */
9935 set_bit(__I40E_TEMP_LINK_POLLING, pf->state);
9936 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
9937 status);
9938 return;
9939 }
9940
9941 old_link_speed = pf->hw.phy.link_info_old.link_speed;
9942 new_link_speed = pf->hw.phy.link_info.link_speed;
9943
9944 if (new_link == old_link &&
9945 new_link_speed == old_link_speed &&
9946 (test_bit(__I40E_VSI_DOWN, vsi->state) ||
9947 new_link == netif_carrier_ok(vsi->netdev)))
9948 return;
9949
9950 i40e_print_link_message(vsi, new_link);
9951
9952 /* Notify the base of the switch tree connected to
9953 * the link. Floating VEBs are not notified.
9954 */
9955 if (pf->lan_veb < I40E_MAX_VEB && pf->veb[pf->lan_veb])
9956 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
9957 else
9958 i40e_vsi_link_event(vsi, new_link);
9959
9960 if (pf->vf)
9961 i40e_vc_notify_link_state(pf);
9962
9963 if (test_bit(I40E_FLAG_PTP_ENA, pf->flags))
9964 i40e_ptp_set_increment(pf);
9965 #ifdef CONFIG_I40E_DCB
9966 if (new_link == old_link)
9967 return;
9968 /* Not SW DCB so firmware will take care of default settings */
9969 if (pf->dcbx_cap & DCB_CAP_DCBX_LLD_MANAGED)
9970 return;
9971
9972 /* We cover here only link down, as after link up in case of SW DCB
9973 * SW LLDP agent will take care of setting it up
9974 */
9975 if (!new_link) {
9976 dev_dbg(&pf->pdev->dev, "Reconfig DCB to single TC as result of Link Down\n");
9977 memset(&pf->tmp_cfg, 0, sizeof(pf->tmp_cfg));
9978 err = i40e_dcb_sw_default_config(pf);
9979 if (err) {
9980 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
9981 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
9982 } else {
9983 pf->dcbx_cap = DCB_CAP_DCBX_HOST |
9984 DCB_CAP_DCBX_VER_IEEE;
9985 set_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
9986 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
9987 }
9988 }
9989 #endif /* CONFIG_I40E_DCB */
9990 }
9991
9992 /**
9993 * i40e_watchdog_subtask - periodic checks not using event driven response
9994 * @pf: board private structure
9995 **/
i40e_watchdog_subtask(struct i40e_pf * pf)9996 static void i40e_watchdog_subtask(struct i40e_pf *pf)
9997 {
9998 int i;
9999
10000 /* if interface is down do nothing */
10001 if (test_bit(__I40E_DOWN, pf->state) ||
10002 test_bit(__I40E_CONFIG_BUSY, pf->state))
10003 return;
10004
10005 /* make sure we don't do these things too often */
10006 if (time_before(jiffies, (pf->service_timer_previous +
10007 pf->service_timer_period)))
10008 return;
10009 pf->service_timer_previous = jiffies;
10010
10011 if (test_bit(I40E_FLAG_LINK_POLLING_ENA, pf->flags) ||
10012 test_bit(__I40E_TEMP_LINK_POLLING, pf->state))
10013 i40e_link_event(pf);
10014
10015 /* Update the stats for active netdevs so the network stack
10016 * can look at updated numbers whenever it cares to
10017 */
10018 for (i = 0; i < pf->num_alloc_vsi; i++)
10019 if (pf->vsi[i] && pf->vsi[i]->netdev)
10020 i40e_update_stats(pf->vsi[i]);
10021
10022 if (test_bit(I40E_FLAG_VEB_STATS_ENA, pf->flags)) {
10023 /* Update the stats for the active switching components */
10024 for (i = 0; i < I40E_MAX_VEB; i++)
10025 if (pf->veb[i])
10026 i40e_update_veb_stats(pf->veb[i]);
10027 }
10028
10029 i40e_ptp_rx_hang(pf);
10030 i40e_ptp_tx_hang(pf);
10031 }
10032
10033 /**
10034 * i40e_reset_subtask - Set up for resetting the device and driver
10035 * @pf: board private structure
10036 **/
i40e_reset_subtask(struct i40e_pf * pf)10037 static void i40e_reset_subtask(struct i40e_pf *pf)
10038 {
10039 u32 reset_flags = 0;
10040
10041 if (test_bit(__I40E_REINIT_REQUESTED, pf->state)) {
10042 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
10043 clear_bit(__I40E_REINIT_REQUESTED, pf->state);
10044 }
10045 if (test_bit(__I40E_PF_RESET_REQUESTED, pf->state)) {
10046 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
10047 clear_bit(__I40E_PF_RESET_REQUESTED, pf->state);
10048 }
10049 if (test_bit(__I40E_CORE_RESET_REQUESTED, pf->state)) {
10050 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
10051 clear_bit(__I40E_CORE_RESET_REQUESTED, pf->state);
10052 }
10053 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state)) {
10054 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
10055 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state);
10056 }
10057 if (test_bit(__I40E_DOWN_REQUESTED, pf->state)) {
10058 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
10059 clear_bit(__I40E_DOWN_REQUESTED, pf->state);
10060 }
10061
10062 /* If there's a recovery already waiting, it takes
10063 * precedence before starting a new reset sequence.
10064 */
10065 if (test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) {
10066 i40e_prep_for_reset(pf);
10067 i40e_reset(pf);
10068 i40e_rebuild(pf, false, false);
10069 }
10070
10071 /* If we're already down or resetting, just bail */
10072 if (reset_flags &&
10073 !test_bit(__I40E_DOWN, pf->state) &&
10074 !test_bit(__I40E_CONFIG_BUSY, pf->state)) {
10075 i40e_do_reset(pf, reset_flags, false);
10076 }
10077 }
10078
10079 /**
10080 * i40e_handle_link_event - Handle link event
10081 * @pf: board private structure
10082 * @e: event info posted on ARQ
10083 **/
i40e_handle_link_event(struct i40e_pf * pf,struct i40e_arq_event_info * e)10084 static void i40e_handle_link_event(struct i40e_pf *pf,
10085 struct i40e_arq_event_info *e)
10086 {
10087 struct i40e_aqc_get_link_status *status =
10088 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
10089
10090 /* Do a new status request to re-enable LSE reporting
10091 * and load new status information into the hw struct
10092 * This completely ignores any state information
10093 * in the ARQ event info, instead choosing to always
10094 * issue the AQ update link status command.
10095 */
10096 i40e_link_event(pf);
10097
10098 /* Check if module meets thermal requirements */
10099 if (status->phy_type == I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP) {
10100 dev_err(&pf->pdev->dev,
10101 "Rx/Tx is disabled on this device because the module does not meet thermal requirements.\n");
10102 dev_err(&pf->pdev->dev,
10103 "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n");
10104 } else {
10105 /* check for unqualified module, if link is down, suppress
10106 * the message if link was forced to be down.
10107 */
10108 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
10109 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
10110 (!(status->link_info & I40E_AQ_LINK_UP)) &&
10111 (!test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, pf->flags))) {
10112 dev_err(&pf->pdev->dev,
10113 "Rx/Tx is disabled on this device because an unsupported SFP module type was detected.\n");
10114 dev_err(&pf->pdev->dev,
10115 "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n");
10116 }
10117 }
10118 }
10119
10120 /**
10121 * i40e_clean_adminq_subtask - Clean the AdminQ rings
10122 * @pf: board private structure
10123 **/
i40e_clean_adminq_subtask(struct i40e_pf * pf)10124 static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
10125 {
10126 struct i40e_arq_event_info event;
10127 struct i40e_hw *hw = &pf->hw;
10128 u16 pending, i = 0;
10129 u16 opcode;
10130 u32 oldval;
10131 int ret;
10132 u32 val;
10133
10134 /* Do not run clean AQ when PF reset fails */
10135 if (test_bit(__I40E_RESET_FAILED, pf->state))
10136 return;
10137
10138 /* check for error indications */
10139 val = rd32(&pf->hw, I40E_PF_ARQLEN);
10140 oldval = val;
10141 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
10142 if (hw->debug_mask & I40E_DEBUG_AQ)
10143 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
10144 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
10145 }
10146 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
10147 if (hw->debug_mask & I40E_DEBUG_AQ)
10148 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
10149 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
10150 pf->arq_overflows++;
10151 }
10152 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
10153 if (hw->debug_mask & I40E_DEBUG_AQ)
10154 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
10155 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
10156 }
10157 if (oldval != val)
10158 wr32(&pf->hw, I40E_PF_ARQLEN, val);
10159
10160 val = rd32(&pf->hw, I40E_PF_ATQLEN);
10161 oldval = val;
10162 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
10163 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
10164 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
10165 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
10166 }
10167 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
10168 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
10169 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
10170 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
10171 }
10172 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
10173 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
10174 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
10175 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
10176 }
10177 if (oldval != val)
10178 wr32(&pf->hw, I40E_PF_ATQLEN, val);
10179
10180 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
10181 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
10182 if (!event.msg_buf)
10183 return;
10184
10185 do {
10186 ret = i40e_clean_arq_element(hw, &event, &pending);
10187 if (ret == -EALREADY)
10188 break;
10189 else if (ret) {
10190 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
10191 break;
10192 }
10193
10194 opcode = le16_to_cpu(event.desc.opcode);
10195 switch (opcode) {
10196
10197 case i40e_aqc_opc_get_link_status:
10198 rtnl_lock();
10199 i40e_handle_link_event(pf, &event);
10200 rtnl_unlock();
10201 break;
10202 case i40e_aqc_opc_send_msg_to_pf:
10203 ret = i40e_vc_process_vf_msg(pf,
10204 le16_to_cpu(event.desc.retval),
10205 le32_to_cpu(event.desc.cookie_high),
10206 le32_to_cpu(event.desc.cookie_low),
10207 event.msg_buf,
10208 event.msg_len);
10209 break;
10210 case i40e_aqc_opc_lldp_update_mib:
10211 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
10212 #ifdef CONFIG_I40E_DCB
10213 rtnl_lock();
10214 i40e_handle_lldp_event(pf, &event);
10215 rtnl_unlock();
10216 #endif /* CONFIG_I40E_DCB */
10217 break;
10218 case i40e_aqc_opc_event_lan_overflow:
10219 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
10220 i40e_handle_lan_overflow_event(pf, &event);
10221 break;
10222 case i40e_aqc_opc_send_msg_to_peer:
10223 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
10224 break;
10225 case i40e_aqc_opc_nvm_erase:
10226 case i40e_aqc_opc_nvm_update:
10227 case i40e_aqc_opc_oem_post_update:
10228 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
10229 "ARQ NVM operation 0x%04x completed\n",
10230 opcode);
10231 break;
10232 default:
10233 dev_info(&pf->pdev->dev,
10234 "ARQ: Unknown event 0x%04x ignored\n",
10235 opcode);
10236 break;
10237 }
10238 } while (i++ < I40E_AQ_WORK_LIMIT);
10239
10240 if (i < I40E_AQ_WORK_LIMIT)
10241 clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state);
10242
10243 /* re-enable Admin queue interrupt cause */
10244 val = rd32(hw, I40E_PFINT_ICR0_ENA);
10245 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
10246 wr32(hw, I40E_PFINT_ICR0_ENA, val);
10247 i40e_flush(hw);
10248
10249 kfree(event.msg_buf);
10250 }
10251
10252 /**
10253 * i40e_verify_eeprom - make sure eeprom is good to use
10254 * @pf: board private structure
10255 **/
i40e_verify_eeprom(struct i40e_pf * pf)10256 static void i40e_verify_eeprom(struct i40e_pf *pf)
10257 {
10258 int err;
10259
10260 err = i40e_diag_eeprom_test(&pf->hw);
10261 if (err) {
10262 /* retry in case of garbage read */
10263 err = i40e_diag_eeprom_test(&pf->hw);
10264 if (err) {
10265 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
10266 err);
10267 set_bit(__I40E_BAD_EEPROM, pf->state);
10268 }
10269 }
10270
10271 if (!err && test_bit(__I40E_BAD_EEPROM, pf->state)) {
10272 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
10273 clear_bit(__I40E_BAD_EEPROM, pf->state);
10274 }
10275 }
10276
10277 /**
10278 * i40e_enable_pf_switch_lb
10279 * @pf: pointer to the PF structure
10280 *
10281 * enable switch loop back or die - no point in a return value
10282 **/
i40e_enable_pf_switch_lb(struct i40e_pf * pf)10283 static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
10284 {
10285 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
10286 struct i40e_vsi_context ctxt;
10287 int ret;
10288
10289 ctxt.seid = pf->main_vsi_seid;
10290 ctxt.pf_num = pf->hw.pf_id;
10291 ctxt.vf_num = 0;
10292 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
10293 if (ret) {
10294 dev_info(&pf->pdev->dev,
10295 "couldn't get PF vsi config, err %pe aq_err %s\n",
10296 ERR_PTR(ret),
10297 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10298 return;
10299 }
10300 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
10301 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10302 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
10303
10304 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
10305 if (ret) {
10306 dev_info(&pf->pdev->dev,
10307 "update vsi switch failed, err %pe aq_err %s\n",
10308 ERR_PTR(ret),
10309 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10310 }
10311 }
10312
10313 /**
10314 * i40e_disable_pf_switch_lb
10315 * @pf: pointer to the PF structure
10316 *
10317 * disable switch loop back or die - no point in a return value
10318 **/
i40e_disable_pf_switch_lb(struct i40e_pf * pf)10319 static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
10320 {
10321 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
10322 struct i40e_vsi_context ctxt;
10323 int ret;
10324
10325 ctxt.seid = pf->main_vsi_seid;
10326 ctxt.pf_num = pf->hw.pf_id;
10327 ctxt.vf_num = 0;
10328 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
10329 if (ret) {
10330 dev_info(&pf->pdev->dev,
10331 "couldn't get PF vsi config, err %pe aq_err %s\n",
10332 ERR_PTR(ret),
10333 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10334 return;
10335 }
10336 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
10337 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10338 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
10339
10340 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
10341 if (ret) {
10342 dev_info(&pf->pdev->dev,
10343 "update vsi switch failed, err %pe aq_err %s\n",
10344 ERR_PTR(ret),
10345 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10346 }
10347 }
10348
10349 /**
10350 * i40e_config_bridge_mode - Configure the HW bridge mode
10351 * @veb: pointer to the bridge instance
10352 *
10353 * Configure the loop back mode for the LAN VSI that is downlink to the
10354 * specified HW bridge instance. It is expected this function is called
10355 * when a new HW bridge is instantiated.
10356 **/
i40e_config_bridge_mode(struct i40e_veb * veb)10357 static void i40e_config_bridge_mode(struct i40e_veb *veb)
10358 {
10359 struct i40e_pf *pf = veb->pf;
10360
10361 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
10362 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
10363 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
10364 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
10365 i40e_disable_pf_switch_lb(pf);
10366 else
10367 i40e_enable_pf_switch_lb(pf);
10368 }
10369
10370 /**
10371 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
10372 * @veb: pointer to the VEB instance
10373 *
10374 * This is a recursive function that first builds the attached VSIs then
10375 * recurses in to build the next layer of VEB. We track the connections
10376 * through our own index numbers because the seid's from the HW could
10377 * change across the reset.
10378 **/
i40e_reconstitute_veb(struct i40e_veb * veb)10379 static int i40e_reconstitute_veb(struct i40e_veb *veb)
10380 {
10381 struct i40e_vsi *ctl_vsi = NULL;
10382 struct i40e_pf *pf = veb->pf;
10383 int v, veb_idx;
10384 int ret;
10385
10386 /* build VSI that owns this VEB, temporarily attached to base VEB */
10387 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
10388 if (pf->vsi[v] &&
10389 pf->vsi[v]->veb_idx == veb->idx &&
10390 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
10391 ctl_vsi = pf->vsi[v];
10392 break;
10393 }
10394 }
10395 if (!ctl_vsi) {
10396 dev_info(&pf->pdev->dev,
10397 "missing owner VSI for veb_idx %d\n", veb->idx);
10398 ret = -ENOENT;
10399 goto end_reconstitute;
10400 }
10401 if (ctl_vsi != pf->vsi[pf->lan_vsi])
10402 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10403 ret = i40e_add_vsi(ctl_vsi);
10404 if (ret) {
10405 dev_info(&pf->pdev->dev,
10406 "rebuild of veb_idx %d owner VSI failed: %d\n",
10407 veb->idx, ret);
10408 goto end_reconstitute;
10409 }
10410 i40e_vsi_reset_stats(ctl_vsi);
10411
10412 /* create the VEB in the switch and move the VSI onto the VEB */
10413 ret = i40e_add_veb(veb, ctl_vsi);
10414 if (ret)
10415 goto end_reconstitute;
10416
10417 if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags))
10418 veb->bridge_mode = BRIDGE_MODE_VEB;
10419 else
10420 veb->bridge_mode = BRIDGE_MODE_VEPA;
10421 i40e_config_bridge_mode(veb);
10422
10423 /* create the remaining VSIs attached to this VEB */
10424 for (v = 0; v < pf->num_alloc_vsi; v++) {
10425 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
10426 continue;
10427
10428 if (pf->vsi[v]->veb_idx == veb->idx) {
10429 struct i40e_vsi *vsi = pf->vsi[v];
10430
10431 vsi->uplink_seid = veb->seid;
10432 ret = i40e_add_vsi(vsi);
10433 if (ret) {
10434 dev_info(&pf->pdev->dev,
10435 "rebuild of vsi_idx %d failed: %d\n",
10436 v, ret);
10437 goto end_reconstitute;
10438 }
10439 i40e_vsi_reset_stats(vsi);
10440 }
10441 }
10442
10443 /* create any VEBs attached to this VEB - RECURSION */
10444 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10445 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
10446 pf->veb[veb_idx]->uplink_seid = veb->seid;
10447 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
10448 if (ret)
10449 break;
10450 }
10451 }
10452
10453 end_reconstitute:
10454 return ret;
10455 }
10456
10457 /**
10458 * i40e_get_capabilities - get info about the HW
10459 * @pf: the PF struct
10460 * @list_type: AQ capability to be queried
10461 **/
i40e_get_capabilities(struct i40e_pf * pf,enum i40e_admin_queue_opc list_type)10462 static int i40e_get_capabilities(struct i40e_pf *pf,
10463 enum i40e_admin_queue_opc list_type)
10464 {
10465 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
10466 u16 data_size;
10467 int buf_len;
10468 int err;
10469
10470 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
10471 do {
10472 cap_buf = kzalloc(buf_len, GFP_KERNEL);
10473 if (!cap_buf)
10474 return -ENOMEM;
10475
10476 /* this loads the data into the hw struct for us */
10477 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
10478 &data_size, list_type,
10479 NULL);
10480 /* data loaded, buffer no longer needed */
10481 kfree(cap_buf);
10482
10483 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
10484 /* retry with a larger buffer */
10485 buf_len = data_size;
10486 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK || err) {
10487 dev_info(&pf->pdev->dev,
10488 "capability discovery failed, err %pe aq_err %s\n",
10489 ERR_PTR(err),
10490 i40e_aq_str(&pf->hw,
10491 pf->hw.aq.asq_last_status));
10492 return -ENODEV;
10493 }
10494 } while (err);
10495
10496 if (pf->hw.debug_mask & I40E_DEBUG_USER) {
10497 if (list_type == i40e_aqc_opc_list_func_capabilities) {
10498 dev_info(&pf->pdev->dev,
10499 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
10500 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
10501 pf->hw.func_caps.num_msix_vectors,
10502 pf->hw.func_caps.num_msix_vectors_vf,
10503 pf->hw.func_caps.fd_filters_guaranteed,
10504 pf->hw.func_caps.fd_filters_best_effort,
10505 pf->hw.func_caps.num_tx_qp,
10506 pf->hw.func_caps.num_vsis);
10507 } else if (list_type == i40e_aqc_opc_list_dev_capabilities) {
10508 dev_info(&pf->pdev->dev,
10509 "switch_mode=0x%04x, function_valid=0x%08x\n",
10510 pf->hw.dev_caps.switch_mode,
10511 pf->hw.dev_caps.valid_functions);
10512 dev_info(&pf->pdev->dev,
10513 "SR-IOV=%d, num_vfs for all function=%u\n",
10514 pf->hw.dev_caps.sr_iov_1_1,
10515 pf->hw.dev_caps.num_vfs);
10516 dev_info(&pf->pdev->dev,
10517 "num_vsis=%u, num_rx:%u, num_tx=%u\n",
10518 pf->hw.dev_caps.num_vsis,
10519 pf->hw.dev_caps.num_rx_qp,
10520 pf->hw.dev_caps.num_tx_qp);
10521 }
10522 }
10523 if (list_type == i40e_aqc_opc_list_func_capabilities) {
10524 #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
10525 + pf->hw.func_caps.num_vfs)
10526 if (pf->hw.revision_id == 0 &&
10527 pf->hw.func_caps.num_vsis < DEF_NUM_VSI) {
10528 dev_info(&pf->pdev->dev,
10529 "got num_vsis %d, setting num_vsis to %d\n",
10530 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
10531 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
10532 }
10533 }
10534 return 0;
10535 }
10536
10537 static int i40e_vsi_clear(struct i40e_vsi *vsi);
10538
10539 /**
10540 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
10541 * @pf: board private structure
10542 **/
i40e_fdir_sb_setup(struct i40e_pf * pf)10543 static void i40e_fdir_sb_setup(struct i40e_pf *pf)
10544 {
10545 struct i40e_vsi *vsi;
10546
10547 /* quick workaround for an NVM issue that leaves a critical register
10548 * uninitialized
10549 */
10550 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
10551 static const u32 hkey[] = {
10552 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
10553 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
10554 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
10555 0x95b3a76d};
10556 int i;
10557
10558 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
10559 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
10560 }
10561
10562 if (!test_bit(I40E_FLAG_FD_SB_ENA, pf->flags))
10563 return;
10564
10565 /* find existing VSI and see if it needs configuring */
10566 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
10567
10568 /* create a new VSI if none exists */
10569 if (!vsi) {
10570 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
10571 pf->vsi[pf->lan_vsi]->seid, 0);
10572 if (!vsi) {
10573 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
10574 clear_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
10575 set_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
10576 return;
10577 }
10578 }
10579
10580 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
10581 }
10582
10583 /**
10584 * i40e_fdir_teardown - release the Flow Director resources
10585 * @pf: board private structure
10586 **/
i40e_fdir_teardown(struct i40e_pf * pf)10587 static void i40e_fdir_teardown(struct i40e_pf *pf)
10588 {
10589 struct i40e_vsi *vsi;
10590
10591 i40e_fdir_filter_exit(pf);
10592 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
10593 if (vsi)
10594 i40e_vsi_release(vsi);
10595 }
10596
10597 /**
10598 * i40e_rebuild_cloud_filters - Rebuilds cloud filters for VSIs
10599 * @vsi: PF main vsi
10600 * @seid: seid of main or channel VSIs
10601 *
10602 * Rebuilds cloud filters associated with main VSI and channel VSIs if they
10603 * existed before reset
10604 **/
i40e_rebuild_cloud_filters(struct i40e_vsi * vsi,u16 seid)10605 static int i40e_rebuild_cloud_filters(struct i40e_vsi *vsi, u16 seid)
10606 {
10607 struct i40e_cloud_filter *cfilter;
10608 struct i40e_pf *pf = vsi->back;
10609 struct hlist_node *node;
10610 int ret;
10611
10612 /* Add cloud filters back if they exist */
10613 hlist_for_each_entry_safe(cfilter, node, &pf->cloud_filter_list,
10614 cloud_node) {
10615 if (cfilter->seid != seid)
10616 continue;
10617
10618 if (cfilter->dst_port)
10619 ret = i40e_add_del_cloud_filter_big_buf(vsi, cfilter,
10620 true);
10621 else
10622 ret = i40e_add_del_cloud_filter(vsi, cfilter, true);
10623
10624 if (ret) {
10625 dev_dbg(&pf->pdev->dev,
10626 "Failed to rebuild cloud filter, err %pe aq_err %s\n",
10627 ERR_PTR(ret),
10628 i40e_aq_str(&pf->hw,
10629 pf->hw.aq.asq_last_status));
10630 return ret;
10631 }
10632 }
10633 return 0;
10634 }
10635
10636 /**
10637 * i40e_rebuild_channels - Rebuilds channel VSIs if they existed before reset
10638 * @vsi: PF main vsi
10639 *
10640 * Rebuilds channel VSIs if they existed before reset
10641 **/
i40e_rebuild_channels(struct i40e_vsi * vsi)10642 static int i40e_rebuild_channels(struct i40e_vsi *vsi)
10643 {
10644 struct i40e_channel *ch, *ch_tmp;
10645 int ret;
10646
10647 if (list_empty(&vsi->ch_list))
10648 return 0;
10649
10650 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) {
10651 if (!ch->initialized)
10652 break;
10653 /* Proceed with creation of channel (VMDq2) VSI */
10654 ret = i40e_add_channel(vsi->back, vsi->uplink_seid, ch);
10655 if (ret) {
10656 dev_info(&vsi->back->pdev->dev,
10657 "failed to rebuild channels using uplink_seid %u\n",
10658 vsi->uplink_seid);
10659 return ret;
10660 }
10661 /* Reconfigure TX queues using QTX_CTL register */
10662 ret = i40e_channel_config_tx_ring(vsi->back, vsi, ch);
10663 if (ret) {
10664 dev_info(&vsi->back->pdev->dev,
10665 "failed to configure TX rings for channel %u\n",
10666 ch->seid);
10667 return ret;
10668 }
10669 /* update 'next_base_queue' */
10670 vsi->next_base_queue = vsi->next_base_queue +
10671 ch->num_queue_pairs;
10672 if (ch->max_tx_rate) {
10673 u64 credits = ch->max_tx_rate;
10674
10675 if (i40e_set_bw_limit(vsi, ch->seid,
10676 ch->max_tx_rate))
10677 return -EINVAL;
10678
10679 do_div(credits, I40E_BW_CREDIT_DIVISOR);
10680 dev_dbg(&vsi->back->pdev->dev,
10681 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
10682 ch->max_tx_rate,
10683 credits,
10684 ch->seid);
10685 }
10686 ret = i40e_rebuild_cloud_filters(vsi, ch->seid);
10687 if (ret) {
10688 dev_dbg(&vsi->back->pdev->dev,
10689 "Failed to rebuild cloud filters for channel VSI %u\n",
10690 ch->seid);
10691 return ret;
10692 }
10693 }
10694 return 0;
10695 }
10696
10697 /**
10698 * i40e_clean_xps_state - clean xps state for every tx_ring
10699 * @vsi: ptr to the VSI
10700 **/
i40e_clean_xps_state(struct i40e_vsi * vsi)10701 static void i40e_clean_xps_state(struct i40e_vsi *vsi)
10702 {
10703 int i;
10704
10705 if (vsi->tx_rings)
10706 for (i = 0; i < vsi->num_queue_pairs; i++)
10707 if (vsi->tx_rings[i])
10708 clear_bit(__I40E_TX_XPS_INIT_DONE,
10709 vsi->tx_rings[i]->state);
10710 }
10711
10712 /**
10713 * i40e_prep_for_reset - prep for the core to reset
10714 * @pf: board private structure
10715 *
10716 * Close up the VFs and other things in prep for PF Reset.
10717 **/
i40e_prep_for_reset(struct i40e_pf * pf)10718 static void i40e_prep_for_reset(struct i40e_pf *pf)
10719 {
10720 struct i40e_hw *hw = &pf->hw;
10721 int ret = 0;
10722 u32 v;
10723
10724 clear_bit(__I40E_RESET_INTR_RECEIVED, pf->state);
10725 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
10726 return;
10727 if (i40e_check_asq_alive(&pf->hw))
10728 i40e_vc_notify_reset(pf);
10729
10730 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
10731
10732 /* quiesce the VSIs and their queues that are not already DOWN */
10733 i40e_pf_quiesce_all_vsi(pf);
10734
10735 for (v = 0; v < pf->num_alloc_vsi; v++) {
10736 if (pf->vsi[v]) {
10737 i40e_clean_xps_state(pf->vsi[v]);
10738 pf->vsi[v]->seid = 0;
10739 }
10740 }
10741
10742 i40e_shutdown_adminq(&pf->hw);
10743
10744 /* call shutdown HMC */
10745 if (hw->hmc.hmc_obj) {
10746 ret = i40e_shutdown_lan_hmc(hw);
10747 if (ret)
10748 dev_warn(&pf->pdev->dev,
10749 "shutdown_lan_hmc failed: %d\n", ret);
10750 }
10751
10752 /* Save the current PTP time so that we can restore the time after the
10753 * reset completes.
10754 */
10755 i40e_ptp_save_hw_time(pf);
10756 }
10757
10758 /**
10759 * i40e_send_version - update firmware with driver version
10760 * @pf: PF struct
10761 */
i40e_send_version(struct i40e_pf * pf)10762 static void i40e_send_version(struct i40e_pf *pf)
10763 {
10764 struct i40e_driver_version dv;
10765
10766 dv.major_version = 0xff;
10767 dv.minor_version = 0xff;
10768 dv.build_version = 0xff;
10769 dv.subbuild_version = 0;
10770 strscpy(dv.driver_string, UTS_RELEASE, sizeof(dv.driver_string));
10771 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
10772 }
10773
10774 /**
10775 * i40e_get_oem_version - get OEM specific version information
10776 * @hw: pointer to the hardware structure
10777 **/
i40e_get_oem_version(struct i40e_hw * hw)10778 static void i40e_get_oem_version(struct i40e_hw *hw)
10779 {
10780 u16 block_offset = 0xffff;
10781 u16 block_length = 0;
10782 u16 capabilities = 0;
10783 u16 gen_snap = 0;
10784 u16 release = 0;
10785
10786 #define I40E_SR_NVM_OEM_VERSION_PTR 0x1B
10787 #define I40E_NVM_OEM_LENGTH_OFFSET 0x00
10788 #define I40E_NVM_OEM_CAPABILITIES_OFFSET 0x01
10789 #define I40E_NVM_OEM_GEN_OFFSET 0x02
10790 #define I40E_NVM_OEM_RELEASE_OFFSET 0x03
10791 #define I40E_NVM_OEM_CAPABILITIES_MASK 0x000F
10792 #define I40E_NVM_OEM_LENGTH 3
10793
10794 /* Check if pointer to OEM version block is valid. */
10795 i40e_read_nvm_word(hw, I40E_SR_NVM_OEM_VERSION_PTR, &block_offset);
10796 if (block_offset == 0xffff)
10797 return;
10798
10799 /* Check if OEM version block has correct length. */
10800 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_LENGTH_OFFSET,
10801 &block_length);
10802 if (block_length < I40E_NVM_OEM_LENGTH)
10803 return;
10804
10805 /* Check if OEM version format is as expected. */
10806 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_CAPABILITIES_OFFSET,
10807 &capabilities);
10808 if ((capabilities & I40E_NVM_OEM_CAPABILITIES_MASK) != 0)
10809 return;
10810
10811 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_GEN_OFFSET,
10812 &gen_snap);
10813 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_RELEASE_OFFSET,
10814 &release);
10815 hw->nvm.oem_ver =
10816 FIELD_PREP(I40E_OEM_GEN_MASK | I40E_OEM_SNAP_MASK, gen_snap) |
10817 FIELD_PREP(I40E_OEM_RELEASE_MASK, release);
10818 hw->nvm.eetrack = I40E_OEM_EETRACK_ID;
10819 }
10820
10821 /**
10822 * i40e_reset - wait for core reset to finish reset, reset pf if corer not seen
10823 * @pf: board private structure
10824 **/
i40e_reset(struct i40e_pf * pf)10825 static int i40e_reset(struct i40e_pf *pf)
10826 {
10827 struct i40e_hw *hw = &pf->hw;
10828 int ret;
10829
10830 ret = i40e_pf_reset(hw);
10831 if (ret) {
10832 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
10833 set_bit(__I40E_RESET_FAILED, pf->state);
10834 clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state);
10835 } else {
10836 pf->pfr_count++;
10837 }
10838 return ret;
10839 }
10840
10841 /**
10842 * i40e_rebuild - rebuild using a saved config
10843 * @pf: board private structure
10844 * @reinit: if the Main VSI needs to re-initialized.
10845 * @lock_acquired: indicates whether or not the lock has been acquired
10846 * before this function was called.
10847 **/
i40e_rebuild(struct i40e_pf * pf,bool reinit,bool lock_acquired)10848 static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)
10849 {
10850 const bool is_recovery_mode_reported = i40e_check_recovery_mode(pf);
10851 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
10852 struct i40e_hw *hw = &pf->hw;
10853 int ret;
10854 u32 val;
10855 int v;
10856
10857 if (test_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state) &&
10858 is_recovery_mode_reported)
10859 i40e_set_ethtool_ops(pf->vsi[pf->lan_vsi]->netdev);
10860
10861 if (test_bit(__I40E_DOWN, pf->state) &&
10862 !test_bit(__I40E_RECOVERY_MODE, pf->state))
10863 goto clear_recovery;
10864 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
10865
10866 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
10867 ret = i40e_init_adminq(&pf->hw);
10868 if (ret) {
10869 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %pe aq_err %s\n",
10870 ERR_PTR(ret),
10871 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10872 goto clear_recovery;
10873 }
10874 i40e_get_oem_version(&pf->hw);
10875
10876 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state)) {
10877 /* The following delay is necessary for firmware update. */
10878 mdelay(1000);
10879 }
10880
10881 /* re-verify the eeprom if we just had an EMP reset */
10882 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state))
10883 i40e_verify_eeprom(pf);
10884
10885 /* if we are going out of or into recovery mode we have to act
10886 * accordingly with regard to resources initialization
10887 * and deinitialization
10888 */
10889 if (test_bit(__I40E_RECOVERY_MODE, pf->state)) {
10890 if (i40e_get_capabilities(pf,
10891 i40e_aqc_opc_list_func_capabilities))
10892 goto end_unlock;
10893
10894 if (is_recovery_mode_reported) {
10895 /* we're staying in recovery mode so we'll reinitialize
10896 * misc vector here
10897 */
10898 if (i40e_setup_misc_vector_for_recovery_mode(pf))
10899 goto end_unlock;
10900 } else {
10901 if (!lock_acquired)
10902 rtnl_lock();
10903 /* we're going out of recovery mode so we'll free
10904 * the IRQ allocated specifically for recovery mode
10905 * and restore the interrupt scheme
10906 */
10907 free_irq(pf->pdev->irq, pf);
10908 i40e_clear_interrupt_scheme(pf);
10909 if (i40e_restore_interrupt_scheme(pf))
10910 goto end_unlock;
10911 }
10912
10913 /* tell the firmware that we're starting */
10914 i40e_send_version(pf);
10915
10916 /* bail out in case recovery mode was detected, as there is
10917 * no need for further configuration.
10918 */
10919 goto end_unlock;
10920 }
10921
10922 i40e_clear_pxe_mode(hw);
10923 ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities);
10924 if (ret)
10925 goto end_core_reset;
10926
10927 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10928 hw->func_caps.num_rx_qp, 0, 0);
10929 if (ret) {
10930 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
10931 goto end_core_reset;
10932 }
10933 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10934 if (ret) {
10935 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
10936 goto end_core_reset;
10937 }
10938
10939 #ifdef CONFIG_I40E_DCB
10940 /* Enable FW to write a default DCB config on link-up
10941 * unless I40E_FLAG_TC_MQPRIO was enabled or DCB
10942 * is not supported with new link speed
10943 */
10944 if (i40e_is_tc_mqprio_enabled(pf)) {
10945 i40e_aq_set_dcb_parameters(hw, false, NULL);
10946 } else {
10947 if (I40E_IS_X710TL_DEVICE(hw->device_id) &&
10948 (hw->phy.link_info.link_speed &
10949 (I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB))) {
10950 i40e_aq_set_dcb_parameters(hw, false, NULL);
10951 dev_warn(&pf->pdev->dev,
10952 "DCB is not supported for X710-T*L 2.5/5G speeds\n");
10953 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
10954 } else {
10955 i40e_aq_set_dcb_parameters(hw, true, NULL);
10956 ret = i40e_init_pf_dcb(pf);
10957 if (ret) {
10958 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n",
10959 ret);
10960 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
10961 /* Continue without DCB enabled */
10962 }
10963 }
10964 }
10965
10966 #endif /* CONFIG_I40E_DCB */
10967 if (!lock_acquired)
10968 rtnl_lock();
10969 ret = i40e_setup_pf_switch(pf, reinit, true);
10970 if (ret)
10971 goto end_unlock;
10972
10973 /* The driver only wants link up/down and module qualification
10974 * reports from firmware. Note the negative logic.
10975 */
10976 ret = i40e_aq_set_phy_int_mask(&pf->hw,
10977 ~(I40E_AQ_EVENT_LINK_UPDOWN |
10978 I40E_AQ_EVENT_MEDIA_NA |
10979 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
10980 if (ret)
10981 dev_info(&pf->pdev->dev, "set phy mask fail, err %pe aq_err %s\n",
10982 ERR_PTR(ret),
10983 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10984
10985 /* Rebuild the VSIs and VEBs that existed before reset.
10986 * They are still in our local switch element arrays, so only
10987 * need to rebuild the switch model in the HW.
10988 *
10989 * If there were VEBs but the reconstitution failed, we'll try
10990 * to recover minimal use by getting the basic PF VSI working.
10991 */
10992 if (vsi->uplink_seid != pf->mac_seid) {
10993 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
10994 /* find the one VEB connected to the MAC, and find orphans */
10995 for (v = 0; v < I40E_MAX_VEB; v++) {
10996 if (!pf->veb[v])
10997 continue;
10998
10999 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
11000 pf->veb[v]->uplink_seid == 0) {
11001 ret = i40e_reconstitute_veb(pf->veb[v]);
11002
11003 if (!ret)
11004 continue;
11005
11006 /* If Main VEB failed, we're in deep doodoo,
11007 * so give up rebuilding the switch and set up
11008 * for minimal rebuild of PF VSI.
11009 * If orphan failed, we'll report the error
11010 * but try to keep going.
11011 */
11012 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
11013 dev_info(&pf->pdev->dev,
11014 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
11015 ret);
11016 vsi->uplink_seid = pf->mac_seid;
11017 break;
11018 } else if (pf->veb[v]->uplink_seid == 0) {
11019 dev_info(&pf->pdev->dev,
11020 "rebuild of orphan VEB failed: %d\n",
11021 ret);
11022 }
11023 }
11024 }
11025 }
11026
11027 if (vsi->uplink_seid == pf->mac_seid) {
11028 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
11029 /* no VEB, so rebuild only the Main VSI */
11030 ret = i40e_add_vsi(vsi);
11031 if (ret) {
11032 dev_info(&pf->pdev->dev,
11033 "rebuild of Main VSI failed: %d\n", ret);
11034 goto end_unlock;
11035 }
11036 }
11037
11038 if (vsi->mqprio_qopt.max_rate[0]) {
11039 u64 max_tx_rate = i40e_bw_bytes_to_mbits(vsi,
11040 vsi->mqprio_qopt.max_rate[0]);
11041 u64 credits = 0;
11042
11043 ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate);
11044 if (ret)
11045 goto end_unlock;
11046
11047 credits = max_tx_rate;
11048 do_div(credits, I40E_BW_CREDIT_DIVISOR);
11049 dev_dbg(&vsi->back->pdev->dev,
11050 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
11051 max_tx_rate,
11052 credits,
11053 vsi->seid);
11054 }
11055
11056 ret = i40e_rebuild_cloud_filters(vsi, vsi->seid);
11057 if (ret)
11058 goto end_unlock;
11059
11060 /* PF Main VSI is rebuild by now, go ahead and rebuild channel VSIs
11061 * for this main VSI if they exist
11062 */
11063 ret = i40e_rebuild_channels(vsi);
11064 if (ret)
11065 goto end_unlock;
11066
11067 /* Reconfigure hardware for allowing smaller MSS in the case
11068 * of TSO, so that we avoid the MDD being fired and causing
11069 * a reset in the case of small MSS+TSO.
11070 */
11071 #define I40E_REG_MSS 0x000E64DC
11072 #define I40E_REG_MSS_MIN_MASK 0x3FF0000
11073 #define I40E_64BYTE_MSS 0x400000
11074 val = rd32(hw, I40E_REG_MSS);
11075 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
11076 val &= ~I40E_REG_MSS_MIN_MASK;
11077 val |= I40E_64BYTE_MSS;
11078 wr32(hw, I40E_REG_MSS, val);
11079 }
11080
11081 if (test_bit(I40E_HW_CAP_RESTART_AUTONEG, pf->hw.caps)) {
11082 msleep(75);
11083 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
11084 if (ret)
11085 dev_info(&pf->pdev->dev, "link restart failed, err %pe aq_err %s\n",
11086 ERR_PTR(ret),
11087 i40e_aq_str(&pf->hw,
11088 pf->hw.aq.asq_last_status));
11089 }
11090 /* reinit the misc interrupt */
11091 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
11092 ret = i40e_setup_misc_vector(pf);
11093 if (ret)
11094 goto end_unlock;
11095 }
11096
11097 /* Add a filter to drop all Flow control frames from any VSI from being
11098 * transmitted. By doing so we stop a malicious VF from sending out
11099 * PAUSE or PFC frames and potentially controlling traffic for other
11100 * PF/VF VSIs.
11101 * The FW can still send Flow control frames if enabled.
11102 */
11103 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11104 pf->main_vsi_seid);
11105
11106 /* restart the VSIs that were rebuilt and running before the reset */
11107 i40e_pf_unquiesce_all_vsi(pf);
11108
11109 /* Release the RTNL lock before we start resetting VFs */
11110 if (!lock_acquired)
11111 rtnl_unlock();
11112
11113 /* Restore promiscuous settings */
11114 ret = i40e_set_promiscuous(pf, pf->cur_promisc);
11115 if (ret)
11116 dev_warn(&pf->pdev->dev,
11117 "Failed to restore promiscuous setting: %s, err %pe aq_err %s\n",
11118 pf->cur_promisc ? "on" : "off",
11119 ERR_PTR(ret),
11120 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11121
11122 i40e_reset_all_vfs(pf, true);
11123
11124 /* tell the firmware that we're starting */
11125 i40e_send_version(pf);
11126
11127 /* We've already released the lock, so don't do it again */
11128 goto end_core_reset;
11129
11130 end_unlock:
11131 if (!lock_acquired)
11132 rtnl_unlock();
11133 end_core_reset:
11134 clear_bit(__I40E_RESET_FAILED, pf->state);
11135 clear_recovery:
11136 clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state);
11137 clear_bit(__I40E_TIMEOUT_RECOVERY_PENDING, pf->state);
11138 }
11139
11140 /**
11141 * i40e_reset_and_rebuild - reset and rebuild using a saved config
11142 * @pf: board private structure
11143 * @reinit: if the Main VSI needs to re-initialized.
11144 * @lock_acquired: indicates whether or not the lock has been acquired
11145 * before this function was called.
11146 **/
i40e_reset_and_rebuild(struct i40e_pf * pf,bool reinit,bool lock_acquired)11147 static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit,
11148 bool lock_acquired)
11149 {
11150 int ret;
11151
11152 if (test_bit(__I40E_IN_REMOVE, pf->state))
11153 return;
11154 /* Now we wait for GRST to settle out.
11155 * We don't have to delete the VEBs or VSIs from the hw switch
11156 * because the reset will make them disappear.
11157 */
11158 ret = i40e_reset(pf);
11159 if (!ret)
11160 i40e_rebuild(pf, reinit, lock_acquired);
11161 }
11162
11163 /**
11164 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
11165 * @pf: board private structure
11166 *
11167 * Close up the VFs and other things in prep for a Core Reset,
11168 * then get ready to rebuild the world.
11169 * @lock_acquired: indicates whether or not the lock has been acquired
11170 * before this function was called.
11171 **/
i40e_handle_reset_warning(struct i40e_pf * pf,bool lock_acquired)11172 static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired)
11173 {
11174 i40e_prep_for_reset(pf);
11175 i40e_reset_and_rebuild(pf, false, lock_acquired);
11176 }
11177
11178 /**
11179 * i40e_handle_mdd_event
11180 * @pf: pointer to the PF structure
11181 *
11182 * Called from the MDD irq handler to identify possibly malicious vfs
11183 **/
i40e_handle_mdd_event(struct i40e_pf * pf)11184 static void i40e_handle_mdd_event(struct i40e_pf *pf)
11185 {
11186 struct i40e_hw *hw = &pf->hw;
11187 bool mdd_detected = false;
11188 struct i40e_vf *vf;
11189 u32 reg;
11190 int i;
11191
11192 if (!test_bit(__I40E_MDD_EVENT_PENDING, pf->state))
11193 return;
11194
11195 /* find what triggered the MDD event */
11196 reg = rd32(hw, I40E_GL_MDET_TX);
11197 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
11198 u8 pf_num = FIELD_GET(I40E_GL_MDET_TX_PF_NUM_MASK, reg);
11199 u16 vf_num = FIELD_GET(I40E_GL_MDET_TX_VF_NUM_MASK, reg);
11200 u8 event = FIELD_GET(I40E_GL_MDET_TX_EVENT_MASK, reg);
11201 u16 queue = FIELD_GET(I40E_GL_MDET_TX_QUEUE_MASK, reg) -
11202 pf->hw.func_caps.base_queue;
11203 if (netif_msg_tx_err(pf))
11204 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
11205 event, queue, pf_num, vf_num);
11206 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
11207 mdd_detected = true;
11208 }
11209 reg = rd32(hw, I40E_GL_MDET_RX);
11210 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
11211 u8 func = FIELD_GET(I40E_GL_MDET_RX_FUNCTION_MASK, reg);
11212 u8 event = FIELD_GET(I40E_GL_MDET_RX_EVENT_MASK, reg);
11213 u16 queue = FIELD_GET(I40E_GL_MDET_RX_QUEUE_MASK, reg) -
11214 pf->hw.func_caps.base_queue;
11215 if (netif_msg_rx_err(pf))
11216 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
11217 event, queue, func);
11218 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
11219 mdd_detected = true;
11220 }
11221
11222 if (mdd_detected) {
11223 reg = rd32(hw, I40E_PF_MDET_TX);
11224 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
11225 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
11226 dev_dbg(&pf->pdev->dev, "TX driver issue detected on PF\n");
11227 }
11228 reg = rd32(hw, I40E_PF_MDET_RX);
11229 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
11230 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
11231 dev_dbg(&pf->pdev->dev, "RX driver issue detected on PF\n");
11232 }
11233 }
11234
11235 /* see if one of the VFs needs its hand slapped */
11236 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
11237 vf = &(pf->vf[i]);
11238 reg = rd32(hw, I40E_VP_MDET_TX(i));
11239 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
11240 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
11241 vf->num_mdd_events++;
11242 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
11243 i);
11244 dev_info(&pf->pdev->dev,
11245 "Use PF Control I/F to re-enable the VF\n");
11246 set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states);
11247 }
11248
11249 reg = rd32(hw, I40E_VP_MDET_RX(i));
11250 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
11251 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
11252 vf->num_mdd_events++;
11253 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
11254 i);
11255 dev_info(&pf->pdev->dev,
11256 "Use PF Control I/F to re-enable the VF\n");
11257 set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states);
11258 }
11259 }
11260
11261 /* re-enable mdd interrupt cause */
11262 clear_bit(__I40E_MDD_EVENT_PENDING, pf->state);
11263 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
11264 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
11265 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
11266 i40e_flush(hw);
11267 }
11268
11269 /**
11270 * i40e_service_task - Run the driver's async subtasks
11271 * @work: pointer to work_struct containing our data
11272 **/
i40e_service_task(struct work_struct * work)11273 static void i40e_service_task(struct work_struct *work)
11274 {
11275 struct i40e_pf *pf = container_of(work,
11276 struct i40e_pf,
11277 service_task);
11278 unsigned long start_time = jiffies;
11279
11280 /* don't bother with service tasks if a reset is in progress */
11281 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
11282 test_bit(__I40E_SUSPENDED, pf->state))
11283 return;
11284
11285 if (test_and_set_bit(__I40E_SERVICE_SCHED, pf->state))
11286 return;
11287
11288 if (!test_bit(__I40E_RECOVERY_MODE, pf->state)) {
11289 i40e_detect_recover_hung(pf->vsi[pf->lan_vsi]);
11290 i40e_sync_filters_subtask(pf);
11291 i40e_reset_subtask(pf);
11292 i40e_handle_mdd_event(pf);
11293 i40e_vc_process_vflr_event(pf);
11294 i40e_watchdog_subtask(pf);
11295 i40e_fdir_reinit_subtask(pf);
11296 if (test_and_clear_bit(__I40E_CLIENT_RESET, pf->state)) {
11297 /* Client subtask will reopen next time through. */
11298 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi],
11299 true);
11300 } else {
11301 i40e_client_subtask(pf);
11302 if (test_and_clear_bit(__I40E_CLIENT_L2_CHANGE,
11303 pf->state))
11304 i40e_notify_client_of_l2_param_changes(
11305 pf->vsi[pf->lan_vsi]);
11306 }
11307 i40e_sync_filters_subtask(pf);
11308 } else {
11309 i40e_reset_subtask(pf);
11310 }
11311
11312 i40e_clean_adminq_subtask(pf);
11313
11314 /* flush memory to make sure state is correct before next watchdog */
11315 smp_mb__before_atomic();
11316 clear_bit(__I40E_SERVICE_SCHED, pf->state);
11317
11318 /* If the tasks have taken longer than one timer cycle or there
11319 * is more work to be done, reschedule the service task now
11320 * rather than wait for the timer to tick again.
11321 */
11322 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
11323 test_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state) ||
11324 test_bit(__I40E_MDD_EVENT_PENDING, pf->state) ||
11325 test_bit(__I40E_VFLR_EVENT_PENDING, pf->state))
11326 i40e_service_event_schedule(pf);
11327 }
11328
11329 /**
11330 * i40e_service_timer - timer callback
11331 * @t: timer list pointer
11332 **/
i40e_service_timer(struct timer_list * t)11333 static void i40e_service_timer(struct timer_list *t)
11334 {
11335 struct i40e_pf *pf = from_timer(pf, t, service_timer);
11336
11337 mod_timer(&pf->service_timer,
11338 round_jiffies(jiffies + pf->service_timer_period));
11339 i40e_service_event_schedule(pf);
11340 }
11341
11342 /**
11343 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
11344 * @vsi: the VSI being configured
11345 **/
i40e_set_num_rings_in_vsi(struct i40e_vsi * vsi)11346 static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
11347 {
11348 struct i40e_pf *pf = vsi->back;
11349
11350 switch (vsi->type) {
11351 case I40E_VSI_MAIN:
11352 vsi->alloc_queue_pairs = pf->num_lan_qps;
11353 if (!vsi->num_tx_desc)
11354 vsi->num_tx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
11355 I40E_REQ_DESCRIPTOR_MULTIPLE);
11356 if (!vsi->num_rx_desc)
11357 vsi->num_rx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
11358 I40E_REQ_DESCRIPTOR_MULTIPLE);
11359 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
11360 vsi->num_q_vectors = pf->num_lan_msix;
11361 else
11362 vsi->num_q_vectors = 1;
11363
11364 break;
11365
11366 case I40E_VSI_FDIR:
11367 vsi->alloc_queue_pairs = 1;
11368 vsi->num_tx_desc = ALIGN(I40E_FDIR_RING_COUNT,
11369 I40E_REQ_DESCRIPTOR_MULTIPLE);
11370 vsi->num_rx_desc = ALIGN(I40E_FDIR_RING_COUNT,
11371 I40E_REQ_DESCRIPTOR_MULTIPLE);
11372 vsi->num_q_vectors = pf->num_fdsb_msix;
11373 break;
11374
11375 case I40E_VSI_VMDQ2:
11376 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
11377 if (!vsi->num_tx_desc)
11378 vsi->num_tx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
11379 I40E_REQ_DESCRIPTOR_MULTIPLE);
11380 if (!vsi->num_rx_desc)
11381 vsi->num_rx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
11382 I40E_REQ_DESCRIPTOR_MULTIPLE);
11383 vsi->num_q_vectors = pf->num_vmdq_msix;
11384 break;
11385
11386 case I40E_VSI_SRIOV:
11387 vsi->alloc_queue_pairs = pf->num_vf_qps;
11388 if (!vsi->num_tx_desc)
11389 vsi->num_tx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
11390 I40E_REQ_DESCRIPTOR_MULTIPLE);
11391 if (!vsi->num_rx_desc)
11392 vsi->num_rx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
11393 I40E_REQ_DESCRIPTOR_MULTIPLE);
11394 break;
11395
11396 default:
11397 WARN_ON(1);
11398 return -ENODATA;
11399 }
11400
11401 if (is_kdump_kernel()) {
11402 vsi->num_tx_desc = I40E_MIN_NUM_DESCRIPTORS;
11403 vsi->num_rx_desc = I40E_MIN_NUM_DESCRIPTORS;
11404 }
11405
11406 return 0;
11407 }
11408
11409 /**
11410 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
11411 * @vsi: VSI pointer
11412 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
11413 *
11414 * On error: returns error code (negative)
11415 * On success: returns 0
11416 **/
i40e_vsi_alloc_arrays(struct i40e_vsi * vsi,bool alloc_qvectors)11417 static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
11418 {
11419 struct i40e_ring **next_rings;
11420 int size;
11421 int ret = 0;
11422
11423 /* allocate memory for both Tx, XDP Tx and Rx ring pointers */
11424 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs *
11425 (i40e_enabled_xdp_vsi(vsi) ? 3 : 2);
11426 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
11427 if (!vsi->tx_rings)
11428 return -ENOMEM;
11429 next_rings = vsi->tx_rings + vsi->alloc_queue_pairs;
11430 if (i40e_enabled_xdp_vsi(vsi)) {
11431 vsi->xdp_rings = next_rings;
11432 next_rings += vsi->alloc_queue_pairs;
11433 }
11434 vsi->rx_rings = next_rings;
11435
11436 if (alloc_qvectors) {
11437 /* allocate memory for q_vector pointers */
11438 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
11439 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
11440 if (!vsi->q_vectors) {
11441 ret = -ENOMEM;
11442 goto err_vectors;
11443 }
11444 }
11445 return ret;
11446
11447 err_vectors:
11448 kfree(vsi->tx_rings);
11449 return ret;
11450 }
11451
11452 /**
11453 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
11454 * @pf: board private structure
11455 * @type: type of VSI
11456 *
11457 * On error: returns error code (negative)
11458 * On success: returns vsi index in PF (positive)
11459 **/
i40e_vsi_mem_alloc(struct i40e_pf * pf,enum i40e_vsi_type type)11460 static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
11461 {
11462 int ret = -ENODEV;
11463 struct i40e_vsi *vsi;
11464 int vsi_idx;
11465 int i;
11466
11467 /* Need to protect the allocation of the VSIs at the PF level */
11468 mutex_lock(&pf->switch_mutex);
11469
11470 /* VSI list may be fragmented if VSI creation/destruction has
11471 * been happening. We can afford to do a quick scan to look
11472 * for any free VSIs in the list.
11473 *
11474 * find next empty vsi slot, looping back around if necessary
11475 */
11476 i = pf->next_vsi;
11477 while (i < pf->num_alloc_vsi && pf->vsi[i])
11478 i++;
11479 if (i >= pf->num_alloc_vsi) {
11480 i = 0;
11481 while (i < pf->next_vsi && pf->vsi[i])
11482 i++;
11483 }
11484
11485 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
11486 vsi_idx = i; /* Found one! */
11487 } else {
11488 ret = -ENODEV;
11489 goto unlock_pf; /* out of VSI slots! */
11490 }
11491 pf->next_vsi = ++i;
11492
11493 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
11494 if (!vsi) {
11495 ret = -ENOMEM;
11496 goto unlock_pf;
11497 }
11498 vsi->type = type;
11499 vsi->back = pf;
11500 set_bit(__I40E_VSI_DOWN, vsi->state);
11501 vsi->flags = 0;
11502 vsi->idx = vsi_idx;
11503 vsi->int_rate_limit = 0;
11504 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
11505 pf->rss_table_size : 64;
11506 vsi->netdev_registered = false;
11507 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
11508 hash_init(vsi->mac_filter_hash);
11509 vsi->irqs_ready = false;
11510
11511 if (type == I40E_VSI_MAIN) {
11512 vsi->af_xdp_zc_qps = bitmap_zalloc(pf->num_lan_qps, GFP_KERNEL);
11513 if (!vsi->af_xdp_zc_qps)
11514 goto err_rings;
11515 }
11516
11517 ret = i40e_set_num_rings_in_vsi(vsi);
11518 if (ret)
11519 goto err_rings;
11520
11521 ret = i40e_vsi_alloc_arrays(vsi, true);
11522 if (ret)
11523 goto err_rings;
11524
11525 /* Setup default MSIX irq handler for VSI */
11526 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
11527
11528 /* Initialize VSI lock */
11529 spin_lock_init(&vsi->mac_filter_hash_lock);
11530 pf->vsi[vsi_idx] = vsi;
11531 ret = vsi_idx;
11532 goto unlock_pf;
11533
11534 err_rings:
11535 bitmap_free(vsi->af_xdp_zc_qps);
11536 pf->next_vsi = i - 1;
11537 kfree(vsi);
11538 unlock_pf:
11539 mutex_unlock(&pf->switch_mutex);
11540 return ret;
11541 }
11542
11543 /**
11544 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
11545 * @vsi: VSI pointer
11546 * @free_qvectors: a bool to specify if q_vectors need to be freed.
11547 *
11548 * On error: returns error code (negative)
11549 * On success: returns 0
11550 **/
i40e_vsi_free_arrays(struct i40e_vsi * vsi,bool free_qvectors)11551 static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
11552 {
11553 /* free the ring and vector containers */
11554 if (free_qvectors) {
11555 kfree(vsi->q_vectors);
11556 vsi->q_vectors = NULL;
11557 }
11558 kfree(vsi->tx_rings);
11559 vsi->tx_rings = NULL;
11560 vsi->rx_rings = NULL;
11561 vsi->xdp_rings = NULL;
11562 }
11563
11564 /**
11565 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
11566 * and lookup table
11567 * @vsi: Pointer to VSI structure
11568 */
i40e_clear_rss_config_user(struct i40e_vsi * vsi)11569 static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
11570 {
11571 if (!vsi)
11572 return;
11573
11574 kfree(vsi->rss_hkey_user);
11575 vsi->rss_hkey_user = NULL;
11576
11577 kfree(vsi->rss_lut_user);
11578 vsi->rss_lut_user = NULL;
11579 }
11580
11581 /**
11582 * i40e_vsi_clear - Deallocate the VSI provided
11583 * @vsi: the VSI being un-configured
11584 **/
i40e_vsi_clear(struct i40e_vsi * vsi)11585 static int i40e_vsi_clear(struct i40e_vsi *vsi)
11586 {
11587 struct i40e_pf *pf;
11588
11589 if (!vsi)
11590 return 0;
11591
11592 if (!vsi->back)
11593 goto free_vsi;
11594 pf = vsi->back;
11595
11596 mutex_lock(&pf->switch_mutex);
11597 if (!pf->vsi[vsi->idx]) {
11598 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](type %d)\n",
11599 vsi->idx, vsi->idx, vsi->type);
11600 goto unlock_vsi;
11601 }
11602
11603 if (pf->vsi[vsi->idx] != vsi) {
11604 dev_err(&pf->pdev->dev,
11605 "pf->vsi[%d](type %d) != vsi[%d](type %d): no free!\n",
11606 pf->vsi[vsi->idx]->idx,
11607 pf->vsi[vsi->idx]->type,
11608 vsi->idx, vsi->type);
11609 goto unlock_vsi;
11610 }
11611
11612 /* updates the PF for this cleared vsi */
11613 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
11614 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
11615
11616 bitmap_free(vsi->af_xdp_zc_qps);
11617 i40e_vsi_free_arrays(vsi, true);
11618 i40e_clear_rss_config_user(vsi);
11619
11620 pf->vsi[vsi->idx] = NULL;
11621 if (vsi->idx < pf->next_vsi)
11622 pf->next_vsi = vsi->idx;
11623
11624 unlock_vsi:
11625 mutex_unlock(&pf->switch_mutex);
11626 free_vsi:
11627 kfree(vsi);
11628
11629 return 0;
11630 }
11631
11632 /**
11633 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
11634 * @vsi: the VSI being cleaned
11635 **/
i40e_vsi_clear_rings(struct i40e_vsi * vsi)11636 static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
11637 {
11638 int i;
11639
11640 if (vsi->tx_rings && vsi->tx_rings[0]) {
11641 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
11642 kfree_rcu(vsi->tx_rings[i], rcu);
11643 WRITE_ONCE(vsi->tx_rings[i], NULL);
11644 WRITE_ONCE(vsi->rx_rings[i], NULL);
11645 if (vsi->xdp_rings)
11646 WRITE_ONCE(vsi->xdp_rings[i], NULL);
11647 }
11648 }
11649 }
11650
11651 /**
11652 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
11653 * @vsi: the VSI being configured
11654 **/
i40e_alloc_rings(struct i40e_vsi * vsi)11655 static int i40e_alloc_rings(struct i40e_vsi *vsi)
11656 {
11657 int i, qpv = i40e_enabled_xdp_vsi(vsi) ? 3 : 2;
11658 struct i40e_pf *pf = vsi->back;
11659 struct i40e_ring *ring;
11660
11661 /* Set basic values in the rings to be used later during open() */
11662 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
11663 /* allocate space for both Tx and Rx in one shot */
11664 ring = kcalloc(qpv, sizeof(struct i40e_ring), GFP_KERNEL);
11665 if (!ring)
11666 goto err_out;
11667
11668 ring->queue_index = i;
11669 ring->reg_idx = vsi->base_queue + i;
11670 ring->ring_active = false;
11671 ring->vsi = vsi;
11672 ring->netdev = vsi->netdev;
11673 ring->dev = &pf->pdev->dev;
11674 ring->count = vsi->num_tx_desc;
11675 ring->size = 0;
11676 ring->dcb_tc = 0;
11677 if (test_bit(I40E_HW_CAP_WB_ON_ITR, vsi->back->hw.caps))
11678 ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
11679 ring->itr_setting = pf->tx_itr_default;
11680 WRITE_ONCE(vsi->tx_rings[i], ring++);
11681
11682 if (!i40e_enabled_xdp_vsi(vsi))
11683 goto setup_rx;
11684
11685 ring->queue_index = vsi->alloc_queue_pairs + i;
11686 ring->reg_idx = vsi->base_queue + ring->queue_index;
11687 ring->ring_active = false;
11688 ring->vsi = vsi;
11689 ring->netdev = NULL;
11690 ring->dev = &pf->pdev->dev;
11691 ring->count = vsi->num_tx_desc;
11692 ring->size = 0;
11693 ring->dcb_tc = 0;
11694 if (test_bit(I40E_HW_CAP_WB_ON_ITR, vsi->back->hw.caps))
11695 ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
11696 set_ring_xdp(ring);
11697 ring->itr_setting = pf->tx_itr_default;
11698 WRITE_ONCE(vsi->xdp_rings[i], ring++);
11699
11700 setup_rx:
11701 ring->queue_index = i;
11702 ring->reg_idx = vsi->base_queue + i;
11703 ring->ring_active = false;
11704 ring->vsi = vsi;
11705 ring->netdev = vsi->netdev;
11706 ring->dev = &pf->pdev->dev;
11707 ring->count = vsi->num_rx_desc;
11708 ring->size = 0;
11709 ring->dcb_tc = 0;
11710 ring->itr_setting = pf->rx_itr_default;
11711 WRITE_ONCE(vsi->rx_rings[i], ring);
11712 }
11713
11714 return 0;
11715
11716 err_out:
11717 i40e_vsi_clear_rings(vsi);
11718 return -ENOMEM;
11719 }
11720
11721 /**
11722 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
11723 * @pf: board private structure
11724 * @vectors: the number of MSI-X vectors to request
11725 *
11726 * Returns the number of vectors reserved, or error
11727 **/
i40e_reserve_msix_vectors(struct i40e_pf * pf,int vectors)11728 static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
11729 {
11730 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
11731 I40E_MIN_MSIX, vectors);
11732 if (vectors < 0) {
11733 dev_info(&pf->pdev->dev,
11734 "MSI-X vector reservation failed: %d\n", vectors);
11735 vectors = 0;
11736 }
11737
11738 return vectors;
11739 }
11740
11741 /**
11742 * i40e_init_msix - Setup the MSIX capability
11743 * @pf: board private structure
11744 *
11745 * Work with the OS to set up the MSIX vectors needed.
11746 *
11747 * Returns the number of vectors reserved or negative on failure
11748 **/
i40e_init_msix(struct i40e_pf * pf)11749 static int i40e_init_msix(struct i40e_pf *pf)
11750 {
11751 struct i40e_hw *hw = &pf->hw;
11752 int cpus, extra_vectors;
11753 int vectors_left;
11754 int v_budget, i;
11755 int v_actual;
11756 int iwarp_requested = 0;
11757
11758 if (!test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
11759 return -ENODEV;
11760
11761 /* The number of vectors we'll request will be comprised of:
11762 * - Add 1 for "other" cause for Admin Queue events, etc.
11763 * - The number of LAN queue pairs
11764 * - Queues being used for RSS.
11765 * We don't need as many as max_rss_size vectors.
11766 * use rss_size instead in the calculation since that
11767 * is governed by number of cpus in the system.
11768 * - assumes symmetric Tx/Rx pairing
11769 * - The number of VMDq pairs
11770 * - The CPU count within the NUMA node if iWARP is enabled
11771 * Once we count this up, try the request.
11772 *
11773 * If we can't get what we want, we'll simplify to nearly nothing
11774 * and try again. If that still fails, we punt.
11775 */
11776 vectors_left = hw->func_caps.num_msix_vectors;
11777 v_budget = 0;
11778
11779 /* reserve one vector for miscellaneous handler */
11780 if (vectors_left) {
11781 v_budget++;
11782 vectors_left--;
11783 }
11784
11785 /* reserve some vectors for the main PF traffic queues. Initially we
11786 * only reserve at most 50% of the available vectors, in the case that
11787 * the number of online CPUs is large. This ensures that we can enable
11788 * extra features as well. Once we've enabled the other features, we
11789 * will use any remaining vectors to reach as close as we can to the
11790 * number of online CPUs.
11791 */
11792 cpus = num_online_cpus();
11793 pf->num_lan_msix = min_t(int, cpus, vectors_left / 2);
11794 vectors_left -= pf->num_lan_msix;
11795
11796 /* reserve one vector for sideband flow director */
11797 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags)) {
11798 if (vectors_left) {
11799 pf->num_fdsb_msix = 1;
11800 v_budget++;
11801 vectors_left--;
11802 } else {
11803 pf->num_fdsb_msix = 0;
11804 }
11805 }
11806
11807 /* can we reserve enough for iWARP? */
11808 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags)) {
11809 iwarp_requested = pf->num_iwarp_msix;
11810
11811 if (!vectors_left)
11812 pf->num_iwarp_msix = 0;
11813 else if (vectors_left < pf->num_iwarp_msix)
11814 pf->num_iwarp_msix = 1;
11815 v_budget += pf->num_iwarp_msix;
11816 vectors_left -= pf->num_iwarp_msix;
11817 }
11818
11819 /* any vectors left over go for VMDq support */
11820 if (test_bit(I40E_FLAG_VMDQ_ENA, pf->flags)) {
11821 if (!vectors_left) {
11822 pf->num_vmdq_msix = 0;
11823 pf->num_vmdq_qps = 0;
11824 } else {
11825 int vmdq_vecs_wanted =
11826 pf->num_vmdq_vsis * pf->num_vmdq_qps;
11827 int vmdq_vecs =
11828 min_t(int, vectors_left, vmdq_vecs_wanted);
11829
11830 /* if we're short on vectors for what's desired, we limit
11831 * the queues per vmdq. If this is still more than are
11832 * available, the user will need to change the number of
11833 * queues/vectors used by the PF later with the ethtool
11834 * channels command
11835 */
11836 if (vectors_left < vmdq_vecs_wanted) {
11837 pf->num_vmdq_qps = 1;
11838 vmdq_vecs_wanted = pf->num_vmdq_vsis;
11839 vmdq_vecs = min_t(int,
11840 vectors_left,
11841 vmdq_vecs_wanted);
11842 }
11843 pf->num_vmdq_msix = pf->num_vmdq_qps;
11844
11845 v_budget += vmdq_vecs;
11846 vectors_left -= vmdq_vecs;
11847 }
11848 }
11849
11850 /* On systems with a large number of SMP cores, we previously limited
11851 * the number of vectors for num_lan_msix to be at most 50% of the
11852 * available vectors, to allow for other features. Now, we add back
11853 * the remaining vectors. However, we ensure that the total
11854 * num_lan_msix will not exceed num_online_cpus(). To do this, we
11855 * calculate the number of vectors we can add without going over the
11856 * cap of CPUs. For systems with a small number of CPUs this will be
11857 * zero.
11858 */
11859 extra_vectors = min_t(int, cpus - pf->num_lan_msix, vectors_left);
11860 pf->num_lan_msix += extra_vectors;
11861 vectors_left -= extra_vectors;
11862
11863 WARN(vectors_left < 0,
11864 "Calculation of remaining vectors underflowed. This is an accounting bug when determining total MSI-X vectors.\n");
11865
11866 v_budget += pf->num_lan_msix;
11867 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
11868 GFP_KERNEL);
11869 if (!pf->msix_entries)
11870 return -ENOMEM;
11871
11872 for (i = 0; i < v_budget; i++)
11873 pf->msix_entries[i].entry = i;
11874 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
11875
11876 if (v_actual < I40E_MIN_MSIX) {
11877 clear_bit(I40E_FLAG_MSIX_ENA, pf->flags);
11878 kfree(pf->msix_entries);
11879 pf->msix_entries = NULL;
11880 pci_disable_msix(pf->pdev);
11881 return -ENODEV;
11882
11883 } else if (v_actual == I40E_MIN_MSIX) {
11884 /* Adjust for minimal MSIX use */
11885 pf->num_vmdq_vsis = 0;
11886 pf->num_vmdq_qps = 0;
11887 pf->num_lan_qps = 1;
11888 pf->num_lan_msix = 1;
11889
11890 } else if (v_actual != v_budget) {
11891 /* If we have limited resources, we will start with no vectors
11892 * for the special features and then allocate vectors to some
11893 * of these features based on the policy and at the end disable
11894 * the features that did not get any vectors.
11895 */
11896 int vec;
11897
11898 dev_info(&pf->pdev->dev,
11899 "MSI-X vector limit reached with %d, wanted %d, attempting to redistribute vectors\n",
11900 v_actual, v_budget);
11901 /* reserve the misc vector */
11902 vec = v_actual - 1;
11903
11904 /* Scale vector usage down */
11905 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
11906 pf->num_vmdq_vsis = 1;
11907 pf->num_vmdq_qps = 1;
11908
11909 /* partition out the remaining vectors */
11910 switch (vec) {
11911 case 2:
11912 pf->num_lan_msix = 1;
11913 break;
11914 case 3:
11915 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags)) {
11916 pf->num_lan_msix = 1;
11917 pf->num_iwarp_msix = 1;
11918 } else {
11919 pf->num_lan_msix = 2;
11920 }
11921 break;
11922 default:
11923 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags)) {
11924 pf->num_iwarp_msix = min_t(int, (vec / 3),
11925 iwarp_requested);
11926 pf->num_vmdq_vsis = min_t(int, (vec / 3),
11927 I40E_DEFAULT_NUM_VMDQ_VSI);
11928 } else {
11929 pf->num_vmdq_vsis = min_t(int, (vec / 2),
11930 I40E_DEFAULT_NUM_VMDQ_VSI);
11931 }
11932 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags)) {
11933 pf->num_fdsb_msix = 1;
11934 vec--;
11935 }
11936 pf->num_lan_msix = min_t(int,
11937 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
11938 pf->num_lan_msix);
11939 pf->num_lan_qps = pf->num_lan_msix;
11940 break;
11941 }
11942 }
11943
11944 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) && pf->num_fdsb_msix == 0) {
11945 dev_info(&pf->pdev->dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n");
11946 clear_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
11947 set_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
11948 }
11949 if (test_bit(I40E_FLAG_VMDQ_ENA, pf->flags) && pf->num_vmdq_msix == 0) {
11950 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
11951 clear_bit(I40E_FLAG_VMDQ_ENA, pf->flags);
11952 }
11953
11954 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags) &&
11955 pf->num_iwarp_msix == 0) {
11956 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
11957 clear_bit(I40E_FLAG_IWARP_ENA, pf->flags);
11958 }
11959 i40e_debug(&pf->hw, I40E_DEBUG_INIT,
11960 "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n",
11961 pf->num_lan_msix,
11962 pf->num_vmdq_msix * pf->num_vmdq_vsis,
11963 pf->num_fdsb_msix,
11964 pf->num_iwarp_msix);
11965
11966 return v_actual;
11967 }
11968
11969 /**
11970 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
11971 * @vsi: the VSI being configured
11972 * @v_idx: index of the vector in the vsi struct
11973 *
11974 * We allocate one q_vector. If allocation fails we return -ENOMEM.
11975 **/
i40e_vsi_alloc_q_vector(struct i40e_vsi * vsi,int v_idx)11976 static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
11977 {
11978 struct i40e_q_vector *q_vector;
11979
11980 /* allocate q_vector */
11981 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
11982 if (!q_vector)
11983 return -ENOMEM;
11984
11985 q_vector->vsi = vsi;
11986 q_vector->v_idx = v_idx;
11987 cpumask_copy(&q_vector->affinity_mask, cpu_possible_mask);
11988
11989 if (vsi->netdev)
11990 netif_napi_add(vsi->netdev, &q_vector->napi, i40e_napi_poll);
11991
11992 /* tie q_vector and vsi together */
11993 vsi->q_vectors[v_idx] = q_vector;
11994
11995 return 0;
11996 }
11997
11998 /**
11999 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
12000 * @vsi: the VSI being configured
12001 *
12002 * We allocate one q_vector per queue interrupt. If allocation fails we
12003 * return -ENOMEM.
12004 **/
i40e_vsi_alloc_q_vectors(struct i40e_vsi * vsi)12005 static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
12006 {
12007 struct i40e_pf *pf = vsi->back;
12008 int err, v_idx, num_q_vectors;
12009
12010 /* if not MSIX, give the one vector only to the LAN VSI */
12011 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
12012 num_q_vectors = vsi->num_q_vectors;
12013 else if (vsi == pf->vsi[pf->lan_vsi])
12014 num_q_vectors = 1;
12015 else
12016 return -EINVAL;
12017
12018 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
12019 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
12020 if (err)
12021 goto err_out;
12022 }
12023
12024 return 0;
12025
12026 err_out:
12027 while (v_idx--)
12028 i40e_free_q_vector(vsi, v_idx);
12029
12030 return err;
12031 }
12032
12033 /**
12034 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
12035 * @pf: board private structure to initialize
12036 **/
i40e_init_interrupt_scheme(struct i40e_pf * pf)12037 static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
12038 {
12039 int vectors = 0;
12040 ssize_t size;
12041
12042 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
12043 vectors = i40e_init_msix(pf);
12044 if (vectors < 0) {
12045 clear_bit(I40E_FLAG_MSIX_ENA, pf->flags);
12046 clear_bit(I40E_FLAG_IWARP_ENA, pf->flags);
12047 clear_bit(I40E_FLAG_RSS_ENA, pf->flags);
12048 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
12049 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
12050 clear_bit(I40E_FLAG_SRIOV_ENA, pf->flags);
12051 clear_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
12052 clear_bit(I40E_FLAG_FD_ATR_ENA, pf->flags);
12053 clear_bit(I40E_FLAG_VMDQ_ENA, pf->flags);
12054 set_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
12055
12056 /* rework the queue expectations without MSIX */
12057 i40e_determine_queue_usage(pf);
12058 }
12059 }
12060
12061 if (!test_bit(I40E_FLAG_MSIX_ENA, pf->flags) &&
12062 test_bit(I40E_FLAG_MSI_ENA, pf->flags)) {
12063 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
12064 vectors = pci_enable_msi(pf->pdev);
12065 if (vectors < 0) {
12066 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
12067 vectors);
12068 clear_bit(I40E_FLAG_MSI_ENA, pf->flags);
12069 }
12070 vectors = 1; /* one MSI or Legacy vector */
12071 }
12072
12073 if (!test_bit(I40E_FLAG_MSI_ENA, pf->flags) &&
12074 !test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
12075 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
12076
12077 /* set up vector assignment tracking */
12078 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
12079 pf->irq_pile = kzalloc(size, GFP_KERNEL);
12080 if (!pf->irq_pile)
12081 return -ENOMEM;
12082
12083 pf->irq_pile->num_entries = vectors;
12084
12085 /* track first vector for misc interrupts, ignore return */
12086 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
12087
12088 return 0;
12089 }
12090
12091 /**
12092 * i40e_restore_interrupt_scheme - Restore the interrupt scheme
12093 * @pf: private board data structure
12094 *
12095 * Restore the interrupt scheme that was cleared when we suspended the
12096 * device. This should be called during resume to re-allocate the q_vectors
12097 * and reacquire IRQs.
12098 */
i40e_restore_interrupt_scheme(struct i40e_pf * pf)12099 static int i40e_restore_interrupt_scheme(struct i40e_pf *pf)
12100 {
12101 int err, i;
12102
12103 /* We cleared the MSI and MSI-X flags when disabling the old interrupt
12104 * scheme. We need to re-enabled them here in order to attempt to
12105 * re-acquire the MSI or MSI-X vectors
12106 */
12107 set_bit(I40E_FLAG_MSI_ENA, pf->flags);
12108 set_bit(I40E_FLAG_MSIX_ENA, pf->flags);
12109
12110 err = i40e_init_interrupt_scheme(pf);
12111 if (err)
12112 return err;
12113
12114 /* Now that we've re-acquired IRQs, we need to remap the vectors and
12115 * rings together again.
12116 */
12117 for (i = 0; i < pf->num_alloc_vsi; i++) {
12118 if (pf->vsi[i]) {
12119 err = i40e_vsi_alloc_q_vectors(pf->vsi[i]);
12120 if (err)
12121 goto err_unwind;
12122 i40e_vsi_map_rings_to_vectors(pf->vsi[i]);
12123 }
12124 }
12125
12126 err = i40e_setup_misc_vector(pf);
12127 if (err)
12128 goto err_unwind;
12129
12130 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags))
12131 i40e_client_update_msix_info(pf);
12132
12133 return 0;
12134
12135 err_unwind:
12136 while (i--) {
12137 if (pf->vsi[i])
12138 i40e_vsi_free_q_vectors(pf->vsi[i]);
12139 }
12140
12141 return err;
12142 }
12143
12144 /**
12145 * i40e_setup_misc_vector_for_recovery_mode - Setup the misc vector to handle
12146 * non queue events in recovery mode
12147 * @pf: board private structure
12148 *
12149 * This sets up the handler for MSIX 0 or MSI/legacy, which is used to manage
12150 * the non-queue interrupts, e.g. AdminQ and errors in recovery mode.
12151 * This is handled differently than in recovery mode since no Tx/Rx resources
12152 * are being allocated.
12153 **/
i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf * pf)12154 static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf)
12155 {
12156 int err;
12157
12158 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
12159 err = i40e_setup_misc_vector(pf);
12160
12161 if (err) {
12162 dev_info(&pf->pdev->dev,
12163 "MSI-X misc vector request failed, error %d\n",
12164 err);
12165 return err;
12166 }
12167 } else {
12168 u32 flags = test_bit(I40E_FLAG_MSI_ENA, pf->flags) ? 0 : IRQF_SHARED;
12169
12170 err = request_irq(pf->pdev->irq, i40e_intr, flags,
12171 pf->int_name, pf);
12172
12173 if (err) {
12174 dev_info(&pf->pdev->dev,
12175 "MSI/legacy misc vector request failed, error %d\n",
12176 err);
12177 return err;
12178 }
12179 i40e_enable_misc_int_causes(pf);
12180 i40e_irq_dynamic_enable_icr0(pf);
12181 }
12182
12183 return 0;
12184 }
12185
12186 /**
12187 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
12188 * @pf: board private structure
12189 *
12190 * This sets up the handler for MSIX 0, which is used to manage the
12191 * non-queue interrupts, e.g. AdminQ and errors. This is not used
12192 * when in MSI or Legacy interrupt mode.
12193 **/
i40e_setup_misc_vector(struct i40e_pf * pf)12194 static int i40e_setup_misc_vector(struct i40e_pf *pf)
12195 {
12196 struct i40e_hw *hw = &pf->hw;
12197 int err = 0;
12198
12199 /* Only request the IRQ once, the first time through. */
12200 if (!test_and_set_bit(__I40E_MISC_IRQ_REQUESTED, pf->state)) {
12201 err = request_irq(pf->msix_entries[0].vector,
12202 i40e_intr, 0, pf->int_name, pf);
12203 if (err) {
12204 clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state);
12205 dev_info(&pf->pdev->dev,
12206 "request_irq for %s failed: %d\n",
12207 pf->int_name, err);
12208 return -EFAULT;
12209 }
12210 }
12211
12212 i40e_enable_misc_int_causes(pf);
12213
12214 /* associate no queues to the misc vector */
12215 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
12216 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K >> 1);
12217
12218 i40e_flush(hw);
12219
12220 i40e_irq_dynamic_enable_icr0(pf);
12221
12222 return err;
12223 }
12224
12225 /**
12226 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
12227 * @vsi: Pointer to vsi structure
12228 * @seed: Buffter to store the hash keys
12229 * @lut: Buffer to store the lookup table entries
12230 * @lut_size: Size of buffer to store the lookup table entries
12231 *
12232 * Return 0 on success, negative on failure
12233 */
i40e_get_rss_aq(struct i40e_vsi * vsi,const u8 * seed,u8 * lut,u16 lut_size)12234 static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
12235 u8 *lut, u16 lut_size)
12236 {
12237 struct i40e_pf *pf = vsi->back;
12238 struct i40e_hw *hw = &pf->hw;
12239 int ret = 0;
12240
12241 if (seed) {
12242 ret = i40e_aq_get_rss_key(hw, vsi->id,
12243 (struct i40e_aqc_get_set_rss_key_data *)seed);
12244 if (ret) {
12245 dev_info(&pf->pdev->dev,
12246 "Cannot get RSS key, err %pe aq_err %s\n",
12247 ERR_PTR(ret),
12248 i40e_aq_str(&pf->hw,
12249 pf->hw.aq.asq_last_status));
12250 return ret;
12251 }
12252 }
12253
12254 if (lut) {
12255 bool pf_lut = vsi->type == I40E_VSI_MAIN;
12256
12257 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
12258 if (ret) {
12259 dev_info(&pf->pdev->dev,
12260 "Cannot get RSS lut, err %pe aq_err %s\n",
12261 ERR_PTR(ret),
12262 i40e_aq_str(&pf->hw,
12263 pf->hw.aq.asq_last_status));
12264 return ret;
12265 }
12266 }
12267
12268 return ret;
12269 }
12270
12271 /**
12272 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
12273 * @vsi: Pointer to vsi structure
12274 * @seed: RSS hash seed
12275 * @lut: Lookup table
12276 * @lut_size: Lookup table size
12277 *
12278 * Returns 0 on success, negative on failure
12279 **/
i40e_config_rss_reg(struct i40e_vsi * vsi,const u8 * seed,const u8 * lut,u16 lut_size)12280 static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
12281 const u8 *lut, u16 lut_size)
12282 {
12283 struct i40e_pf *pf = vsi->back;
12284 struct i40e_hw *hw = &pf->hw;
12285 u16 vf_id = vsi->vf_id;
12286 u8 i;
12287
12288 /* Fill out hash function seed */
12289 if (seed) {
12290 u32 *seed_dw = (u32 *)seed;
12291
12292 if (vsi->type == I40E_VSI_MAIN) {
12293 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
12294 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
12295 } else if (vsi->type == I40E_VSI_SRIOV) {
12296 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++)
12297 wr32(hw, I40E_VFQF_HKEY1(i, vf_id), seed_dw[i]);
12298 } else {
12299 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n");
12300 }
12301 }
12302
12303 if (lut) {
12304 u32 *lut_dw = (u32 *)lut;
12305
12306 if (vsi->type == I40E_VSI_MAIN) {
12307 if (lut_size != I40E_HLUT_ARRAY_SIZE)
12308 return -EINVAL;
12309 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
12310 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
12311 } else if (vsi->type == I40E_VSI_SRIOV) {
12312 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE)
12313 return -EINVAL;
12314 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
12315 wr32(hw, I40E_VFQF_HLUT1(i, vf_id), lut_dw[i]);
12316 } else {
12317 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
12318 }
12319 }
12320 i40e_flush(hw);
12321
12322 return 0;
12323 }
12324
12325 /**
12326 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
12327 * @vsi: Pointer to VSI structure
12328 * @seed: Buffer to store the keys
12329 * @lut: Buffer to store the lookup table entries
12330 * @lut_size: Size of buffer to store the lookup table entries
12331 *
12332 * Returns 0 on success, negative on failure
12333 */
i40e_get_rss_reg(struct i40e_vsi * vsi,u8 * seed,u8 * lut,u16 lut_size)12334 static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
12335 u8 *lut, u16 lut_size)
12336 {
12337 struct i40e_pf *pf = vsi->back;
12338 struct i40e_hw *hw = &pf->hw;
12339 u16 i;
12340
12341 if (seed) {
12342 u32 *seed_dw = (u32 *)seed;
12343
12344 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
12345 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
12346 }
12347 if (lut) {
12348 u32 *lut_dw = (u32 *)lut;
12349
12350 if (lut_size != I40E_HLUT_ARRAY_SIZE)
12351 return -EINVAL;
12352 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
12353 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
12354 }
12355
12356 return 0;
12357 }
12358
12359 /**
12360 * i40e_config_rss - Configure RSS keys and lut
12361 * @vsi: Pointer to VSI structure
12362 * @seed: RSS hash seed
12363 * @lut: Lookup table
12364 * @lut_size: Lookup table size
12365 *
12366 * Returns 0 on success, negative on failure
12367 */
i40e_config_rss(struct i40e_vsi * vsi,u8 * seed,u8 * lut,u16 lut_size)12368 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
12369 {
12370 struct i40e_pf *pf = vsi->back;
12371
12372 if (test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps))
12373 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
12374 else
12375 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
12376 }
12377
12378 /**
12379 * i40e_get_rss - Get RSS keys and lut
12380 * @vsi: Pointer to VSI structure
12381 * @seed: Buffer to store the keys
12382 * @lut: Buffer to store the lookup table entries
12383 * @lut_size: Size of buffer to store the lookup table entries
12384 *
12385 * Returns 0 on success, negative on failure
12386 */
i40e_get_rss(struct i40e_vsi * vsi,u8 * seed,u8 * lut,u16 lut_size)12387 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
12388 {
12389 struct i40e_pf *pf = vsi->back;
12390
12391 if (test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps))
12392 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
12393 else
12394 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
12395 }
12396
12397 /**
12398 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
12399 * @pf: Pointer to board private structure
12400 * @lut: Lookup table
12401 * @rss_table_size: Lookup table size
12402 * @rss_size: Range of queue number for hashing
12403 */
i40e_fill_rss_lut(struct i40e_pf * pf,u8 * lut,u16 rss_table_size,u16 rss_size)12404 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
12405 u16 rss_table_size, u16 rss_size)
12406 {
12407 u16 i;
12408
12409 for (i = 0; i < rss_table_size; i++)
12410 lut[i] = i % rss_size;
12411 }
12412
12413 /**
12414 * i40e_pf_config_rss - Prepare for RSS if used
12415 * @pf: board private structure
12416 **/
i40e_pf_config_rss(struct i40e_pf * pf)12417 static int i40e_pf_config_rss(struct i40e_pf *pf)
12418 {
12419 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
12420 u8 seed[I40E_HKEY_ARRAY_SIZE];
12421 u8 *lut;
12422 struct i40e_hw *hw = &pf->hw;
12423 u32 reg_val;
12424 u64 hena;
12425 int ret;
12426
12427 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
12428 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
12429 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
12430 hena |= i40e_pf_get_default_rss_hena(pf);
12431
12432 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
12433 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
12434
12435 /* Determine the RSS table size based on the hardware capabilities */
12436 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
12437 reg_val = (pf->rss_table_size == 512) ?
12438 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
12439 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
12440 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
12441
12442 /* Determine the RSS size of the VSI */
12443 if (!vsi->rss_size) {
12444 u16 qcount;
12445 /* If the firmware does something weird during VSI init, we
12446 * could end up with zero TCs. Check for that to avoid
12447 * divide-by-zero. It probably won't pass traffic, but it also
12448 * won't panic.
12449 */
12450 qcount = vsi->num_queue_pairs /
12451 (vsi->tc_config.numtc ? vsi->tc_config.numtc : 1);
12452 vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount);
12453 }
12454 if (!vsi->rss_size)
12455 return -EINVAL;
12456
12457 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
12458 if (!lut)
12459 return -ENOMEM;
12460
12461 /* Use user configured lut if there is one, otherwise use default */
12462 if (vsi->rss_lut_user)
12463 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
12464 else
12465 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
12466
12467 /* Use user configured hash key if there is one, otherwise
12468 * use default.
12469 */
12470 if (vsi->rss_hkey_user)
12471 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
12472 else
12473 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
12474 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
12475 kfree(lut);
12476
12477 return ret;
12478 }
12479
12480 /**
12481 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
12482 * @pf: board private structure
12483 * @queue_count: the requested queue count for rss.
12484 *
12485 * returns 0 if rss is not enabled, if enabled returns the final rss queue
12486 * count which may be different from the requested queue count.
12487 * Note: expects to be called while under rtnl_lock()
12488 **/
i40e_reconfig_rss_queues(struct i40e_pf * pf,int queue_count)12489 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
12490 {
12491 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
12492 int new_rss_size;
12493
12494 if (!test_bit(I40E_FLAG_RSS_ENA, pf->flags))
12495 return 0;
12496
12497 queue_count = min_t(int, queue_count, num_online_cpus());
12498 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
12499
12500 if (queue_count != vsi->num_queue_pairs) {
12501 u16 qcount;
12502
12503 vsi->req_queue_pairs = queue_count;
12504 i40e_prep_for_reset(pf);
12505 if (test_bit(__I40E_IN_REMOVE, pf->state))
12506 return pf->alloc_rss_size;
12507
12508 pf->alloc_rss_size = new_rss_size;
12509
12510 i40e_reset_and_rebuild(pf, true, true);
12511
12512 /* Discard the user configured hash keys and lut, if less
12513 * queues are enabled.
12514 */
12515 if (queue_count < vsi->rss_size) {
12516 i40e_clear_rss_config_user(vsi);
12517 dev_dbg(&pf->pdev->dev,
12518 "discard user configured hash keys and lut\n");
12519 }
12520
12521 /* Reset vsi->rss_size, as number of enabled queues changed */
12522 qcount = vsi->num_queue_pairs / vsi->tc_config.numtc;
12523 vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount);
12524
12525 i40e_pf_config_rss(pf);
12526 }
12527 dev_info(&pf->pdev->dev, "User requested queue count/HW max RSS count: %d/%d\n",
12528 vsi->req_queue_pairs, pf->rss_size_max);
12529 return pf->alloc_rss_size;
12530 }
12531
12532 /**
12533 * i40e_get_partition_bw_setting - Retrieve BW settings for this PF partition
12534 * @pf: board private structure
12535 **/
i40e_get_partition_bw_setting(struct i40e_pf * pf)12536 int i40e_get_partition_bw_setting(struct i40e_pf *pf)
12537 {
12538 bool min_valid, max_valid;
12539 u32 max_bw, min_bw;
12540 int status;
12541
12542 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
12543 &min_valid, &max_valid);
12544
12545 if (!status) {
12546 if (min_valid)
12547 pf->min_bw = min_bw;
12548 if (max_valid)
12549 pf->max_bw = max_bw;
12550 }
12551
12552 return status;
12553 }
12554
12555 /**
12556 * i40e_set_partition_bw_setting - Set BW settings for this PF partition
12557 * @pf: board private structure
12558 **/
i40e_set_partition_bw_setting(struct i40e_pf * pf)12559 int i40e_set_partition_bw_setting(struct i40e_pf *pf)
12560 {
12561 struct i40e_aqc_configure_partition_bw_data bw_data;
12562 int status;
12563
12564 memset(&bw_data, 0, sizeof(bw_data));
12565
12566 /* Set the valid bit for this PF */
12567 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
12568 bw_data.max_bw[pf->hw.pf_id] = pf->max_bw & I40E_ALT_BW_VALUE_MASK;
12569 bw_data.min_bw[pf->hw.pf_id] = pf->min_bw & I40E_ALT_BW_VALUE_MASK;
12570
12571 /* Set the new bandwidths */
12572 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
12573
12574 return status;
12575 }
12576
12577 /**
12578 * i40e_commit_partition_bw_setting - Commit BW settings for this PF partition
12579 * @pf: board private structure
12580 **/
i40e_commit_partition_bw_setting(struct i40e_pf * pf)12581 int i40e_commit_partition_bw_setting(struct i40e_pf *pf)
12582 {
12583 /* Commit temporary BW setting to permanent NVM image */
12584 enum i40e_admin_queue_err last_aq_status;
12585 u16 nvm_word;
12586 int ret;
12587
12588 if (pf->hw.partition_id != 1) {
12589 dev_info(&pf->pdev->dev,
12590 "Commit BW only works on partition 1! This is partition %d",
12591 pf->hw.partition_id);
12592 ret = -EOPNOTSUPP;
12593 goto bw_commit_out;
12594 }
12595
12596 /* Acquire NVM for read access */
12597 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
12598 last_aq_status = pf->hw.aq.asq_last_status;
12599 if (ret) {
12600 dev_info(&pf->pdev->dev,
12601 "Cannot acquire NVM for read access, err %pe aq_err %s\n",
12602 ERR_PTR(ret),
12603 i40e_aq_str(&pf->hw, last_aq_status));
12604 goto bw_commit_out;
12605 }
12606
12607 /* Read word 0x10 of NVM - SW compatibility word 1 */
12608 ret = i40e_aq_read_nvm(&pf->hw,
12609 I40E_SR_NVM_CONTROL_WORD,
12610 0x10, sizeof(nvm_word), &nvm_word,
12611 false, NULL);
12612 /* Save off last admin queue command status before releasing
12613 * the NVM
12614 */
12615 last_aq_status = pf->hw.aq.asq_last_status;
12616 i40e_release_nvm(&pf->hw);
12617 if (ret) {
12618 dev_info(&pf->pdev->dev, "NVM read error, err %pe aq_err %s\n",
12619 ERR_PTR(ret),
12620 i40e_aq_str(&pf->hw, last_aq_status));
12621 goto bw_commit_out;
12622 }
12623
12624 /* Wait a bit for NVM release to complete */
12625 msleep(50);
12626
12627 /* Acquire NVM for write access */
12628 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
12629 last_aq_status = pf->hw.aq.asq_last_status;
12630 if (ret) {
12631 dev_info(&pf->pdev->dev,
12632 "Cannot acquire NVM for write access, err %pe aq_err %s\n",
12633 ERR_PTR(ret),
12634 i40e_aq_str(&pf->hw, last_aq_status));
12635 goto bw_commit_out;
12636 }
12637 /* Write it back out unchanged to initiate update NVM,
12638 * which will force a write of the shadow (alt) RAM to
12639 * the NVM - thus storing the bandwidth values permanently.
12640 */
12641 ret = i40e_aq_update_nvm(&pf->hw,
12642 I40E_SR_NVM_CONTROL_WORD,
12643 0x10, sizeof(nvm_word),
12644 &nvm_word, true, 0, NULL);
12645 /* Save off last admin queue command status before releasing
12646 * the NVM
12647 */
12648 last_aq_status = pf->hw.aq.asq_last_status;
12649 i40e_release_nvm(&pf->hw);
12650 if (ret)
12651 dev_info(&pf->pdev->dev,
12652 "BW settings NOT SAVED, err %pe aq_err %s\n",
12653 ERR_PTR(ret),
12654 i40e_aq_str(&pf->hw, last_aq_status));
12655 bw_commit_out:
12656
12657 return ret;
12658 }
12659
12660 /**
12661 * i40e_is_total_port_shutdown_enabled - read NVM and return value
12662 * if total port shutdown feature is enabled for this PF
12663 * @pf: board private structure
12664 **/
i40e_is_total_port_shutdown_enabled(struct i40e_pf * pf)12665 static bool i40e_is_total_port_shutdown_enabled(struct i40e_pf *pf)
12666 {
12667 #define I40E_TOTAL_PORT_SHUTDOWN_ENABLED BIT(4)
12668 #define I40E_FEATURES_ENABLE_PTR 0x2A
12669 #define I40E_CURRENT_SETTING_PTR 0x2B
12670 #define I40E_LINK_BEHAVIOR_WORD_OFFSET 0x2D
12671 #define I40E_LINK_BEHAVIOR_WORD_LENGTH 0x1
12672 #define I40E_LINK_BEHAVIOR_OS_FORCED_ENABLED BIT(0)
12673 #define I40E_LINK_BEHAVIOR_PORT_BIT_LENGTH 4
12674 u16 sr_emp_sr_settings_ptr = 0;
12675 u16 features_enable = 0;
12676 u16 link_behavior = 0;
12677 int read_status = 0;
12678 bool ret = false;
12679
12680 read_status = i40e_read_nvm_word(&pf->hw,
12681 I40E_SR_EMP_SR_SETTINGS_PTR,
12682 &sr_emp_sr_settings_ptr);
12683 if (read_status)
12684 goto err_nvm;
12685 read_status = i40e_read_nvm_word(&pf->hw,
12686 sr_emp_sr_settings_ptr +
12687 I40E_FEATURES_ENABLE_PTR,
12688 &features_enable);
12689 if (read_status)
12690 goto err_nvm;
12691 if (I40E_TOTAL_PORT_SHUTDOWN_ENABLED & features_enable) {
12692 read_status = i40e_read_nvm_module_data(&pf->hw,
12693 I40E_SR_EMP_SR_SETTINGS_PTR,
12694 I40E_CURRENT_SETTING_PTR,
12695 I40E_LINK_BEHAVIOR_WORD_OFFSET,
12696 I40E_LINK_BEHAVIOR_WORD_LENGTH,
12697 &link_behavior);
12698 if (read_status)
12699 goto err_nvm;
12700 link_behavior >>= (pf->hw.port * I40E_LINK_BEHAVIOR_PORT_BIT_LENGTH);
12701 ret = I40E_LINK_BEHAVIOR_OS_FORCED_ENABLED & link_behavior;
12702 }
12703 return ret;
12704
12705 err_nvm:
12706 dev_warn(&pf->pdev->dev,
12707 "total-port-shutdown feature is off due to read nvm error: %pe\n",
12708 ERR_PTR(read_status));
12709 return ret;
12710 }
12711
12712 /**
12713 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
12714 * @pf: board private structure to initialize
12715 *
12716 * i40e_sw_init initializes the Adapter private data structure.
12717 * Fields are initialized based on PCI device information and
12718 * OS network device settings (MTU size).
12719 **/
i40e_sw_init(struct i40e_pf * pf)12720 static int i40e_sw_init(struct i40e_pf *pf)
12721 {
12722 int err = 0;
12723 int size;
12724 u16 pow;
12725
12726 /* Set default capability flags */
12727 bitmap_zero(pf->flags, I40E_PF_FLAGS_NBITS);
12728 set_bit(I40E_FLAG_MSI_ENA, pf->flags);
12729 set_bit(I40E_FLAG_MSIX_ENA, pf->flags);
12730
12731 /* Set default ITR */
12732 pf->rx_itr_default = I40E_ITR_RX_DEF;
12733 pf->tx_itr_default = I40E_ITR_TX_DEF;
12734
12735 /* Depending on PF configurations, it is possible that the RSS
12736 * maximum might end up larger than the available queues
12737 */
12738 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
12739 pf->alloc_rss_size = 1;
12740 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
12741 pf->rss_size_max = min_t(int, pf->rss_size_max,
12742 pf->hw.func_caps.num_tx_qp);
12743
12744 /* find the next higher power-of-2 of num cpus */
12745 pow = roundup_pow_of_two(num_online_cpus());
12746 pf->rss_size_max = min_t(int, pf->rss_size_max, pow);
12747
12748 if (pf->hw.func_caps.rss) {
12749 set_bit(I40E_FLAG_RSS_ENA, pf->flags);
12750 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
12751 num_online_cpus());
12752 }
12753
12754 /* MFP mode enabled */
12755 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
12756 set_bit(I40E_FLAG_MFP_ENA, pf->flags);
12757 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
12758 if (i40e_get_partition_bw_setting(pf)) {
12759 dev_warn(&pf->pdev->dev,
12760 "Could not get partition bw settings\n");
12761 } else {
12762 dev_info(&pf->pdev->dev,
12763 "Partition BW Min = %8.8x, Max = %8.8x\n",
12764 pf->min_bw, pf->max_bw);
12765
12766 /* nudge the Tx scheduler */
12767 i40e_set_partition_bw_setting(pf);
12768 }
12769 }
12770
12771 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
12772 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
12773 set_bit(I40E_FLAG_FD_ATR_ENA, pf->flags);
12774 if (test_bit(I40E_FLAG_MFP_ENA, pf->flags) &&
12775 pf->hw.num_partitions > 1)
12776 dev_info(&pf->pdev->dev,
12777 "Flow Director Sideband mode Disabled in MFP mode\n");
12778 else
12779 set_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
12780 pf->fdir_pf_filter_count =
12781 pf->hw.func_caps.fd_filters_guaranteed;
12782 pf->hw.fdir_shared_filter_count =
12783 pf->hw.func_caps.fd_filters_best_effort;
12784 }
12785
12786 /* Enable HW ATR eviction if possible */
12787 if (test_bit(I40E_HW_CAP_ATR_EVICT, pf->hw.caps))
12788 set_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags);
12789
12790 if (pf->hw.func_caps.vmdq && num_online_cpus() != 1) {
12791 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
12792 set_bit(I40E_FLAG_VMDQ_ENA, pf->flags);
12793 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
12794 }
12795
12796 if (pf->hw.func_caps.iwarp && num_online_cpus() != 1) {
12797 set_bit(I40E_FLAG_IWARP_ENA, pf->flags);
12798 /* IWARP needs one extra vector for CQP just like MISC.*/
12799 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
12800 }
12801 /* Stopping FW LLDP engine is supported on XL710 and X722
12802 * starting from FW versions determined in i40e_init_adminq.
12803 * Stopping the FW LLDP engine is not supported on XL710
12804 * if NPAR is functioning so unset this hw flag in this case.
12805 */
12806 if (pf->hw.mac.type == I40E_MAC_XL710 &&
12807 pf->hw.func_caps.npar_enable)
12808 clear_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, pf->hw.caps);
12809
12810 #ifdef CONFIG_PCI_IOV
12811 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
12812 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
12813 set_bit(I40E_FLAG_SRIOV_ENA, pf->flags);
12814 pf->num_req_vfs = min_t(int,
12815 pf->hw.func_caps.num_vfs,
12816 I40E_MAX_VF_COUNT);
12817 }
12818 #endif /* CONFIG_PCI_IOV */
12819 pf->lan_veb = I40E_NO_VEB;
12820 pf->lan_vsi = I40E_NO_VSI;
12821
12822 /* By default FW has this off for performance reasons */
12823 clear_bit(I40E_FLAG_VEB_STATS_ENA, pf->flags);
12824
12825 /* set up queue assignment tracking */
12826 size = sizeof(struct i40e_lump_tracking)
12827 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
12828 pf->qp_pile = kzalloc(size, GFP_KERNEL);
12829 if (!pf->qp_pile) {
12830 err = -ENOMEM;
12831 goto sw_init_done;
12832 }
12833 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
12834
12835 pf->tx_timeout_recovery_level = 1;
12836
12837 if (pf->hw.mac.type != I40E_MAC_X722 &&
12838 i40e_is_total_port_shutdown_enabled(pf)) {
12839 /* Link down on close must be on when total port shutdown
12840 * is enabled for a given port
12841 */
12842 set_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, pf->flags);
12843 set_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, pf->flags);
12844 dev_info(&pf->pdev->dev,
12845 "total-port-shutdown was enabled, link-down-on-close is forced on\n");
12846 }
12847 mutex_init(&pf->switch_mutex);
12848
12849 sw_init_done:
12850 return err;
12851 }
12852
12853 /**
12854 * i40e_set_ntuple - set the ntuple feature flag and take action
12855 * @pf: board private structure to initialize
12856 * @features: the feature set that the stack is suggesting
12857 *
12858 * returns a bool to indicate if reset needs to happen
12859 **/
i40e_set_ntuple(struct i40e_pf * pf,netdev_features_t features)12860 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
12861 {
12862 bool need_reset = false;
12863
12864 /* Check if Flow Director n-tuple support was enabled or disabled. If
12865 * the state changed, we need to reset.
12866 */
12867 if (features & NETIF_F_NTUPLE) {
12868 /* Enable filters and mark for reset */
12869 if (!test_bit(I40E_FLAG_FD_SB_ENA, pf->flags))
12870 need_reset = true;
12871 /* enable FD_SB only if there is MSI-X vector and no cloud
12872 * filters exist
12873 */
12874 if (pf->num_fdsb_msix > 0 && !pf->num_cloud_filters) {
12875 set_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
12876 clear_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
12877 }
12878 } else {
12879 /* turn off filters, mark for reset and clear SW filter list */
12880 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags)) {
12881 need_reset = true;
12882 i40e_fdir_filter_exit(pf);
12883 }
12884 clear_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
12885 clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state);
12886 set_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
12887
12888 /* reset fd counters */
12889 pf->fd_add_err = 0;
12890 pf->fd_atr_cnt = 0;
12891 /* if ATR was auto disabled it can be re-enabled. */
12892 if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
12893 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) &&
12894 (I40E_DEBUG_FD & pf->hw.debug_mask))
12895 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
12896 }
12897 return need_reset;
12898 }
12899
12900 /**
12901 * i40e_clear_rss_lut - clear the rx hash lookup table
12902 * @vsi: the VSI being configured
12903 **/
i40e_clear_rss_lut(struct i40e_vsi * vsi)12904 static void i40e_clear_rss_lut(struct i40e_vsi *vsi)
12905 {
12906 struct i40e_pf *pf = vsi->back;
12907 struct i40e_hw *hw = &pf->hw;
12908 u16 vf_id = vsi->vf_id;
12909 u8 i;
12910
12911 if (vsi->type == I40E_VSI_MAIN) {
12912 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
12913 wr32(hw, I40E_PFQF_HLUT(i), 0);
12914 } else if (vsi->type == I40E_VSI_SRIOV) {
12915 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
12916 i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0);
12917 } else {
12918 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
12919 }
12920 }
12921
12922 /**
12923 * i40e_set_loopback - turn on/off loopback mode on underlying PF
12924 * @vsi: ptr to VSI
12925 * @ena: flag to indicate the on/off setting
12926 */
i40e_set_loopback(struct i40e_vsi * vsi,bool ena)12927 static int i40e_set_loopback(struct i40e_vsi *vsi, bool ena)
12928 {
12929 bool if_running = netif_running(vsi->netdev) &&
12930 !test_and_set_bit(__I40E_VSI_DOWN, vsi->state);
12931 int ret;
12932
12933 if (if_running)
12934 i40e_down(vsi);
12935
12936 ret = i40e_aq_set_mac_loopback(&vsi->back->hw, ena, NULL);
12937 if (ret)
12938 netdev_err(vsi->netdev, "Failed to toggle loopback state\n");
12939 if (if_running)
12940 i40e_up(vsi);
12941
12942 return ret;
12943 }
12944
12945 /**
12946 * i40e_set_features - set the netdev feature flags
12947 * @netdev: ptr to the netdev being adjusted
12948 * @features: the feature set that the stack is suggesting
12949 * Note: expects to be called while under rtnl_lock()
12950 **/
i40e_set_features(struct net_device * netdev,netdev_features_t features)12951 static int i40e_set_features(struct net_device *netdev,
12952 netdev_features_t features)
12953 {
12954 struct i40e_netdev_priv *np = netdev_priv(netdev);
12955 struct i40e_vsi *vsi = np->vsi;
12956 struct i40e_pf *pf = vsi->back;
12957 bool need_reset;
12958
12959 if (features & NETIF_F_RXHASH && !(netdev->features & NETIF_F_RXHASH))
12960 i40e_pf_config_rss(pf);
12961 else if (!(features & NETIF_F_RXHASH) &&
12962 netdev->features & NETIF_F_RXHASH)
12963 i40e_clear_rss_lut(vsi);
12964
12965 if (features & NETIF_F_HW_VLAN_CTAG_RX)
12966 i40e_vlan_stripping_enable(vsi);
12967 else
12968 i40e_vlan_stripping_disable(vsi);
12969
12970 if (!(features & NETIF_F_HW_TC) &&
12971 (netdev->features & NETIF_F_HW_TC) && pf->num_cloud_filters) {
12972 dev_err(&pf->pdev->dev,
12973 "Offloaded tc filters active, can't turn hw_tc_offload off");
12974 return -EINVAL;
12975 }
12976
12977 if (!(features & NETIF_F_HW_L2FW_DOFFLOAD) && vsi->macvlan_cnt)
12978 i40e_del_all_macvlans(vsi);
12979
12980 need_reset = i40e_set_ntuple(pf, features);
12981
12982 if (need_reset)
12983 i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);
12984
12985 if ((features ^ netdev->features) & NETIF_F_LOOPBACK)
12986 return i40e_set_loopback(vsi, !!(features & NETIF_F_LOOPBACK));
12987
12988 return 0;
12989 }
12990
i40e_udp_tunnel_set_port(struct net_device * netdev,unsigned int table,unsigned int idx,struct udp_tunnel_info * ti)12991 static int i40e_udp_tunnel_set_port(struct net_device *netdev,
12992 unsigned int table, unsigned int idx,
12993 struct udp_tunnel_info *ti)
12994 {
12995 struct i40e_netdev_priv *np = netdev_priv(netdev);
12996 struct i40e_hw *hw = &np->vsi->back->hw;
12997 u8 type, filter_index;
12998 int ret;
12999
13000 type = ti->type == UDP_TUNNEL_TYPE_VXLAN ? I40E_AQC_TUNNEL_TYPE_VXLAN :
13001 I40E_AQC_TUNNEL_TYPE_NGE;
13002
13003 ret = i40e_aq_add_udp_tunnel(hw, ntohs(ti->port), type, &filter_index,
13004 NULL);
13005 if (ret) {
13006 netdev_info(netdev, "add UDP port failed, err %pe aq_err %s\n",
13007 ERR_PTR(ret),
13008 i40e_aq_str(hw, hw->aq.asq_last_status));
13009 return -EIO;
13010 }
13011
13012 udp_tunnel_nic_set_port_priv(netdev, table, idx, filter_index);
13013 return 0;
13014 }
13015
i40e_udp_tunnel_unset_port(struct net_device * netdev,unsigned int table,unsigned int idx,struct udp_tunnel_info * ti)13016 static int i40e_udp_tunnel_unset_port(struct net_device *netdev,
13017 unsigned int table, unsigned int idx,
13018 struct udp_tunnel_info *ti)
13019 {
13020 struct i40e_netdev_priv *np = netdev_priv(netdev);
13021 struct i40e_hw *hw = &np->vsi->back->hw;
13022 int ret;
13023
13024 ret = i40e_aq_del_udp_tunnel(hw, ti->hw_priv, NULL);
13025 if (ret) {
13026 netdev_info(netdev, "delete UDP port failed, err %pe aq_err %s\n",
13027 ERR_PTR(ret),
13028 i40e_aq_str(hw, hw->aq.asq_last_status));
13029 return -EIO;
13030 }
13031
13032 return 0;
13033 }
13034
i40e_get_phys_port_id(struct net_device * netdev,struct netdev_phys_item_id * ppid)13035 static int i40e_get_phys_port_id(struct net_device *netdev,
13036 struct netdev_phys_item_id *ppid)
13037 {
13038 struct i40e_netdev_priv *np = netdev_priv(netdev);
13039 struct i40e_pf *pf = np->vsi->back;
13040 struct i40e_hw *hw = &pf->hw;
13041
13042 if (!test_bit(I40E_HW_CAP_PORT_ID_VALID, pf->hw.caps))
13043 return -EOPNOTSUPP;
13044
13045 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
13046 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
13047
13048 return 0;
13049 }
13050
13051 /**
13052 * i40e_ndo_fdb_add - add an entry to the hardware database
13053 * @ndm: the input from the stack
13054 * @tb: pointer to array of nladdr (unused)
13055 * @dev: the net device pointer
13056 * @addr: the MAC address entry being added
13057 * @vid: VLAN ID
13058 * @flags: instructions from stack about fdb operation
13059 * @extack: netlink extended ack, unused currently
13060 */
i40e_ndo_fdb_add(struct ndmsg * ndm,struct nlattr * tb[],struct net_device * dev,const unsigned char * addr,u16 vid,u16 flags,struct netlink_ext_ack * extack)13061 static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
13062 struct net_device *dev,
13063 const unsigned char *addr, u16 vid,
13064 u16 flags,
13065 struct netlink_ext_ack *extack)
13066 {
13067 struct i40e_netdev_priv *np = netdev_priv(dev);
13068 struct i40e_pf *pf = np->vsi->back;
13069 int err = 0;
13070
13071 if (!test_bit(I40E_FLAG_SRIOV_ENA, pf->flags))
13072 return -EOPNOTSUPP;
13073
13074 if (vid) {
13075 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
13076 return -EINVAL;
13077 }
13078
13079 /* Hardware does not support aging addresses so if a
13080 * ndm_state is given only allow permanent addresses
13081 */
13082 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
13083 netdev_info(dev, "FDB only supports static addresses\n");
13084 return -EINVAL;
13085 }
13086
13087 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
13088 err = dev_uc_add_excl(dev, addr);
13089 else if (is_multicast_ether_addr(addr))
13090 err = dev_mc_add_excl(dev, addr);
13091 else
13092 err = -EINVAL;
13093
13094 /* Only return duplicate errors if NLM_F_EXCL is set */
13095 if (err == -EEXIST && !(flags & NLM_F_EXCL))
13096 err = 0;
13097
13098 return err;
13099 }
13100
13101 /**
13102 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
13103 * @dev: the netdev being configured
13104 * @nlh: RTNL message
13105 * @flags: bridge flags
13106 * @extack: netlink extended ack
13107 *
13108 * Inserts a new hardware bridge if not already created and
13109 * enables the bridging mode requested (VEB or VEPA). If the
13110 * hardware bridge has already been inserted and the request
13111 * is to change the mode then that requires a PF reset to
13112 * allow rebuild of the components with required hardware
13113 * bridge mode enabled.
13114 *
13115 * Note: expects to be called while under rtnl_lock()
13116 **/
i40e_ndo_bridge_setlink(struct net_device * dev,struct nlmsghdr * nlh,u16 flags,struct netlink_ext_ack * extack)13117 static int i40e_ndo_bridge_setlink(struct net_device *dev,
13118 struct nlmsghdr *nlh,
13119 u16 flags,
13120 struct netlink_ext_ack *extack)
13121 {
13122 struct i40e_netdev_priv *np = netdev_priv(dev);
13123 struct i40e_vsi *vsi = np->vsi;
13124 struct i40e_pf *pf = vsi->back;
13125 struct i40e_veb *veb = NULL;
13126 struct nlattr *attr, *br_spec;
13127 int i, rem;
13128
13129 /* Only for PF VSI for now */
13130 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
13131 return -EOPNOTSUPP;
13132
13133 /* Find the HW bridge for PF VSI */
13134 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
13135 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
13136 veb = pf->veb[i];
13137 }
13138
13139 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
13140 if (!br_spec)
13141 return -EINVAL;
13142
13143 nla_for_each_nested(attr, br_spec, rem) {
13144 __u16 mode;
13145
13146 if (nla_type(attr) != IFLA_BRIDGE_MODE)
13147 continue;
13148
13149 mode = nla_get_u16(attr);
13150 if ((mode != BRIDGE_MODE_VEPA) &&
13151 (mode != BRIDGE_MODE_VEB))
13152 return -EINVAL;
13153
13154 /* Insert a new HW bridge */
13155 if (!veb) {
13156 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
13157 vsi->tc_config.enabled_tc);
13158 if (veb) {
13159 veb->bridge_mode = mode;
13160 i40e_config_bridge_mode(veb);
13161 } else {
13162 /* No Bridge HW offload available */
13163 return -ENOENT;
13164 }
13165 break;
13166 } else if (mode != veb->bridge_mode) {
13167 /* Existing HW bridge but different mode needs reset */
13168 veb->bridge_mode = mode;
13169 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
13170 if (mode == BRIDGE_MODE_VEB)
13171 set_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
13172 else
13173 clear_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
13174 i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);
13175 break;
13176 }
13177 }
13178
13179 return 0;
13180 }
13181
13182 /**
13183 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
13184 * @skb: skb buff
13185 * @pid: process id
13186 * @seq: RTNL message seq #
13187 * @dev: the netdev being configured
13188 * @filter_mask: unused
13189 * @nlflags: netlink flags passed in
13190 *
13191 * Return the mode in which the hardware bridge is operating in
13192 * i.e VEB or VEPA.
13193 **/
i40e_ndo_bridge_getlink(struct sk_buff * skb,u32 pid,u32 seq,struct net_device * dev,u32 __always_unused filter_mask,int nlflags)13194 static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
13195 struct net_device *dev,
13196 u32 __always_unused filter_mask,
13197 int nlflags)
13198 {
13199 struct i40e_netdev_priv *np = netdev_priv(dev);
13200 struct i40e_vsi *vsi = np->vsi;
13201 struct i40e_pf *pf = vsi->back;
13202 struct i40e_veb *veb = NULL;
13203 int i;
13204
13205 /* Only for PF VSI for now */
13206 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
13207 return -EOPNOTSUPP;
13208
13209 /* Find the HW bridge for the PF VSI */
13210 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
13211 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
13212 veb = pf->veb[i];
13213 }
13214
13215 if (!veb)
13216 return 0;
13217
13218 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
13219 0, 0, nlflags, filter_mask, NULL);
13220 }
13221
13222 /**
13223 * i40e_features_check - Validate encapsulated packet conforms to limits
13224 * @skb: skb buff
13225 * @dev: This physical port's netdev
13226 * @features: Offload features that the stack believes apply
13227 **/
i40e_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)13228 static netdev_features_t i40e_features_check(struct sk_buff *skb,
13229 struct net_device *dev,
13230 netdev_features_t features)
13231 {
13232 size_t len;
13233
13234 /* No point in doing any of this if neither checksum nor GSO are
13235 * being requested for this frame. We can rule out both by just
13236 * checking for CHECKSUM_PARTIAL
13237 */
13238 if (skb->ip_summed != CHECKSUM_PARTIAL)
13239 return features;
13240
13241 /* We cannot support GSO if the MSS is going to be less than
13242 * 64 bytes. If it is then we need to drop support for GSO.
13243 */
13244 if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_size < 64))
13245 features &= ~NETIF_F_GSO_MASK;
13246
13247 /* MACLEN can support at most 63 words */
13248 len = skb_network_header(skb) - skb->data;
13249 if (len & ~(63 * 2))
13250 goto out_err;
13251
13252 /* IPLEN and EIPLEN can support at most 127 dwords */
13253 len = skb_transport_header(skb) - skb_network_header(skb);
13254 if (len & ~(127 * 4))
13255 goto out_err;
13256
13257 if (skb->encapsulation) {
13258 /* L4TUNLEN can support 127 words */
13259 len = skb_inner_network_header(skb) - skb_transport_header(skb);
13260 if (len & ~(127 * 2))
13261 goto out_err;
13262
13263 /* IPLEN can support at most 127 dwords */
13264 len = skb_inner_transport_header(skb) -
13265 skb_inner_network_header(skb);
13266 if (len & ~(127 * 4))
13267 goto out_err;
13268 }
13269
13270 /* No need to validate L4LEN as TCP is the only protocol with a
13271 * flexible value and we support all possible values supported
13272 * by TCP, which is at most 15 dwords
13273 */
13274
13275 return features;
13276 out_err:
13277 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
13278 }
13279
13280 /**
13281 * i40e_xdp_setup - add/remove an XDP program
13282 * @vsi: VSI to changed
13283 * @prog: XDP program
13284 * @extack: netlink extended ack
13285 **/
i40e_xdp_setup(struct i40e_vsi * vsi,struct bpf_prog * prog,struct netlink_ext_ack * extack)13286 static int i40e_xdp_setup(struct i40e_vsi *vsi, struct bpf_prog *prog,
13287 struct netlink_ext_ack *extack)
13288 {
13289 int frame_size = i40e_max_vsi_frame_size(vsi, prog);
13290 struct i40e_pf *pf = vsi->back;
13291 struct bpf_prog *old_prog;
13292 bool need_reset;
13293 int i;
13294
13295 /* Don't allow frames that span over multiple buffers */
13296 if (vsi->netdev->mtu > frame_size - I40E_PACKET_HDR_PAD) {
13297 NL_SET_ERR_MSG_MOD(extack, "MTU too large for linear frames and XDP prog does not support frags");
13298 return -EINVAL;
13299 }
13300
13301 /* When turning XDP on->off/off->on we reset and rebuild the rings. */
13302 need_reset = (i40e_enabled_xdp_vsi(vsi) != !!prog);
13303
13304 if (need_reset)
13305 i40e_prep_for_reset(pf);
13306
13307 /* VSI shall be deleted in a moment, just return EINVAL */
13308 if (test_bit(__I40E_IN_REMOVE, pf->state))
13309 return -EINVAL;
13310
13311 old_prog = xchg(&vsi->xdp_prog, prog);
13312
13313 if (need_reset) {
13314 if (!prog) {
13315 xdp_features_clear_redirect_target(vsi->netdev);
13316 /* Wait until ndo_xsk_wakeup completes. */
13317 synchronize_rcu();
13318 }
13319 i40e_reset_and_rebuild(pf, true, true);
13320 }
13321
13322 if (!i40e_enabled_xdp_vsi(vsi) && prog) {
13323 if (i40e_realloc_rx_bi_zc(vsi, true))
13324 return -ENOMEM;
13325 } else if (i40e_enabled_xdp_vsi(vsi) && !prog) {
13326 if (i40e_realloc_rx_bi_zc(vsi, false))
13327 return -ENOMEM;
13328 }
13329
13330 for (i = 0; i < vsi->num_queue_pairs; i++)
13331 WRITE_ONCE(vsi->rx_rings[i]->xdp_prog, vsi->xdp_prog);
13332
13333 if (old_prog)
13334 bpf_prog_put(old_prog);
13335
13336 /* Kick start the NAPI context if there is an AF_XDP socket open
13337 * on that queue id. This so that receiving will start.
13338 */
13339 if (need_reset && prog) {
13340 for (i = 0; i < vsi->num_queue_pairs; i++)
13341 if (vsi->xdp_rings[i]->xsk_pool)
13342 (void)i40e_xsk_wakeup(vsi->netdev, i,
13343 XDP_WAKEUP_RX);
13344 xdp_features_set_redirect_target(vsi->netdev, true);
13345 }
13346
13347 return 0;
13348 }
13349
13350 /**
13351 * i40e_enter_busy_conf - Enters busy config state
13352 * @vsi: vsi
13353 *
13354 * Returns 0 on success, <0 for failure.
13355 **/
i40e_enter_busy_conf(struct i40e_vsi * vsi)13356 static int i40e_enter_busy_conf(struct i40e_vsi *vsi)
13357 {
13358 struct i40e_pf *pf = vsi->back;
13359 int timeout = 50;
13360
13361 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
13362 timeout--;
13363 if (!timeout)
13364 return -EBUSY;
13365 usleep_range(1000, 2000);
13366 }
13367
13368 return 0;
13369 }
13370
13371 /**
13372 * i40e_exit_busy_conf - Exits busy config state
13373 * @vsi: vsi
13374 **/
i40e_exit_busy_conf(struct i40e_vsi * vsi)13375 static void i40e_exit_busy_conf(struct i40e_vsi *vsi)
13376 {
13377 struct i40e_pf *pf = vsi->back;
13378
13379 clear_bit(__I40E_CONFIG_BUSY, pf->state);
13380 }
13381
13382 /**
13383 * i40e_queue_pair_reset_stats - Resets all statistics for a queue pair
13384 * @vsi: vsi
13385 * @queue_pair: queue pair
13386 **/
i40e_queue_pair_reset_stats(struct i40e_vsi * vsi,int queue_pair)13387 static void i40e_queue_pair_reset_stats(struct i40e_vsi *vsi, int queue_pair)
13388 {
13389 memset(&vsi->rx_rings[queue_pair]->rx_stats, 0,
13390 sizeof(vsi->rx_rings[queue_pair]->rx_stats));
13391 memset(&vsi->tx_rings[queue_pair]->stats, 0,
13392 sizeof(vsi->tx_rings[queue_pair]->stats));
13393 if (i40e_enabled_xdp_vsi(vsi)) {
13394 memset(&vsi->xdp_rings[queue_pair]->stats, 0,
13395 sizeof(vsi->xdp_rings[queue_pair]->stats));
13396 }
13397 }
13398
13399 /**
13400 * i40e_queue_pair_clean_rings - Cleans all the rings of a queue pair
13401 * @vsi: vsi
13402 * @queue_pair: queue pair
13403 **/
i40e_queue_pair_clean_rings(struct i40e_vsi * vsi,int queue_pair)13404 static void i40e_queue_pair_clean_rings(struct i40e_vsi *vsi, int queue_pair)
13405 {
13406 i40e_clean_tx_ring(vsi->tx_rings[queue_pair]);
13407 if (i40e_enabled_xdp_vsi(vsi)) {
13408 /* Make sure that in-progress ndo_xdp_xmit calls are
13409 * completed.
13410 */
13411 synchronize_rcu();
13412 i40e_clean_tx_ring(vsi->xdp_rings[queue_pair]);
13413 }
13414 i40e_clean_rx_ring(vsi->rx_rings[queue_pair]);
13415 }
13416
13417 /**
13418 * i40e_queue_pair_toggle_napi - Enables/disables NAPI for a queue pair
13419 * @vsi: vsi
13420 * @queue_pair: queue pair
13421 * @enable: true for enable, false for disable
13422 **/
i40e_queue_pair_toggle_napi(struct i40e_vsi * vsi,int queue_pair,bool enable)13423 static void i40e_queue_pair_toggle_napi(struct i40e_vsi *vsi, int queue_pair,
13424 bool enable)
13425 {
13426 struct i40e_ring *rxr = vsi->rx_rings[queue_pair];
13427 struct i40e_q_vector *q_vector = rxr->q_vector;
13428
13429 if (!vsi->netdev)
13430 return;
13431
13432 /* All rings in a qp belong to the same qvector. */
13433 if (q_vector->rx.ring || q_vector->tx.ring) {
13434 if (enable)
13435 napi_enable(&q_vector->napi);
13436 else
13437 napi_disable(&q_vector->napi);
13438 }
13439 }
13440
13441 /**
13442 * i40e_queue_pair_toggle_rings - Enables/disables all rings for a queue pair
13443 * @vsi: vsi
13444 * @queue_pair: queue pair
13445 * @enable: true for enable, false for disable
13446 *
13447 * Returns 0 on success, <0 on failure.
13448 **/
i40e_queue_pair_toggle_rings(struct i40e_vsi * vsi,int queue_pair,bool enable)13449 static int i40e_queue_pair_toggle_rings(struct i40e_vsi *vsi, int queue_pair,
13450 bool enable)
13451 {
13452 struct i40e_pf *pf = vsi->back;
13453 int pf_q, ret = 0;
13454
13455 pf_q = vsi->base_queue + queue_pair;
13456 ret = i40e_control_wait_tx_q(vsi->seid, pf, pf_q,
13457 false /*is xdp*/, enable);
13458 if (ret) {
13459 dev_info(&pf->pdev->dev,
13460 "VSI seid %d Tx ring %d %sable timeout\n",
13461 vsi->seid, pf_q, (enable ? "en" : "dis"));
13462 return ret;
13463 }
13464
13465 i40e_control_rx_q(pf, pf_q, enable);
13466 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
13467 if (ret) {
13468 dev_info(&pf->pdev->dev,
13469 "VSI seid %d Rx ring %d %sable timeout\n",
13470 vsi->seid, pf_q, (enable ? "en" : "dis"));
13471 return ret;
13472 }
13473
13474 /* Due to HW errata, on Rx disable only, the register can
13475 * indicate done before it really is. Needs 50ms to be sure
13476 */
13477 if (!enable)
13478 mdelay(50);
13479
13480 if (!i40e_enabled_xdp_vsi(vsi))
13481 return ret;
13482
13483 ret = i40e_control_wait_tx_q(vsi->seid, pf,
13484 pf_q + vsi->alloc_queue_pairs,
13485 true /*is xdp*/, enable);
13486 if (ret) {
13487 dev_info(&pf->pdev->dev,
13488 "VSI seid %d XDP Tx ring %d %sable timeout\n",
13489 vsi->seid, pf_q, (enable ? "en" : "dis"));
13490 }
13491
13492 return ret;
13493 }
13494
13495 /**
13496 * i40e_queue_pair_enable_irq - Enables interrupts for a queue pair
13497 * @vsi: vsi
13498 * @queue_pair: queue_pair
13499 **/
i40e_queue_pair_enable_irq(struct i40e_vsi * vsi,int queue_pair)13500 static void i40e_queue_pair_enable_irq(struct i40e_vsi *vsi, int queue_pair)
13501 {
13502 struct i40e_ring *rxr = vsi->rx_rings[queue_pair];
13503 struct i40e_pf *pf = vsi->back;
13504 struct i40e_hw *hw = &pf->hw;
13505
13506 /* All rings in a qp belong to the same qvector. */
13507 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
13508 i40e_irq_dynamic_enable(vsi, rxr->q_vector->v_idx);
13509 else
13510 i40e_irq_dynamic_enable_icr0(pf);
13511
13512 i40e_flush(hw);
13513 }
13514
13515 /**
13516 * i40e_queue_pair_disable_irq - Disables interrupts for a queue pair
13517 * @vsi: vsi
13518 * @queue_pair: queue_pair
13519 **/
i40e_queue_pair_disable_irq(struct i40e_vsi * vsi,int queue_pair)13520 static void i40e_queue_pair_disable_irq(struct i40e_vsi *vsi, int queue_pair)
13521 {
13522 struct i40e_ring *rxr = vsi->rx_rings[queue_pair];
13523 struct i40e_pf *pf = vsi->back;
13524 struct i40e_hw *hw = &pf->hw;
13525
13526 /* For simplicity, instead of removing the qp interrupt causes
13527 * from the interrupt linked list, we simply disable the interrupt, and
13528 * leave the list intact.
13529 *
13530 * All rings in a qp belong to the same qvector.
13531 */
13532 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
13533 u32 intpf = vsi->base_vector + rxr->q_vector->v_idx;
13534
13535 wr32(hw, I40E_PFINT_DYN_CTLN(intpf - 1), 0);
13536 i40e_flush(hw);
13537 synchronize_irq(pf->msix_entries[intpf].vector);
13538 } else {
13539 /* Legacy and MSI mode - this stops all interrupt handling */
13540 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
13541 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
13542 i40e_flush(hw);
13543 synchronize_irq(pf->pdev->irq);
13544 }
13545 }
13546
13547 /**
13548 * i40e_queue_pair_disable - Disables a queue pair
13549 * @vsi: vsi
13550 * @queue_pair: queue pair
13551 *
13552 * Returns 0 on success, <0 on failure.
13553 **/
i40e_queue_pair_disable(struct i40e_vsi * vsi,int queue_pair)13554 int i40e_queue_pair_disable(struct i40e_vsi *vsi, int queue_pair)
13555 {
13556 int err;
13557
13558 err = i40e_enter_busy_conf(vsi);
13559 if (err)
13560 return err;
13561
13562 i40e_queue_pair_disable_irq(vsi, queue_pair);
13563 i40e_queue_pair_toggle_napi(vsi, queue_pair, false /* off */);
13564 err = i40e_queue_pair_toggle_rings(vsi, queue_pair, false /* off */);
13565 i40e_clean_rx_ring(vsi->rx_rings[queue_pair]);
13566 i40e_queue_pair_clean_rings(vsi, queue_pair);
13567 i40e_queue_pair_reset_stats(vsi, queue_pair);
13568
13569 return err;
13570 }
13571
13572 /**
13573 * i40e_queue_pair_enable - Enables a queue pair
13574 * @vsi: vsi
13575 * @queue_pair: queue pair
13576 *
13577 * Returns 0 on success, <0 on failure.
13578 **/
i40e_queue_pair_enable(struct i40e_vsi * vsi,int queue_pair)13579 int i40e_queue_pair_enable(struct i40e_vsi *vsi, int queue_pair)
13580 {
13581 int err;
13582
13583 err = i40e_configure_tx_ring(vsi->tx_rings[queue_pair]);
13584 if (err)
13585 return err;
13586
13587 if (i40e_enabled_xdp_vsi(vsi)) {
13588 err = i40e_configure_tx_ring(vsi->xdp_rings[queue_pair]);
13589 if (err)
13590 return err;
13591 }
13592
13593 err = i40e_configure_rx_ring(vsi->rx_rings[queue_pair]);
13594 if (err)
13595 return err;
13596
13597 err = i40e_queue_pair_toggle_rings(vsi, queue_pair, true /* on */);
13598 i40e_queue_pair_toggle_napi(vsi, queue_pair, true /* on */);
13599 i40e_queue_pair_enable_irq(vsi, queue_pair);
13600
13601 i40e_exit_busy_conf(vsi);
13602
13603 return err;
13604 }
13605
13606 /**
13607 * i40e_xdp - implements ndo_bpf for i40e
13608 * @dev: netdevice
13609 * @xdp: XDP command
13610 **/
i40e_xdp(struct net_device * dev,struct netdev_bpf * xdp)13611 static int i40e_xdp(struct net_device *dev,
13612 struct netdev_bpf *xdp)
13613 {
13614 struct i40e_netdev_priv *np = netdev_priv(dev);
13615 struct i40e_vsi *vsi = np->vsi;
13616
13617 if (vsi->type != I40E_VSI_MAIN)
13618 return -EINVAL;
13619
13620 switch (xdp->command) {
13621 case XDP_SETUP_PROG:
13622 return i40e_xdp_setup(vsi, xdp->prog, xdp->extack);
13623 case XDP_SETUP_XSK_POOL:
13624 return i40e_xsk_pool_setup(vsi, xdp->xsk.pool,
13625 xdp->xsk.queue_id);
13626 default:
13627 return -EINVAL;
13628 }
13629 }
13630
13631 static const struct net_device_ops i40e_netdev_ops = {
13632 .ndo_open = i40e_open,
13633 .ndo_stop = i40e_close,
13634 .ndo_start_xmit = i40e_lan_xmit_frame,
13635 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
13636 .ndo_set_rx_mode = i40e_set_rx_mode,
13637 .ndo_validate_addr = eth_validate_addr,
13638 .ndo_set_mac_address = i40e_set_mac,
13639 .ndo_change_mtu = i40e_change_mtu,
13640 .ndo_eth_ioctl = i40e_ioctl,
13641 .ndo_tx_timeout = i40e_tx_timeout,
13642 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
13643 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
13644 #ifdef CONFIG_NET_POLL_CONTROLLER
13645 .ndo_poll_controller = i40e_netpoll,
13646 #endif
13647 .ndo_setup_tc = __i40e_setup_tc,
13648 .ndo_select_queue = i40e_lan_select_queue,
13649 .ndo_set_features = i40e_set_features,
13650 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
13651 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
13652 .ndo_get_vf_stats = i40e_get_vf_stats,
13653 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
13654 .ndo_get_vf_config = i40e_ndo_get_vf_config,
13655 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
13656 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
13657 .ndo_set_vf_trust = i40e_ndo_set_vf_trust,
13658 .ndo_get_phys_port_id = i40e_get_phys_port_id,
13659 .ndo_fdb_add = i40e_ndo_fdb_add,
13660 .ndo_features_check = i40e_features_check,
13661 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
13662 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
13663 .ndo_bpf = i40e_xdp,
13664 .ndo_xdp_xmit = i40e_xdp_xmit,
13665 .ndo_xsk_wakeup = i40e_xsk_wakeup,
13666 .ndo_dfwd_add_station = i40e_fwd_add,
13667 .ndo_dfwd_del_station = i40e_fwd_del,
13668 };
13669
13670 /**
13671 * i40e_config_netdev - Setup the netdev flags
13672 * @vsi: the VSI being configured
13673 *
13674 * Returns 0 on success, negative value on failure
13675 **/
i40e_config_netdev(struct i40e_vsi * vsi)13676 static int i40e_config_netdev(struct i40e_vsi *vsi)
13677 {
13678 struct i40e_pf *pf = vsi->back;
13679 struct i40e_hw *hw = &pf->hw;
13680 struct i40e_netdev_priv *np;
13681 struct net_device *netdev;
13682 u8 broadcast[ETH_ALEN];
13683 u8 mac_addr[ETH_ALEN];
13684 int etherdev_size;
13685 netdev_features_t hw_enc_features;
13686 netdev_features_t hw_features;
13687
13688 etherdev_size = sizeof(struct i40e_netdev_priv);
13689 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
13690 if (!netdev)
13691 return -ENOMEM;
13692
13693 vsi->netdev = netdev;
13694 np = netdev_priv(netdev);
13695 np->vsi = vsi;
13696
13697 hw_enc_features = NETIF_F_SG |
13698 NETIF_F_HW_CSUM |
13699 NETIF_F_HIGHDMA |
13700 NETIF_F_SOFT_FEATURES |
13701 NETIF_F_TSO |
13702 NETIF_F_TSO_ECN |
13703 NETIF_F_TSO6 |
13704 NETIF_F_GSO_GRE |
13705 NETIF_F_GSO_GRE_CSUM |
13706 NETIF_F_GSO_PARTIAL |
13707 NETIF_F_GSO_IPXIP4 |
13708 NETIF_F_GSO_IPXIP6 |
13709 NETIF_F_GSO_UDP_TUNNEL |
13710 NETIF_F_GSO_UDP_TUNNEL_CSUM |
13711 NETIF_F_GSO_UDP_L4 |
13712 NETIF_F_SCTP_CRC |
13713 NETIF_F_RXHASH |
13714 NETIF_F_RXCSUM |
13715 0;
13716
13717 if (!test_bit(I40E_HW_CAP_OUTER_UDP_CSUM, pf->hw.caps))
13718 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
13719
13720 netdev->udp_tunnel_nic_info = &pf->udp_tunnel_nic;
13721
13722 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
13723
13724 netdev->hw_enc_features |= hw_enc_features;
13725
13726 /* record features VLANs can make use of */
13727 netdev->vlan_features |= hw_enc_features | NETIF_F_TSO_MANGLEID;
13728
13729 #define I40E_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
13730 NETIF_F_GSO_GRE_CSUM | \
13731 NETIF_F_GSO_IPXIP4 | \
13732 NETIF_F_GSO_IPXIP6 | \
13733 NETIF_F_GSO_UDP_TUNNEL | \
13734 NETIF_F_GSO_UDP_TUNNEL_CSUM)
13735
13736 netdev->gso_partial_features = I40E_GSO_PARTIAL_FEATURES;
13737 netdev->features |= NETIF_F_GSO_PARTIAL |
13738 I40E_GSO_PARTIAL_FEATURES;
13739
13740 netdev->mpls_features |= NETIF_F_SG;
13741 netdev->mpls_features |= NETIF_F_HW_CSUM;
13742 netdev->mpls_features |= NETIF_F_TSO;
13743 netdev->mpls_features |= NETIF_F_TSO6;
13744 netdev->mpls_features |= I40E_GSO_PARTIAL_FEATURES;
13745
13746 /* enable macvlan offloads */
13747 netdev->hw_features |= NETIF_F_HW_L2FW_DOFFLOAD;
13748
13749 hw_features = hw_enc_features |
13750 NETIF_F_HW_VLAN_CTAG_TX |
13751 NETIF_F_HW_VLAN_CTAG_RX;
13752
13753 if (!test_bit(I40E_FLAG_MFP_ENA, pf->flags))
13754 hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC;
13755
13756 netdev->hw_features |= hw_features | NETIF_F_LOOPBACK;
13757
13758 netdev->features |= hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
13759 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
13760
13761 netdev->features &= ~NETIF_F_HW_TC;
13762
13763 if (vsi->type == I40E_VSI_MAIN) {
13764 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
13765 ether_addr_copy(mac_addr, hw->mac.perm_addr);
13766 /* The following steps are necessary for two reasons. First,
13767 * some older NVM configurations load a default MAC-VLAN
13768 * filter that will accept any tagged packet, and we want to
13769 * replace this with a normal filter. Additionally, it is
13770 * possible our MAC address was provided by the platform using
13771 * Open Firmware or similar.
13772 *
13773 * Thus, we need to remove the default filter and install one
13774 * specific to the MAC address.
13775 */
13776 i40e_rm_default_mac_filter(vsi, mac_addr);
13777 spin_lock_bh(&vsi->mac_filter_hash_lock);
13778 i40e_add_mac_filter(vsi, mac_addr);
13779 spin_unlock_bh(&vsi->mac_filter_hash_lock);
13780
13781 netdev->xdp_features = NETDEV_XDP_ACT_BASIC |
13782 NETDEV_XDP_ACT_REDIRECT |
13783 NETDEV_XDP_ACT_XSK_ZEROCOPY |
13784 NETDEV_XDP_ACT_RX_SG;
13785 netdev->xdp_zc_max_segs = I40E_MAX_BUFFER_TXD;
13786 } else {
13787 /* Relate the VSI_VMDQ name to the VSI_MAIN name. Note that we
13788 * are still limited by IFNAMSIZ, but we're adding 'v%d\0' to
13789 * the end, which is 4 bytes long, so force truncation of the
13790 * original name by IFNAMSIZ - 4
13791 */
13792 snprintf(netdev->name, IFNAMSIZ, "%.*sv%%d",
13793 IFNAMSIZ - 4,
13794 pf->vsi[pf->lan_vsi]->netdev->name);
13795 eth_random_addr(mac_addr);
13796
13797 spin_lock_bh(&vsi->mac_filter_hash_lock);
13798 i40e_add_mac_filter(vsi, mac_addr);
13799 spin_unlock_bh(&vsi->mac_filter_hash_lock);
13800 }
13801
13802 /* Add the broadcast filter so that we initially will receive
13803 * broadcast packets. Note that when a new VLAN is first added the
13804 * driver will convert all filters marked I40E_VLAN_ANY into VLAN
13805 * specific filters as part of transitioning into "vlan" operation.
13806 * When more VLANs are added, the driver will copy each existing MAC
13807 * filter and add it for the new VLAN.
13808 *
13809 * Broadcast filters are handled specially by
13810 * i40e_sync_filters_subtask, as the driver must to set the broadcast
13811 * promiscuous bit instead of adding this directly as a MAC/VLAN
13812 * filter. The subtask will update the correct broadcast promiscuous
13813 * bits as VLANs become active or inactive.
13814 */
13815 eth_broadcast_addr(broadcast);
13816 spin_lock_bh(&vsi->mac_filter_hash_lock);
13817 i40e_add_mac_filter(vsi, broadcast);
13818 spin_unlock_bh(&vsi->mac_filter_hash_lock);
13819
13820 eth_hw_addr_set(netdev, mac_addr);
13821 ether_addr_copy(netdev->perm_addr, mac_addr);
13822
13823 /* i40iw_net_event() reads 16 bytes from neigh->primary_key */
13824 netdev->neigh_priv_len = sizeof(u32) * 4;
13825
13826 netdev->priv_flags |= IFF_UNICAST_FLT;
13827 netdev->priv_flags |= IFF_SUPP_NOFCS;
13828 /* Setup netdev TC information */
13829 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
13830
13831 netdev->netdev_ops = &i40e_netdev_ops;
13832 netdev->watchdog_timeo = 5 * HZ;
13833 i40e_set_ethtool_ops(netdev);
13834
13835 /* MTU range: 68 - 9706 */
13836 netdev->min_mtu = ETH_MIN_MTU;
13837 netdev->max_mtu = I40E_MAX_RXBUFFER - I40E_PACKET_HDR_PAD;
13838
13839 return 0;
13840 }
13841
13842 /**
13843 * i40e_vsi_delete - Delete a VSI from the switch
13844 * @vsi: the VSI being removed
13845 *
13846 * Returns 0 on success, negative value on failure
13847 **/
i40e_vsi_delete(struct i40e_vsi * vsi)13848 static void i40e_vsi_delete(struct i40e_vsi *vsi)
13849 {
13850 /* remove default VSI is not allowed */
13851 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
13852 return;
13853
13854 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
13855 }
13856
13857 /**
13858 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
13859 * @vsi: the VSI being queried
13860 *
13861 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
13862 **/
i40e_is_vsi_uplink_mode_veb(struct i40e_vsi * vsi)13863 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
13864 {
13865 struct i40e_veb *veb;
13866 struct i40e_pf *pf = vsi->back;
13867
13868 /* Uplink is not a bridge so default to VEB */
13869 if (vsi->veb_idx >= I40E_MAX_VEB)
13870 return 1;
13871
13872 veb = pf->veb[vsi->veb_idx];
13873 if (!veb) {
13874 dev_info(&pf->pdev->dev,
13875 "There is no veb associated with the bridge\n");
13876 return -ENOENT;
13877 }
13878
13879 /* Uplink is a bridge in VEPA mode */
13880 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
13881 return 0;
13882 } else {
13883 /* Uplink is a bridge in VEB mode */
13884 return 1;
13885 }
13886
13887 /* VEPA is now default bridge, so return 0 */
13888 return 0;
13889 }
13890
13891 /**
13892 * i40e_add_vsi - Add a VSI to the switch
13893 * @vsi: the VSI being configured
13894 *
13895 * This initializes a VSI context depending on the VSI type to be added and
13896 * passes it down to the add_vsi aq command.
13897 **/
i40e_add_vsi(struct i40e_vsi * vsi)13898 static int i40e_add_vsi(struct i40e_vsi *vsi)
13899 {
13900 int ret = -ENODEV;
13901 struct i40e_pf *pf = vsi->back;
13902 struct i40e_hw *hw = &pf->hw;
13903 struct i40e_vsi_context ctxt;
13904 struct i40e_mac_filter *f;
13905 struct hlist_node *h;
13906 int bkt;
13907
13908 u8 enabled_tc = 0x1; /* TC0 enabled */
13909 int f_count = 0;
13910
13911 memset(&ctxt, 0, sizeof(ctxt));
13912 switch (vsi->type) {
13913 case I40E_VSI_MAIN:
13914 /* The PF's main VSI is already setup as part of the
13915 * device initialization, so we'll not bother with
13916 * the add_vsi call, but we will retrieve the current
13917 * VSI context.
13918 */
13919 ctxt.seid = pf->main_vsi_seid;
13920 ctxt.pf_num = pf->hw.pf_id;
13921 ctxt.vf_num = 0;
13922 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
13923 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
13924 if (ret) {
13925 dev_info(&pf->pdev->dev,
13926 "couldn't get PF vsi config, err %pe aq_err %s\n",
13927 ERR_PTR(ret),
13928 i40e_aq_str(&pf->hw,
13929 pf->hw.aq.asq_last_status));
13930 return -ENOENT;
13931 }
13932 vsi->info = ctxt.info;
13933 vsi->info.valid_sections = 0;
13934
13935 vsi->seid = ctxt.seid;
13936 vsi->id = ctxt.vsi_number;
13937
13938 enabled_tc = i40e_pf_get_tc_map(pf);
13939
13940 /* Source pruning is enabled by default, so the flag is
13941 * negative logic - if it's set, we need to fiddle with
13942 * the VSI to disable source pruning.
13943 */
13944 if (test_bit(I40E_FLAG_SOURCE_PRUNING_DIS, pf->flags)) {
13945 memset(&ctxt, 0, sizeof(ctxt));
13946 ctxt.seid = pf->main_vsi_seid;
13947 ctxt.pf_num = pf->hw.pf_id;
13948 ctxt.vf_num = 0;
13949 ctxt.info.valid_sections |=
13950 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
13951 ctxt.info.switch_id =
13952 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
13953 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
13954 if (ret) {
13955 dev_info(&pf->pdev->dev,
13956 "update vsi failed, err %d aq_err %s\n",
13957 ret,
13958 i40e_aq_str(&pf->hw,
13959 pf->hw.aq.asq_last_status));
13960 ret = -ENOENT;
13961 goto err;
13962 }
13963 }
13964
13965 /* MFP mode setup queue map and update VSI */
13966 if (test_bit(I40E_FLAG_MFP_ENA, pf->flags) &&
13967 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
13968 memset(&ctxt, 0, sizeof(ctxt));
13969 ctxt.seid = pf->main_vsi_seid;
13970 ctxt.pf_num = pf->hw.pf_id;
13971 ctxt.vf_num = 0;
13972 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
13973 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
13974 if (ret) {
13975 dev_info(&pf->pdev->dev,
13976 "update vsi failed, err %pe aq_err %s\n",
13977 ERR_PTR(ret),
13978 i40e_aq_str(&pf->hw,
13979 pf->hw.aq.asq_last_status));
13980 ret = -ENOENT;
13981 goto err;
13982 }
13983 /* update the local VSI info queue map */
13984 i40e_vsi_update_queue_map(vsi, &ctxt);
13985 vsi->info.valid_sections = 0;
13986 } else {
13987 /* Default/Main VSI is only enabled for TC0
13988 * reconfigure it to enable all TCs that are
13989 * available on the port in SFP mode.
13990 * For MFP case the iSCSI PF would use this
13991 * flow to enable LAN+iSCSI TC.
13992 */
13993 ret = i40e_vsi_config_tc(vsi, enabled_tc);
13994 if (ret) {
13995 /* Single TC condition is not fatal,
13996 * message and continue
13997 */
13998 dev_info(&pf->pdev->dev,
13999 "failed to configure TCs for main VSI tc_map 0x%08x, err %pe aq_err %s\n",
14000 enabled_tc,
14001 ERR_PTR(ret),
14002 i40e_aq_str(&pf->hw,
14003 pf->hw.aq.asq_last_status));
14004 }
14005 }
14006 break;
14007
14008 case I40E_VSI_FDIR:
14009 ctxt.pf_num = hw->pf_id;
14010 ctxt.vf_num = 0;
14011 ctxt.uplink_seid = vsi->uplink_seid;
14012 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
14013 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
14014 if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags) &&
14015 (i40e_is_vsi_uplink_mode_veb(vsi))) {
14016 ctxt.info.valid_sections |=
14017 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
14018 ctxt.info.switch_id =
14019 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
14020 }
14021 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
14022 break;
14023
14024 case I40E_VSI_VMDQ2:
14025 ctxt.pf_num = hw->pf_id;
14026 ctxt.vf_num = 0;
14027 ctxt.uplink_seid = vsi->uplink_seid;
14028 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
14029 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
14030
14031 /* This VSI is connected to VEB so the switch_id
14032 * should be set to zero by default.
14033 */
14034 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
14035 ctxt.info.valid_sections |=
14036 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
14037 ctxt.info.switch_id =
14038 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
14039 }
14040
14041 /* Setup the VSI tx/rx queue map for TC0 only for now */
14042 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
14043 break;
14044
14045 case I40E_VSI_SRIOV:
14046 ctxt.pf_num = hw->pf_id;
14047 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
14048 ctxt.uplink_seid = vsi->uplink_seid;
14049 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
14050 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
14051
14052 /* This VSI is connected to VEB so the switch_id
14053 * should be set to zero by default.
14054 */
14055 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
14056 ctxt.info.valid_sections |=
14057 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
14058 ctxt.info.switch_id =
14059 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
14060 }
14061
14062 if (test_bit(I40E_FLAG_IWARP_ENA, vsi->back->flags)) {
14063 ctxt.info.valid_sections |=
14064 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
14065 ctxt.info.queueing_opt_flags |=
14066 (I40E_AQ_VSI_QUE_OPT_TCP_ENA |
14067 I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI);
14068 }
14069
14070 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
14071 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
14072 if (pf->vf[vsi->vf_id].spoofchk) {
14073 ctxt.info.valid_sections |=
14074 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
14075 ctxt.info.sec_flags |=
14076 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
14077 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
14078 }
14079 /* Setup the VSI tx/rx queue map for TC0 only for now */
14080 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
14081 break;
14082
14083 case I40E_VSI_IWARP:
14084 /* send down message to iWARP */
14085 break;
14086
14087 default:
14088 return -ENODEV;
14089 }
14090
14091 if (vsi->type != I40E_VSI_MAIN) {
14092 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
14093 if (ret) {
14094 dev_info(&vsi->back->pdev->dev,
14095 "add vsi failed, err %pe aq_err %s\n",
14096 ERR_PTR(ret),
14097 i40e_aq_str(&pf->hw,
14098 pf->hw.aq.asq_last_status));
14099 ret = -ENOENT;
14100 goto err;
14101 }
14102 vsi->info = ctxt.info;
14103 vsi->info.valid_sections = 0;
14104 vsi->seid = ctxt.seid;
14105 vsi->id = ctxt.vsi_number;
14106 }
14107
14108 spin_lock_bh(&vsi->mac_filter_hash_lock);
14109 vsi->active_filters = 0;
14110 /* If macvlan filters already exist, force them to get loaded */
14111 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
14112 f->state = I40E_FILTER_NEW;
14113 f_count++;
14114 }
14115 spin_unlock_bh(&vsi->mac_filter_hash_lock);
14116 clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
14117
14118 if (f_count) {
14119 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
14120 set_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state);
14121 }
14122
14123 /* Update VSI BW information */
14124 ret = i40e_vsi_get_bw_info(vsi);
14125 if (ret) {
14126 dev_info(&pf->pdev->dev,
14127 "couldn't get vsi bw info, err %pe aq_err %s\n",
14128 ERR_PTR(ret),
14129 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
14130 /* VSI is already added so not tearing that up */
14131 ret = 0;
14132 }
14133
14134 err:
14135 return ret;
14136 }
14137
14138 /**
14139 * i40e_vsi_release - Delete a VSI and free its resources
14140 * @vsi: the VSI being removed
14141 *
14142 * Returns 0 on success or < 0 on error
14143 **/
i40e_vsi_release(struct i40e_vsi * vsi)14144 int i40e_vsi_release(struct i40e_vsi *vsi)
14145 {
14146 struct i40e_mac_filter *f;
14147 struct hlist_node *h;
14148 struct i40e_veb *veb = NULL;
14149 struct i40e_pf *pf;
14150 u16 uplink_seid;
14151 int i, n, bkt;
14152
14153 pf = vsi->back;
14154
14155 /* release of a VEB-owner or last VSI is not allowed */
14156 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
14157 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
14158 vsi->seid, vsi->uplink_seid);
14159 return -ENODEV;
14160 }
14161 if (vsi == pf->vsi[pf->lan_vsi] &&
14162 !test_bit(__I40E_DOWN, pf->state)) {
14163 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
14164 return -ENODEV;
14165 }
14166 set_bit(__I40E_VSI_RELEASING, vsi->state);
14167 uplink_seid = vsi->uplink_seid;
14168
14169 if (vsi->type != I40E_VSI_SRIOV) {
14170 if (vsi->netdev_registered) {
14171 vsi->netdev_registered = false;
14172 if (vsi->netdev) {
14173 /* results in a call to i40e_close() */
14174 unregister_netdev(vsi->netdev);
14175 }
14176 } else {
14177 i40e_vsi_close(vsi);
14178 }
14179 i40e_vsi_disable_irq(vsi);
14180 }
14181
14182 if (vsi->type == I40E_VSI_MAIN)
14183 i40e_devlink_destroy_port(pf);
14184
14185 spin_lock_bh(&vsi->mac_filter_hash_lock);
14186
14187 /* clear the sync flag on all filters */
14188 if (vsi->netdev) {
14189 __dev_uc_unsync(vsi->netdev, NULL);
14190 __dev_mc_unsync(vsi->netdev, NULL);
14191 }
14192
14193 /* make sure any remaining filters are marked for deletion */
14194 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist)
14195 __i40e_del_filter(vsi, f);
14196
14197 spin_unlock_bh(&vsi->mac_filter_hash_lock);
14198
14199 i40e_sync_vsi_filters(vsi);
14200
14201 i40e_vsi_delete(vsi);
14202 i40e_vsi_free_q_vectors(vsi);
14203 if (vsi->netdev) {
14204 free_netdev(vsi->netdev);
14205 vsi->netdev = NULL;
14206 }
14207 i40e_vsi_clear_rings(vsi);
14208 i40e_vsi_clear(vsi);
14209
14210 /* If this was the last thing on the VEB, except for the
14211 * controlling VSI, remove the VEB, which puts the controlling
14212 * VSI onto the next level down in the switch.
14213 *
14214 * Well, okay, there's one more exception here: don't remove
14215 * the orphan VEBs yet. We'll wait for an explicit remove request
14216 * from up the network stack.
14217 */
14218 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
14219 if (pf->vsi[i] &&
14220 pf->vsi[i]->uplink_seid == uplink_seid &&
14221 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
14222 n++; /* count the VSIs */
14223 }
14224 }
14225 for (i = 0; i < I40E_MAX_VEB; i++) {
14226 if (!pf->veb[i])
14227 continue;
14228 if (pf->veb[i]->uplink_seid == uplink_seid)
14229 n++; /* count the VEBs */
14230 if (pf->veb[i]->seid == uplink_seid)
14231 veb = pf->veb[i];
14232 }
14233 if (n == 0 && veb && veb->uplink_seid != 0)
14234 i40e_veb_release(veb);
14235
14236 return 0;
14237 }
14238
14239 /**
14240 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
14241 * @vsi: ptr to the VSI
14242 *
14243 * This should only be called after i40e_vsi_mem_alloc() which allocates the
14244 * corresponding SW VSI structure and initializes num_queue_pairs for the
14245 * newly allocated VSI.
14246 *
14247 * Returns 0 on success or negative on failure
14248 **/
i40e_vsi_setup_vectors(struct i40e_vsi * vsi)14249 static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
14250 {
14251 int ret = -ENOENT;
14252 struct i40e_pf *pf = vsi->back;
14253
14254 if (vsi->q_vectors[0]) {
14255 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
14256 vsi->seid);
14257 return -EEXIST;
14258 }
14259
14260 if (vsi->base_vector) {
14261 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
14262 vsi->seid, vsi->base_vector);
14263 return -EEXIST;
14264 }
14265
14266 ret = i40e_vsi_alloc_q_vectors(vsi);
14267 if (ret) {
14268 dev_info(&pf->pdev->dev,
14269 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
14270 vsi->num_q_vectors, vsi->seid, ret);
14271 vsi->num_q_vectors = 0;
14272 goto vector_setup_out;
14273 }
14274
14275 /* In Legacy mode, we do not have to get any other vector since we
14276 * piggyback on the misc/ICR0 for queue interrupts.
14277 */
14278 if (!test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
14279 return ret;
14280 if (vsi->num_q_vectors)
14281 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
14282 vsi->num_q_vectors, vsi->idx);
14283 if (vsi->base_vector < 0) {
14284 dev_info(&pf->pdev->dev,
14285 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
14286 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
14287 i40e_vsi_free_q_vectors(vsi);
14288 ret = -ENOENT;
14289 goto vector_setup_out;
14290 }
14291
14292 vector_setup_out:
14293 return ret;
14294 }
14295
14296 /**
14297 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
14298 * @vsi: pointer to the vsi.
14299 *
14300 * This re-allocates a vsi's queue resources.
14301 *
14302 * Returns pointer to the successfully allocated and configured VSI sw struct
14303 * on success, otherwise returns NULL on failure.
14304 **/
i40e_vsi_reinit_setup(struct i40e_vsi * vsi)14305 static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
14306 {
14307 u16 alloc_queue_pairs;
14308 struct i40e_pf *pf;
14309 u8 enabled_tc;
14310 int ret;
14311
14312 if (!vsi)
14313 return NULL;
14314
14315 pf = vsi->back;
14316
14317 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
14318 i40e_vsi_clear_rings(vsi);
14319
14320 i40e_vsi_free_arrays(vsi, false);
14321 i40e_set_num_rings_in_vsi(vsi);
14322 ret = i40e_vsi_alloc_arrays(vsi, false);
14323 if (ret)
14324 goto err_vsi;
14325
14326 alloc_queue_pairs = vsi->alloc_queue_pairs *
14327 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
14328
14329 ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx);
14330 if (ret < 0) {
14331 dev_info(&pf->pdev->dev,
14332 "failed to get tracking for %d queues for VSI %d err %d\n",
14333 alloc_queue_pairs, vsi->seid, ret);
14334 goto err_vsi;
14335 }
14336 vsi->base_queue = ret;
14337
14338 /* Update the FW view of the VSI. Force a reset of TC and queue
14339 * layout configurations.
14340 */
14341 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
14342 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
14343 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
14344 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
14345 if (vsi->type == I40E_VSI_MAIN)
14346 i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr);
14347
14348 /* assign it some queues */
14349 ret = i40e_alloc_rings(vsi);
14350 if (ret)
14351 goto err_rings;
14352
14353 /* map all of the rings to the q_vectors */
14354 i40e_vsi_map_rings_to_vectors(vsi);
14355 return vsi;
14356
14357 err_rings:
14358 i40e_vsi_free_q_vectors(vsi);
14359 if (vsi->netdev_registered) {
14360 vsi->netdev_registered = false;
14361 unregister_netdev(vsi->netdev);
14362 free_netdev(vsi->netdev);
14363 vsi->netdev = NULL;
14364 }
14365 if (vsi->type == I40E_VSI_MAIN)
14366 i40e_devlink_destroy_port(pf);
14367 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
14368 err_vsi:
14369 i40e_vsi_clear(vsi);
14370 return NULL;
14371 }
14372
14373 /**
14374 * i40e_vsi_setup - Set up a VSI by a given type
14375 * @pf: board private structure
14376 * @type: VSI type
14377 * @uplink_seid: the switch element to link to
14378 * @param1: usage depends upon VSI type. For VF types, indicates VF id
14379 *
14380 * This allocates the sw VSI structure and its queue resources, then add a VSI
14381 * to the identified VEB.
14382 *
14383 * Returns pointer to the successfully allocated and configure VSI sw struct on
14384 * success, otherwise returns NULL on failure.
14385 **/
i40e_vsi_setup(struct i40e_pf * pf,u8 type,u16 uplink_seid,u32 param1)14386 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
14387 u16 uplink_seid, u32 param1)
14388 {
14389 struct i40e_vsi *vsi = NULL;
14390 struct i40e_veb *veb = NULL;
14391 u16 alloc_queue_pairs;
14392 int ret, i;
14393 int v_idx;
14394
14395 /* The requested uplink_seid must be either
14396 * - the PF's port seid
14397 * no VEB is needed because this is the PF
14398 * or this is a Flow Director special case VSI
14399 * - seid of an existing VEB
14400 * - seid of a VSI that owns an existing VEB
14401 * - seid of a VSI that doesn't own a VEB
14402 * a new VEB is created and the VSI becomes the owner
14403 * - seid of the PF VSI, which is what creates the first VEB
14404 * this is a special case of the previous
14405 *
14406 * Find which uplink_seid we were given and create a new VEB if needed
14407 */
14408 for (i = 0; i < I40E_MAX_VEB; i++) {
14409 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
14410 veb = pf->veb[i];
14411 break;
14412 }
14413 }
14414
14415 if (!veb && uplink_seid != pf->mac_seid) {
14416
14417 for (i = 0; i < pf->num_alloc_vsi; i++) {
14418 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
14419 vsi = pf->vsi[i];
14420 break;
14421 }
14422 }
14423 if (!vsi) {
14424 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
14425 uplink_seid);
14426 return NULL;
14427 }
14428
14429 if (vsi->uplink_seid == pf->mac_seid)
14430 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
14431 vsi->tc_config.enabled_tc);
14432 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
14433 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
14434 vsi->tc_config.enabled_tc);
14435 if (veb) {
14436 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
14437 dev_info(&vsi->back->pdev->dev,
14438 "New VSI creation error, uplink seid of LAN VSI expected.\n");
14439 return NULL;
14440 }
14441 /* We come up by default in VEPA mode if SRIOV is not
14442 * already enabled, in which case we can't force VEPA
14443 * mode.
14444 */
14445 if (!test_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags)) {
14446 veb->bridge_mode = BRIDGE_MODE_VEPA;
14447 clear_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
14448 }
14449 i40e_config_bridge_mode(veb);
14450 }
14451 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
14452 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
14453 veb = pf->veb[i];
14454 }
14455 if (!veb) {
14456 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
14457 return NULL;
14458 }
14459
14460 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
14461 uplink_seid = veb->seid;
14462 }
14463
14464 /* get vsi sw struct */
14465 v_idx = i40e_vsi_mem_alloc(pf, type);
14466 if (v_idx < 0)
14467 goto err_alloc;
14468 vsi = pf->vsi[v_idx];
14469 if (!vsi)
14470 goto err_alloc;
14471 vsi->type = type;
14472 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
14473
14474 if (type == I40E_VSI_MAIN)
14475 pf->lan_vsi = v_idx;
14476 else if (type == I40E_VSI_SRIOV)
14477 vsi->vf_id = param1;
14478 /* assign it some queues */
14479 alloc_queue_pairs = vsi->alloc_queue_pairs *
14480 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
14481
14482 ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx);
14483 if (ret < 0) {
14484 dev_info(&pf->pdev->dev,
14485 "failed to get tracking for %d queues for VSI %d err=%d\n",
14486 alloc_queue_pairs, vsi->seid, ret);
14487 goto err_vsi;
14488 }
14489 vsi->base_queue = ret;
14490
14491 /* get a VSI from the hardware */
14492 vsi->uplink_seid = uplink_seid;
14493 ret = i40e_add_vsi(vsi);
14494 if (ret)
14495 goto err_vsi;
14496
14497 switch (vsi->type) {
14498 /* setup the netdev if needed */
14499 case I40E_VSI_MAIN:
14500 case I40E_VSI_VMDQ2:
14501 ret = i40e_config_netdev(vsi);
14502 if (ret)
14503 goto err_netdev;
14504 ret = i40e_netif_set_realnum_tx_rx_queues(vsi);
14505 if (ret)
14506 goto err_netdev;
14507 if (vsi->type == I40E_VSI_MAIN) {
14508 ret = i40e_devlink_create_port(pf);
14509 if (ret)
14510 goto err_netdev;
14511 SET_NETDEV_DEVLINK_PORT(vsi->netdev, &pf->devlink_port);
14512 }
14513 ret = register_netdev(vsi->netdev);
14514 if (ret)
14515 goto err_dl_port;
14516 vsi->netdev_registered = true;
14517 netif_carrier_off(vsi->netdev);
14518 #ifdef CONFIG_I40E_DCB
14519 /* Setup DCB netlink interface */
14520 i40e_dcbnl_setup(vsi);
14521 #endif /* CONFIG_I40E_DCB */
14522 fallthrough;
14523 case I40E_VSI_FDIR:
14524 /* set up vectors and rings if needed */
14525 ret = i40e_vsi_setup_vectors(vsi);
14526 if (ret)
14527 goto err_msix;
14528
14529 ret = i40e_alloc_rings(vsi);
14530 if (ret)
14531 goto err_rings;
14532
14533 /* map all of the rings to the q_vectors */
14534 i40e_vsi_map_rings_to_vectors(vsi);
14535
14536 i40e_vsi_reset_stats(vsi);
14537 break;
14538 default:
14539 /* no netdev or rings for the other VSI types */
14540 break;
14541 }
14542
14543 if (test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps) &&
14544 vsi->type == I40E_VSI_VMDQ2) {
14545 ret = i40e_vsi_config_rss(vsi);
14546 if (ret)
14547 goto err_config;
14548 }
14549 return vsi;
14550
14551 err_config:
14552 i40e_vsi_clear_rings(vsi);
14553 err_rings:
14554 i40e_vsi_free_q_vectors(vsi);
14555 err_msix:
14556 if (vsi->netdev_registered) {
14557 vsi->netdev_registered = false;
14558 unregister_netdev(vsi->netdev);
14559 free_netdev(vsi->netdev);
14560 vsi->netdev = NULL;
14561 }
14562 err_dl_port:
14563 if (vsi->type == I40E_VSI_MAIN)
14564 i40e_devlink_destroy_port(pf);
14565 err_netdev:
14566 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
14567 err_vsi:
14568 i40e_vsi_clear(vsi);
14569 err_alloc:
14570 return NULL;
14571 }
14572
14573 /**
14574 * i40e_veb_get_bw_info - Query VEB BW information
14575 * @veb: the veb to query
14576 *
14577 * Query the Tx scheduler BW configuration data for given VEB
14578 **/
i40e_veb_get_bw_info(struct i40e_veb * veb)14579 static int i40e_veb_get_bw_info(struct i40e_veb *veb)
14580 {
14581 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
14582 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
14583 struct i40e_pf *pf = veb->pf;
14584 struct i40e_hw *hw = &pf->hw;
14585 u32 tc_bw_max;
14586 int ret = 0;
14587 int i;
14588
14589 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
14590 &bw_data, NULL);
14591 if (ret) {
14592 dev_info(&pf->pdev->dev,
14593 "query veb bw config failed, err %pe aq_err %s\n",
14594 ERR_PTR(ret),
14595 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
14596 goto out;
14597 }
14598
14599 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
14600 &ets_data, NULL);
14601 if (ret) {
14602 dev_info(&pf->pdev->dev,
14603 "query veb bw ets config failed, err %pe aq_err %s\n",
14604 ERR_PTR(ret),
14605 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
14606 goto out;
14607 }
14608
14609 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
14610 veb->bw_max_quanta = ets_data.tc_bw_max;
14611 veb->is_abs_credits = bw_data.absolute_credits_enable;
14612 veb->enabled_tc = ets_data.tc_valid_bits;
14613 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
14614 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
14615 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
14616 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
14617 veb->bw_tc_limit_credits[i] =
14618 le16_to_cpu(bw_data.tc_bw_limits[i]);
14619 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
14620 }
14621
14622 out:
14623 return ret;
14624 }
14625
14626 /**
14627 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
14628 * @pf: board private structure
14629 *
14630 * On error: returns error code (negative)
14631 * On success: returns vsi index in PF (positive)
14632 **/
i40e_veb_mem_alloc(struct i40e_pf * pf)14633 static int i40e_veb_mem_alloc(struct i40e_pf *pf)
14634 {
14635 int ret = -ENOENT;
14636 struct i40e_veb *veb;
14637 int i;
14638
14639 /* Need to protect the allocation of switch elements at the PF level */
14640 mutex_lock(&pf->switch_mutex);
14641
14642 /* VEB list may be fragmented if VEB creation/destruction has
14643 * been happening. We can afford to do a quick scan to look
14644 * for any free slots in the list.
14645 *
14646 * find next empty veb slot, looping back around if necessary
14647 */
14648 i = 0;
14649 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
14650 i++;
14651 if (i >= I40E_MAX_VEB) {
14652 ret = -ENOMEM;
14653 goto err_alloc_veb; /* out of VEB slots! */
14654 }
14655
14656 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
14657 if (!veb) {
14658 ret = -ENOMEM;
14659 goto err_alloc_veb;
14660 }
14661 veb->pf = pf;
14662 veb->idx = i;
14663 veb->enabled_tc = 1;
14664
14665 pf->veb[i] = veb;
14666 ret = i;
14667 err_alloc_veb:
14668 mutex_unlock(&pf->switch_mutex);
14669 return ret;
14670 }
14671
14672 /**
14673 * i40e_switch_branch_release - Delete a branch of the switch tree
14674 * @branch: where to start deleting
14675 *
14676 * This uses recursion to find the tips of the branch to be
14677 * removed, deleting until we get back to and can delete this VEB.
14678 **/
i40e_switch_branch_release(struct i40e_veb * branch)14679 static void i40e_switch_branch_release(struct i40e_veb *branch)
14680 {
14681 struct i40e_pf *pf = branch->pf;
14682 u16 branch_seid = branch->seid;
14683 u16 veb_idx = branch->idx;
14684 int i;
14685
14686 /* release any VEBs on this VEB - RECURSION */
14687 for (i = 0; i < I40E_MAX_VEB; i++) {
14688 if (!pf->veb[i])
14689 continue;
14690 if (pf->veb[i]->uplink_seid == branch->seid)
14691 i40e_switch_branch_release(pf->veb[i]);
14692 }
14693
14694 /* Release the VSIs on this VEB, but not the owner VSI.
14695 *
14696 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
14697 * the VEB itself, so don't use (*branch) after this loop.
14698 */
14699 for (i = 0; i < pf->num_alloc_vsi; i++) {
14700 if (!pf->vsi[i])
14701 continue;
14702 if (pf->vsi[i]->uplink_seid == branch_seid &&
14703 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
14704 i40e_vsi_release(pf->vsi[i]);
14705 }
14706 }
14707
14708 /* There's one corner case where the VEB might not have been
14709 * removed, so double check it here and remove it if needed.
14710 * This case happens if the veb was created from the debugfs
14711 * commands and no VSIs were added to it.
14712 */
14713 if (pf->veb[veb_idx])
14714 i40e_veb_release(pf->veb[veb_idx]);
14715 }
14716
14717 /**
14718 * i40e_veb_clear - remove veb struct
14719 * @veb: the veb to remove
14720 **/
i40e_veb_clear(struct i40e_veb * veb)14721 static void i40e_veb_clear(struct i40e_veb *veb)
14722 {
14723 if (!veb)
14724 return;
14725
14726 if (veb->pf) {
14727 struct i40e_pf *pf = veb->pf;
14728
14729 mutex_lock(&pf->switch_mutex);
14730 if (pf->veb[veb->idx] == veb)
14731 pf->veb[veb->idx] = NULL;
14732 mutex_unlock(&pf->switch_mutex);
14733 }
14734
14735 kfree(veb);
14736 }
14737
14738 /**
14739 * i40e_veb_release - Delete a VEB and free its resources
14740 * @veb: the VEB being removed
14741 **/
i40e_veb_release(struct i40e_veb * veb)14742 void i40e_veb_release(struct i40e_veb *veb)
14743 {
14744 struct i40e_vsi *vsi = NULL;
14745 struct i40e_pf *pf;
14746 int i, n = 0;
14747
14748 pf = veb->pf;
14749
14750 /* find the remaining VSI and check for extras */
14751 for (i = 0; i < pf->num_alloc_vsi; i++) {
14752 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
14753 n++;
14754 vsi = pf->vsi[i];
14755 }
14756 }
14757 if (n != 1) {
14758 dev_info(&pf->pdev->dev,
14759 "can't remove VEB %d with %d VSIs left\n",
14760 veb->seid, n);
14761 return;
14762 }
14763
14764 /* move the remaining VSI to uplink veb */
14765 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
14766 if (veb->uplink_seid) {
14767 vsi->uplink_seid = veb->uplink_seid;
14768 if (veb->uplink_seid == pf->mac_seid)
14769 vsi->veb_idx = I40E_NO_VEB;
14770 else
14771 vsi->veb_idx = veb->veb_idx;
14772 } else {
14773 /* floating VEB */
14774 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
14775 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
14776 }
14777
14778 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
14779 i40e_veb_clear(veb);
14780 }
14781
14782 /**
14783 * i40e_add_veb - create the VEB in the switch
14784 * @veb: the VEB to be instantiated
14785 * @vsi: the controlling VSI
14786 **/
i40e_add_veb(struct i40e_veb * veb,struct i40e_vsi * vsi)14787 static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
14788 {
14789 struct i40e_pf *pf = veb->pf;
14790 bool enable_stats = !!test_bit(I40E_FLAG_VEB_STATS_ENA, pf->flags);
14791 int ret;
14792
14793 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
14794 veb->enabled_tc, false,
14795 &veb->seid, enable_stats, NULL);
14796
14797 /* get a VEB from the hardware */
14798 if (ret) {
14799 dev_info(&pf->pdev->dev,
14800 "couldn't add VEB, err %pe aq_err %s\n",
14801 ERR_PTR(ret),
14802 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
14803 return -EPERM;
14804 }
14805
14806 /* get statistics counter */
14807 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
14808 &veb->stats_idx, NULL, NULL, NULL);
14809 if (ret) {
14810 dev_info(&pf->pdev->dev,
14811 "couldn't get VEB statistics idx, err %pe aq_err %s\n",
14812 ERR_PTR(ret),
14813 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
14814 return -EPERM;
14815 }
14816 ret = i40e_veb_get_bw_info(veb);
14817 if (ret) {
14818 dev_info(&pf->pdev->dev,
14819 "couldn't get VEB bw info, err %pe aq_err %s\n",
14820 ERR_PTR(ret),
14821 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
14822 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
14823 return -ENOENT;
14824 }
14825
14826 vsi->uplink_seid = veb->seid;
14827 vsi->veb_idx = veb->idx;
14828 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
14829
14830 return 0;
14831 }
14832
14833 /**
14834 * i40e_veb_setup - Set up a VEB
14835 * @pf: board private structure
14836 * @flags: VEB setup flags
14837 * @uplink_seid: the switch element to link to
14838 * @vsi_seid: the initial VSI seid
14839 * @enabled_tc: Enabled TC bit-map
14840 *
14841 * This allocates the sw VEB structure and links it into the switch
14842 * It is possible and legal for this to be a duplicate of an already
14843 * existing VEB. It is also possible for both uplink and vsi seids
14844 * to be zero, in order to create a floating VEB.
14845 *
14846 * Returns pointer to the successfully allocated VEB sw struct on
14847 * success, otherwise returns NULL on failure.
14848 **/
i40e_veb_setup(struct i40e_pf * pf,u16 flags,u16 uplink_seid,u16 vsi_seid,u8 enabled_tc)14849 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
14850 u16 uplink_seid, u16 vsi_seid,
14851 u8 enabled_tc)
14852 {
14853 struct i40e_veb *veb, *uplink_veb = NULL;
14854 int vsi_idx, veb_idx;
14855 int ret;
14856
14857 /* if one seid is 0, the other must be 0 to create a floating relay */
14858 if ((uplink_seid == 0 || vsi_seid == 0) &&
14859 (uplink_seid + vsi_seid != 0)) {
14860 dev_info(&pf->pdev->dev,
14861 "one, not both seid's are 0: uplink=%d vsi=%d\n",
14862 uplink_seid, vsi_seid);
14863 return NULL;
14864 }
14865
14866 /* make sure there is such a vsi and uplink */
14867 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
14868 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
14869 break;
14870 if (vsi_idx == pf->num_alloc_vsi && vsi_seid != 0) {
14871 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
14872 vsi_seid);
14873 return NULL;
14874 }
14875
14876 if (uplink_seid && uplink_seid != pf->mac_seid) {
14877 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
14878 if (pf->veb[veb_idx] &&
14879 pf->veb[veb_idx]->seid == uplink_seid) {
14880 uplink_veb = pf->veb[veb_idx];
14881 break;
14882 }
14883 }
14884 if (!uplink_veb) {
14885 dev_info(&pf->pdev->dev,
14886 "uplink seid %d not found\n", uplink_seid);
14887 return NULL;
14888 }
14889 }
14890
14891 /* get veb sw struct */
14892 veb_idx = i40e_veb_mem_alloc(pf);
14893 if (veb_idx < 0)
14894 goto err_alloc;
14895 veb = pf->veb[veb_idx];
14896 veb->flags = flags;
14897 veb->uplink_seid = uplink_seid;
14898 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
14899 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
14900
14901 /* create the VEB in the switch */
14902 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
14903 if (ret)
14904 goto err_veb;
14905 if (vsi_idx == pf->lan_vsi)
14906 pf->lan_veb = veb->idx;
14907
14908 return veb;
14909
14910 err_veb:
14911 i40e_veb_clear(veb);
14912 err_alloc:
14913 return NULL;
14914 }
14915
14916 /**
14917 * i40e_setup_pf_switch_element - set PF vars based on switch type
14918 * @pf: board private structure
14919 * @ele: element we are building info from
14920 * @num_reported: total number of elements
14921 * @printconfig: should we print the contents
14922 *
14923 * helper function to assist in extracting a few useful SEID values.
14924 **/
i40e_setup_pf_switch_element(struct i40e_pf * pf,struct i40e_aqc_switch_config_element_resp * ele,u16 num_reported,bool printconfig)14925 static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
14926 struct i40e_aqc_switch_config_element_resp *ele,
14927 u16 num_reported, bool printconfig)
14928 {
14929 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
14930 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
14931 u8 element_type = ele->element_type;
14932 u16 seid = le16_to_cpu(ele->seid);
14933
14934 if (printconfig)
14935 dev_info(&pf->pdev->dev,
14936 "type=%d seid=%d uplink=%d downlink=%d\n",
14937 element_type, seid, uplink_seid, downlink_seid);
14938
14939 switch (element_type) {
14940 case I40E_SWITCH_ELEMENT_TYPE_MAC:
14941 pf->mac_seid = seid;
14942 break;
14943 case I40E_SWITCH_ELEMENT_TYPE_VEB:
14944 /* Main VEB? */
14945 if (uplink_seid != pf->mac_seid)
14946 break;
14947 if (pf->lan_veb >= I40E_MAX_VEB) {
14948 int v;
14949
14950 /* find existing or else empty VEB */
14951 for (v = 0; v < I40E_MAX_VEB; v++) {
14952 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
14953 pf->lan_veb = v;
14954 break;
14955 }
14956 }
14957 if (pf->lan_veb >= I40E_MAX_VEB) {
14958 v = i40e_veb_mem_alloc(pf);
14959 if (v < 0)
14960 break;
14961 pf->lan_veb = v;
14962 }
14963 }
14964 if (pf->lan_veb >= I40E_MAX_VEB)
14965 break;
14966
14967 pf->veb[pf->lan_veb]->seid = seid;
14968 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
14969 pf->veb[pf->lan_veb]->pf = pf;
14970 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
14971 break;
14972 case I40E_SWITCH_ELEMENT_TYPE_VSI:
14973 if (num_reported != 1)
14974 break;
14975 /* This is immediately after a reset so we can assume this is
14976 * the PF's VSI
14977 */
14978 pf->mac_seid = uplink_seid;
14979 pf->main_vsi_seid = seid;
14980 if (printconfig)
14981 dev_info(&pf->pdev->dev,
14982 "pf_seid=%d main_vsi_seid=%d\n",
14983 downlink_seid, pf->main_vsi_seid);
14984 break;
14985 case I40E_SWITCH_ELEMENT_TYPE_PF:
14986 case I40E_SWITCH_ELEMENT_TYPE_VF:
14987 case I40E_SWITCH_ELEMENT_TYPE_EMP:
14988 case I40E_SWITCH_ELEMENT_TYPE_BMC:
14989 case I40E_SWITCH_ELEMENT_TYPE_PE:
14990 case I40E_SWITCH_ELEMENT_TYPE_PA:
14991 /* ignore these for now */
14992 break;
14993 default:
14994 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
14995 element_type, seid);
14996 break;
14997 }
14998 }
14999
15000 /**
15001 * i40e_fetch_switch_configuration - Get switch config from firmware
15002 * @pf: board private structure
15003 * @printconfig: should we print the contents
15004 *
15005 * Get the current switch configuration from the device and
15006 * extract a few useful SEID values.
15007 **/
i40e_fetch_switch_configuration(struct i40e_pf * pf,bool printconfig)15008 int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
15009 {
15010 struct i40e_aqc_get_switch_config_resp *sw_config;
15011 u16 next_seid = 0;
15012 int ret = 0;
15013 u8 *aq_buf;
15014 int i;
15015
15016 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
15017 if (!aq_buf)
15018 return -ENOMEM;
15019
15020 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
15021 do {
15022 u16 num_reported, num_total;
15023
15024 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
15025 I40E_AQ_LARGE_BUF,
15026 &next_seid, NULL);
15027 if (ret) {
15028 dev_info(&pf->pdev->dev,
15029 "get switch config failed err %d aq_err %s\n",
15030 ret,
15031 i40e_aq_str(&pf->hw,
15032 pf->hw.aq.asq_last_status));
15033 kfree(aq_buf);
15034 return -ENOENT;
15035 }
15036
15037 num_reported = le16_to_cpu(sw_config->header.num_reported);
15038 num_total = le16_to_cpu(sw_config->header.num_total);
15039
15040 if (printconfig)
15041 dev_info(&pf->pdev->dev,
15042 "header: %d reported %d total\n",
15043 num_reported, num_total);
15044
15045 for (i = 0; i < num_reported; i++) {
15046 struct i40e_aqc_switch_config_element_resp *ele =
15047 &sw_config->element[i];
15048
15049 i40e_setup_pf_switch_element(pf, ele, num_reported,
15050 printconfig);
15051 }
15052 } while (next_seid != 0);
15053
15054 kfree(aq_buf);
15055 return ret;
15056 }
15057
15058 /**
15059 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
15060 * @pf: board private structure
15061 * @reinit: if the Main VSI needs to re-initialized.
15062 * @lock_acquired: indicates whether or not the lock has been acquired
15063 *
15064 * Returns 0 on success, negative value on failure
15065 **/
i40e_setup_pf_switch(struct i40e_pf * pf,bool reinit,bool lock_acquired)15066 static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acquired)
15067 {
15068 u16 flags = 0;
15069 int ret;
15070
15071 /* find out what's out there already */
15072 ret = i40e_fetch_switch_configuration(pf, false);
15073 if (ret) {
15074 dev_info(&pf->pdev->dev,
15075 "couldn't fetch switch config, err %pe aq_err %s\n",
15076 ERR_PTR(ret),
15077 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
15078 return ret;
15079 }
15080 i40e_pf_reset_stats(pf);
15081
15082 /* set the switch config bit for the whole device to
15083 * support limited promisc or true promisc
15084 * when user requests promisc. The default is limited
15085 * promisc.
15086 */
15087
15088 if ((pf->hw.pf_id == 0) &&
15089 !test_bit(I40E_FLAG_TRUE_PROMISC_ENA, pf->flags)) {
15090 flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
15091 pf->last_sw_conf_flags = flags;
15092 }
15093
15094 if (pf->hw.pf_id == 0) {
15095 u16 valid_flags;
15096
15097 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
15098 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 0,
15099 NULL);
15100 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
15101 dev_info(&pf->pdev->dev,
15102 "couldn't set switch config bits, err %pe aq_err %s\n",
15103 ERR_PTR(ret),
15104 i40e_aq_str(&pf->hw,
15105 pf->hw.aq.asq_last_status));
15106 /* not a fatal problem, just keep going */
15107 }
15108 pf->last_sw_conf_valid_flags = valid_flags;
15109 }
15110
15111 /* first time setup */
15112 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
15113 struct i40e_vsi *vsi = NULL;
15114 u16 uplink_seid;
15115
15116 /* Set up the PF VSI associated with the PF's main VSI
15117 * that is already in the HW switch
15118 */
15119 if (pf->lan_veb < I40E_MAX_VEB && pf->veb[pf->lan_veb])
15120 uplink_seid = pf->veb[pf->lan_veb]->seid;
15121 else
15122 uplink_seid = pf->mac_seid;
15123 if (pf->lan_vsi == I40E_NO_VSI)
15124 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
15125 else if (reinit)
15126 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
15127 if (!vsi) {
15128 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
15129 i40e_cloud_filter_exit(pf);
15130 i40e_fdir_teardown(pf);
15131 return -EAGAIN;
15132 }
15133 } else {
15134 /* force a reset of TC and queue layout configurations */
15135 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
15136
15137 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
15138 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
15139 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
15140 }
15141 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
15142
15143 i40e_fdir_sb_setup(pf);
15144
15145 /* Setup static PF queue filter control settings */
15146 ret = i40e_setup_pf_filter_control(pf);
15147 if (ret) {
15148 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
15149 ret);
15150 /* Failure here should not stop continuing other steps */
15151 }
15152
15153 /* enable RSS in the HW, even for only one queue, as the stack can use
15154 * the hash
15155 */
15156 if (test_bit(I40E_FLAG_RSS_ENA, pf->flags))
15157 i40e_pf_config_rss(pf);
15158
15159 /* fill in link information and enable LSE reporting */
15160 i40e_link_event(pf);
15161
15162 i40e_ptp_init(pf);
15163
15164 if (!lock_acquired)
15165 rtnl_lock();
15166
15167 /* repopulate tunnel port filters */
15168 udp_tunnel_nic_reset_ntf(pf->vsi[pf->lan_vsi]->netdev);
15169
15170 if (!lock_acquired)
15171 rtnl_unlock();
15172
15173 return ret;
15174 }
15175
15176 /**
15177 * i40e_determine_queue_usage - Work out queue distribution
15178 * @pf: board private structure
15179 **/
i40e_determine_queue_usage(struct i40e_pf * pf)15180 static void i40e_determine_queue_usage(struct i40e_pf *pf)
15181 {
15182 int queues_left;
15183 int q_max;
15184
15185 pf->num_lan_qps = 0;
15186
15187 /* Find the max queues to be put into basic use. We'll always be
15188 * using TC0, whether or not DCB is running, and TC0 will get the
15189 * big RSS set.
15190 */
15191 queues_left = pf->hw.func_caps.num_tx_qp;
15192
15193 if ((queues_left == 1) ||
15194 !test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
15195 /* one qp for PF, no queues for anything else */
15196 queues_left = 0;
15197 pf->alloc_rss_size = pf->num_lan_qps = 1;
15198
15199 /* make sure all the fancies are disabled */
15200 clear_bit(I40E_FLAG_RSS_ENA, pf->flags);
15201 clear_bit(I40E_FLAG_IWARP_ENA, pf->flags);
15202 clear_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
15203 clear_bit(I40E_FLAG_FD_ATR_ENA, pf->flags);
15204 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
15205 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
15206 clear_bit(I40E_FLAG_SRIOV_ENA, pf->flags);
15207 clear_bit(I40E_FLAG_VMDQ_ENA, pf->flags);
15208 set_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
15209 } else if (!test_bit(I40E_FLAG_RSS_ENA, pf->flags) &&
15210 !test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) &&
15211 !test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) &&
15212 !test_bit(I40E_FLAG_DCB_CAPABLE, pf->flags)) {
15213 /* one qp for PF */
15214 pf->alloc_rss_size = pf->num_lan_qps = 1;
15215 queues_left -= pf->num_lan_qps;
15216
15217 clear_bit(I40E_FLAG_RSS_ENA, pf->flags);
15218 clear_bit(I40E_FLAG_IWARP_ENA, pf->flags);
15219 clear_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
15220 clear_bit(I40E_FLAG_FD_ATR_ENA, pf->flags);
15221 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
15222 clear_bit(I40E_FLAG_VMDQ_ENA, pf->flags);
15223 set_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
15224 } else {
15225 /* Not enough queues for all TCs */
15226 if (test_bit(I40E_FLAG_DCB_CAPABLE, pf->flags) &&
15227 queues_left < I40E_MAX_TRAFFIC_CLASS) {
15228 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
15229 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
15230 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
15231 }
15232
15233 /* limit lan qps to the smaller of qps, cpus or msix */
15234 q_max = max_t(int, pf->rss_size_max, num_online_cpus());
15235 q_max = min_t(int, q_max, pf->hw.func_caps.num_tx_qp);
15236 q_max = min_t(int, q_max, pf->hw.func_caps.num_msix_vectors);
15237 pf->num_lan_qps = q_max;
15238
15239 queues_left -= pf->num_lan_qps;
15240 }
15241
15242 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags)) {
15243 if (queues_left > 1) {
15244 queues_left -= 1; /* save 1 queue for FD */
15245 } else {
15246 clear_bit(I40E_FLAG_FD_SB_ENA, pf->flags);
15247 set_bit(I40E_FLAG_FD_SB_INACTIVE, pf->flags);
15248 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
15249 }
15250 }
15251
15252 if (test_bit(I40E_FLAG_SRIOV_ENA, pf->flags) &&
15253 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
15254 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
15255 (queues_left / pf->num_vf_qps));
15256 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
15257 }
15258
15259 if (test_bit(I40E_FLAG_VMDQ_ENA, pf->flags) &&
15260 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
15261 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
15262 (queues_left / pf->num_vmdq_qps));
15263 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
15264 }
15265
15266 pf->queues_left = queues_left;
15267 dev_dbg(&pf->pdev->dev,
15268 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
15269 pf->hw.func_caps.num_tx_qp,
15270 !!test_bit(I40E_FLAG_FD_SB_ENA, pf->flags),
15271 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
15272 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
15273 queues_left);
15274 }
15275
15276 /**
15277 * i40e_setup_pf_filter_control - Setup PF static filter control
15278 * @pf: PF to be setup
15279 *
15280 * i40e_setup_pf_filter_control sets up a PF's initial filter control
15281 * settings. If PE/FCoE are enabled then it will also set the per PF
15282 * based filter sizes required for them. It also enables Flow director,
15283 * ethertype and macvlan type filter settings for the pf.
15284 *
15285 * Returns 0 on success, negative on failure
15286 **/
i40e_setup_pf_filter_control(struct i40e_pf * pf)15287 static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
15288 {
15289 struct i40e_filter_control_settings *settings = &pf->filter_settings;
15290
15291 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
15292
15293 /* Flow Director is enabled */
15294 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) ||
15295 test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags))
15296 settings->enable_fdir = true;
15297
15298 /* Ethtype and MACVLAN filters enabled for PF */
15299 settings->enable_ethtype = true;
15300 settings->enable_macvlan = true;
15301
15302 if (i40e_set_filter_control(&pf->hw, settings))
15303 return -ENOENT;
15304
15305 return 0;
15306 }
15307
15308 #define INFO_STRING_LEN 255
15309 #define REMAIN(__x) (INFO_STRING_LEN - (__x))
i40e_print_features(struct i40e_pf * pf)15310 static void i40e_print_features(struct i40e_pf *pf)
15311 {
15312 struct i40e_hw *hw = &pf->hw;
15313 char *buf;
15314 int i;
15315
15316 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
15317 if (!buf)
15318 return;
15319
15320 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
15321 #ifdef CONFIG_PCI_IOV
15322 i += scnprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
15323 #endif
15324 i += scnprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d",
15325 pf->hw.func_caps.num_vsis,
15326 pf->vsi[pf->lan_vsi]->num_queue_pairs);
15327 if (test_bit(I40E_FLAG_RSS_ENA, pf->flags))
15328 i += scnprintf(&buf[i], REMAIN(i), " RSS");
15329 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags))
15330 i += scnprintf(&buf[i], REMAIN(i), " FD_ATR");
15331 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags)) {
15332 i += scnprintf(&buf[i], REMAIN(i), " FD_SB");
15333 i += scnprintf(&buf[i], REMAIN(i), " NTUPLE");
15334 }
15335 if (test_bit(I40E_FLAG_DCB_CAPABLE, pf->flags))
15336 i += scnprintf(&buf[i], REMAIN(i), " DCB");
15337 i += scnprintf(&buf[i], REMAIN(i), " VxLAN");
15338 i += scnprintf(&buf[i], REMAIN(i), " Geneve");
15339 if (test_bit(I40E_FLAG_PTP_ENA, pf->flags))
15340 i += scnprintf(&buf[i], REMAIN(i), " PTP");
15341 if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags))
15342 i += scnprintf(&buf[i], REMAIN(i), " VEB");
15343 else
15344 i += scnprintf(&buf[i], REMAIN(i), " VEPA");
15345
15346 dev_info(&pf->pdev->dev, "%s\n", buf);
15347 kfree(buf);
15348 WARN_ON(i > INFO_STRING_LEN);
15349 }
15350
15351 /**
15352 * i40e_get_platform_mac_addr - get platform-specific MAC address
15353 * @pdev: PCI device information struct
15354 * @pf: board private structure
15355 *
15356 * Look up the MAC address for the device. First we'll try
15357 * eth_platform_get_mac_address, which will check Open Firmware, or arch
15358 * specific fallback. Otherwise, we'll default to the stored value in
15359 * firmware.
15360 **/
i40e_get_platform_mac_addr(struct pci_dev * pdev,struct i40e_pf * pf)15361 static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
15362 {
15363 if (eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
15364 i40e_get_mac_addr(&pf->hw, pf->hw.mac.addr);
15365 }
15366
15367 /**
15368 * i40e_set_fec_in_flags - helper function for setting FEC options in flags
15369 * @fec_cfg: FEC option to set in flags
15370 * @flags: ptr to flags in which we set FEC option
15371 **/
i40e_set_fec_in_flags(u8 fec_cfg,unsigned long * flags)15372 void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags)
15373 {
15374 if (fec_cfg & I40E_AQ_SET_FEC_AUTO) {
15375 set_bit(I40E_FLAG_RS_FEC, flags);
15376 set_bit(I40E_FLAG_BASE_R_FEC, flags);
15377 }
15378 if ((fec_cfg & I40E_AQ_SET_FEC_REQUEST_RS) ||
15379 (fec_cfg & I40E_AQ_SET_FEC_ABILITY_RS)) {
15380 set_bit(I40E_FLAG_RS_FEC, flags);
15381 clear_bit(I40E_FLAG_BASE_R_FEC, flags);
15382 }
15383 if ((fec_cfg & I40E_AQ_SET_FEC_REQUEST_KR) ||
15384 (fec_cfg & I40E_AQ_SET_FEC_ABILITY_KR)) {
15385 set_bit(I40E_FLAG_BASE_R_FEC, flags);
15386 clear_bit(I40E_FLAG_RS_FEC, flags);
15387 }
15388 if (fec_cfg == 0) {
15389 clear_bit(I40E_FLAG_RS_FEC, flags);
15390 clear_bit(I40E_FLAG_BASE_R_FEC, flags);
15391 }
15392 }
15393
15394 /**
15395 * i40e_check_recovery_mode - check if we are running transition firmware
15396 * @pf: board private structure
15397 *
15398 * Check registers indicating the firmware runs in recovery mode. Sets the
15399 * appropriate driver state.
15400 *
15401 * Returns true if the recovery mode was detected, false otherwise
15402 **/
i40e_check_recovery_mode(struct i40e_pf * pf)15403 static bool i40e_check_recovery_mode(struct i40e_pf *pf)
15404 {
15405 u32 val = rd32(&pf->hw, I40E_GL_FWSTS);
15406
15407 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
15408 dev_crit(&pf->pdev->dev, "Firmware recovery mode detected. Limiting functionality.\n");
15409 dev_crit(&pf->pdev->dev, "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
15410 set_bit(__I40E_RECOVERY_MODE, pf->state);
15411
15412 return true;
15413 }
15414 if (test_bit(__I40E_RECOVERY_MODE, pf->state))
15415 dev_info(&pf->pdev->dev, "Please do Power-On Reset to initialize adapter in normal mode with full functionality.\n");
15416
15417 return false;
15418 }
15419
15420 /**
15421 * i40e_pf_loop_reset - perform reset in a loop.
15422 * @pf: board private structure
15423 *
15424 * This function is useful when a NIC is about to enter recovery mode.
15425 * When a NIC's internal data structures are corrupted the NIC's
15426 * firmware is going to enter recovery mode.
15427 * Right after a POR it takes about 7 minutes for firmware to enter
15428 * recovery mode. Until that time a NIC is in some kind of intermediate
15429 * state. After that time period the NIC almost surely enters
15430 * recovery mode. The only way for a driver to detect intermediate
15431 * state is to issue a series of pf-resets and check a return value.
15432 * If a PF reset returns success then the firmware could be in recovery
15433 * mode so the caller of this code needs to check for recovery mode
15434 * if this function returns success. There is a little chance that
15435 * firmware will hang in intermediate state forever.
15436 * Since waiting 7 minutes is quite a lot of time this function waits
15437 * 10 seconds and then gives up by returning an error.
15438 *
15439 * Return 0 on success, negative on failure.
15440 **/
i40e_pf_loop_reset(struct i40e_pf * pf)15441 static int i40e_pf_loop_reset(struct i40e_pf *pf)
15442 {
15443 /* wait max 10 seconds for PF reset to succeed */
15444 const unsigned long time_end = jiffies + 10 * HZ;
15445 struct i40e_hw *hw = &pf->hw;
15446 int ret;
15447
15448 ret = i40e_pf_reset(hw);
15449 while (ret != 0 && time_before(jiffies, time_end)) {
15450 usleep_range(10000, 20000);
15451 ret = i40e_pf_reset(hw);
15452 }
15453
15454 if (ret == 0)
15455 pf->pfr_count++;
15456 else
15457 dev_info(&pf->pdev->dev, "PF reset failed: %d\n", ret);
15458
15459 return ret;
15460 }
15461
15462 /**
15463 * i40e_check_fw_empr - check if FW issued unexpected EMP Reset
15464 * @pf: board private structure
15465 *
15466 * Check FW registers to determine if FW issued unexpected EMP Reset.
15467 * Every time when unexpected EMP Reset occurs the FW increments
15468 * a counter of unexpected EMP Resets. When the counter reaches 10
15469 * the FW should enter the Recovery mode
15470 *
15471 * Returns true if FW issued unexpected EMP Reset
15472 **/
i40e_check_fw_empr(struct i40e_pf * pf)15473 static bool i40e_check_fw_empr(struct i40e_pf *pf)
15474 {
15475 const u32 fw_sts = rd32(&pf->hw, I40E_GL_FWSTS) &
15476 I40E_GL_FWSTS_FWS1B_MASK;
15477 return (fw_sts > I40E_GL_FWSTS_FWS1B_EMPR_0) &&
15478 (fw_sts <= I40E_GL_FWSTS_FWS1B_EMPR_10);
15479 }
15480
15481 /**
15482 * i40e_handle_resets - handle EMP resets and PF resets
15483 * @pf: board private structure
15484 *
15485 * Handle both EMP resets and PF resets and conclude whether there are
15486 * any issues regarding these resets. If there are any issues then
15487 * generate log entry.
15488 *
15489 * Return 0 if NIC is healthy or negative value when there are issues
15490 * with resets
15491 **/
i40e_handle_resets(struct i40e_pf * pf)15492 static int i40e_handle_resets(struct i40e_pf *pf)
15493 {
15494 const int pfr = i40e_pf_loop_reset(pf);
15495 const bool is_empr = i40e_check_fw_empr(pf);
15496
15497 if (is_empr || pfr != 0)
15498 dev_crit(&pf->pdev->dev, "Entering recovery mode due to repeated FW resets. This may take several minutes. Refer to the Intel(R) Ethernet Adapters and Devices User Guide.\n");
15499
15500 return is_empr ? -EIO : pfr;
15501 }
15502
15503 /**
15504 * i40e_init_recovery_mode - initialize subsystems needed in recovery mode
15505 * @pf: board private structure
15506 * @hw: ptr to the hardware info
15507 *
15508 * This function does a minimal setup of all subsystems needed for running
15509 * recovery mode.
15510 *
15511 * Returns 0 on success, negative on failure
15512 **/
i40e_init_recovery_mode(struct i40e_pf * pf,struct i40e_hw * hw)15513 static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw)
15514 {
15515 struct i40e_vsi *vsi;
15516 int err;
15517 int v_idx;
15518
15519 pci_set_drvdata(pf->pdev, pf);
15520 pci_save_state(pf->pdev);
15521
15522 /* set up periodic task facility */
15523 timer_setup(&pf->service_timer, i40e_service_timer, 0);
15524 pf->service_timer_period = HZ;
15525
15526 INIT_WORK(&pf->service_task, i40e_service_task);
15527 clear_bit(__I40E_SERVICE_SCHED, pf->state);
15528
15529 err = i40e_init_interrupt_scheme(pf);
15530 if (err)
15531 goto err_switch_setup;
15532
15533 /* The number of VSIs reported by the FW is the minimum guaranteed
15534 * to us; HW supports far more and we share the remaining pool with
15535 * the other PFs. We allocate space for more than the guarantee with
15536 * the understanding that we might not get them all later.
15537 */
15538 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
15539 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
15540 else
15541 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
15542
15543 /* Set up the vsi struct and our local tracking of the MAIN PF vsi. */
15544 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
15545 GFP_KERNEL);
15546 if (!pf->vsi) {
15547 err = -ENOMEM;
15548 goto err_switch_setup;
15549 }
15550
15551 /* We allocate one VSI which is needed as absolute minimum
15552 * in order to register the netdev
15553 */
15554 v_idx = i40e_vsi_mem_alloc(pf, I40E_VSI_MAIN);
15555 if (v_idx < 0) {
15556 err = v_idx;
15557 goto err_switch_setup;
15558 }
15559 pf->lan_vsi = v_idx;
15560 vsi = pf->vsi[v_idx];
15561 if (!vsi) {
15562 err = -EFAULT;
15563 goto err_switch_setup;
15564 }
15565 vsi->alloc_queue_pairs = 1;
15566 err = i40e_config_netdev(vsi);
15567 if (err)
15568 goto err_switch_setup;
15569 err = register_netdev(vsi->netdev);
15570 if (err)
15571 goto err_switch_setup;
15572 vsi->netdev_registered = true;
15573 i40e_dbg_pf_init(pf);
15574
15575 err = i40e_setup_misc_vector_for_recovery_mode(pf);
15576 if (err)
15577 goto err_switch_setup;
15578
15579 /* tell the firmware that we're starting */
15580 i40e_send_version(pf);
15581
15582 /* since everything's happy, start the service_task timer */
15583 mod_timer(&pf->service_timer,
15584 round_jiffies(jiffies + pf->service_timer_period));
15585
15586 return 0;
15587
15588 err_switch_setup:
15589 i40e_reset_interrupt_capability(pf);
15590 timer_shutdown_sync(&pf->service_timer);
15591 i40e_shutdown_adminq(hw);
15592 iounmap(hw->hw_addr);
15593 pci_release_mem_regions(pf->pdev);
15594 pci_disable_device(pf->pdev);
15595 i40e_free_pf(pf);
15596
15597 return err;
15598 }
15599
15600 /**
15601 * i40e_set_subsystem_device_id - set subsystem device id
15602 * @hw: pointer to the hardware info
15603 *
15604 * Set PCI subsystem device id either from a pci_dev structure or
15605 * a specific FW register.
15606 **/
i40e_set_subsystem_device_id(struct i40e_hw * hw)15607 static inline void i40e_set_subsystem_device_id(struct i40e_hw *hw)
15608 {
15609 struct i40e_pf *pf = i40e_hw_to_pf(hw);
15610
15611 hw->subsystem_device_id = pf->pdev->subsystem_device ?
15612 pf->pdev->subsystem_device :
15613 (ushort)(rd32(hw, I40E_PFPCI_SUBSYSID) & USHRT_MAX);
15614 }
15615
15616 /**
15617 * i40e_probe - Device initialization routine
15618 * @pdev: PCI device information struct
15619 * @ent: entry in i40e_pci_tbl
15620 *
15621 * i40e_probe initializes a PF identified by a pci_dev structure.
15622 * The OS initialization, configuring of the PF private structure,
15623 * and a hardware reset occur.
15624 *
15625 * Returns 0 on success, negative on failure
15626 **/
i40e_probe(struct pci_dev * pdev,const struct pci_device_id * ent)15627 static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
15628 {
15629 struct i40e_aq_get_phy_abilities_resp abilities;
15630 #ifdef CONFIG_I40E_DCB
15631 enum i40e_get_fw_lldp_status_resp lldp_status;
15632 #endif /* CONFIG_I40E_DCB */
15633 struct i40e_pf *pf;
15634 struct i40e_hw *hw;
15635 u16 wol_nvm_bits;
15636 char nvm_ver[32];
15637 u16 link_status;
15638 #ifdef CONFIG_I40E_DCB
15639 int status;
15640 #endif /* CONFIG_I40E_DCB */
15641 int err;
15642 u32 val;
15643 u32 i;
15644
15645 err = pci_enable_device_mem(pdev);
15646 if (err)
15647 return err;
15648
15649 /* set up for high or low dma */
15650 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
15651 if (err) {
15652 dev_err(&pdev->dev,
15653 "DMA configuration failed: 0x%x\n", err);
15654 goto err_dma;
15655 }
15656
15657 /* set up pci connections */
15658 err = pci_request_mem_regions(pdev, i40e_driver_name);
15659 if (err) {
15660 dev_info(&pdev->dev,
15661 "pci_request_selected_regions failed %d\n", err);
15662 goto err_pci_reg;
15663 }
15664
15665 pci_set_master(pdev);
15666
15667 /* Now that we have a PCI connection, we need to do the
15668 * low level device setup. This is primarily setting up
15669 * the Admin Queue structures and then querying for the
15670 * device's current profile information.
15671 */
15672 pf = i40e_alloc_pf(&pdev->dev);
15673 if (!pf) {
15674 err = -ENOMEM;
15675 goto err_pf_alloc;
15676 }
15677 pf->next_vsi = 0;
15678 pf->pdev = pdev;
15679 set_bit(__I40E_DOWN, pf->state);
15680
15681 hw = &pf->hw;
15682
15683 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
15684 I40E_MAX_CSR_SPACE);
15685 /* We believe that the highest register to read is
15686 * I40E_GLGEN_STAT_CLEAR, so we check if the BAR size
15687 * is not less than that before mapping to prevent a
15688 * kernel panic.
15689 */
15690 if (pf->ioremap_len < I40E_GLGEN_STAT_CLEAR) {
15691 dev_err(&pdev->dev, "Cannot map registers, bar size 0x%X too small, aborting\n",
15692 pf->ioremap_len);
15693 err = -ENOMEM;
15694 goto err_ioremap;
15695 }
15696 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
15697 if (!hw->hw_addr) {
15698 err = -EIO;
15699 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
15700 (unsigned int)pci_resource_start(pdev, 0),
15701 pf->ioremap_len, err);
15702 goto err_ioremap;
15703 }
15704 hw->vendor_id = pdev->vendor;
15705 hw->device_id = pdev->device;
15706 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
15707 hw->subsystem_vendor_id = pdev->subsystem_vendor;
15708 i40e_set_subsystem_device_id(hw);
15709 hw->bus.device = PCI_SLOT(pdev->devfn);
15710 hw->bus.func = PCI_FUNC(pdev->devfn);
15711 hw->bus.bus_id = pdev->bus->number;
15712
15713 /* Select something other than the 802.1ad ethertype for the
15714 * switch to use internally and drop on ingress.
15715 */
15716 hw->switch_tag = 0xffff;
15717 hw->first_tag = ETH_P_8021AD;
15718 hw->second_tag = ETH_P_8021Q;
15719
15720 INIT_LIST_HEAD(&pf->l3_flex_pit_list);
15721 INIT_LIST_HEAD(&pf->l4_flex_pit_list);
15722 INIT_LIST_HEAD(&pf->ddp_old_prof);
15723
15724 /* set up the locks for the AQ, do this only once in probe
15725 * and destroy them only once in remove
15726 */
15727 mutex_init(&hw->aq.asq_mutex);
15728 mutex_init(&hw->aq.arq_mutex);
15729
15730 pf->msg_enable = netif_msg_init(debug,
15731 NETIF_MSG_DRV |
15732 NETIF_MSG_PROBE |
15733 NETIF_MSG_LINK);
15734 if (debug < -1)
15735 pf->hw.debug_mask = debug;
15736
15737 /* do a special CORER for clearing PXE mode once at init */
15738 if (hw->revision_id == 0 &&
15739 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
15740 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
15741 i40e_flush(hw);
15742 msleep(200);
15743 pf->corer_count++;
15744
15745 i40e_clear_pxe_mode(hw);
15746 }
15747
15748 /* Reset here to make sure all is clean and to define PF 'n' */
15749 i40e_clear_hw(hw);
15750
15751 err = i40e_set_mac_type(hw);
15752 if (err) {
15753 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
15754 err);
15755 goto err_pf_reset;
15756 }
15757
15758 err = i40e_handle_resets(pf);
15759 if (err)
15760 goto err_pf_reset;
15761
15762 i40e_check_recovery_mode(pf);
15763
15764 if (is_kdump_kernel()) {
15765 hw->aq.num_arq_entries = I40E_MIN_ARQ_LEN;
15766 hw->aq.num_asq_entries = I40E_MIN_ASQ_LEN;
15767 } else {
15768 hw->aq.num_arq_entries = I40E_AQ_LEN;
15769 hw->aq.num_asq_entries = I40E_AQ_LEN;
15770 }
15771 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
15772 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
15773
15774 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
15775 "%s-%s:misc",
15776 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
15777
15778 err = i40e_init_shared_code(hw);
15779 if (err) {
15780 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
15781 err);
15782 goto err_pf_reset;
15783 }
15784
15785 /* set up a default setting for link flow control */
15786 pf->hw.fc.requested_mode = I40E_FC_NONE;
15787
15788 err = i40e_init_adminq(hw);
15789 if (err) {
15790 if (err == -EIO)
15791 dev_info(&pdev->dev,
15792 "The driver for the device stopped because the NVM image v%u.%u is newer than expected v%u.%u. You must install the most recent version of the network driver.\n",
15793 hw->aq.api_maj_ver,
15794 hw->aq.api_min_ver,
15795 I40E_FW_API_VERSION_MAJOR,
15796 I40E_FW_MINOR_VERSION(hw));
15797 else
15798 dev_info(&pdev->dev,
15799 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
15800
15801 goto err_pf_reset;
15802 }
15803 i40e_get_oem_version(hw);
15804 i40e_get_pba_string(hw);
15805
15806 /* provide nvm, fw, api versions, vendor:device id, subsys vendor:device id */
15807 i40e_nvm_version_str(hw, nvm_ver, sizeof(nvm_ver));
15808 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s [%04x:%04x] [%04x:%04x]\n",
15809 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
15810 hw->aq.api_maj_ver, hw->aq.api_min_ver, nvm_ver,
15811 hw->vendor_id, hw->device_id, hw->subsystem_vendor_id,
15812 hw->subsystem_device_id);
15813
15814 if (i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR,
15815 I40E_FW_MINOR_VERSION(hw) + 1))
15816 dev_dbg(&pdev->dev,
15817 "The driver for the device detected a newer version of the NVM image v%u.%u than v%u.%u.\n",
15818 hw->aq.api_maj_ver,
15819 hw->aq.api_min_ver,
15820 I40E_FW_API_VERSION_MAJOR,
15821 I40E_FW_MINOR_VERSION(hw));
15822 else if (i40e_is_aq_api_ver_lt(hw, 1, 4))
15823 dev_info(&pdev->dev,
15824 "The driver for the device detected an older version of the NVM image v%u.%u than expected v%u.%u. Please update the NVM image.\n",
15825 hw->aq.api_maj_ver,
15826 hw->aq.api_min_ver,
15827 I40E_FW_API_VERSION_MAJOR,
15828 I40E_FW_MINOR_VERSION(hw));
15829
15830 i40e_verify_eeprom(pf);
15831
15832 /* Rev 0 hardware was never productized */
15833 if (hw->revision_id < 1)
15834 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
15835
15836 i40e_clear_pxe_mode(hw);
15837
15838 err = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities);
15839 if (err)
15840 goto err_adminq_setup;
15841
15842 err = i40e_sw_init(pf);
15843 if (err) {
15844 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
15845 goto err_sw_init;
15846 }
15847
15848 if (test_bit(__I40E_RECOVERY_MODE, pf->state))
15849 return i40e_init_recovery_mode(pf, hw);
15850
15851 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
15852 hw->func_caps.num_rx_qp, 0, 0);
15853 if (err) {
15854 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
15855 goto err_init_lan_hmc;
15856 }
15857
15858 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
15859 if (err) {
15860 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
15861 err = -ENOENT;
15862 goto err_configure_lan_hmc;
15863 }
15864
15865 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
15866 * Ignore error return codes because if it was already disabled via
15867 * hardware settings this will fail
15868 */
15869 if (test_bit(I40E_HW_CAP_STOP_FW_LLDP, pf->hw.caps)) {
15870 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
15871 i40e_aq_stop_lldp(hw, true, false, NULL);
15872 }
15873
15874 /* allow a platform config to override the HW addr */
15875 i40e_get_platform_mac_addr(pdev, pf);
15876
15877 if (!is_valid_ether_addr(hw->mac.addr)) {
15878 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
15879 err = -EIO;
15880 goto err_mac_addr;
15881 }
15882 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
15883 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
15884 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
15885 if (is_valid_ether_addr(hw->mac.port_addr))
15886 set_bit(I40E_HW_CAP_PORT_ID_VALID, pf->hw.caps);
15887
15888 i40e_ptp_alloc_pins(pf);
15889 pci_set_drvdata(pdev, pf);
15890 pci_save_state(pdev);
15891
15892 #ifdef CONFIG_I40E_DCB
15893 status = i40e_get_fw_lldp_status(&pf->hw, &lldp_status);
15894 (!status &&
15895 lldp_status == I40E_GET_FW_LLDP_STATUS_ENABLED) ?
15896 (clear_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags)) :
15897 (set_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags));
15898 dev_info(&pdev->dev,
15899 test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags) ?
15900 "FW LLDP is disabled\n" :
15901 "FW LLDP is enabled\n");
15902
15903 /* Enable FW to write default DCB config on link-up */
15904 i40e_aq_set_dcb_parameters(hw, true, NULL);
15905
15906 err = i40e_init_pf_dcb(pf);
15907 if (err) {
15908 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
15909 clear_bit(I40E_FLAG_DCB_CAPABLE, pf->flags);
15910 clear_bit(I40E_FLAG_DCB_ENA, pf->flags);
15911 /* Continue without DCB enabled */
15912 }
15913 #endif /* CONFIG_I40E_DCB */
15914
15915 /* set up periodic task facility */
15916 timer_setup(&pf->service_timer, i40e_service_timer, 0);
15917 pf->service_timer_period = HZ;
15918
15919 INIT_WORK(&pf->service_task, i40e_service_task);
15920 clear_bit(__I40E_SERVICE_SCHED, pf->state);
15921
15922 /* NVM bit on means WoL disabled for the port */
15923 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
15924 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
15925 pf->wol_en = false;
15926 else
15927 pf->wol_en = true;
15928 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
15929
15930 /* set up the main switch operations */
15931 i40e_determine_queue_usage(pf);
15932 err = i40e_init_interrupt_scheme(pf);
15933 if (err)
15934 goto err_switch_setup;
15935
15936 /* Reduce Tx and Rx pairs for kdump
15937 * When MSI-X is enabled, it's not allowed to use more TC queue
15938 * pairs than MSI-X vectors (pf->num_lan_msix) exist. Thus
15939 * vsi->num_queue_pairs will be equal to pf->num_lan_msix, i.e., 1.
15940 */
15941 if (is_kdump_kernel())
15942 pf->num_lan_msix = 1;
15943
15944 pf->udp_tunnel_nic.set_port = i40e_udp_tunnel_set_port;
15945 pf->udp_tunnel_nic.unset_port = i40e_udp_tunnel_unset_port;
15946 pf->udp_tunnel_nic.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP;
15947 pf->udp_tunnel_nic.shared = &pf->udp_tunnel_shared;
15948 pf->udp_tunnel_nic.tables[0].n_entries = I40E_MAX_PF_UDP_OFFLOAD_PORTS;
15949 pf->udp_tunnel_nic.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN |
15950 UDP_TUNNEL_TYPE_GENEVE;
15951
15952 /* The number of VSIs reported by the FW is the minimum guaranteed
15953 * to us; HW supports far more and we share the remaining pool with
15954 * the other PFs. We allocate space for more than the guarantee with
15955 * the understanding that we might not get them all later.
15956 */
15957 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
15958 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
15959 else
15960 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
15961 if (pf->num_alloc_vsi > UDP_TUNNEL_NIC_MAX_SHARING_DEVICES) {
15962 dev_warn(&pf->pdev->dev,
15963 "limiting the VSI count due to UDP tunnel limitation %d > %d\n",
15964 pf->num_alloc_vsi, UDP_TUNNEL_NIC_MAX_SHARING_DEVICES);
15965 pf->num_alloc_vsi = UDP_TUNNEL_NIC_MAX_SHARING_DEVICES;
15966 }
15967
15968 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
15969 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
15970 GFP_KERNEL);
15971 if (!pf->vsi) {
15972 err = -ENOMEM;
15973 goto err_switch_setup;
15974 }
15975
15976 #ifdef CONFIG_PCI_IOV
15977 /* prep for VF support */
15978 if (test_bit(I40E_FLAG_SRIOV_ENA, pf->flags) &&
15979 test_bit(I40E_FLAG_MSIX_ENA, pf->flags) &&
15980 !test_bit(__I40E_BAD_EEPROM, pf->state)) {
15981 if (pci_num_vf(pdev))
15982 set_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
15983 }
15984 #endif
15985 err = i40e_setup_pf_switch(pf, false, false);
15986 if (err) {
15987 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
15988 goto err_vsis;
15989 }
15990 INIT_LIST_HEAD(&pf->vsi[pf->lan_vsi]->ch_list);
15991
15992 /* if FDIR VSI was set up, start it now */
15993 for (i = 0; i < pf->num_alloc_vsi; i++) {
15994 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
15995 i40e_vsi_open(pf->vsi[i]);
15996 break;
15997 }
15998 }
15999
16000 /* The driver only wants link up/down and module qualification
16001 * reports from firmware. Note the negative logic.
16002 */
16003 err = i40e_aq_set_phy_int_mask(&pf->hw,
16004 ~(I40E_AQ_EVENT_LINK_UPDOWN |
16005 I40E_AQ_EVENT_MEDIA_NA |
16006 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
16007 if (err)
16008 dev_info(&pf->pdev->dev, "set phy mask fail, err %pe aq_err %s\n",
16009 ERR_PTR(err),
16010 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
16011
16012 /* Reconfigure hardware for allowing smaller MSS in the case
16013 * of TSO, so that we avoid the MDD being fired and causing
16014 * a reset in the case of small MSS+TSO.
16015 */
16016 val = rd32(hw, I40E_REG_MSS);
16017 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
16018 val &= ~I40E_REG_MSS_MIN_MASK;
16019 val |= I40E_64BYTE_MSS;
16020 wr32(hw, I40E_REG_MSS, val);
16021 }
16022
16023 if (test_bit(I40E_HW_CAP_RESTART_AUTONEG, pf->hw.caps)) {
16024 msleep(75);
16025 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
16026 if (err)
16027 dev_info(&pf->pdev->dev, "link restart failed, err %pe aq_err %s\n",
16028 ERR_PTR(err),
16029 i40e_aq_str(&pf->hw,
16030 pf->hw.aq.asq_last_status));
16031 }
16032 /* The main driver is (mostly) up and happy. We need to set this state
16033 * before setting up the misc vector or we get a race and the vector
16034 * ends up disabled forever.
16035 */
16036 clear_bit(__I40E_DOWN, pf->state);
16037
16038 /* In case of MSIX we are going to setup the misc vector right here
16039 * to handle admin queue events etc. In case of legacy and MSI
16040 * the misc functionality and queue processing is combined in
16041 * the same vector and that gets setup at open.
16042 */
16043 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
16044 err = i40e_setup_misc_vector(pf);
16045 if (err) {
16046 dev_info(&pdev->dev,
16047 "setup of misc vector failed: %d\n", err);
16048 i40e_cloud_filter_exit(pf);
16049 i40e_fdir_teardown(pf);
16050 goto err_vsis;
16051 }
16052 }
16053
16054 #ifdef CONFIG_PCI_IOV
16055 /* prep for VF support */
16056 if (test_bit(I40E_FLAG_SRIOV_ENA, pf->flags) &&
16057 test_bit(I40E_FLAG_MSIX_ENA, pf->flags) &&
16058 !test_bit(__I40E_BAD_EEPROM, pf->state)) {
16059 /* disable link interrupts for VFs */
16060 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
16061 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
16062 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
16063 i40e_flush(hw);
16064
16065 if (pci_num_vf(pdev)) {
16066 dev_info(&pdev->dev,
16067 "Active VFs found, allocating resources.\n");
16068 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
16069 if (err)
16070 dev_info(&pdev->dev,
16071 "Error %d allocating resources for existing VFs\n",
16072 err);
16073 }
16074 }
16075 #endif /* CONFIG_PCI_IOV */
16076
16077 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags)) {
16078 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
16079 pf->num_iwarp_msix,
16080 I40E_IWARP_IRQ_PILE_ID);
16081 if (pf->iwarp_base_vector < 0) {
16082 dev_info(&pdev->dev,
16083 "failed to get tracking for %d vectors for IWARP err=%d\n",
16084 pf->num_iwarp_msix, pf->iwarp_base_vector);
16085 clear_bit(I40E_FLAG_IWARP_ENA, pf->flags);
16086 }
16087 }
16088
16089 i40e_dbg_pf_init(pf);
16090
16091 /* tell the firmware that we're starting */
16092 i40e_send_version(pf);
16093
16094 /* since everything's happy, start the service_task timer */
16095 mod_timer(&pf->service_timer,
16096 round_jiffies(jiffies + pf->service_timer_period));
16097
16098 /* add this PF to client device list and launch a client service task */
16099 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags)) {
16100 err = i40e_lan_add_device(pf);
16101 if (err)
16102 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
16103 err);
16104 }
16105
16106 #define PCI_SPEED_SIZE 8
16107 #define PCI_WIDTH_SIZE 8
16108 /* Devices on the IOSF bus do not have this information
16109 * and will report PCI Gen 1 x 1 by default so don't bother
16110 * checking them.
16111 */
16112 if (!test_bit(I40E_HW_CAP_NO_PCI_LINK_CHECK, pf->hw.caps)) {
16113 char speed[PCI_SPEED_SIZE] = "Unknown";
16114 char width[PCI_WIDTH_SIZE] = "Unknown";
16115
16116 /* Get the negotiated link width and speed from PCI config
16117 * space
16118 */
16119 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
16120 &link_status);
16121
16122 i40e_set_pci_config_data(hw, link_status);
16123
16124 switch (hw->bus.speed) {
16125 case i40e_bus_speed_8000:
16126 strscpy(speed, "8.0", PCI_SPEED_SIZE); break;
16127 case i40e_bus_speed_5000:
16128 strscpy(speed, "5.0", PCI_SPEED_SIZE); break;
16129 case i40e_bus_speed_2500:
16130 strscpy(speed, "2.5", PCI_SPEED_SIZE); break;
16131 default:
16132 break;
16133 }
16134 switch (hw->bus.width) {
16135 case i40e_bus_width_pcie_x8:
16136 strscpy(width, "8", PCI_WIDTH_SIZE); break;
16137 case i40e_bus_width_pcie_x4:
16138 strscpy(width, "4", PCI_WIDTH_SIZE); break;
16139 case i40e_bus_width_pcie_x2:
16140 strscpy(width, "2", PCI_WIDTH_SIZE); break;
16141 case i40e_bus_width_pcie_x1:
16142 strscpy(width, "1", PCI_WIDTH_SIZE); break;
16143 default:
16144 break;
16145 }
16146
16147 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
16148 speed, width);
16149
16150 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
16151 hw->bus.speed < i40e_bus_speed_8000) {
16152 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
16153 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
16154 }
16155 }
16156
16157 /* get the requested speeds from the fw */
16158 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
16159 if (err)
16160 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %pe last_status = %s\n",
16161 ERR_PTR(err),
16162 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
16163 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
16164
16165 /* set the FEC config due to the board capabilities */
16166 i40e_set_fec_in_flags(abilities.fec_cfg_curr_mod_ext_info, pf->flags);
16167
16168 /* get the supported phy types from the fw */
16169 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
16170 if (err)
16171 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %pe last_status = %s\n",
16172 ERR_PTR(err),
16173 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
16174
16175 /* make sure the MFS hasn't been set lower than the default */
16176 #define MAX_FRAME_SIZE_DEFAULT 0x2600
16177 val = FIELD_GET(I40E_PRTGL_SAH_MFS_MASK,
16178 rd32(&pf->hw, I40E_PRTGL_SAH));
16179 if (val < MAX_FRAME_SIZE_DEFAULT)
16180 dev_warn(&pdev->dev, "MFS for port %x has been set below the default: %x\n",
16181 pf->hw.port, val);
16182
16183 /* Add a filter to drop all Flow control frames from any VSI from being
16184 * transmitted. By doing so we stop a malicious VF from sending out
16185 * PAUSE or PFC frames and potentially controlling traffic for other
16186 * PF/VF VSIs.
16187 * The FW can still send Flow control frames if enabled.
16188 */
16189 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
16190 pf->main_vsi_seid);
16191
16192 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
16193 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
16194 set_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf->hw.caps);
16195 if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722)
16196 set_bit(I40E_HW_CAP_CRT_RETIMER, pf->hw.caps);
16197 /* print a string summarizing features */
16198 i40e_print_features(pf);
16199
16200 i40e_devlink_register(pf);
16201
16202 return 0;
16203
16204 /* Unwind what we've done if something failed in the setup */
16205 err_vsis:
16206 set_bit(__I40E_DOWN, pf->state);
16207 i40e_clear_interrupt_scheme(pf);
16208 kfree(pf->vsi);
16209 err_switch_setup:
16210 i40e_reset_interrupt_capability(pf);
16211 timer_shutdown_sync(&pf->service_timer);
16212 err_mac_addr:
16213 err_configure_lan_hmc:
16214 (void)i40e_shutdown_lan_hmc(hw);
16215 err_init_lan_hmc:
16216 kfree(pf->qp_pile);
16217 err_sw_init:
16218 err_adminq_setup:
16219 err_pf_reset:
16220 iounmap(hw->hw_addr);
16221 err_ioremap:
16222 i40e_free_pf(pf);
16223 err_pf_alloc:
16224 pci_release_mem_regions(pdev);
16225 err_pci_reg:
16226 err_dma:
16227 pci_disable_device(pdev);
16228 return err;
16229 }
16230
16231 /**
16232 * i40e_remove - Device removal routine
16233 * @pdev: PCI device information struct
16234 *
16235 * i40e_remove is called by the PCI subsystem to alert the driver
16236 * that is should release a PCI device. This could be caused by a
16237 * Hot-Plug event, or because the driver is going to be removed from
16238 * memory.
16239 **/
i40e_remove(struct pci_dev * pdev)16240 static void i40e_remove(struct pci_dev *pdev)
16241 {
16242 struct i40e_pf *pf = pci_get_drvdata(pdev);
16243 struct i40e_hw *hw = &pf->hw;
16244 int ret_code;
16245 int i;
16246
16247 i40e_devlink_unregister(pf);
16248
16249 i40e_dbg_pf_exit(pf);
16250
16251 i40e_ptp_stop(pf);
16252
16253 /* Disable RSS in hw */
16254 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
16255 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
16256
16257 /* Grab __I40E_RESET_RECOVERY_PENDING and set __I40E_IN_REMOVE
16258 * flags, once they are set, i40e_rebuild should not be called as
16259 * i40e_prep_for_reset always returns early.
16260 */
16261 while (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
16262 usleep_range(1000, 2000);
16263 set_bit(__I40E_IN_REMOVE, pf->state);
16264
16265 if (test_bit(I40E_FLAG_SRIOV_ENA, pf->flags)) {
16266 set_bit(__I40E_VF_RESETS_DISABLED, pf->state);
16267 i40e_free_vfs(pf);
16268 clear_bit(I40E_FLAG_SRIOV_ENA, pf->flags);
16269 }
16270 /* no more scheduling of any task */
16271 set_bit(__I40E_SUSPENDED, pf->state);
16272 set_bit(__I40E_DOWN, pf->state);
16273 if (pf->service_timer.function)
16274 timer_shutdown_sync(&pf->service_timer);
16275 if (pf->service_task.func)
16276 cancel_work_sync(&pf->service_task);
16277
16278 if (test_bit(__I40E_RECOVERY_MODE, pf->state)) {
16279 struct i40e_vsi *vsi = pf->vsi[0];
16280
16281 /* We know that we have allocated only one vsi for this PF,
16282 * it was just for registering netdevice, so the interface
16283 * could be visible in the 'ifconfig' output
16284 */
16285 unregister_netdev(vsi->netdev);
16286 free_netdev(vsi->netdev);
16287
16288 goto unmap;
16289 }
16290
16291 /* Client close must be called explicitly here because the timer
16292 * has been stopped.
16293 */
16294 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
16295
16296 i40e_fdir_teardown(pf);
16297
16298 /* If there is a switch structure or any orphans, remove them.
16299 * This will leave only the PF's VSI remaining.
16300 */
16301 for (i = 0; i < I40E_MAX_VEB; i++) {
16302 if (!pf->veb[i])
16303 continue;
16304
16305 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
16306 pf->veb[i]->uplink_seid == 0)
16307 i40e_switch_branch_release(pf->veb[i]);
16308 }
16309
16310 /* Now we can shutdown the PF's VSIs, just before we kill
16311 * adminq and hmc.
16312 */
16313 for (i = pf->num_alloc_vsi; i--;)
16314 if (pf->vsi[i]) {
16315 i40e_vsi_close(pf->vsi[i]);
16316 i40e_vsi_release(pf->vsi[i]);
16317 pf->vsi[i] = NULL;
16318 }
16319
16320 i40e_cloud_filter_exit(pf);
16321
16322 /* remove attached clients */
16323 if (test_bit(I40E_FLAG_IWARP_ENA, pf->flags)) {
16324 ret_code = i40e_lan_del_device(pf);
16325 if (ret_code)
16326 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
16327 ret_code);
16328 }
16329
16330 /* shutdown and destroy the HMC */
16331 if (hw->hmc.hmc_obj) {
16332 ret_code = i40e_shutdown_lan_hmc(hw);
16333 if (ret_code)
16334 dev_warn(&pdev->dev,
16335 "Failed to destroy the HMC resources: %d\n",
16336 ret_code);
16337 }
16338
16339 unmap:
16340 /* Free MSI/legacy interrupt 0 when in recovery mode. */
16341 if (test_bit(__I40E_RECOVERY_MODE, pf->state) &&
16342 !test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
16343 free_irq(pf->pdev->irq, pf);
16344
16345 /* shutdown the adminq */
16346 i40e_shutdown_adminq(hw);
16347
16348 /* destroy the locks only once, here */
16349 mutex_destroy(&hw->aq.arq_mutex);
16350 mutex_destroy(&hw->aq.asq_mutex);
16351
16352 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
16353 rtnl_lock();
16354 i40e_clear_interrupt_scheme(pf);
16355 for (i = 0; i < pf->num_alloc_vsi; i++) {
16356 if (pf->vsi[i]) {
16357 if (!test_bit(__I40E_RECOVERY_MODE, pf->state))
16358 i40e_vsi_clear_rings(pf->vsi[i]);
16359 i40e_vsi_clear(pf->vsi[i]);
16360 pf->vsi[i] = NULL;
16361 }
16362 }
16363 rtnl_unlock();
16364
16365 for (i = 0; i < I40E_MAX_VEB; i++) {
16366 kfree(pf->veb[i]);
16367 pf->veb[i] = NULL;
16368 }
16369
16370 kfree(pf->qp_pile);
16371 kfree(pf->vsi);
16372
16373 iounmap(hw->hw_addr);
16374 i40e_free_pf(pf);
16375 pci_release_mem_regions(pdev);
16376
16377 pci_disable_device(pdev);
16378 }
16379
16380 /**
16381 * i40e_pci_error_detected - warning that something funky happened in PCI land
16382 * @pdev: PCI device information struct
16383 * @error: the type of PCI error
16384 *
16385 * Called to warn that something happened and the error handling steps
16386 * are in progress. Allows the driver to quiesce things, be ready for
16387 * remediation.
16388 **/
i40e_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t error)16389 static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
16390 pci_channel_state_t error)
16391 {
16392 struct i40e_pf *pf = pci_get_drvdata(pdev);
16393
16394 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
16395
16396 if (!pf) {
16397 dev_info(&pdev->dev,
16398 "Cannot recover - error happened during device probe\n");
16399 return PCI_ERS_RESULT_DISCONNECT;
16400 }
16401
16402 /* shutdown all operations */
16403 if (!test_bit(__I40E_SUSPENDED, pf->state))
16404 i40e_prep_for_reset(pf);
16405
16406 /* Request a slot reset */
16407 return PCI_ERS_RESULT_NEED_RESET;
16408 }
16409
16410 /**
16411 * i40e_pci_error_slot_reset - a PCI slot reset just happened
16412 * @pdev: PCI device information struct
16413 *
16414 * Called to find if the driver can work with the device now that
16415 * the pci slot has been reset. If a basic connection seems good
16416 * (registers are readable and have sane content) then return a
16417 * happy little PCI_ERS_RESULT_xxx.
16418 **/
i40e_pci_error_slot_reset(struct pci_dev * pdev)16419 static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
16420 {
16421 struct i40e_pf *pf = pci_get_drvdata(pdev);
16422 pci_ers_result_t result;
16423 u32 reg;
16424
16425 dev_dbg(&pdev->dev, "%s\n", __func__);
16426 if (pci_enable_device_mem(pdev)) {
16427 dev_info(&pdev->dev,
16428 "Cannot re-enable PCI device after reset.\n");
16429 result = PCI_ERS_RESULT_DISCONNECT;
16430 } else {
16431 pci_set_master(pdev);
16432 pci_restore_state(pdev);
16433 pci_save_state(pdev);
16434 pci_wake_from_d3(pdev, false);
16435
16436 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
16437 if (reg == 0)
16438 result = PCI_ERS_RESULT_RECOVERED;
16439 else
16440 result = PCI_ERS_RESULT_DISCONNECT;
16441 }
16442
16443 return result;
16444 }
16445
16446 /**
16447 * i40e_pci_error_reset_prepare - prepare device driver for pci reset
16448 * @pdev: PCI device information struct
16449 */
i40e_pci_error_reset_prepare(struct pci_dev * pdev)16450 static void i40e_pci_error_reset_prepare(struct pci_dev *pdev)
16451 {
16452 struct i40e_pf *pf = pci_get_drvdata(pdev);
16453
16454 i40e_prep_for_reset(pf);
16455 }
16456
16457 /**
16458 * i40e_pci_error_reset_done - pci reset done, device driver reset can begin
16459 * @pdev: PCI device information struct
16460 */
i40e_pci_error_reset_done(struct pci_dev * pdev)16461 static void i40e_pci_error_reset_done(struct pci_dev *pdev)
16462 {
16463 struct i40e_pf *pf = pci_get_drvdata(pdev);
16464
16465 if (test_bit(__I40E_IN_REMOVE, pf->state))
16466 return;
16467
16468 i40e_reset_and_rebuild(pf, false, false);
16469 #ifdef CONFIG_PCI_IOV
16470 i40e_restore_all_vfs_msi_state(pdev);
16471 #endif /* CONFIG_PCI_IOV */
16472 }
16473
16474 /**
16475 * i40e_pci_error_resume - restart operations after PCI error recovery
16476 * @pdev: PCI device information struct
16477 *
16478 * Called to allow the driver to bring things back up after PCI error
16479 * and/or reset recovery has finished.
16480 **/
i40e_pci_error_resume(struct pci_dev * pdev)16481 static void i40e_pci_error_resume(struct pci_dev *pdev)
16482 {
16483 struct i40e_pf *pf = pci_get_drvdata(pdev);
16484
16485 dev_dbg(&pdev->dev, "%s\n", __func__);
16486 if (test_bit(__I40E_SUSPENDED, pf->state))
16487 return;
16488
16489 i40e_handle_reset_warning(pf, false);
16490 }
16491
16492 /**
16493 * i40e_enable_mc_magic_wake - enable multicast magic packet wake up
16494 * using the mac_address_write admin q function
16495 * @pf: pointer to i40e_pf struct
16496 **/
i40e_enable_mc_magic_wake(struct i40e_pf * pf)16497 static void i40e_enable_mc_magic_wake(struct i40e_pf *pf)
16498 {
16499 struct i40e_hw *hw = &pf->hw;
16500 u8 mac_addr[6];
16501 u16 flags = 0;
16502 int ret;
16503
16504 /* Get current MAC address in case it's an LAA */
16505 if (pf->vsi[pf->lan_vsi] && pf->vsi[pf->lan_vsi]->netdev) {
16506 ether_addr_copy(mac_addr,
16507 pf->vsi[pf->lan_vsi]->netdev->dev_addr);
16508 } else {
16509 dev_err(&pf->pdev->dev,
16510 "Failed to retrieve MAC address; using default\n");
16511 ether_addr_copy(mac_addr, hw->mac.addr);
16512 }
16513
16514 /* The FW expects the mac address write cmd to first be called with
16515 * one of these flags before calling it again with the multicast
16516 * enable flags.
16517 */
16518 flags = I40E_AQC_WRITE_TYPE_LAA_WOL;
16519
16520 if (hw->func_caps.flex10_enable && hw->partition_id != 1)
16521 flags = I40E_AQC_WRITE_TYPE_LAA_ONLY;
16522
16523 ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL);
16524 if (ret) {
16525 dev_err(&pf->pdev->dev,
16526 "Failed to update MAC address registers; cannot enable Multicast Magic packet wake up");
16527 return;
16528 }
16529
16530 flags = I40E_AQC_MC_MAG_EN
16531 | I40E_AQC_WOL_PRESERVE_ON_PFR
16532 | I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG;
16533 ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL);
16534 if (ret)
16535 dev_err(&pf->pdev->dev,
16536 "Failed to enable Multicast Magic Packet wake up\n");
16537 }
16538
16539 /**
16540 * i40e_shutdown - PCI callback for shutting down
16541 * @pdev: PCI device information struct
16542 **/
i40e_shutdown(struct pci_dev * pdev)16543 static void i40e_shutdown(struct pci_dev *pdev)
16544 {
16545 struct i40e_pf *pf = pci_get_drvdata(pdev);
16546 struct i40e_hw *hw = &pf->hw;
16547
16548 set_bit(__I40E_SUSPENDED, pf->state);
16549 set_bit(__I40E_DOWN, pf->state);
16550
16551 del_timer_sync(&pf->service_timer);
16552 cancel_work_sync(&pf->service_task);
16553 i40e_cloud_filter_exit(pf);
16554 i40e_fdir_teardown(pf);
16555
16556 /* Client close must be called explicitly here because the timer
16557 * has been stopped.
16558 */
16559 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
16560
16561 if (test_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, pf->hw.caps) &&
16562 pf->wol_en)
16563 i40e_enable_mc_magic_wake(pf);
16564
16565 i40e_prep_for_reset(pf);
16566
16567 wr32(hw, I40E_PFPM_APM,
16568 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
16569 wr32(hw, I40E_PFPM_WUFC,
16570 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
16571
16572 /* Free MSI/legacy interrupt 0 when in recovery mode. */
16573 if (test_bit(__I40E_RECOVERY_MODE, pf->state) &&
16574 !test_bit(I40E_FLAG_MSIX_ENA, pf->flags))
16575 free_irq(pf->pdev->irq, pf);
16576
16577 /* Since we're going to destroy queues during the
16578 * i40e_clear_interrupt_scheme() we should hold the RTNL lock for this
16579 * whole section
16580 */
16581 rtnl_lock();
16582 i40e_clear_interrupt_scheme(pf);
16583 rtnl_unlock();
16584
16585 if (system_state == SYSTEM_POWER_OFF) {
16586 pci_wake_from_d3(pdev, pf->wol_en);
16587 pci_set_power_state(pdev, PCI_D3hot);
16588 }
16589 }
16590
16591 /**
16592 * i40e_suspend - PM callback for moving to D3
16593 * @dev: generic device information structure
16594 **/
i40e_suspend(struct device * dev)16595 static int __maybe_unused i40e_suspend(struct device *dev)
16596 {
16597 struct i40e_pf *pf = dev_get_drvdata(dev);
16598 struct i40e_hw *hw = &pf->hw;
16599
16600 /* If we're already suspended, then there is nothing to do */
16601 if (test_and_set_bit(__I40E_SUSPENDED, pf->state))
16602 return 0;
16603
16604 set_bit(__I40E_DOWN, pf->state);
16605
16606 /* Ensure service task will not be running */
16607 del_timer_sync(&pf->service_timer);
16608 cancel_work_sync(&pf->service_task);
16609
16610 /* Client close must be called explicitly here because the timer
16611 * has been stopped.
16612 */
16613 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
16614
16615 if (test_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, pf->hw.caps) &&
16616 pf->wol_en)
16617 i40e_enable_mc_magic_wake(pf);
16618
16619 /* Since we're going to destroy queues during the
16620 * i40e_clear_interrupt_scheme() we should hold the RTNL lock for this
16621 * whole section
16622 */
16623 rtnl_lock();
16624
16625 i40e_prep_for_reset(pf);
16626
16627 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
16628 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
16629
16630 /* Clear the interrupt scheme and release our IRQs so that the system
16631 * can safely hibernate even when there are a large number of CPUs.
16632 * Otherwise hibernation might fail when mapping all the vectors back
16633 * to CPU0.
16634 */
16635 i40e_clear_interrupt_scheme(pf);
16636
16637 rtnl_unlock();
16638
16639 return 0;
16640 }
16641
16642 /**
16643 * i40e_resume - PM callback for waking up from D3
16644 * @dev: generic device information structure
16645 **/
i40e_resume(struct device * dev)16646 static int __maybe_unused i40e_resume(struct device *dev)
16647 {
16648 struct i40e_pf *pf = dev_get_drvdata(dev);
16649 int err;
16650
16651 /* If we're not suspended, then there is nothing to do */
16652 if (!test_bit(__I40E_SUSPENDED, pf->state))
16653 return 0;
16654
16655 /* We need to hold the RTNL lock prior to restoring interrupt schemes,
16656 * since we're going to be restoring queues
16657 */
16658 rtnl_lock();
16659
16660 /* We cleared the interrupt scheme when we suspended, so we need to
16661 * restore it now to resume device functionality.
16662 */
16663 err = i40e_restore_interrupt_scheme(pf);
16664 if (err) {
16665 dev_err(dev, "Cannot restore interrupt scheme: %d\n",
16666 err);
16667 }
16668
16669 clear_bit(__I40E_DOWN, pf->state);
16670 i40e_reset_and_rebuild(pf, false, true);
16671
16672 rtnl_unlock();
16673
16674 /* Clear suspended state last after everything is recovered */
16675 clear_bit(__I40E_SUSPENDED, pf->state);
16676
16677 /* Restart the service task */
16678 mod_timer(&pf->service_timer,
16679 round_jiffies(jiffies + pf->service_timer_period));
16680
16681 return 0;
16682 }
16683
16684 static const struct pci_error_handlers i40e_err_handler = {
16685 .error_detected = i40e_pci_error_detected,
16686 .slot_reset = i40e_pci_error_slot_reset,
16687 .reset_prepare = i40e_pci_error_reset_prepare,
16688 .reset_done = i40e_pci_error_reset_done,
16689 .resume = i40e_pci_error_resume,
16690 };
16691
16692 static SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume);
16693
16694 static struct pci_driver i40e_driver = {
16695 .name = i40e_driver_name,
16696 .id_table = i40e_pci_tbl,
16697 .probe = i40e_probe,
16698 .remove = i40e_remove,
16699 .driver = {
16700 .pm = &i40e_pm_ops,
16701 },
16702 .shutdown = i40e_shutdown,
16703 .err_handler = &i40e_err_handler,
16704 .sriov_configure = i40e_pci_sriov_configure,
16705 };
16706
16707 /**
16708 * i40e_init_module - Driver registration routine
16709 *
16710 * i40e_init_module is the first routine called when the driver is
16711 * loaded. All it does is register with the PCI subsystem.
16712 **/
i40e_init_module(void)16713 static int __init i40e_init_module(void)
16714 {
16715 int err;
16716
16717 pr_info("%s: %s\n", i40e_driver_name, i40e_driver_string);
16718 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
16719
16720 /* There is no need to throttle the number of active tasks because
16721 * each device limits its own task using a state bit for scheduling
16722 * the service task, and the device tasks do not interfere with each
16723 * other, so we don't set a max task limit. We must set WQ_MEM_RECLAIM
16724 * since we need to be able to guarantee forward progress even under
16725 * memory pressure.
16726 */
16727 i40e_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, i40e_driver_name);
16728 if (!i40e_wq) {
16729 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
16730 return -ENOMEM;
16731 }
16732
16733 i40e_dbg_init();
16734 err = pci_register_driver(&i40e_driver);
16735 if (err) {
16736 destroy_workqueue(i40e_wq);
16737 i40e_dbg_exit();
16738 return err;
16739 }
16740
16741 return 0;
16742 }
16743 module_init(i40e_init_module);
16744
16745 /**
16746 * i40e_exit_module - Driver exit cleanup routine
16747 *
16748 * i40e_exit_module is called just before the driver is removed
16749 * from memory.
16750 **/
i40e_exit_module(void)16751 static void __exit i40e_exit_module(void)
16752 {
16753 pci_unregister_driver(&i40e_driver);
16754 destroy_workqueue(i40e_wq);
16755 ida_destroy(&i40e_client_ida);
16756 i40e_dbg_exit();
16757 }
16758 module_exit(i40e_exit_module);
16759