1 /*
2 * QEMU Malta board support
3 *
4 * Copyright (c) 2006 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/bitops.h"
28 #include "qemu/datadir.h"
29 #include "qemu/cutils.h"
30 #include "qemu/guest-random.h"
31 #include "exec/tswap.h"
32 #include "hw/clock.h"
33 #include "hw/southbridge/piix.h"
34 #include "hw/isa/superio.h"
35 #include "hw/char/serial-mm.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/i2c/smbus_eeprom.h"
39 #include "hw/block/flash.h"
40 #include "hw/mips/mips.h"
41 #include "hw/mips/bootloader.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci/pci_bus.h"
44 #include "qemu/log.h"
45 #include "hw/ide/pci.h"
46 #include "hw/irq.h"
47 #include "hw/loader.h"
48 #include "elf.h"
49 #include "qom/object.h"
50 #include "hw/sysbus.h" /* SysBusDevice */
51 #include "qemu/host-utils.h"
52 #include "system/qtest.h"
53 #include "system/reset.h"
54 #include "system/runstate.h"
55 #include "qapi/error.h"
56 #include "qemu/error-report.h"
57 #include "system/kvm.h"
58 #include "semihosting/semihost.h"
59 #include "hw/mips/cps.h"
60 #include "hw/qdev-clock.h"
61 #include "target/mips/internal.h"
62 #include "trace.h"
63 #include "cpu.h"
64
65 #define ENVP_PADDR 0x2000
66 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
67 #define ENVP_NB_ENTRIES 16
68 #define ENVP_ENTRY_SIZE 256
69
70 /* Hardware addresses */
71 #define FLASH_ADDRESS 0x1e000000ULL
72 #define FPGA_ADDRESS 0x1f000000ULL
73 #define RESET_ADDRESS 0x1fc00000ULL
74
75 #define FLASH_SIZE 0x400000
76 #define BIOS_SIZE (4 * MiB)
77
78 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
79
80 typedef struct {
81 MemoryRegion iomem;
82 MemoryRegion iomem_lo; /* 0 - 0x900 */
83 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
84 uint32_t leds;
85 uint32_t brk;
86 uint32_t gpout;
87 uint32_t i2cin;
88 uint32_t i2coe;
89 uint32_t i2cout;
90 uint32_t i2csel;
91 CharBackend display;
92 char display_text[9];
93 SerialMM *uart;
94 bool display_inited;
95 } MaltaFPGAState;
96
97 #define TYPE_MIPS_MALTA "mips-malta"
98 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
99
100 struct MaltaState {
101 SysBusDevice parent_obj;
102
103 Clock *cpuclk;
104 MIPSCPSState cps;
105 };
106
107 static struct _loaderparams {
108 int ram_size, ram_low_size;
109 const char *kernel_filename;
110 const char *kernel_cmdline;
111 const char *initrd_filename;
112 } loaderparams;
113
114 /* Malta FPGA */
malta_fpga_update_display_leds(MaltaFPGAState * s)115 static void malta_fpga_update_display_leds(MaltaFPGAState *s)
116 {
117 char leds_text[9];
118 int i;
119
120 for (i = 7 ; i >= 0 ; i--) {
121 if (s->leds & (1 << i)) {
122 leds_text[i] = '#';
123 } else {
124 leds_text[i] = ' ';
125 }
126 }
127 leds_text[8] = '\0';
128
129 trace_malta_fpga_leds(leds_text);
130 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
131 leds_text);
132 }
133
malta_fpga_update_display_ascii(MaltaFPGAState * s)134 static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
135 {
136 trace_malta_fpga_display(s->display_text);
137 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
138 s->display_text);
139 }
140
141 /*
142 * EEPROM 24C01 / 24C02 emulation.
143 *
144 * Emulation for serial EEPROMs:
145 * 24C01 - 1024 bit (128 x 8)
146 * 24C02 - 2048 bit (256 x 8)
147 *
148 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
149 */
150
151 #if defined(DEBUG)
152 # define logout(fmt, ...) \
153 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
154 #else
155 # define logout(fmt, ...) ((void)0)
156 #endif
157
158 struct _eeprom24c0x_t {
159 uint8_t tick;
160 uint8_t address;
161 uint8_t command;
162 uint8_t ack;
163 uint8_t scl;
164 uint8_t sda;
165 uint8_t data;
166 /* uint16_t size; */
167 uint8_t contents[256];
168 };
169
170 typedef struct _eeprom24c0x_t eeprom24c0x_t;
171
172 static eeprom24c0x_t spd_eeprom = {
173 .contents = {
174 /* 00000000: */
175 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
176 /* 00000008: */
177 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
178 /* 00000010: */
179 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
180 /* 00000018: */
181 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
182 /* 00000020: */
183 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
184 /* 00000028: */
185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
186 /* 00000030: */
187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
188 /* 00000038: */
189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
190 /* 00000040: */
191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 /* 00000048: */
193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 /* 00000050: */
195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
196 /* 00000058: */
197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198 /* 00000060: */
199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
200 /* 00000068: */
201 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
202 /* 00000070: */
203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
204 /* 00000078: */
205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
206 },
207 };
208
generate_eeprom_spd(uint8_t * eeprom,ram_addr_t ram_size)209 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
210 {
211 enum sdram_type type;
212 uint8_t *spd = spd_eeprom.contents;
213 uint8_t nbanks = 0;
214 uint16_t density = 0;
215 int i;
216
217 /* work in terms of MB */
218 ram_size /= MiB;
219
220 while ((ram_size >= 4) && (nbanks <= 2)) {
221 int sz_log2 = MIN(31 - clz32(ram_size), 14);
222 nbanks++;
223 density |= 1 << (sz_log2 - 2);
224 ram_size -= 1 << sz_log2;
225 }
226
227 /* split to 2 banks if possible */
228 if ((nbanks == 1) && (density > 1)) {
229 nbanks++;
230 density >>= 1;
231 }
232
233 if (density & 0xff00) {
234 density = (density & 0xe0) | ((density >> 8) & 0x1f);
235 type = DDR2;
236 } else if (!(density & 0x1f)) {
237 type = DDR2;
238 } else {
239 type = SDR;
240 }
241
242 if (ram_size) {
243 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
244 " of SDRAM", ram_size);
245 }
246
247 /* fill in SPD memory information */
248 spd[2] = type;
249 spd[5] = nbanks;
250 spd[31] = density;
251
252 /* checksum */
253 spd[63] = 0;
254 for (i = 0; i < 63; i++) {
255 spd[63] += spd[i];
256 }
257
258 /* copy for SMBUS */
259 memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
260 }
261
generate_eeprom_serial(uint8_t * eeprom)262 static void generate_eeprom_serial(uint8_t *eeprom)
263 {
264 int i, pos = 0;
265 uint8_t mac[6] = { 0x00 };
266 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
267
268 /* version */
269 eeprom[pos++] = 0x01;
270
271 /* count */
272 eeprom[pos++] = 0x02;
273
274 /* MAC address */
275 eeprom[pos++] = 0x01; /* MAC */
276 eeprom[pos++] = 0x06; /* length */
277 memcpy(&eeprom[pos], mac, sizeof(mac));
278 pos += sizeof(mac);
279
280 /* serial number */
281 eeprom[pos++] = 0x02; /* serial */
282 eeprom[pos++] = 0x05; /* length */
283 memcpy(&eeprom[pos], sn, sizeof(sn));
284 pos += sizeof(sn);
285
286 /* checksum */
287 eeprom[pos] = 0;
288 for (i = 0; i < pos; i++) {
289 eeprom[pos] += eeprom[i];
290 }
291 }
292
eeprom24c0x_read(eeprom24c0x_t * eeprom)293 static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
294 {
295 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
296 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
297 return eeprom->sda;
298 }
299
eeprom24c0x_write(eeprom24c0x_t * eeprom,int scl,int sda)300 static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
301 {
302 if (eeprom->scl && scl && (eeprom->sda != sda)) {
303 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
304 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
305 sda ? "stop" : "start");
306 if (!sda) {
307 eeprom->tick = 1;
308 eeprom->command = 0;
309 }
310 } else if (eeprom->tick == 0 && !eeprom->ack) {
311 /* Waiting for start. */
312 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
313 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
314 } else if (!eeprom->scl && scl) {
315 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
316 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
317 if (eeprom->ack) {
318 logout("\ti2c ack bit = 0\n");
319 sda = 0;
320 eeprom->ack = 0;
321 } else if (eeprom->sda == sda) {
322 uint8_t bit = (sda != 0);
323 logout("\ti2c bit = %d\n", bit);
324 if (eeprom->tick < 9) {
325 eeprom->command <<= 1;
326 eeprom->command += bit;
327 eeprom->tick++;
328 if (eeprom->tick == 9) {
329 logout("\tcommand 0x%04x, %s\n", eeprom->command,
330 bit ? "read" : "write");
331 eeprom->ack = 1;
332 }
333 } else if (eeprom->tick < 17) {
334 if (eeprom->command & 1) {
335 sda = ((eeprom->data & 0x80) != 0);
336 }
337 eeprom->address <<= 1;
338 eeprom->address += bit;
339 eeprom->tick++;
340 eeprom->data <<= 1;
341 if (eeprom->tick == 17) {
342 eeprom->data = eeprom->contents[eeprom->address];
343 logout("\taddress 0x%04x, data 0x%02x\n",
344 eeprom->address, eeprom->data);
345 eeprom->ack = 1;
346 eeprom->tick = 0;
347 }
348 } else if (eeprom->tick >= 17) {
349 sda = 0;
350 }
351 } else {
352 logout("\tsda changed with raising scl\n");
353 }
354 } else {
355 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
356 scl, eeprom->sda, sda);
357 }
358 eeprom->scl = scl;
359 eeprom->sda = sda;
360 }
361
malta_fpga_read(void * opaque,hwaddr addr,unsigned size)362 static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
363 unsigned size)
364 {
365 MaltaFPGAState *s = opaque;
366 uint32_t val = 0;
367 uint32_t saddr;
368
369 saddr = (addr & 0xfffff);
370
371 switch (saddr) {
372
373 /* SWITCH Register */
374 case 0x00200:
375 val = 0x00000000;
376 break;
377
378 /* STATUS Register */
379 case 0x00208:
380 val = TARGET_BIG_ENDIAN ? 0x00000012 : 0x00000010;
381 break;
382
383 /* JMPRS Register */
384 case 0x00210:
385 val = 0x00;
386 break;
387
388 /* LEDBAR Register */
389 case 0x00408:
390 val = s->leds;
391 break;
392
393 /* BRKRES Register */
394 case 0x00508:
395 val = s->brk;
396 break;
397
398 /* UART Registers are handled directly by the serial device */
399
400 /* GPOUT Register */
401 case 0x00a00:
402 val = s->gpout;
403 break;
404
405 /* XXX: implement a real I2C controller */
406
407 /* GPINP Register */
408 case 0x00a08:
409 /* IN = OUT until a real I2C control is implemented */
410 if (s->i2csel) {
411 val = s->i2cout;
412 } else {
413 val = 0x00;
414 }
415 break;
416
417 /* I2CINP Register */
418 case 0x00b00:
419 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
420 break;
421
422 /* I2COE Register */
423 case 0x00b08:
424 val = s->i2coe;
425 break;
426
427 /* I2COUT Register */
428 case 0x00b10:
429 val = s->i2cout;
430 break;
431
432 /* I2CSEL Register */
433 case 0x00b18:
434 val = s->i2csel;
435 break;
436
437 default:
438 qemu_log_mask(LOG_GUEST_ERROR,
439 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
440 addr);
441 break;
442 }
443 return val;
444 }
445
malta_fpga_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)446 static void malta_fpga_write(void *opaque, hwaddr addr,
447 uint64_t val, unsigned size)
448 {
449 MaltaFPGAState *s = opaque;
450 uint32_t saddr;
451
452 saddr = (addr & 0xfffff);
453
454 switch (saddr) {
455
456 /* SWITCH Register */
457 case 0x00200:
458 break;
459
460 /* JMPRS Register */
461 case 0x00210:
462 break;
463
464 /* LEDBAR Register */
465 case 0x00408:
466 s->leds = val & 0xff;
467 malta_fpga_update_display_leds(s);
468 break;
469
470 /* ASCIIWORD Register */
471 case 0x00410:
472 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
473 malta_fpga_update_display_ascii(s);
474 break;
475
476 /* ASCIIPOS0 to ASCIIPOS7 Registers */
477 case 0x00418:
478 case 0x00420:
479 case 0x00428:
480 case 0x00430:
481 case 0x00438:
482 case 0x00440:
483 case 0x00448:
484 case 0x00450:
485 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
486 malta_fpga_update_display_ascii(s);
487 break;
488
489 /* SOFTRES Register */
490 case 0x00500:
491 if (val == 0x42) {
492 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
493 }
494 break;
495
496 /* BRKRES Register */
497 case 0x00508:
498 s->brk = val & 0xff;
499 break;
500
501 /* UART Registers are handled directly by the serial device */
502
503 /* GPOUT Register */
504 case 0x00a00:
505 s->gpout = val & 0xff;
506 break;
507
508 /* I2COE Register */
509 case 0x00b08:
510 s->i2coe = val & 0x03;
511 break;
512
513 /* I2COUT Register */
514 case 0x00b10:
515 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
516 s->i2cout = val;
517 break;
518
519 /* I2CSEL Register */
520 case 0x00b18:
521 s->i2csel = val & 0x01;
522 break;
523
524 default:
525 qemu_log_mask(LOG_GUEST_ERROR,
526 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
527 addr);
528 break;
529 }
530 }
531
532 static const MemoryRegionOps malta_fpga_ops = {
533 .read = malta_fpga_read,
534 .write = malta_fpga_write,
535 .endianness = DEVICE_NATIVE_ENDIAN,
536 };
537
malta_fpga_reset(void * opaque)538 static void malta_fpga_reset(void *opaque)
539 {
540 MaltaFPGAState *s = opaque;
541
542 s->leds = 0x00;
543 s->brk = 0x0a;
544 s->gpout = 0x00;
545 s->i2cin = 0x3;
546 s->i2coe = 0x0;
547 s->i2cout = 0x3;
548 s->i2csel = 0x1;
549
550 s->display_text[8] = '\0';
551 snprintf(s->display_text, 9, " ");
552 }
553
malta_fgpa_display_event(void * opaque,QEMUChrEvent event)554 static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event)
555 {
556 MaltaFPGAState *s = opaque;
557
558 if (event == CHR_EVENT_OPENED && !s->display_inited) {
559 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
560 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
561 qemu_chr_fe_printf(&s->display, "+ +\r\n");
562 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
563 qemu_chr_fe_printf(&s->display, "\n");
564 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
565 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
566 qemu_chr_fe_printf(&s->display, "+ +\r\n");
567 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
568 s->display_inited = true;
569 }
570 }
571
malta_fpga_init(MemoryRegion * address_space,hwaddr base,qemu_irq uart_irq,Chardev * uart_chr)572 static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
573 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
574 {
575 MaltaFPGAState *s;
576 Chardev *chr;
577
578 s = g_new0(MaltaFPGAState, 1);
579
580 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
581 "malta-fpga", 0x100000);
582 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
583 &s->iomem, 0, 0x900);
584 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
585 &s->iomem, 0xa00, 0x100000 - 0xa00);
586
587 memory_region_add_subregion(address_space, base, &s->iomem_lo);
588 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
589
590 chr = qemu_chr_new("fpga", "vc:320x200", NULL);
591 qemu_chr_fe_init(&s->display, chr, NULL);
592 qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
593 malta_fgpa_display_event, NULL, s, NULL, true);
594
595 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
596 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
597
598 malta_fpga_reset(s);
599 qemu_register_reset(malta_fpga_reset, s);
600
601 return s;
602 }
603
604 /* Network support */
network_init(PCIBus * pci_bus)605 static void network_init(PCIBus *pci_bus)
606 {
607 /* The malta board has a PCNet card using PCI SLOT 11 */
608 pci_init_nic_in_slot(pci_bus, "pcnet", NULL, "0b");
609 pci_init_nic_devices(pci_bus, "pcnet");
610 }
611
bl_setup_gt64120_jump_kernel(void ** p,uint64_t run_addr,uint64_t kernel_entry)612 static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
613 uint64_t kernel_entry)
614 {
615 static const char pci_pins_cfg[PCI_NUM_PINS] = {
616 10, 10, 11, 11 /* PIIX IRQRC[A:D] */
617 };
618
619 /* Bus endianness is always reversed */
620 #if TARGET_BIG_ENDIAN
621 #define cpu_to_gt32(x) (x)
622 #else
623 #define cpu_to_gt32(x) bswap32(x)
624 #endif
625
626 /* setup MEM-to-PCI0 mapping as done by YAMON */
627
628 /* move GT64120 registers from 0x14000000 to 0x1be00000 */
629 bl_gen_write_u32(p, /* GT_ISD */
630 cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
631 cpu_to_gt32(0x1be00000 << 3));
632
633 /* setup PCI0 io window to 0x18000000-0x181fffff */
634 bl_gen_write_u32(p, /* GT_PCI0IOLD */
635 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
636 cpu_to_gt32(0x18000000 << 3));
637 bl_gen_write_u32(p, /* GT_PCI0IOHD */
638 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
639 cpu_to_gt32(0x08000000 << 3));
640
641 /* setup PCI0 mem windows */
642 bl_gen_write_u32(p, /* GT_PCI0M0LD */
643 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
644 cpu_to_gt32(0x10000000 << 3));
645 bl_gen_write_u32(p, /* GT_PCI0M0HD */
646 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
647 cpu_to_gt32(0x07e00000 << 3));
648 bl_gen_write_u32(p, /* GT_PCI0M1LD */
649 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
650 cpu_to_gt32(0x18200000 << 3));
651 bl_gen_write_u32(p, /* GT_PCI0M1HD */
652 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
653 cpu_to_gt32(0x0bc00000 << 3));
654
655 #undef cpu_to_gt32
656
657 /*
658 * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
659 * Load the PIIX IRQC[A:D] routing config address, then
660 * write routing configuration to the config data register.
661 */
662 bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */
663 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
664 tswap32((1 << 31) /* ConfigEn */
665 | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
666 | PIIX_PIRQCA));
667 bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */
668 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
669 tswap32(ldl_be_p(pci_pins_cfg)));
670
671 bl_gen_jump_kernel(p,
672 true, ENVP_VADDR - 64,
673 /*
674 * If semihosting is used, arguments have already
675 * been passed, so we preserve $a0.
676 */
677 !semihosting_get_argc(), 2,
678 true, ENVP_VADDR,
679 true, ENVP_VADDR + 8,
680 true, loaderparams.ram_low_size,
681 kernel_entry);
682 }
683
write_bootloader_nanomips(uint8_t * base,uint64_t run_addr,uint64_t kernel_entry)684 static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
685 uint64_t kernel_entry)
686 {
687 uint16_t *p;
688
689 /* Small bootloader */
690 p = (uint16_t *)base;
691
692 stw_p(p++, 0x2800); stw_p(p++, 0x001c);
693 /* bc to_here */
694 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
695 /* nop */
696 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
697 /* nop */
698 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
699 /* nop */
700 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
701 /* nop */
702 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
703 /* nop */
704 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
705 /* nop */
706 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
707 /* nop */
708
709 /* to_here: */
710
711 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
712 }
713
714 /*
715 * ROM and pseudo bootloader
716 *
717 * The following code implements a very very simple bootloader. It first
718 * loads the registers a0 to a3 to the values expected by the OS, and
719 * then jump at the kernel address.
720 *
721 * The bootloader should pass the locations of the kernel arguments and
722 * environment variables tables. Those tables contain the 32-bit address
723 * of NULL terminated strings. The environment variables table should be
724 * terminated by a NULL address.
725 *
726 * For a simpler implementation, the number of kernel arguments is fixed
727 * to two (the name of the kernel and the command line), and the two
728 * tables are actually the same one.
729 *
730 * The registers a0 to a3 should contain the following values:
731 * a0 - number of kernel arguments
732 * a1 - 32-bit address of the kernel arguments table
733 * a2 - 32-bit address of the environment variables table
734 * a3 - RAM size in bytes
735 */
write_bootloader(uint8_t * base,uint64_t run_addr,uint64_t kernel_entry)736 static void write_bootloader(uint8_t *base, uint64_t run_addr,
737 uint64_t kernel_entry)
738 {
739 uint32_t *p;
740
741 /* Small bootloader */
742 p = (uint32_t *)base;
743
744 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */
745 ((run_addr + 0x580) & 0x0fffffff) >> 2);
746 stl_p(p++, 0x00000000); /* nop */
747
748 /* YAMON service vector */
749 stl_p(base + 0x500, run_addr + 0x0580); /* start: */
750 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */
751 stl_p(base + 0x520, run_addr + 0x0580); /* start: */
752 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */
753 stl_p(base + 0x534, run_addr + 0x0808); /* print: */
754 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */
755 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */
756 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */
757 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */
758 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */
759 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */
760 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */
761 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */
762
763
764 /* Second part of the bootloader */
765 p = (uint32_t *) (base + 0x580);
766
767 /*
768 * Load BAR registers as done by YAMON:
769 *
770 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
771 * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
772 * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
773 *
774 */
775
776 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
777
778 /* YAMON subroutines */
779 p = (uint32_t *) (base + 0x800);
780 stl_p(p++, 0x03e00009); /* jalr ra */
781 stl_p(p++, 0x24020000); /* li v0,0 */
782 /* 808 YAMON print */
783 stl_p(p++, 0x03e06821); /* move t5,ra */
784 stl_p(p++, 0x00805821); /* move t3,a0 */
785 stl_p(p++, 0x00a05021); /* move t2,a1 */
786 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
787 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
788 stl_p(p++, 0x10800005); /* beqz a0,834 */
789 stl_p(p++, 0x00000000); /* nop */
790 stl_p(p++, 0x0ff0021c); /* jal 870 */
791 stl_p(p++, 0x00000000); /* nop */
792 stl_p(p++, 0x1000fff9); /* b 814 */
793 stl_p(p++, 0x00000000); /* nop */
794 stl_p(p++, 0x01a00009); /* jalr t5 */
795 stl_p(p++, 0x01602021); /* move a0,t3 */
796 /* 0x83c YAMON print_count */
797 stl_p(p++, 0x03e06821); /* move t5,ra */
798 stl_p(p++, 0x00805821); /* move t3,a0 */
799 stl_p(p++, 0x00a05021); /* move t2,a1 */
800 stl_p(p++, 0x00c06021); /* move t4,a2 */
801 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
802 stl_p(p++, 0x0ff0021c); /* jal 870 */
803 stl_p(p++, 0x00000000); /* nop */
804 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
805 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */
806 stl_p(p++, 0x1580fffa); /* bnez t4,84c */
807 stl_p(p++, 0x00000000); /* nop */
808 stl_p(p++, 0x01a00009); /* jalr t5 */
809 stl_p(p++, 0x01602021); /* move a0,t3 */
810 /* 0x870 */
811 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */
812 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
813 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */
814 stl_p(p++, 0x00000000); /* nop */
815 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */
816 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
817 stl_p(p++, 0x00000000); /* nop */
818 stl_p(p++, 0x03e00009); /* jalr ra */
819 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
820 }
821
prom_set(uint32_t * prom_buf,int index,const char * string,...)822 static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
823 const char *string, ...)
824 {
825 va_list ap;
826 uint32_t table_addr;
827
828 if (index >= ENVP_NB_ENTRIES) {
829 return;
830 }
831
832 if (string == NULL) {
833 prom_buf[index] = 0;
834 return;
835 }
836
837 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
838 prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
839
840 va_start(ap, string);
841 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
842 va_end(ap);
843 }
844
rng_seed_hex_new(void)845 static GString *rng_seed_hex_new(void)
846 {
847 uint8_t rng_seed[32];
848
849 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
850 return qemu_hexdump_line(NULL, rng_seed, sizeof(rng_seed), 0, 0);
851 }
852
reinitialize_rng_seed(void * opaque)853 static void reinitialize_rng_seed(void *opaque)
854 {
855 g_autoptr(GString) hex = rng_seed_hex_new();
856 memcpy(opaque, hex->str, hex->len);
857 }
858
859 /* Kernel */
load_kernel(void)860 static uint64_t load_kernel(void)
861 {
862 uint64_t kernel_entry, kernel_high, initrd_size;
863 long kernel_size;
864 ram_addr_t initrd_offset;
865 uint32_t *prom_buf;
866 long prom_size;
867 int prom_index = 0;
868 size_t rng_seed_prom_offset;
869
870 kernel_size = load_elf(loaderparams.kernel_filename, NULL,
871 cpu_mips_kseg0_to_phys, NULL,
872 &kernel_entry, NULL,
873 &kernel_high, NULL,
874 TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB,
875 EM_MIPS, 1, 0);
876 if (kernel_size < 0) {
877 error_report("could not load kernel '%s': %s",
878 loaderparams.kernel_filename,
879 load_elf_strerror(kernel_size));
880 exit(1);
881 }
882
883 /* Check where the kernel has been linked */
884 if (kernel_entry <= USEG_LIMIT) {
885 error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)"
886 " are not supported");
887 exit(1);
888 }
889
890 /* load initrd */
891 initrd_size = 0;
892 initrd_offset = 0;
893 if (loaderparams.initrd_filename) {
894 initrd_size = get_image_size(loaderparams.initrd_filename);
895 if (initrd_size > 0) {
896 /*
897 * The kernel allocates the bootmap memory in the low memory after
898 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
899 * pages.
900 */
901 initrd_offset = ROUND_UP(loaderparams.ram_low_size
902 - (initrd_size + 128 * KiB),
903 INITRD_PAGE_SIZE);
904 if (kernel_high >= initrd_offset) {
905 error_report("memory too small for initial ram disk '%s'",
906 loaderparams.initrd_filename);
907 exit(1);
908 }
909 initrd_size = load_image_targphys(loaderparams.initrd_filename,
910 initrd_offset,
911 loaderparams.ram_size - initrd_offset);
912 }
913 if (initrd_size == (target_ulong) -1) {
914 error_report("could not load initial ram disk '%s'",
915 loaderparams.initrd_filename);
916 exit(1);
917 }
918 }
919
920 /* Setup prom parameters. */
921 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
922 prom_buf = g_malloc(prom_size);
923
924 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
925 if (initrd_size > 0) {
926 prom_set(prom_buf, prom_index++,
927 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
928 cpu_mips_phys_to_kseg0(NULL, initrd_offset),
929 initrd_size, loaderparams.kernel_cmdline);
930 } else {
931 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
932 }
933
934 prom_set(prom_buf, prom_index++, "memsize");
935 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
936
937 prom_set(prom_buf, prom_index++, "ememsize");
938 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
939
940 prom_set(prom_buf, prom_index++, "modetty0");
941 prom_set(prom_buf, prom_index++, "38400n8r");
942
943 prom_set(prom_buf, prom_index++, "rngseed");
944 rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE +
945 sizeof(uint32_t) * ENVP_NB_ENTRIES;
946 {
947 g_autoptr(GString) hex = rng_seed_hex_new();
948 prom_set(prom_buf, prom_index++, "%s", hex->str);
949 }
950
951 prom_set(prom_buf, prom_index++, NULL);
952
953 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
954 qemu_register_reset_nosnapshotload(reinitialize_rng_seed,
955 rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset);
956
957 g_free(prom_buf);
958 return kernel_entry;
959 }
960
malta_mips_config(MIPSCPU * cpu)961 static void malta_mips_config(MIPSCPU *cpu)
962 {
963 MachineState *ms = MACHINE(qdev_get_machine());
964 unsigned int smp_cpus = ms->smp.cpus;
965 CPUMIPSState *env = &cpu->env;
966 CPUState *cs = CPU(cpu);
967
968 if (ase_mt_available(env)) {
969 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
970 CP0MVPC0_PTC, 8,
971 smp_cpus * cs->nr_threads - 1);
972 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
973 CP0MVPC0_PVPE, 4, smp_cpus - 1);
974 }
975 }
976
malta_pci_slot_get_pirq(PCIDevice * pci_dev,int irq_num)977 static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
978 {
979 int slot;
980
981 slot = PCI_SLOT(pci_dev->devfn);
982
983 switch (slot) {
984 /* PIIX4 USB */
985 case 10:
986 return 3;
987 /* AMD 79C973 Ethernet */
988 case 11:
989 return 1;
990 /* Crystal 4281 Sound */
991 case 12:
992 return 2;
993 /* PCI slot 1 to 4 */
994 case 18 ... 21:
995 return ((slot - 18) + irq_num) & 0x03;
996 /* Unknown device, don't do any translation */
997 default:
998 return irq_num;
999 }
1000 }
1001
main_cpu_reset(void * opaque)1002 static void main_cpu_reset(void *opaque)
1003 {
1004 MIPSCPU *cpu = opaque;
1005 CPUMIPSState *env = &cpu->env;
1006
1007 cpu_reset(CPU(cpu));
1008
1009 /*
1010 * The bootloader does not need to be rewritten as it is located in a
1011 * read only location. The kernel location and the arguments table
1012 * location does not change.
1013 */
1014 if (loaderparams.kernel_filename) {
1015 env->CP0_Status &= ~(1 << CP0St_ERL);
1016 }
1017
1018 malta_mips_config(cpu);
1019 }
1020
create_cpu_without_cps(MachineState * ms,MaltaState * s,qemu_irq * cbus_irq,qemu_irq * i8259_irq)1021 static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
1022 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1023 {
1024 CPUMIPSState *env;
1025 MIPSCPU *cpu;
1026 int i;
1027
1028 for (i = 0; i < ms->smp.cpus; i++) {
1029 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
1030 TARGET_BIG_ENDIAN);
1031
1032 /* Init internal devices */
1033 cpu_mips_irq_init_cpu(cpu);
1034 cpu_mips_clock_init(cpu);
1035 qemu_register_reset(main_cpu_reset, cpu);
1036 }
1037
1038 cpu = MIPS_CPU(first_cpu);
1039 env = &cpu->env;
1040 *i8259_irq = env->irq[2];
1041 *cbus_irq = env->irq[4];
1042 }
1043
create_cps(MachineState * ms,MaltaState * s,qemu_irq * cbus_irq,qemu_irq * i8259_irq)1044 static void create_cps(MachineState *ms, MaltaState *s,
1045 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1046 {
1047 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
1048 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
1049 &error_fatal);
1050 object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian",
1051 TARGET_BIG_ENDIAN, &error_abort);
1052 object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
1053 &error_fatal);
1054 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
1055 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
1056
1057 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
1058
1059 *i8259_irq = get_cps_irq(&s->cps, 3);
1060 *cbus_irq = NULL;
1061 }
1062
mips_create_cpu(MachineState * ms,MaltaState * s,qemu_irq * cbus_irq,qemu_irq * i8259_irq)1063 static void mips_create_cpu(MachineState *ms, MaltaState *s,
1064 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1065 {
1066 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
1067 create_cps(ms, s, cbus_irq, i8259_irq);
1068 } else {
1069 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
1070 }
1071 }
1072
1073 static
mips_malta_init(MachineState * machine)1074 void mips_malta_init(MachineState *machine)
1075 {
1076 ram_addr_t ram_size = machine->ram_size;
1077 ram_addr_t ram_low_size;
1078 const char *kernel_filename = machine->kernel_filename;
1079 const char *kernel_cmdline = machine->kernel_cmdline;
1080 const char *initrd_filename = machine->initrd_filename;
1081 char *filename;
1082 PFlashCFI01 *fl;
1083 MemoryRegion *system_memory = get_system_memory();
1084 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
1085 MemoryRegion *ram_low_postio;
1086 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
1087 const size_t smbus_eeprom_size = 8 * 256;
1088 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
1089 uint64_t kernel_entry, bootloader_run_addr;
1090 PCIBus *pci_bus;
1091 ISABus *isa_bus;
1092 qemu_irq cbus_irq, i8259_irq;
1093 I2CBus *smbus;
1094 DriveInfo *dinfo;
1095 int fl_idx = 0;
1096 MaltaState *s;
1097 PCIDevice *piix4;
1098 DeviceState *dev;
1099
1100 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
1101 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
1102
1103 /* create CPU */
1104 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
1105
1106 /* allocate RAM */
1107 if (ram_size > 2 * GiB) {
1108 error_report("Too much memory for this machine: %" PRId64 "MB,"
1109 " maximum 2048MB", ram_size / MiB);
1110 exit(1);
1111 }
1112
1113 /* register RAM at high address where it is undisturbed by IO */
1114 memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
1115
1116 /* alias for pre IO hole access */
1117 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1118 machine->ram, 0, MIN(ram_size, 256 * MiB));
1119 memory_region_add_subregion(system_memory, 0, ram_low_preio);
1120
1121 /* alias for post IO hole access, if there is enough RAM */
1122 if (ram_size > 512 * MiB) {
1123 ram_low_postio = g_new(MemoryRegion, 1);
1124 memory_region_init_alias(ram_low_postio, NULL,
1125 "mips_malta_low_postio.ram",
1126 machine->ram, 512 * MiB,
1127 ram_size - 512 * MiB);
1128 memory_region_add_subregion(system_memory, 512 * MiB,
1129 ram_low_postio);
1130 }
1131
1132 /* FPGA */
1133
1134 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
1135 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
1136
1137 /* Load firmware in flash / BIOS. */
1138 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1139 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
1140 FLASH_SIZE,
1141 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1142 65536,
1143 4, 0x0000, 0x0000, 0x0000, 0x0000,
1144 TARGET_BIG_ENDIAN);
1145 bios = pflash_cfi01_get_memory(fl);
1146 fl_idx++;
1147 if (kernel_filename) {
1148 ram_low_size = MIN(ram_size, 256 * MiB);
1149 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
1150
1151 /* Write a small bootloader to the flash location. */
1152 loaderparams.ram_size = ram_size;
1153 loaderparams.ram_low_size = ram_low_size;
1154 loaderparams.kernel_filename = kernel_filename;
1155 loaderparams.kernel_cmdline = kernel_cmdline;
1156 loaderparams.initrd_filename = initrd_filename;
1157 kernel_entry = load_kernel();
1158
1159 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
1160 write_bootloader(memory_region_get_ram_ptr(bios),
1161 bootloader_run_addr, kernel_entry);
1162 } else {
1163 write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
1164 bootloader_run_addr, kernel_entry);
1165 }
1166 } else {
1167 target_long bios_size = FLASH_SIZE;
1168 /* Load firmware from flash. */
1169 if (!dinfo) {
1170 const char *bios_name = TARGET_BIG_ENDIAN ? "mips_bios.bin"
1171 : "mipsel_bios.bin";
1172
1173 /* Load a BIOS image. */
1174 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
1175 machine->firmware ?: bios_name);
1176 if (filename) {
1177 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1178 BIOS_SIZE);
1179 g_free(filename);
1180 } else {
1181 bios_size = -1;
1182 }
1183 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1184 machine->firmware && !qtest_enabled()) {
1185 error_report("Could not load MIPS bios '%s'", machine->firmware);
1186 exit(1);
1187 }
1188 }
1189 /*
1190 * In little endian mode the 32bit words in the bios are swapped,
1191 * a neat trick which allows bi-endian firmware.
1192 */
1193 if (!TARGET_BIG_ENDIAN) {
1194 uint32_t *end, *addr;
1195 const size_t swapsize = MIN(bios_size, 0x3e0000);
1196 addr = rom_ptr(FLASH_ADDRESS, swapsize);
1197 if (!addr) {
1198 addr = memory_region_get_ram_ptr(bios);
1199 }
1200 end = (void *)addr + swapsize;
1201 while (addr < end) {
1202 bswap32s(addr);
1203 addr++;
1204 }
1205 }
1206 }
1207
1208 /*
1209 * Map the BIOS at a 2nd physical location, as on the real board.
1210 * Copy it so that we can patch in the MIPS revision, which cannot be
1211 * handled by an overlapping region as the resulting ROM code subpage
1212 * regions are not executable.
1213 */
1214 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1215 &error_fatal);
1216 if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1217 FLASH_ADDRESS, BIOS_SIZE)) {
1218 memcpy(memory_region_get_ram_ptr(bios_copy),
1219 memory_region_get_ram_ptr(bios), BIOS_SIZE);
1220 }
1221 memory_region_set_readonly(bios_copy, true);
1222 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1223
1224 /* Board ID = 0x420 (Malta Board with CoreLV) */
1225 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1226
1227 /* Northbridge */
1228 dev = qdev_new("gt64120");
1229 qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN);
1230 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1231 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
1232 pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);
1233
1234 /* Southbridge */
1235 piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE);
1236 qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
1237 pci_realize_and_unref(piix4, pci_bus, &error_fatal);
1238 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
1239
1240 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
1241 pci_ide_create_devs(PCI_DEVICE(dev));
1242
1243 /* Interrupt controller */
1244 qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq);
1245
1246 /* generate SPD EEPROM data */
1247 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm"));
1248 smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
1249 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1250 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1251 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1252 g_free(smbus_eeprom_buf);
1253
1254 /* Super I/O: SMS FDC37M817 */
1255 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
1256
1257 /* Network card */
1258 network_init(pci_bus);
1259
1260 /* Optional PCI video card */
1261 pci_vga_init(pci_bus);
1262 }
1263
mips_malta_instance_init(Object * obj)1264 static void mips_malta_instance_init(Object *obj)
1265 {
1266 MaltaState *s = MIPS_MALTA(obj);
1267
1268 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
1269 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */
1270 }
1271
1272 static const TypeInfo mips_malta_device = {
1273 .name = TYPE_MIPS_MALTA,
1274 .parent = TYPE_SYS_BUS_DEVICE,
1275 .instance_size = sizeof(MaltaState),
1276 .instance_init = mips_malta_instance_init,
1277 };
1278
1279 GlobalProperty malta_compat[] = {
1280 { "PIIX4_PM", "memory-hotplug-support", "off" },
1281 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
1282 { "PIIX4_PM", "acpi-root-pci-hotplug", "off" },
1283 { "PIIX4_PM", "x-not-migrate-acpi-index", "true" },
1284 };
1285 const size_t malta_compat_len = G_N_ELEMENTS(malta_compat);
1286
mips_malta_machine_init(MachineClass * mc)1287 static void mips_malta_machine_init(MachineClass *mc)
1288 {
1289 mc->desc = "MIPS Malta Core LV";
1290 mc->init = mips_malta_init;
1291 mc->block_default_type = IF_IDE;
1292 mc->max_cpus = 16;
1293 mc->is_default = true;
1294 #ifdef TARGET_MIPS64
1295 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
1296 #else
1297 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
1298 #endif
1299 mc->default_ram_id = "mips_malta.ram";
1300 compat_props_add(mc->compat_props, malta_compat, malta_compat_len);
1301 }
1302
1303 DEFINE_MACHINE("malta", mips_malta_machine_init)
1304
mips_malta_register_types(void)1305 static void mips_malta_register_types(void)
1306 {
1307 type_register_static(&mips_malta_device);
1308 }
1309
1310 type_init(mips_malta_register_types)
1311