1 /*
2 * QEMU I2C bus interface.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the LGPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "hw/i2c/i2c.h"
12 #include "hw/qdev-properties.h"
13 #include "migration/vmstate.h"
14 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "qemu/main-loop.h"
17 #include "trace.h"
18
19 #define I2C_BROADCAST 0x00
20
21 static const Property i2c_props[] = {
22 DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
23 };
24
25 static const TypeInfo i2c_bus_info = {
26 .name = TYPE_I2C_BUS,
27 .parent = TYPE_BUS,
28 .instance_size = sizeof(I2CBus),
29 };
30
i2c_bus_pre_save(void * opaque)31 static int i2c_bus_pre_save(void *opaque)
32 {
33 I2CBus *bus = opaque;
34
35 bus->saved_address = -1;
36 if (!QLIST_EMPTY(&bus->current_devs)) {
37 if (!bus->broadcast) {
38 bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address;
39 } else {
40 bus->saved_address = I2C_BROADCAST;
41 }
42 }
43
44 return 0;
45 }
46
47 static const VMStateDescription vmstate_i2c_bus = {
48 .name = "i2c_bus",
49 .version_id = 1,
50 .minimum_version_id = 1,
51 .pre_save = i2c_bus_pre_save,
52 .fields = (const VMStateField[]) {
53 VMSTATE_UINT8(saved_address, I2CBus),
54 VMSTATE_END_OF_LIST()
55 }
56 };
57
58 /* Create a new I2C bus. */
i2c_init_bus(DeviceState * parent,const char * name)59 I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
60 {
61 I2CBus *bus;
62
63 bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
64 QLIST_INIT(&bus->current_devs);
65 QSIMPLEQ_INIT(&bus->pending_masters);
66 vmstate_register_any(NULL, &vmstate_i2c_bus, bus);
67 return bus;
68 }
69
i2c_slave_set_address(I2CSlave * dev,uint8_t address)70 void i2c_slave_set_address(I2CSlave *dev, uint8_t address)
71 {
72 dev->address = address;
73 }
74
75 /* Return nonzero if bus is busy. */
i2c_bus_busy(I2CBus * bus)76 int i2c_bus_busy(I2CBus *bus)
77 {
78 return !QLIST_EMPTY(&bus->current_devs) || bus->bh;
79 }
80
i2c_scan_bus(I2CBus * bus,uint8_t address,bool broadcast,I2CNodeList * current_devs)81 bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
82 I2CNodeList *current_devs)
83 {
84 BusChild *kid;
85
86 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
87 DeviceState *qdev = kid->child;
88 I2CSlave *candidate = I2C_SLAVE(qdev);
89 I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(candidate);
90
91 if (sc->match_and_add(candidate, address, broadcast, current_devs)) {
92 if (!broadcast) {
93 return true;
94 }
95 }
96 }
97
98 /*
99 * If broadcast was true, and the list was full or empty, return true. If
100 * broadcast was false, return false.
101 */
102 return broadcast;
103 }
104
105 /* TODO: Make this handle multiple masters. */
106 /*
107 * Start or continue an i2c transaction. When this is called for the
108 * first time or after an i2c_end_transfer(), if it returns an error
109 * the bus transaction is terminated (or really never started). If
110 * this is called after another i2c_start_transfer() without an
111 * intervening i2c_end_transfer(), and it returns an error, the
112 * transaction will not be terminated. The caller must do it.
113 *
114 * This corresponds with the way real hardware works. The SMBus
115 * protocol uses a start transfer to switch from write to read mode
116 * without releasing the bus. If that fails, the bus is still
117 * in a transaction.
118 *
119 * @event must be I2C_START_RECV or I2C_START_SEND.
120 */
i2c_do_start_transfer(I2CBus * bus,uint8_t address,enum i2c_event event)121 static int i2c_do_start_transfer(I2CBus *bus, uint8_t address,
122 enum i2c_event event)
123 {
124 I2CSlaveClass *sc;
125 I2CNode *node;
126 bool bus_scanned = false;
127
128 if (address == I2C_BROADCAST) {
129 /*
130 * This is a broadcast, the current_devs will be all the devices of the
131 * bus.
132 */
133 bus->broadcast = true;
134 }
135
136 /*
137 * If there are already devices in the list, that means we are in
138 * the middle of a transaction and we shouldn't rescan the bus.
139 *
140 * This happens with any SMBus transaction, even on a pure I2C
141 * device. The interface does a transaction start without
142 * terminating the previous transaction.
143 */
144 if (QLIST_EMPTY(&bus->current_devs)) {
145 /* Disregard whether devices were found. */
146 (void)i2c_scan_bus(bus, address, bus->broadcast, &bus->current_devs);
147 bus_scanned = true;
148 }
149
150 if (QLIST_EMPTY(&bus->current_devs)) {
151 return 1;
152 }
153
154 QLIST_FOREACH(node, &bus->current_devs, next) {
155 I2CSlave *s = node->elt;
156 int rv;
157
158 sc = I2C_SLAVE_GET_CLASS(s);
159 /* If the bus is already busy, assume this is a repeated
160 start condition. */
161
162 if (sc->event) {
163 trace_i2c_event(event == I2C_START_SEND ? "start" : "start_async",
164 s->address);
165 rv = sc->event(s, event);
166 if (rv && !bus->broadcast) {
167 if (bus_scanned) {
168 /* First call, terminate the transfer. */
169 i2c_end_transfer(bus);
170 }
171 return rv;
172 }
173 }
174 }
175 return 0;
176 }
177
i2c_start_transfer(I2CBus * bus,uint8_t address,bool is_recv)178 int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv)
179 {
180 return i2c_do_start_transfer(bus, address, is_recv
181 ? I2C_START_RECV
182 : I2C_START_SEND);
183 }
184
i2c_bus_master(I2CBus * bus,QEMUBH * bh)185 void i2c_bus_master(I2CBus *bus, QEMUBH *bh)
186 {
187 I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
188 node->bh = bh;
189
190 QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
191 }
192
i2c_schedule_pending_master(I2CBus * bus)193 void i2c_schedule_pending_master(I2CBus *bus)
194 {
195 I2CPendingMaster *node;
196
197 if (i2c_bus_busy(bus)) {
198 /* someone is already controlling the bus; wait for it to release it */
199 return;
200 }
201
202 if (QSIMPLEQ_EMPTY(&bus->pending_masters)) {
203 return;
204 }
205
206 node = QSIMPLEQ_FIRST(&bus->pending_masters);
207 bus->bh = node->bh;
208
209 QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
210 g_free(node);
211
212 qemu_bh_schedule(bus->bh);
213 }
214
i2c_bus_release(I2CBus * bus)215 void i2c_bus_release(I2CBus *bus)
216 {
217 bus->bh = NULL;
218
219 i2c_schedule_pending_master(bus);
220 }
221
i2c_start_recv(I2CBus * bus,uint8_t address)222 int i2c_start_recv(I2CBus *bus, uint8_t address)
223 {
224 return i2c_do_start_transfer(bus, address, I2C_START_RECV);
225 }
226
i2c_start_send(I2CBus * bus,uint8_t address)227 int i2c_start_send(I2CBus *bus, uint8_t address)
228 {
229 return i2c_do_start_transfer(bus, address, I2C_START_SEND);
230 }
231
i2c_start_send_async(I2CBus * bus,uint8_t address)232 int i2c_start_send_async(I2CBus *bus, uint8_t address)
233 {
234 return i2c_do_start_transfer(bus, address, I2C_START_SEND_ASYNC);
235 }
236
i2c_end_transfer(I2CBus * bus)237 void i2c_end_transfer(I2CBus *bus)
238 {
239 I2CSlaveClass *sc;
240 I2CNode *node, *next;
241
242 QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
243 I2CSlave *s = node->elt;
244 sc = I2C_SLAVE_GET_CLASS(s);
245 if (sc->event) {
246 trace_i2c_event("finish", s->address);
247 sc->event(s, I2C_FINISH);
248 }
249 QLIST_REMOVE(node, next);
250 g_free(node);
251 }
252 bus->broadcast = false;
253 }
254
i2c_send(I2CBus * bus,uint8_t data)255 int i2c_send(I2CBus *bus, uint8_t data)
256 {
257 I2CSlaveClass *sc;
258 I2CSlave *s;
259 I2CNode *node;
260 int ret = 0;
261
262 QLIST_FOREACH(node, &bus->current_devs, next) {
263 s = node->elt;
264 sc = I2C_SLAVE_GET_CLASS(s);
265 if (sc->send) {
266 trace_i2c_send(s->address, data);
267 ret = ret || sc->send(s, data);
268 } else {
269 ret = -1;
270 }
271 }
272
273 return ret ? -1 : 0;
274 }
275
i2c_send_async(I2CBus * bus,uint8_t data)276 int i2c_send_async(I2CBus *bus, uint8_t data)
277 {
278 I2CNode *node = QLIST_FIRST(&bus->current_devs);
279 I2CSlave *slave = node->elt;
280 I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(slave);
281
282 if (!sc->send_async) {
283 return -1;
284 }
285
286 trace_i2c_send_async(slave->address, data);
287
288 sc->send_async(slave, data);
289
290 return 0;
291 }
292
i2c_recv(I2CBus * bus)293 uint8_t i2c_recv(I2CBus *bus)
294 {
295 uint8_t data = 0xff;
296 I2CSlaveClass *sc;
297 I2CSlave *s;
298
299 if (!QLIST_EMPTY(&bus->current_devs) && !bus->broadcast) {
300 sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
301 if (sc->recv) {
302 s = QLIST_FIRST(&bus->current_devs)->elt;
303 data = sc->recv(s);
304 trace_i2c_recv(s->address, data);
305 }
306 }
307
308 return data;
309 }
310
i2c_nack(I2CBus * bus)311 void i2c_nack(I2CBus *bus)
312 {
313 I2CSlaveClass *sc;
314 I2CNode *node;
315
316 if (QLIST_EMPTY(&bus->current_devs)) {
317 return;
318 }
319
320 QLIST_FOREACH(node, &bus->current_devs, next) {
321 sc = I2C_SLAVE_GET_CLASS(node->elt);
322 if (sc->event) {
323 trace_i2c_event("nack", node->elt->address);
324 sc->event(node->elt, I2C_NACK);
325 }
326 }
327 }
328
i2c_ack(I2CBus * bus)329 void i2c_ack(I2CBus *bus)
330 {
331 if (!bus->bh) {
332 return;
333 }
334
335 trace_i2c_ack();
336
337 qemu_bh_schedule(bus->bh);
338 }
339
i2c_slave_post_load(void * opaque,int version_id)340 static int i2c_slave_post_load(void *opaque, int version_id)
341 {
342 I2CSlave *dev = opaque;
343 I2CBus *bus;
344 I2CNode *node;
345
346 bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
347 if ((bus->saved_address == dev->address) ||
348 (bus->saved_address == I2C_BROADCAST)) {
349 node = g_new(struct I2CNode, 1);
350 node->elt = dev;
351 QLIST_INSERT_HEAD(&bus->current_devs, node, next);
352 }
353 return 0;
354 }
355
356 const VMStateDescription vmstate_i2c_slave = {
357 .name = "I2CSlave",
358 .version_id = 1,
359 .minimum_version_id = 1,
360 .post_load = i2c_slave_post_load,
361 .fields = (const VMStateField[]) {
362 VMSTATE_UINT8(address, I2CSlave),
363 VMSTATE_END_OF_LIST()
364 }
365 };
366
i2c_slave_new(const char * name,uint8_t addr)367 I2CSlave *i2c_slave_new(const char *name, uint8_t addr)
368 {
369 DeviceState *dev;
370
371 dev = qdev_new(name);
372 qdev_prop_set_uint8(dev, "address", addr);
373 return I2C_SLAVE(dev);
374 }
375
i2c_slave_realize_and_unref(I2CSlave * dev,I2CBus * bus,Error ** errp)376 bool i2c_slave_realize_and_unref(I2CSlave *dev, I2CBus *bus, Error **errp)
377 {
378 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
379 }
380
i2c_slave_create_simple(I2CBus * bus,const char * name,uint8_t addr)381 I2CSlave *i2c_slave_create_simple(I2CBus *bus, const char *name, uint8_t addr)
382 {
383 I2CSlave *dev = i2c_slave_new(name, addr);
384
385 i2c_slave_realize_and_unref(dev, bus, &error_abort);
386
387 return dev;
388 }
389
i2c_slave_match(I2CSlave * candidate,uint8_t address,bool broadcast,I2CNodeList * current_devs)390 static bool i2c_slave_match(I2CSlave *candidate, uint8_t address,
391 bool broadcast, I2CNodeList *current_devs)
392 {
393 if ((candidate->address == address) || (broadcast)) {
394 I2CNode *node = g_new(struct I2CNode, 1);
395 node->elt = candidate;
396 QLIST_INSERT_HEAD(current_devs, node, next);
397 return true;
398 }
399
400 /* Not found and not broadcast. */
401 return false;
402 }
403
i2c_slave_class_init(ObjectClass * klass,const void * data)404 static void i2c_slave_class_init(ObjectClass *klass, const void *data)
405 {
406 DeviceClass *k = DEVICE_CLASS(klass);
407 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
408 set_bit(DEVICE_CATEGORY_MISC, k->categories);
409 k->bus_type = TYPE_I2C_BUS;
410 device_class_set_props(k, i2c_props);
411 sc->match_and_add = i2c_slave_match;
412 }
413
414 static const TypeInfo i2c_slave_type_info = {
415 .name = TYPE_I2C_SLAVE,
416 .parent = TYPE_DEVICE,
417 .instance_size = sizeof(I2CSlave),
418 .abstract = true,
419 .class_size = sizeof(I2CSlaveClass),
420 .class_init = i2c_slave_class_init,
421 };
422
i2c_slave_register_types(void)423 static void i2c_slave_register_types(void)
424 {
425 type_register_static(&i2c_bus_info);
426 type_register_static(&i2c_slave_type_info);
427 }
428
429 type_init(i2c_slave_register_types)
430