1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "timing_generator.h"
29 #include "hw_sequencer.h"
30 #include "hw_sequencer_private.h"
31 #include "basics/dc_common.h"
32 #include "resource.h"
33 #include "dc_dmub_srv.h"
34 #include "dc_state_priv.h"
35
36 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
37 #define MAX_NUM_MCACHE 8
38
39 /* used as index in array of black_color_format */
40 enum black_color_format {
41 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
42 BLACK_COLOR_FORMAT_RGB_LIMITED,
43 BLACK_COLOR_FORMAT_YUV_TV,
44 BLACK_COLOR_FORMAT_YUV_CV,
45 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
46 BLACK_COLOR_FORMAT_DEBUG,
47 };
48
49 enum dc_color_space_type {
50 COLOR_SPACE_RGB_TYPE,
51 COLOR_SPACE_RGB_LIMITED_TYPE,
52 COLOR_SPACE_YCBCR601_TYPE,
53 COLOR_SPACE_YCBCR709_TYPE,
54 COLOR_SPACE_YCBCR2020_TYPE,
55 COLOR_SPACE_YCBCR601_LIMITED_TYPE,
56 COLOR_SPACE_YCBCR709_LIMITED_TYPE,
57 COLOR_SPACE_YCBCR709_BLACK_TYPE,
58 };
59
60 static const struct tg_color black_color_format[] = {
61 /* BlackColorFormat_RGB_FullRange */
62 {0, 0, 0},
63 /* BlackColorFormat_RGB_Limited */
64 {0x40, 0x40, 0x40},
65 /* BlackColorFormat_YUV_TV */
66 {0x200, 0x40, 0x200},
67 /* BlackColorFormat_YUV_CV */
68 {0x1f4, 0x40, 0x1f4},
69 /* BlackColorFormat_YUV_SuperAA */
70 {0x1a2, 0x20, 0x1a2},
71 /* visual confirm debug */
72 {0xff, 0xff, 0},
73 };
74
75 struct out_csc_color_matrix_type {
76 enum dc_color_space_type color_space_type;
77 uint16_t regval[12];
78 };
79
80 static const struct out_csc_color_matrix_type output_csc_matrix[] = {
81 { COLOR_SPACE_RGB_TYPE,
82 { 0x2000, 0, 0, 0,
83 0, 0x2000, 0, 0,
84 0, 0, 0x2000, 0} },
85 { COLOR_SPACE_RGB_LIMITED_TYPE,
86 { 0x1B67, 0, 0, 0x201,
87 0, 0x1B67, 0, 0x201,
88 0, 0, 0x1B67, 0x201} },
89 { COLOR_SPACE_YCBCR601_TYPE,
90 { 0xE04, 0xF444, 0xFDB9, 0x1004,
91 0x831, 0x1016, 0x320, 0x201,
92 0xFB45, 0xF6B7, 0xE04, 0x1004} },
93 { COLOR_SPACE_YCBCR709_TYPE,
94 { 0xE04, 0xF345, 0xFEB7, 0x1004,
95 0x5D3, 0x1399, 0x1FA, 0x201,
96 0xFCCA, 0xF533, 0xE04, 0x1004} },
97 /* TODO: correct values below */
98 { COLOR_SPACE_YCBCR601_LIMITED_TYPE,
99 { 0xE00, 0xF447, 0xFDB9, 0x1000,
100 0x991, 0x12C9, 0x3A6, 0x200,
101 0xFB47, 0xF6B9, 0xE00, 0x1000} },
102 { COLOR_SPACE_YCBCR709_LIMITED_TYPE,
103 { 0xE00, 0xF349, 0xFEB7, 0x1000,
104 0x6CE, 0x16E3, 0x24F, 0x200,
105 0xFCCB, 0xF535, 0xE00, 0x1000} },
106 { COLOR_SPACE_YCBCR2020_TYPE,
107 { 0x1000, 0xF149, 0xFEB7, 0x1004,
108 0x0868, 0x15B2, 0x01E6, 0x201,
109 0xFB88, 0xF478, 0x1000, 0x1004} },
110 { COLOR_SPACE_YCBCR709_BLACK_TYPE,
111 { 0x0000, 0x0000, 0x0000, 0x1000,
112 0x0000, 0x0000, 0x0000, 0x0200,
113 0x0000, 0x0000, 0x0000, 0x1000} },
114 };
115
is_rgb_type(enum dc_color_space color_space)116 static bool is_rgb_type(
117 enum dc_color_space color_space)
118 {
119 bool ret = false;
120
121 if (color_space == COLOR_SPACE_SRGB ||
122 color_space == COLOR_SPACE_XR_RGB ||
123 color_space == COLOR_SPACE_MSREF_SCRGB ||
124 color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
125 color_space == COLOR_SPACE_ADOBERGB ||
126 color_space == COLOR_SPACE_DCIP3 ||
127 color_space == COLOR_SPACE_DOLBYVISION)
128 ret = true;
129 return ret;
130 }
131
is_rgb_limited_type(enum dc_color_space color_space)132 static bool is_rgb_limited_type(
133 enum dc_color_space color_space)
134 {
135 bool ret = false;
136
137 if (color_space == COLOR_SPACE_SRGB_LIMITED ||
138 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
139 ret = true;
140 return ret;
141 }
142
is_ycbcr601_type(enum dc_color_space color_space)143 static bool is_ycbcr601_type(
144 enum dc_color_space color_space)
145 {
146 bool ret = false;
147
148 if (color_space == COLOR_SPACE_YCBCR601 ||
149 color_space == COLOR_SPACE_XV_YCC_601)
150 ret = true;
151 return ret;
152 }
153
is_ycbcr601_limited_type(enum dc_color_space color_space)154 static bool is_ycbcr601_limited_type(
155 enum dc_color_space color_space)
156 {
157 bool ret = false;
158
159 if (color_space == COLOR_SPACE_YCBCR601_LIMITED)
160 ret = true;
161 return ret;
162 }
163
is_ycbcr709_type(enum dc_color_space color_space)164 static bool is_ycbcr709_type(
165 enum dc_color_space color_space)
166 {
167 bool ret = false;
168
169 if (color_space == COLOR_SPACE_YCBCR709 ||
170 color_space == COLOR_SPACE_XV_YCC_709)
171 ret = true;
172 return ret;
173 }
174
is_ycbcr2020_type(enum dc_color_space color_space)175 static bool is_ycbcr2020_type(
176 enum dc_color_space color_space)
177 {
178 bool ret = false;
179
180 if (color_space == COLOR_SPACE_2020_YCBCR_LIMITED || color_space == COLOR_SPACE_2020_YCBCR_FULL)
181 ret = true;
182 return ret;
183 }
184
is_ycbcr709_limited_type(enum dc_color_space color_space)185 static bool is_ycbcr709_limited_type(
186 enum dc_color_space color_space)
187 {
188 bool ret = false;
189
190 if (color_space == COLOR_SPACE_YCBCR709_LIMITED)
191 ret = true;
192 return ret;
193 }
194
get_color_space_type(enum dc_color_space color_space)195 static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space)
196 {
197 enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE;
198
199 if (is_rgb_type(color_space))
200 type = COLOR_SPACE_RGB_TYPE;
201 else if (is_rgb_limited_type(color_space))
202 type = COLOR_SPACE_RGB_LIMITED_TYPE;
203 else if (is_ycbcr601_type(color_space))
204 type = COLOR_SPACE_YCBCR601_TYPE;
205 else if (is_ycbcr709_type(color_space))
206 type = COLOR_SPACE_YCBCR709_TYPE;
207 else if (is_ycbcr601_limited_type(color_space))
208 type = COLOR_SPACE_YCBCR601_LIMITED_TYPE;
209 else if (is_ycbcr709_limited_type(color_space))
210 type = COLOR_SPACE_YCBCR709_LIMITED_TYPE;
211 else if (is_ycbcr2020_type(color_space))
212 type = COLOR_SPACE_YCBCR2020_TYPE;
213 else if (color_space == COLOR_SPACE_YCBCR709)
214 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
215 else if (color_space == COLOR_SPACE_YCBCR709_BLACK)
216 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
217 return type;
218 }
219
find_color_matrix(enum dc_color_space color_space,uint32_t * array_size)220 const uint16_t *find_color_matrix(enum dc_color_space color_space,
221 uint32_t *array_size)
222 {
223 int i;
224 enum dc_color_space_type type;
225 const uint16_t *val = NULL;
226 int arr_size = NUM_ELEMENTS(output_csc_matrix);
227
228 type = get_color_space_type(color_space);
229 for (i = 0; i < arr_size; i++)
230 if (output_csc_matrix[i].color_space_type == type) {
231 val = output_csc_matrix[i].regval;
232 *array_size = 12;
233 break;
234 }
235
236 return val;
237 }
238
239
color_space_to_black_color(const struct dc * dc,enum dc_color_space colorspace,struct tg_color * black_color)240 void color_space_to_black_color(
241 const struct dc *dc,
242 enum dc_color_space colorspace,
243 struct tg_color *black_color)
244 {
245 switch (colorspace) {
246 case COLOR_SPACE_YCBCR601:
247 case COLOR_SPACE_YCBCR709:
248 case COLOR_SPACE_YCBCR709_BLACK:
249 case COLOR_SPACE_YCBCR601_LIMITED:
250 case COLOR_SPACE_YCBCR709_LIMITED:
251 case COLOR_SPACE_2020_YCBCR_LIMITED:
252 case COLOR_SPACE_2020_YCBCR_FULL:
253 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
254 break;
255
256 case COLOR_SPACE_SRGB_LIMITED:
257 *black_color =
258 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
259 break;
260
261 /**
262 * Remove default and add case for all color space
263 * so when we forget to add new color space
264 * compiler will give a warning
265 */
266 case COLOR_SPACE_UNKNOWN:
267 case COLOR_SPACE_SRGB:
268 case COLOR_SPACE_XR_RGB:
269 case COLOR_SPACE_MSREF_SCRGB:
270 case COLOR_SPACE_XV_YCC_709:
271 case COLOR_SPACE_XV_YCC_601:
272 case COLOR_SPACE_2020_RGB_FULLRANGE:
273 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
274 case COLOR_SPACE_ADOBERGB:
275 case COLOR_SPACE_DCIP3:
276 case COLOR_SPACE_DISPLAYNATIVE:
277 case COLOR_SPACE_DOLBYVISION:
278 case COLOR_SPACE_APPCTRL:
279 case COLOR_SPACE_CUSTOMPOINTS:
280 /* fefault is sRGB black (full range). */
281 *black_color =
282 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
283 /* default is sRGB black 0. */
284 break;
285 }
286 }
287
hwss_wait_for_blank_complete(struct timing_generator * tg)288 bool hwss_wait_for_blank_complete(
289 struct timing_generator *tg)
290 {
291 int counter;
292
293 /* Not applicable if the pipe is not primary, save 300ms of boot time */
294 if (!tg->funcs->is_blanked)
295 return true;
296 for (counter = 0; counter < 100; counter++) {
297 if (tg->funcs->is_blanked(tg))
298 break;
299
300 msleep(1);
301 }
302
303 if (counter == 100) {
304 dm_error("DC: failed to blank crtc!\n");
305 return false;
306 }
307
308 return true;
309 }
310
get_mpctree_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)311 void get_mpctree_visual_confirm_color(
312 struct pipe_ctx *pipe_ctx,
313 struct tg_color *color)
314 {
315 const struct tg_color pipe_colors[6] = {
316 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */
317 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
318 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
319 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
320 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
321 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
322 };
323
324 struct pipe_ctx *top_pipe = pipe_ctx;
325
326 while (top_pipe->top_pipe)
327 top_pipe = top_pipe->top_pipe;
328
329 *color = pipe_colors[top_pipe->pipe_idx];
330 }
331
get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)332 void get_surface_visual_confirm_color(
333 const struct pipe_ctx *pipe_ctx,
334 struct tg_color *color)
335 {
336 uint32_t color_value = MAX_TG_COLOR_VALUE;
337
338 switch (pipe_ctx->plane_res.scl_data.format) {
339 case PIXEL_FORMAT_ARGB8888:
340 /* set border color to red */
341 color->color_r_cr = color_value;
342 if (pipe_ctx->plane_state->layer_index > 0) {
343 /* set border color to pink */
344 color->color_b_cb = color_value;
345 color->color_g_y = color_value * 0.5;
346 }
347 break;
348
349 case PIXEL_FORMAT_ARGB2101010:
350 /* set border color to blue */
351 color->color_b_cb = color_value;
352 if (pipe_ctx->plane_state->layer_index > 0) {
353 /* set border color to cyan */
354 color->color_g_y = color_value;
355 }
356 break;
357 case PIXEL_FORMAT_420BPP8:
358 /* set border color to green */
359 color->color_g_y = color_value;
360 break;
361 case PIXEL_FORMAT_420BPP10:
362 /* set border color to yellow */
363 color->color_g_y = color_value;
364 color->color_r_cr = color_value;
365 break;
366 case PIXEL_FORMAT_FP16:
367 /* set border color to white */
368 color->color_r_cr = color_value;
369 color->color_b_cb = color_value;
370 color->color_g_y = color_value;
371 if (pipe_ctx->plane_state->layer_index > 0) {
372 /* set border color to orange */
373 color->color_g_y = 0.22 * color_value;
374 color->color_b_cb = 0;
375 }
376 break;
377 default:
378 break;
379 }
380 }
381
get_hdr_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)382 void get_hdr_visual_confirm_color(
383 struct pipe_ctx *pipe_ctx,
384 struct tg_color *color)
385 {
386 uint32_t color_value = MAX_TG_COLOR_VALUE;
387 bool is_sdr = false;
388
389 /* Determine the overscan color based on the top-most (desktop) plane's context */
390 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
391
392 while (top_pipe_ctx->top_pipe != NULL)
393 top_pipe_ctx = top_pipe_ctx->top_pipe;
394
395 switch (top_pipe_ctx->plane_res.scl_data.format) {
396 case PIXEL_FORMAT_ARGB2101010:
397 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
398 /* HDR10, ARGB2101010 - set border color to red */
399 color->color_r_cr = color_value;
400 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
401 /* FreeSync 2 ARGB2101010 - set border color to pink */
402 color->color_r_cr = color_value;
403 color->color_b_cb = color_value;
404 } else
405 is_sdr = true;
406 break;
407 case PIXEL_FORMAT_FP16:
408 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
409 /* HDR10, FP16 - set border color to blue */
410 color->color_b_cb = color_value;
411 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
412 /* FreeSync 2 HDR - set border color to green */
413 color->color_g_y = color_value;
414 } else
415 is_sdr = true;
416 break;
417 default:
418 is_sdr = true;
419 break;
420 }
421
422 if (is_sdr) {
423 /* SDR - set border color to Gray */
424 color->color_r_cr = color_value/2;
425 color->color_b_cb = color_value/2;
426 color->color_g_y = color_value/2;
427 }
428 }
429
430 /* Visual Confirm color definition for Smart Mux */
get_smartmux_visual_confirm_color(struct dc * dc,struct tg_color * color)431 void get_smartmux_visual_confirm_color(
432 struct dc *dc,
433 struct tg_color *color)
434 {
435 uint32_t color_value = MAX_TG_COLOR_VALUE;
436
437 const struct tg_color sm_ver_colors[5] = {
438 {0, 0, 0}, /* SMUX_MUXCONTROL_UNSUPPORTED - Black */
439 {0, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_v10 - Green */
440 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_v15 - Cyan */
441 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_MDM - Yellow */
442 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_vUNKNOWN - Magenta*/
443 };
444
445 if (dc->caps.is_apu) {
446 /* APU driving the eDP */
447 *color = sm_ver_colors[dc->config.smart_mux_version];
448 } else {
449 /* dGPU driving the eDP - red */
450 color->color_r_cr = color_value;
451 color->color_g_y = 0;
452 color->color_b_cb = 0;
453 }
454 }
455
456 /* Visual Confirm color definition for VABC */
get_vabc_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)457 void get_vabc_visual_confirm_color(
458 struct pipe_ctx *pipe_ctx,
459 struct tg_color *color)
460 {
461 uint32_t color_value = MAX_TG_COLOR_VALUE;
462 struct dc_link *edp_link = NULL;
463
464 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) {
465 if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP)
466 edp_link = pipe_ctx->stream->link;
467 }
468
469 if (edp_link) {
470 switch (edp_link->backlight_control_type) {
471 case BACKLIGHT_CONTROL_PWM:
472 color->color_r_cr = color_value;
473 color->color_g_y = 0;
474 color->color_b_cb = 0;
475 break;
476 case BACKLIGHT_CONTROL_AMD_AUX:
477 color->color_r_cr = 0;
478 color->color_g_y = color_value;
479 color->color_b_cb = 0;
480 break;
481 case BACKLIGHT_CONTROL_VESA_AUX:
482 color->color_r_cr = 0;
483 color->color_g_y = 0;
484 color->color_b_cb = color_value;
485 break;
486 }
487 } else {
488 color->color_r_cr = 0;
489 color->color_g_y = 0;
490 color->color_b_cb = 0;
491 }
492 }
493
get_subvp_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)494 void get_subvp_visual_confirm_color(
495 struct pipe_ctx *pipe_ctx,
496 struct tg_color *color)
497 {
498 uint32_t color_value = MAX_TG_COLOR_VALUE;
499 if (pipe_ctx) {
500 switch (pipe_ctx->p_state_type) {
501 case P_STATE_SUB_VP:
502 color->color_r_cr = color_value;
503 color->color_g_y = 0;
504 color->color_b_cb = 0;
505 break;
506 case P_STATE_DRR_SUB_VP:
507 color->color_r_cr = 0;
508 color->color_g_y = color_value;
509 color->color_b_cb = 0;
510 break;
511 case P_STATE_V_BLANK_SUB_VP:
512 color->color_r_cr = 0;
513 color->color_g_y = 0;
514 color->color_b_cb = color_value;
515 break;
516 default:
517 break;
518 }
519 }
520 }
521
get_mclk_switch_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)522 void get_mclk_switch_visual_confirm_color(
523 struct pipe_ctx *pipe_ctx,
524 struct tg_color *color)
525 {
526 uint32_t color_value = MAX_TG_COLOR_VALUE;
527
528 if (pipe_ctx) {
529 switch (pipe_ctx->p_state_type) {
530 case P_STATE_V_BLANK:
531 color->color_r_cr = color_value;
532 color->color_g_y = color_value;
533 color->color_b_cb = 0;
534 break;
535 case P_STATE_FPO:
536 color->color_r_cr = 0;
537 color->color_g_y = color_value;
538 color->color_b_cb = color_value;
539 break;
540 case P_STATE_V_ACTIVE:
541 color->color_r_cr = color_value;
542 color->color_g_y = 0;
543 color->color_b_cb = color_value;
544 break;
545 case P_STATE_SUB_VP:
546 color->color_r_cr = color_value;
547 color->color_g_y = 0;
548 color->color_b_cb = 0;
549 break;
550 case P_STATE_DRR_SUB_VP:
551 color->color_r_cr = 0;
552 color->color_g_y = color_value;
553 color->color_b_cb = 0;
554 break;
555 case P_STATE_V_BLANK_SUB_VP:
556 color->color_r_cr = 0;
557 color->color_g_y = 0;
558 color->color_b_cb = color_value;
559 break;
560 default:
561 break;
562 }
563 }
564 }
565
get_cursor_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)566 void get_cursor_visual_confirm_color(
567 struct pipe_ctx *pipe_ctx,
568 struct tg_color *color)
569 {
570 uint32_t color_value = MAX_TG_COLOR_VALUE;
571
572 if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {
573 color->color_r_cr = color_value;
574 color->color_g_y = 0;
575 color->color_b_cb = 0;
576 } else {
577 color->color_r_cr = 0;
578 color->color_g_y = 0;
579 color->color_b_cb = color_value;
580 }
581 }
582
get_dcc_visual_confirm_color(struct dc * dc,struct pipe_ctx * pipe_ctx,struct tg_color * color)583 void get_dcc_visual_confirm_color(
584 struct dc *dc,
585 struct pipe_ctx *pipe_ctx,
586 struct tg_color *color)
587 {
588 const uint32_t MCACHE_ID_UNASSIGNED = 0xF;
589
590 if (!pipe_ctx->plane_state->dcc.enable) {
591 color->color_r_cr = 0; /* black - DCC disabled */
592 color->color_g_y = 0;
593 color->color_b_cb = 0;
594 return;
595 }
596
597 if (dc->ctx->dce_version < DCN_VERSION_4_01) {
598 color->color_r_cr = MAX_TG_COLOR_VALUE; /* red - DCC enabled */
599 color->color_g_y = 0;
600 color->color_b_cb = 0;
601 return;
602 }
603
604 uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;
605 uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;
606
607 if (first_id != MCACHE_ID_UNASSIGNED && second_id != MCACHE_ID_UNASSIGNED && first_id != second_id) {
608 color->color_r_cr = MAX_TG_COLOR_VALUE/2; /* grey - 2 mcache */
609 color->color_g_y = MAX_TG_COLOR_VALUE/2;
610 color->color_b_cb = MAX_TG_COLOR_VALUE/2;
611 }
612
613 else if (first_id != MCACHE_ID_UNASSIGNED || second_id != MCACHE_ID_UNASSIGNED) {
614 const struct tg_color id_colors[MAX_NUM_MCACHE] = {
615 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
616 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
617 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
618 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
619 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
620 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* white */
621 {MAX_TG_COLOR_VALUE/2, 0, 0}, /* dark red */
622 {0, MAX_TG_COLOR_VALUE/2, 0}, /* dark green */
623 };
624
625 uint32_t assigned_id = (first_id != MCACHE_ID_UNASSIGNED) ? first_id : second_id;
626 *color = id_colors[assigned_id];
627 }
628 }
629
set_p_state_switch_method(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)630 void set_p_state_switch_method(
631 struct dc *dc,
632 struct dc_state *context,
633 struct pipe_ctx *pipe_ctx)
634 {
635 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
636 bool enable_subvp;
637
638 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
639 return;
640
641 pipe_ctx->p_state_type = P_STATE_UNKNOWN;
642 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
643 dm_dram_clock_change_unsupported) {
644 /* MCLK switching is supported */
645 if (!pipe_ctx->has_vactive_margin) {
646 /* In Vblank - yellow */
647 pipe_ctx->p_state_type = P_STATE_V_BLANK;
648
649 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
650 /* FPO + Vblank - cyan */
651 pipe_ctx->p_state_type = P_STATE_FPO;
652 }
653 } else {
654 /* In Vactive - pink */
655 pipe_ctx->p_state_type = P_STATE_V_ACTIVE;
656 }
657
658 /* SubVP */
659 enable_subvp = false;
660
661 for (int i = 0; i < dc->res_pool->pipe_count; i++) {
662 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
663
664 if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&
665 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
666 /* SubVP enable - red */
667 pipe_ctx->p_state_type = P_STATE_SUB_VP;
668 enable_subvp = true;
669
670 if (pipe_ctx->stream == pipe->stream)
671 return;
672 break;
673 }
674 }
675
676 if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {
677 if (pipe_ctx->stream->allow_freesync == 1) {
678 /* SubVP enable and DRR on - green */
679 pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;
680 } else {
681 /* SubVP enable and No DRR - blue */
682 pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;
683 }
684 }
685 }
686 }
687
set_drr_and_clear_adjust_pending(struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream,struct drr_params * params)688 void set_drr_and_clear_adjust_pending(
689 struct pipe_ctx *pipe_ctx,
690 struct dc_stream_state *stream,
691 struct drr_params *params)
692 {
693 /* params can be null.*/
694 if (pipe_ctx && pipe_ctx->stream_res.tg &&
695 pipe_ctx->stream_res.tg->funcs->set_drr)
696 pipe_ctx->stream_res.tg->funcs->set_drr(
697 pipe_ctx->stream_res.tg, params);
698
699 if (stream)
700 stream->adjust.timing_adjust_pending = false;
701 }
702
get_fams2_visual_confirm_color(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx,struct tg_color * color)703 void get_fams2_visual_confirm_color(
704 struct dc *dc,
705 struct dc_state *context,
706 struct pipe_ctx *pipe_ctx,
707 struct tg_color *color)
708 {
709 uint32_t color_value = MAX_TG_COLOR_VALUE;
710
711 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)
712 return;
713
714 /* driver only handles visual confirm when FAMS2 is disabled */
715 if (!dc_state_is_fams2_in_use(dc, context)) {
716 /* when FAMS2 is disabled, all pipes are grey */
717 color->color_g_y = color_value / 2;
718 color->color_b_cb = color_value / 2;
719 color->color_r_cr = color_value / 2;
720 }
721 }
722
hwss_build_fast_sequence(struct dc * dc,struct dc_dmub_cmd * dc_dmub_cmd,unsigned int dmub_cmd_count,struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],unsigned int * num_steps,struct pipe_ctx * pipe_ctx,struct dc_stream_status * stream_status,struct dc_state * context)723 void hwss_build_fast_sequence(struct dc *dc,
724 struct dc_dmub_cmd *dc_dmub_cmd,
725 unsigned int dmub_cmd_count,
726 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
727 unsigned int *num_steps,
728 struct pipe_ctx *pipe_ctx,
729 struct dc_stream_status *stream_status,
730 struct dc_state *context)
731 {
732 struct dc_plane_state *plane = pipe_ctx->plane_state;
733 struct dc_stream_state *stream = pipe_ctx->stream;
734 struct dce_hwseq *hws = dc->hwseq;
735 struct pipe_ctx *current_pipe = NULL;
736 struct pipe_ctx *current_mpc_pipe = NULL;
737 unsigned int i = 0;
738
739 *num_steps = 0; // Initialize to 0
740
741 if (!plane || !stream)
742 return;
743
744 if (dc->hwss.wait_for_dcc_meta_propagation) {
745 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
746 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;
747 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
748 (*num_steps)++;
749 }
750 if (dc->hwss.subvp_pipe_control_lock_fast) {
751 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
752 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
753 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
754 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
755 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
756 (*num_steps)++;
757 }
758 if (dc->hwss.fams2_global_control_lock_fast) {
759 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
760 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true;
761 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
762 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
763 (*num_steps)++;
764 }
765 if (dc->hwss.pipe_control_lock) {
766 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
767 block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
768 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
769 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
770 (*num_steps)++;
771 }
772
773 for (i = 0; i < dmub_cmd_count; i++) {
774 block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
775 block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
776 block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
777 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
778 (*num_steps)++;
779 }
780
781 current_pipe = pipe_ctx;
782 while (current_pipe) {
783 current_mpc_pipe = current_pipe;
784 while (current_mpc_pipe) {
785 if (current_mpc_pipe->plane_state) {
786 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {
787 block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;
788 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
789 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
790 (*num_steps)++;
791 }
792 if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
793 block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
794 block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
795 block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
796 block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
797 (*num_steps)++;
798 }
799 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
800 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
801 stream_status->mall_stream_config.type == SUBVP_MAIN) {
802 block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
803 block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address;
804 block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
805 block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
806 (*num_steps)++;
807 }
808
809 block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
810 block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
811 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
812 (*num_steps)++;
813 }
814
815 if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
816 block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
817 block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
818 block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
819 block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
820 (*num_steps)++;
821 }
822
823 if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
824 block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
825 block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
826 (*num_steps)++;
827 }
828 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
829 block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
830 block_sequence[*num_steps].func = DPP_SETUP_DPP;
831 (*num_steps)++;
832 }
833 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
834 block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
835 block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
836 (*num_steps)++;
837 }
838 }
839 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
840 block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
841 block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
842 block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
843 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
844 (*num_steps)++;
845 }
846 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE &&
847 dc->hwss.update_visual_confirm_color) {
848 block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;
849 block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;
850 block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
851 block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;
852 (*num_steps)++;
853 }
854 if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
855 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
856 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
857 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
858 block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
859 (*num_steps)++;
860
861 if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
862 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
863 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
864 block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
865 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
866 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
867 (*num_steps)++;
868 } else {
869 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
870 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
871 block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
872 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
873 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
874 (*num_steps)++;
875 }
876 }
877 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
878 }
879 current_pipe = current_pipe->next_odm_pipe;
880 }
881
882 if (dc->hwss.pipe_control_lock) {
883 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
884 block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
885 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
886 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
887 (*num_steps)++;
888 }
889 if (dc->hwss.subvp_pipe_control_lock_fast) {
890 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
891 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
892 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
893 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
894 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
895 (*num_steps)++;
896 }
897 if (dc->hwss.fams2_global_control_lock_fast) {
898 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
899 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = false;
900 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
901 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
902 (*num_steps)++;
903 }
904
905 current_pipe = pipe_ctx;
906 while (current_pipe) {
907 current_mpc_pipe = current_pipe;
908
909 while (current_mpc_pipe) {
910 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe &&
911 current_mpc_pipe->stream && current_mpc_pipe->plane_state &&
912 current_mpc_pipe->plane_state->update_flags.bits.addr_update &&
913 !current_mpc_pipe->plane_state->skip_manual_trigger) {
914 block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
915 block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
916 (*num_steps)++;
917 }
918 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
919 }
920 current_pipe = current_pipe->next_odm_pipe;
921 }
922 }
923
hwss_execute_sequence(struct dc * dc,struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],int num_steps)924 void hwss_execute_sequence(struct dc *dc,
925 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
926 int num_steps)
927 {
928 unsigned int i;
929 union block_sequence_params *params;
930 struct dce_hwseq *hws = dc->hwseq;
931
932 for (i = 0; i < num_steps; i++) {
933 params = &(block_sequence[i].params);
934 switch (block_sequence[i].func) {
935
936 case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST:
937 dc->hwss.subvp_pipe_control_lock_fast(params);
938 break;
939 case OPTC_PIPE_CONTROL_LOCK:
940 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,
941 params->pipe_control_lock_params.pipe_ctx,
942 params->pipe_control_lock_params.lock);
943 break;
944 case HUBP_SET_FLIP_CONTROL_GSL:
945 dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx,
946 params->set_flip_control_gsl_params.flip_immediate);
947 break;
948 case HUBP_PROGRAM_TRIPLEBUFFER:
949 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,
950 params->program_triplebuffer_params.pipe_ctx,
951 params->program_triplebuffer_params.enableTripleBuffer);
952 break;
953 case HUBP_UPDATE_PLANE_ADDR:
954 dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,
955 params->update_plane_addr_params.pipe_ctx);
956 break;
957 case DPP_SET_INPUT_TRANSFER_FUNC:
958 hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,
959 params->set_input_transfer_func_params.pipe_ctx,
960 params->set_input_transfer_func_params.plane_state);
961 break;
962 case DPP_PROGRAM_GAMUT_REMAP:
963 dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
964 break;
965 case DPP_SETUP_DPP:
966 hwss_setup_dpp(params);
967 break;
968 case DPP_PROGRAM_BIAS_AND_SCALE:
969 hwss_program_bias_and_scale(params);
970 break;
971 case OPTC_PROGRAM_MANUAL_TRIGGER:
972 hwss_program_manual_trigger(params);
973 break;
974 case DPP_SET_OUTPUT_TRANSFER_FUNC:
975 hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,
976 params->set_output_transfer_func_params.pipe_ctx,
977 params->set_output_transfer_func_params.stream);
978 break;
979 case MPC_UPDATE_VISUAL_CONFIRM:
980 dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,
981 params->update_visual_confirm_params.pipe_ctx,
982 params->update_visual_confirm_params.mpcc_id);
983 break;
984 case MPC_POWER_ON_MPC_MEM_PWR:
985 hwss_power_on_mpc_mem_pwr(params);
986 break;
987 case MPC_SET_OUTPUT_CSC:
988 hwss_set_output_csc(params);
989 break;
990 case MPC_SET_OCSC_DEFAULT:
991 hwss_set_ocsc_default(params);
992 break;
993 case DMUB_SEND_DMCUB_CMD:
994 hwss_send_dmcub_cmd(params);
995 break;
996 case DMUB_SUBVP_SAVE_SURF_ADDR:
997 hwss_subvp_save_surf_addr(params);
998 break;
999 case HUBP_WAIT_FOR_DCC_META_PROP:
1000 dc->hwss.wait_for_dcc_meta_propagation(
1001 params->wait_for_dcc_meta_propagation_params.dc,
1002 params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);
1003 break;
1004 case DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST:
1005 dc->hwss.fams2_global_control_lock_fast(params);
1006 break;
1007 default:
1008 ASSERT(false);
1009 break;
1010 }
1011 }
1012 }
1013
hwss_send_dmcub_cmd(union block_sequence_params * params)1014 void hwss_send_dmcub_cmd(union block_sequence_params *params)
1015 {
1016 struct dc_context *ctx = params->send_dmcub_cmd_params.ctx;
1017 union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd;
1018 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type;
1019
1020 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);
1021 }
1022
hwss_program_manual_trigger(union block_sequence_params * params)1023 void hwss_program_manual_trigger(union block_sequence_params *params)
1024 {
1025 struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;
1026
1027 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
1028 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
1029 }
1030
hwss_setup_dpp(union block_sequence_params * params)1031 void hwss_setup_dpp(union block_sequence_params *params)
1032 {
1033 struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;
1034 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1035 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1036
1037 if (!plane_state)
1038 return;
1039
1040 if (dpp && dpp->funcs->dpp_setup) {
1041 // program the input csc
1042 dpp->funcs->dpp_setup(dpp,
1043 plane_state->format,
1044 EXPANSION_MODE_ZERO,
1045 plane_state->input_csc_color_matrix,
1046 plane_state->color_space,
1047 NULL);
1048 }
1049
1050 if (dpp && dpp->funcs->set_cursor_matrix) {
1051 dpp->funcs->set_cursor_matrix(dpp,
1052 plane_state->color_space,
1053 plane_state->cursor_csc_color_matrix);
1054 }
1055 }
1056
hwss_program_bias_and_scale(union block_sequence_params * params)1057 void hwss_program_bias_and_scale(union block_sequence_params *params)
1058 {
1059 struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
1060 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1061 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1062 struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
1063
1064 //TODO :for CNVC set scale and bias registers if necessary
1065 if (dpp->funcs->dpp_program_bias_and_scale) {
1066 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1067 }
1068 }
1069
hwss_power_on_mpc_mem_pwr(union block_sequence_params * params)1070 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
1071 {
1072 struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
1073 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
1074 bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
1075
1076 if (mpc->funcs->power_on_mpc_mem_pwr)
1077 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
1078 }
1079
hwss_set_output_csc(union block_sequence_params * params)1080 void hwss_set_output_csc(union block_sequence_params *params)
1081 {
1082 struct mpc *mpc = params->set_output_csc_params.mpc;
1083 int opp_id = params->set_output_csc_params.opp_id;
1084 const uint16_t *matrix = params->set_output_csc_params.regval;
1085 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
1086
1087 if (mpc->funcs->set_output_csc != NULL)
1088 mpc->funcs->set_output_csc(mpc,
1089 opp_id,
1090 matrix,
1091 ocsc_mode);
1092 }
1093
hwss_set_ocsc_default(union block_sequence_params * params)1094 void hwss_set_ocsc_default(union block_sequence_params *params)
1095 {
1096 struct mpc *mpc = params->set_ocsc_default_params.mpc;
1097 int opp_id = params->set_ocsc_default_params.opp_id;
1098 enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
1099 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
1100
1101 if (mpc->funcs->set_ocsc_default != NULL)
1102 mpc->funcs->set_ocsc_default(mpc,
1103 opp_id,
1104 colorspace,
1105 ocsc_mode);
1106 }
1107
hwss_subvp_save_surf_addr(union block_sequence_params * params)1108 void hwss_subvp_save_surf_addr(union block_sequence_params *params)
1109 {
1110 struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv;
1111 const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr;
1112 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index;
1113
1114 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);
1115 }
1116
get_surface_tile_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)1117 void get_surface_tile_visual_confirm_color(
1118 struct pipe_ctx *pipe_ctx,
1119 struct tg_color *color)
1120 {
1121 uint32_t color_value = MAX_TG_COLOR_VALUE;
1122 /* Determine the overscan color based on the bottom-most plane's context */
1123 struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
1124
1125 while (bottom_pipe_ctx->bottom_pipe != NULL)
1126 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
1127
1128 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
1129 case DC_SW_LINEAR:
1130 /* LINEAR Surface - set border color to red */
1131 color->color_r_cr = color_value;
1132 break;
1133 default:
1134 break;
1135 }
1136 }
1137
1138 /**
1139 * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank
1140 * pattern updates
1141 *
1142 * @dc: [in] dc reference
1143 * @context: [in] hardware context in use
1144 */
hwss_wait_for_all_blank_complete(struct dc * dc,struct dc_state * context)1145 void hwss_wait_for_all_blank_complete(struct dc *dc,
1146 struct dc_state *context)
1147 {
1148 struct pipe_ctx *opp_head;
1149 struct dce_hwseq *hws = dc->hwseq;
1150 int i;
1151
1152 if (!hws->funcs.wait_for_blank_complete)
1153 return;
1154
1155 for (i = 0; i < MAX_PIPES; i++) {
1156 opp_head = &context->res_ctx.pipe_ctx[i];
1157
1158 if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
1159 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)
1160 continue;
1161
1162 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
1163 }
1164 }
1165
hwss_wait_for_odm_update_pending_complete(struct dc * dc,struct dc_state * context)1166 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)
1167 {
1168 struct pipe_ctx *otg_master;
1169 struct timing_generator *tg;
1170 int i;
1171
1172 for (i = 0; i < MAX_PIPES; i++) {
1173 otg_master = &context->res_ctx.pipe_ctx[i];
1174 if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
1175 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)
1176 continue;
1177 tg = otg_master->stream_res.tg;
1178 if (tg->funcs->wait_odm_doublebuffer_pending_clear)
1179 tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
1180 }
1181
1182 /* ODM update may require to reprogram blank pattern for each OPP */
1183 hwss_wait_for_all_blank_complete(dc, context);
1184 }
1185
hwss_wait_for_no_pipes_pending(struct dc * dc,struct dc_state * context)1186 void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1187 {
1188 int i;
1189 for (i = 0; i < MAX_PIPES; i++) {
1190 int count = 0;
1191 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1192
1193 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1194 continue;
1195
1196 /* Timeout 100 ms */
1197 while (count < 100000) {
1198 /* Must set to false to start with, due to OR in update function */
1199 pipe->plane_state->status.is_flip_pending = false;
1200 dc->hwss.update_pending_status(pipe);
1201 if (!pipe->plane_state->status.is_flip_pending)
1202 break;
1203 udelay(1);
1204 count++;
1205 }
1206 ASSERT(!pipe->plane_state->status.is_flip_pending);
1207 }
1208 }
1209
hwss_wait_for_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1210 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1211 {
1212 /*
1213 * This function calls HWSS to wait for any potentially double buffered
1214 * operations to complete. It should be invoked as a pre-amble prior
1215 * to full update programming before asserting any HW locks.
1216 */
1217 int pipe_idx;
1218 int opp_inst;
1219 int opp_count = dc->res_pool->res_cap->num_opp;
1220 struct hubp *hubp;
1221 int mpcc_inst;
1222 const struct pipe_ctx *pipe_ctx;
1223
1224 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
1225 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
1226
1227 if (!pipe_ctx->stream)
1228 continue;
1229
1230 /* For full update we must wait for all double buffer updates, not just DRR updates. This
1231 * is particularly important for minimal transitions. Only check for OTG_MASTER pipes,
1232 * as non-OTG Master pipes share the same OTG as
1233 */
1234 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {
1235 dc->hwss.wait_for_all_pending_updates(pipe_ctx);
1236 }
1237
1238 hubp = pipe_ctx->plane_res.hubp;
1239 if (!hubp)
1240 continue;
1241
1242 mpcc_inst = hubp->inst;
1243 // MPCC inst is equal to pipe index in practice
1244 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1245 if ((dc->res_pool->opps[opp_inst] != NULL) &&
1246 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
1247 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1248 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1249 break;
1250 }
1251 }
1252 }
1253 hwss_wait_for_odm_update_pending_complete(dc, dc_context);
1254 }
1255
hwss_process_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1256 void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1257 {
1258 /* wait for outstanding updates */
1259 hwss_wait_for_outstanding_hw_updates(dc, dc_context);
1260
1261 /* perform outstanding post update programming */
1262 if (dc->hwss.program_outstanding_updates)
1263 dc->hwss.program_outstanding_updates(dc, dc_context);
1264 }
1265