1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This header defines architecture specific interfaces, x86 version
6 */
7
8 #ifndef _ASM_X86_KVM_HOST_H
9 #define _ASM_X86_KVM_HOST_H
10
11 #include <linux/types.h>
12 #include <linux/mm.h>
13 #include <linux/mmu_notifier.h>
14 #include <linux/tracepoint.h>
15 #include <linux/cpumask.h>
16 #include <linux/irq_work.h>
17 #include <linux/irq.h>
18 #include <linux/workqueue.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22 #include <linux/kvm_types.h>
23 #include <linux/perf_event.h>
24 #include <linux/pvclock_gtod.h>
25 #include <linux/clocksource.h>
26 #include <linux/irqbypass.h>
27 #include <linux/hyperv.h>
28 #include <linux/kfifo.h>
29
30 #include <asm/apic.h>
31 #include <asm/pvclock-abi.h>
32 #include <asm/desc.h>
33 #include <asm/mtrr.h>
34 #include <asm/msr-index.h>
35 #include <asm/asm.h>
36 #include <asm/kvm_page_track.h>
37 #include <asm/kvm_vcpu_regs.h>
38 #include <asm/hyperv-tlfs.h>
39
40 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS
41
42 /*
43 * CONFIG_KVM_MAX_NR_VCPUS is defined iff CONFIG_KVM!=n, provide a dummy max if
44 * KVM is disabled (arbitrarily use the default from CONFIG_KVM_MAX_NR_VCPUS).
45 */
46 #ifdef CONFIG_KVM_MAX_NR_VCPUS
47 #define KVM_MAX_VCPUS CONFIG_KVM_MAX_NR_VCPUS
48 #else
49 #define KVM_MAX_VCPUS 1024
50 #endif
51
52 /*
53 * In x86, the VCPU ID corresponds to the APIC ID, and APIC IDs
54 * might be larger than the actual number of VCPUs because the
55 * APIC ID encodes CPU topology information.
56 *
57 * In the worst case, we'll need less than one extra bit for the
58 * Core ID, and less than one extra bit for the Package (Die) ID,
59 * so ratio of 4 should be enough.
60 */
61 #define KVM_VCPU_ID_RATIO 4
62 #define KVM_MAX_VCPU_IDS (KVM_MAX_VCPUS * KVM_VCPU_ID_RATIO)
63
64 /* memory slots that are not exposed to userspace */
65 #define KVM_INTERNAL_MEM_SLOTS 3
66
67 #define KVM_HALT_POLL_NS_DEFAULT 200000
68
69 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
70
71 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
72 KVM_DIRTY_LOG_INITIALLY_SET)
73
74 #define KVM_BUS_LOCK_DETECTION_VALID_MODE (KVM_BUS_LOCK_DETECTION_OFF | \
75 KVM_BUS_LOCK_DETECTION_EXIT)
76
77 #define KVM_X86_NOTIFY_VMEXIT_VALID_BITS (KVM_X86_NOTIFY_VMEXIT_ENABLED | \
78 KVM_X86_NOTIFY_VMEXIT_USER)
79
80 /* x86-specific vcpu->requests bit members */
81 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0)
82 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1)
83 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2)
84 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3)
85 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4)
86 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5)
87 #define KVM_REQ_EVENT KVM_ARCH_REQ(6)
88 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7)
89 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8)
90 #define KVM_REQ_NMI KVM_ARCH_REQ(9)
91 #define KVM_REQ_PMU KVM_ARCH_REQ(10)
92 #define KVM_REQ_PMI KVM_ARCH_REQ(11)
93 #ifdef CONFIG_KVM_SMM
94 #define KVM_REQ_SMI KVM_ARCH_REQ(12)
95 #endif
96 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13)
97 #define KVM_REQ_MCLOCK_INPROGRESS \
98 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
99 #define KVM_REQ_SCAN_IOAPIC \
100 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
101 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16)
102 #define KVM_REQ_APIC_PAGE_RELOAD \
103 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
104 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18)
105 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19)
106 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
107 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
108 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
109 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
110 #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24)
111 #define KVM_REQ_APICV_UPDATE \
112 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
113 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26)
114 #define KVM_REQ_TLB_FLUSH_GUEST \
115 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
116 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28)
117 #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29)
118 #define KVM_REQ_UPDATE_CPU_DIRTY_LOGGING \
119 KVM_ARCH_REQ_FLAGS(30, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
120 #define KVM_REQ_MMU_FREE_OBSOLETE_ROOTS \
121 KVM_ARCH_REQ_FLAGS(31, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
122 #define KVM_REQ_HV_TLB_FLUSH \
123 KVM_ARCH_REQ_FLAGS(32, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
124
125 #define CR0_RESERVED_BITS \
126 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
127 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
128 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
129
130 #define CR4_RESERVED_BITS \
131 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
132 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
133 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
134 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
135 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
136 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \
137 | X86_CR4_LAM_SUP))
138
139 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
140
141
142
143 #define INVALID_PAGE (~(hpa_t)0)
144 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
145
146 /* KVM Hugepage definitions for x86 */
147 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G
148 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1)
149 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
150 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
151 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
152 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
153 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
154
155 #define KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO 50
156 #define KVM_MIN_ALLOC_MMU_PAGES 64UL
157 #define KVM_MMU_HASH_SHIFT 12
158 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
159 #define KVM_MIN_FREE_MMU_PAGES 5
160 #define KVM_REFILL_PAGES 25
161 #define KVM_MAX_CPUID_ENTRIES 256
162 #define KVM_NR_FIXED_MTRR_REGION 88
163 #define KVM_NR_VAR_MTRR 8
164
165 #define ASYNC_PF_PER_VCPU 64
166
167 enum kvm_reg {
168 VCPU_REGS_RAX = __VCPU_REGS_RAX,
169 VCPU_REGS_RCX = __VCPU_REGS_RCX,
170 VCPU_REGS_RDX = __VCPU_REGS_RDX,
171 VCPU_REGS_RBX = __VCPU_REGS_RBX,
172 VCPU_REGS_RSP = __VCPU_REGS_RSP,
173 VCPU_REGS_RBP = __VCPU_REGS_RBP,
174 VCPU_REGS_RSI = __VCPU_REGS_RSI,
175 VCPU_REGS_RDI = __VCPU_REGS_RDI,
176 #ifdef CONFIG_X86_64
177 VCPU_REGS_R8 = __VCPU_REGS_R8,
178 VCPU_REGS_R9 = __VCPU_REGS_R9,
179 VCPU_REGS_R10 = __VCPU_REGS_R10,
180 VCPU_REGS_R11 = __VCPU_REGS_R11,
181 VCPU_REGS_R12 = __VCPU_REGS_R12,
182 VCPU_REGS_R13 = __VCPU_REGS_R13,
183 VCPU_REGS_R14 = __VCPU_REGS_R14,
184 VCPU_REGS_R15 = __VCPU_REGS_R15,
185 #endif
186 VCPU_REGS_RIP,
187 NR_VCPU_REGS,
188
189 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
190 VCPU_EXREG_CR0,
191 VCPU_EXREG_CR3,
192 VCPU_EXREG_CR4,
193 VCPU_EXREG_RFLAGS,
194 VCPU_EXREG_SEGMENTS,
195 VCPU_EXREG_EXIT_INFO_1,
196 VCPU_EXREG_EXIT_INFO_2,
197 };
198
199 enum {
200 VCPU_SREG_ES,
201 VCPU_SREG_CS,
202 VCPU_SREG_SS,
203 VCPU_SREG_DS,
204 VCPU_SREG_FS,
205 VCPU_SREG_GS,
206 VCPU_SREG_TR,
207 VCPU_SREG_LDTR,
208 };
209
210 enum exit_fastpath_completion {
211 EXIT_FASTPATH_NONE,
212 EXIT_FASTPATH_REENTER_GUEST,
213 EXIT_FASTPATH_EXIT_HANDLED,
214 };
215 typedef enum exit_fastpath_completion fastpath_t;
216
217 struct x86_emulate_ctxt;
218 struct x86_exception;
219 union kvm_smram;
220 enum x86_intercept;
221 enum x86_intercept_stage;
222
223 #define KVM_NR_DB_REGS 4
224
225 #define DR6_BUS_LOCK (1 << 11)
226 #define DR6_BD (1 << 13)
227 #define DR6_BS (1 << 14)
228 #define DR6_BT (1 << 15)
229 #define DR6_RTM (1 << 16)
230 /*
231 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits.
232 * We can regard all the bits in DR6_FIXED_1 as active_low bits;
233 * they will never be 0 for now, but when they are defined
234 * in the future it will require no code change.
235 *
236 * DR6_ACTIVE_LOW is also used as the init/reset value for DR6.
237 */
238 #define DR6_ACTIVE_LOW 0xffff0ff0
239 #define DR6_VOLATILE 0x0001e80f
240 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE)
241
242 #define DR7_BP_EN_MASK 0x000000ff
243 #define DR7_GE (1 << 9)
244 #define DR7_GD (1 << 13)
245 #define DR7_FIXED_1 0x00000400
246 #define DR7_VOLATILE 0xffff2bff
247
248 #define KVM_GUESTDBG_VALID_MASK \
249 (KVM_GUESTDBG_ENABLE | \
250 KVM_GUESTDBG_SINGLESTEP | \
251 KVM_GUESTDBG_USE_HW_BP | \
252 KVM_GUESTDBG_USE_SW_BP | \
253 KVM_GUESTDBG_INJECT_BP | \
254 KVM_GUESTDBG_INJECT_DB | \
255 KVM_GUESTDBG_BLOCKIRQ)
256
257
258 #define PFERR_PRESENT_BIT 0
259 #define PFERR_WRITE_BIT 1
260 #define PFERR_USER_BIT 2
261 #define PFERR_RSVD_BIT 3
262 #define PFERR_FETCH_BIT 4
263 #define PFERR_PK_BIT 5
264 #define PFERR_SGX_BIT 15
265 #define PFERR_GUEST_FINAL_BIT 32
266 #define PFERR_GUEST_PAGE_BIT 33
267 #define PFERR_IMPLICIT_ACCESS_BIT 48
268
269 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT)
270 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT)
271 #define PFERR_USER_MASK BIT(PFERR_USER_BIT)
272 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT)
273 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT)
274 #define PFERR_PK_MASK BIT(PFERR_PK_BIT)
275 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT)
276 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT)
277 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT)
278 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT)
279
280 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \
281 PFERR_WRITE_MASK | \
282 PFERR_PRESENT_MASK)
283
284 /* apic attention bits */
285 #define KVM_APIC_CHECK_VAPIC 0
286 /*
287 * The following bit is set with PV-EOI, unset on EOI.
288 * We detect PV-EOI changes by guest by comparing
289 * this bit with PV-EOI in guest memory.
290 * See the implementation in apic_update_pv_eoi.
291 */
292 #define KVM_APIC_PV_EOI_PENDING 1
293
294 struct kvm_kernel_irq_routing_entry;
295
296 /*
297 * kvm_mmu_page_role tracks the properties of a shadow page (where shadow page
298 * also includes TDP pages) to determine whether or not a page can be used in
299 * the given MMU context. This is a subset of the overall kvm_cpu_role to
300 * minimize the size of kvm_memory_slot.arch.gfn_write_track, i.e. allows
301 * allocating 2 bytes per gfn instead of 4 bytes per gfn.
302 *
303 * Upper-level shadow pages having gptes are tracked for write-protection via
304 * gfn_write_track. As above, gfn_write_track is a 16 bit counter, so KVM must
305 * not create more than 2^16-1 upper-level shadow pages at a single gfn,
306 * otherwise gfn_write_track will overflow and explosions will ensue.
307 *
308 * A unique shadow page (SP) for a gfn is created if and only if an existing SP
309 * cannot be reused. The ability to reuse a SP is tracked by its role, which
310 * incorporates various mode bits and properties of the SP. Roughly speaking,
311 * the number of unique SPs that can theoretically be created is 2^n, where n
312 * is the number of bits that are used to compute the role.
313 *
314 * But, even though there are 19 bits in the mask below, not all combinations
315 * of modes and flags are possible:
316 *
317 * - invalid shadow pages are not accounted, so the bits are effectively 18
318 *
319 * - quadrant will only be used if has_4_byte_gpte=1 (non-PAE paging);
320 * execonly and ad_disabled are only used for nested EPT which has
321 * has_4_byte_gpte=0. Therefore, 2 bits are always unused.
322 *
323 * - the 4 bits of level are effectively limited to the values 2/3/4/5,
324 * as 4k SPs are not tracked (allowed to go unsync). In addition non-PAE
325 * paging has exactly one upper level, making level completely redundant
326 * when has_4_byte_gpte=1.
327 *
328 * - on top of this, smep_andnot_wp and smap_andnot_wp are only set if
329 * cr0_wp=0, therefore these three bits only give rise to 5 possibilities.
330 *
331 * Therefore, the maximum number of possible upper-level shadow pages for a
332 * single gfn is a bit less than 2^13.
333 */
334 union kvm_mmu_page_role {
335 u32 word;
336 struct {
337 unsigned level:4;
338 unsigned has_4_byte_gpte:1;
339 unsigned quadrant:2;
340 unsigned direct:1;
341 unsigned access:3;
342 unsigned invalid:1;
343 unsigned efer_nx:1;
344 unsigned cr0_wp:1;
345 unsigned smep_andnot_wp:1;
346 unsigned smap_andnot_wp:1;
347 unsigned ad_disabled:1;
348 unsigned guest_mode:1;
349 unsigned passthrough:1;
350 unsigned :5;
351
352 /*
353 * This is left at the top of the word so that
354 * kvm_memslots_for_spte_role can extract it with a
355 * simple shift. While there is room, give it a whole
356 * byte so it is also faster to load it from memory.
357 */
358 unsigned smm:8;
359 };
360 };
361
362 /*
363 * kvm_mmu_extended_role complements kvm_mmu_page_role, tracking properties
364 * relevant to the current MMU configuration. When loading CR0, CR4, or EFER,
365 * including on nested transitions, if nothing in the full role changes then
366 * MMU re-configuration can be skipped. @valid bit is set on first usage so we
367 * don't treat all-zero structure as valid data.
368 *
369 * The properties that are tracked in the extended role but not the page role
370 * are for things that either (a) do not affect the validity of the shadow page
371 * or (b) are indirectly reflected in the shadow page's role. For example,
372 * CR4.PKE only affects permission checks for software walks of the guest page
373 * tables (because KVM doesn't support Protection Keys with shadow paging), and
374 * CR0.PG, CR4.PAE, and CR4.PSE are indirectly reflected in role.level.
375 *
376 * Note, SMEP and SMAP are not redundant with sm*p_andnot_wp in the page role.
377 * If CR0.WP=1, KVM can reuse shadow pages for the guest regardless of SMEP and
378 * SMAP, but the MMU's permission checks for software walks need to be SMEP and
379 * SMAP aware regardless of CR0.WP.
380 */
381 union kvm_mmu_extended_role {
382 u32 word;
383 struct {
384 unsigned int valid:1;
385 unsigned int execonly:1;
386 unsigned int cr4_pse:1;
387 unsigned int cr4_pke:1;
388 unsigned int cr4_smap:1;
389 unsigned int cr4_smep:1;
390 unsigned int cr4_la57:1;
391 unsigned int efer_lma:1;
392 };
393 };
394
395 union kvm_cpu_role {
396 u64 as_u64;
397 struct {
398 union kvm_mmu_page_role base;
399 union kvm_mmu_extended_role ext;
400 };
401 };
402
403 struct kvm_rmap_head {
404 unsigned long val;
405 };
406
407 struct kvm_pio_request {
408 unsigned long linear_rip;
409 unsigned long count;
410 int in;
411 int port;
412 int size;
413 };
414
415 #define PT64_ROOT_MAX_LEVEL 5
416
417 struct rsvd_bits_validate {
418 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
419 u64 bad_mt_xwr;
420 };
421
422 struct kvm_mmu_root_info {
423 gpa_t pgd;
424 hpa_t hpa;
425 };
426
427 #define KVM_MMU_ROOT_INFO_INVALID \
428 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE })
429
430 #define KVM_MMU_NUM_PREV_ROOTS 3
431
432 #define KVM_MMU_ROOT_CURRENT BIT(0)
433 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i)
434 #define KVM_MMU_ROOTS_ALL (BIT(1 + KVM_MMU_NUM_PREV_ROOTS) - 1)
435
436 #define KVM_HAVE_MMU_RWLOCK
437
438 struct kvm_mmu_page;
439 struct kvm_page_fault;
440
441 /*
442 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit,
443 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the
444 * current mmu mode.
445 */
446 struct kvm_mmu {
447 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu);
448 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
449 int (*page_fault)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault);
450 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
451 struct x86_exception *fault);
452 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
453 gpa_t gva_or_gpa, u64 access,
454 struct x86_exception *exception);
455 int (*sync_spte)(struct kvm_vcpu *vcpu,
456 struct kvm_mmu_page *sp, int i);
457 struct kvm_mmu_root_info root;
458 union kvm_cpu_role cpu_role;
459 union kvm_mmu_page_role root_role;
460
461 /*
462 * The pkru_mask indicates if protection key checks are needed. It
463 * consists of 16 domains indexed by page fault error code bits [4:1],
464 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
465 * Each domain has 2 bits which are ANDed with AD and WD from PKRU.
466 */
467 u32 pkru_mask;
468
469 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS];
470
471 /*
472 * Bitmap; bit set = permission fault
473 * Byte index: page fault error code [4:1]
474 * Bit index: pte permissions in ACC_* format
475 */
476 u8 permissions[16];
477
478 u64 *pae_root;
479 u64 *pml4_root;
480 u64 *pml5_root;
481
482 /*
483 * check zero bits on shadow page table entries, these
484 * bits include not only hardware reserved bits but also
485 * the bits spte never used.
486 */
487 struct rsvd_bits_validate shadow_zero_check;
488
489 struct rsvd_bits_validate guest_rsvd_check;
490
491 u64 pdptrs[4]; /* pae */
492 };
493
494 enum pmc_type {
495 KVM_PMC_GP = 0,
496 KVM_PMC_FIXED,
497 };
498
499 struct kvm_pmc {
500 enum pmc_type type;
501 u8 idx;
502 bool is_paused;
503 bool intr;
504 /*
505 * Base value of the PMC counter, relative to the *consumed* count in
506 * the associated perf_event. This value includes counter updates from
507 * the perf_event and emulated_count since the last time the counter
508 * was reprogrammed, but it is *not* the current value as seen by the
509 * guest or userspace.
510 *
511 * The count is relative to the associated perf_event so that KVM
512 * doesn't need to reprogram the perf_event every time the guest writes
513 * to the counter.
514 */
515 u64 counter;
516 /*
517 * PMC events triggered by KVM emulation that haven't been fully
518 * processed, i.e. haven't undergone overflow detection.
519 */
520 u64 emulated_counter;
521 u64 eventsel;
522 struct perf_event *perf_event;
523 struct kvm_vcpu *vcpu;
524 /*
525 * only for creating or reusing perf_event,
526 * eventsel value for general purpose counters,
527 * ctrl value for fixed counters.
528 */
529 u64 current_config;
530 };
531
532 /* More counters may conflict with other existing Architectural MSRs */
533 #define KVM_INTEL_PMC_MAX_GENERIC 8
534 #define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
535 #define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
536 #define KVM_PMC_MAX_FIXED 3
537 #define MSR_ARCH_PERFMON_FIXED_CTR_MAX (MSR_ARCH_PERFMON_FIXED_CTR0 + KVM_PMC_MAX_FIXED - 1)
538 #define KVM_AMD_PMC_MAX_GENERIC 6
539 struct kvm_pmu {
540 u8 version;
541 unsigned nr_arch_gp_counters;
542 unsigned nr_arch_fixed_counters;
543 unsigned available_event_types;
544 u64 fixed_ctr_ctrl;
545 u64 fixed_ctr_ctrl_mask;
546 u64 global_ctrl;
547 u64 global_status;
548 u64 counter_bitmask[2];
549 u64 global_ctrl_mask;
550 u64 global_status_mask;
551 u64 reserved_bits;
552 u64 raw_event_mask;
553 struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC];
554 struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED];
555
556 /*
557 * Overlay the bitmap with a 64-bit atomic so that all bits can be
558 * set in a single access, e.g. to reprogram all counters when the PMU
559 * filter changes.
560 */
561 union {
562 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
563 atomic64_t __reprogram_pmi;
564 };
565 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
566 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);
567
568 u64 ds_area;
569 u64 pebs_enable;
570 u64 pebs_enable_mask;
571 u64 pebs_data_cfg;
572 u64 pebs_data_cfg_mask;
573
574 /*
575 * If a guest counter is cross-mapped to host counter with different
576 * index, its PEBS capability will be temporarily disabled.
577 *
578 * The user should make sure that this mask is updated
579 * after disabling interrupts and before perf_guest_get_msrs();
580 */
581 u64 host_cross_mapped_mask;
582
583 /*
584 * The gate to release perf_events not marked in
585 * pmc_in_use only once in a vcpu time slice.
586 */
587 bool need_cleanup;
588
589 /*
590 * The total number of programmed perf_events and it helps to avoid
591 * redundant check before cleanup if guest don't use vPMU at all.
592 */
593 u8 event_count;
594 };
595
596 struct kvm_pmu_ops;
597
598 enum {
599 KVM_DEBUGREG_BP_ENABLED = 1,
600 KVM_DEBUGREG_WONT_EXIT = 2,
601 };
602
603 struct kvm_mtrr_range {
604 u64 base;
605 u64 mask;
606 struct list_head node;
607 };
608
609 struct kvm_mtrr {
610 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR];
611 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION];
612 u64 deftype;
613
614 struct list_head head;
615 };
616
617 /* Hyper-V SynIC timer */
618 struct kvm_vcpu_hv_stimer {
619 struct hrtimer timer;
620 int index;
621 union hv_stimer_config config;
622 u64 count;
623 u64 exp_time;
624 struct hv_message msg;
625 bool msg_pending;
626 };
627
628 /* Hyper-V synthetic interrupt controller (SynIC)*/
629 struct kvm_vcpu_hv_synic {
630 u64 version;
631 u64 control;
632 u64 msg_page;
633 u64 evt_page;
634 atomic64_t sint[HV_SYNIC_SINT_COUNT];
635 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT];
636 DECLARE_BITMAP(auto_eoi_bitmap, 256);
637 DECLARE_BITMAP(vec_bitmap, 256);
638 bool active;
639 bool dont_zero_synic_pages;
640 };
641
642 /* The maximum number of entries on the TLB flush fifo. */
643 #define KVM_HV_TLB_FLUSH_FIFO_SIZE (16)
644 /*
645 * Note: the following 'magic' entry is made up by KVM to avoid putting
646 * anything besides GVA on the TLB flush fifo. It is theoretically possible
647 * to observe a request to flush 4095 PFNs starting from 0xfffffffffffff000
648 * which will look identical. KVM's action to 'flush everything' instead of
649 * flushing these particular addresses is, however, fully legitimate as
650 * flushing more than requested is always OK.
651 */
652 #define KVM_HV_TLB_FLUSHALL_ENTRY ((u64)-1)
653
654 enum hv_tlb_flush_fifos {
655 HV_L1_TLB_FLUSH_FIFO,
656 HV_L2_TLB_FLUSH_FIFO,
657 HV_NR_TLB_FLUSH_FIFOS,
658 };
659
660 struct kvm_vcpu_hv_tlb_flush_fifo {
661 spinlock_t write_lock;
662 DECLARE_KFIFO(entries, u64, KVM_HV_TLB_FLUSH_FIFO_SIZE);
663 };
664
665 /* Hyper-V per vcpu emulation context */
666 struct kvm_vcpu_hv {
667 struct kvm_vcpu *vcpu;
668 u32 vp_index;
669 u64 hv_vapic;
670 s64 runtime_offset;
671 struct kvm_vcpu_hv_synic synic;
672 struct kvm_hyperv_exit exit;
673 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT];
674 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT);
675 bool enforce_cpuid;
676 struct {
677 u32 features_eax; /* HYPERV_CPUID_FEATURES.EAX */
678 u32 features_ebx; /* HYPERV_CPUID_FEATURES.EBX */
679 u32 features_edx; /* HYPERV_CPUID_FEATURES.EDX */
680 u32 enlightenments_eax; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EAX */
681 u32 enlightenments_ebx; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EBX */
682 u32 syndbg_cap_eax; /* HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX */
683 u32 nested_eax; /* HYPERV_CPUID_NESTED_FEATURES.EAX */
684 u32 nested_ebx; /* HYPERV_CPUID_NESTED_FEATURES.EBX */
685 } cpuid_cache;
686
687 struct kvm_vcpu_hv_tlb_flush_fifo tlb_flush_fifo[HV_NR_TLB_FLUSH_FIFOS];
688
689 /* Preallocated buffer for handling hypercalls passing sparse vCPU set */
690 u64 sparse_banks[HV_MAX_SPARSE_VCPU_BANKS];
691
692 struct hv_vp_assist_page vp_assist_page;
693
694 struct {
695 u64 pa_page_gpa;
696 u64 vm_id;
697 u32 vp_id;
698 } nested;
699 };
700
701 struct kvm_hypervisor_cpuid {
702 u32 base;
703 u32 limit;
704 };
705
706 #ifdef CONFIG_KVM_XEN
707 /* Xen HVM per vcpu emulation context */
708 struct kvm_vcpu_xen {
709 u64 hypercall_rip;
710 u32 current_runstate;
711 u8 upcall_vector;
712 struct gfn_to_pfn_cache vcpu_info_cache;
713 struct gfn_to_pfn_cache vcpu_time_info_cache;
714 struct gfn_to_pfn_cache runstate_cache;
715 struct gfn_to_pfn_cache runstate2_cache;
716 u64 last_steal;
717 u64 runstate_entry_time;
718 u64 runstate_times[4];
719 unsigned long evtchn_pending_sel;
720 u32 vcpu_id; /* The Xen / ACPI vCPU ID */
721 u32 timer_virq;
722 u64 timer_expires; /* In guest epoch */
723 atomic_t timer_pending;
724 struct hrtimer timer;
725 int poll_evtchn;
726 struct timer_list poll_timer;
727 struct kvm_hypervisor_cpuid cpuid;
728 };
729 #endif
730
731 struct kvm_queued_exception {
732 bool pending;
733 bool injected;
734 bool has_error_code;
735 u8 vector;
736 u32 error_code;
737 unsigned long payload;
738 bool has_payload;
739 };
740
741 struct kvm_vcpu_arch {
742 /*
743 * rip and regs accesses must go through
744 * kvm_{register,rip}_{read,write} functions.
745 */
746 unsigned long regs[NR_VCPU_REGS];
747 u32 regs_avail;
748 u32 regs_dirty;
749
750 unsigned long cr0;
751 unsigned long cr0_guest_owned_bits;
752 unsigned long cr2;
753 unsigned long cr3;
754 unsigned long cr4;
755 unsigned long cr4_guest_owned_bits;
756 unsigned long cr4_guest_rsvd_bits;
757 unsigned long cr8;
758 u32 host_pkru;
759 u32 pkru;
760 u32 hflags;
761 u64 efer;
762 u64 apic_base;
763 struct kvm_lapic *apic; /* kernel irqchip context */
764 bool load_eoi_exitmap_pending;
765 DECLARE_BITMAP(ioapic_handled_vectors, 256);
766 unsigned long apic_attention;
767 int32_t apic_arb_prio;
768 int mp_state;
769 u64 ia32_misc_enable_msr;
770 u64 smbase;
771 u64 smi_count;
772 bool at_instruction_boundary;
773 bool tpr_access_reporting;
774 bool xfd_no_write_intercept;
775 u64 ia32_xss;
776 u64 microcode_version;
777 u64 arch_capabilities;
778 u64 perf_capabilities;
779
780 /*
781 * Paging state of the vcpu
782 *
783 * If the vcpu runs in guest mode with two level paging this still saves
784 * the paging mode of the l1 guest. This context is always used to
785 * handle faults.
786 */
787 struct kvm_mmu *mmu;
788
789 /* Non-nested MMU for L1 */
790 struct kvm_mmu root_mmu;
791
792 /* L1 MMU when running nested */
793 struct kvm_mmu guest_mmu;
794
795 /*
796 * Paging state of an L2 guest (used for nested npt)
797 *
798 * This context will save all necessary information to walk page tables
799 * of an L2 guest. This context is only initialized for page table
800 * walking and not for faulting since we never handle l2 page faults on
801 * the host.
802 */
803 struct kvm_mmu nested_mmu;
804
805 /*
806 * Pointer to the mmu context currently used for
807 * gva_to_gpa translations.
808 */
809 struct kvm_mmu *walk_mmu;
810
811 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
812 struct kvm_mmu_memory_cache mmu_shadow_page_cache;
813 struct kvm_mmu_memory_cache mmu_shadowed_info_cache;
814 struct kvm_mmu_memory_cache mmu_page_header_cache;
815
816 /*
817 * QEMU userspace and the guest each have their own FPU state.
818 * In vcpu_run, we switch between the user and guest FPU contexts.
819 * While running a VCPU, the VCPU thread will have the guest FPU
820 * context.
821 *
822 * Note that while the PKRU state lives inside the fpu registers,
823 * it is switched out separately at VMENTER and VMEXIT time. The
824 * "guest_fpstate" state here contains the guest FPU context, with the
825 * host PRKU bits.
826 */
827 struct fpu_guest guest_fpu;
828
829 u64 xcr0;
830 u64 guest_supported_xcr0;
831
832 struct kvm_pio_request pio;
833 void *pio_data;
834 void *sev_pio_data;
835 unsigned sev_pio_count;
836
837 u8 event_exit_inst_len;
838
839 bool exception_from_userspace;
840
841 /* Exceptions to be injected to the guest. */
842 struct kvm_queued_exception exception;
843 /* Exception VM-Exits to be synthesized to L1. */
844 struct kvm_queued_exception exception_vmexit;
845
846 struct kvm_queued_interrupt {
847 bool injected;
848 bool soft;
849 u8 nr;
850 } interrupt;
851
852 int halt_request; /* real mode on Intel only */
853
854 int cpuid_nent;
855 struct kvm_cpuid_entry2 *cpuid_entries;
856 struct kvm_hypervisor_cpuid kvm_cpuid;
857
858 /*
859 * FIXME: Drop this macro and use KVM_NR_GOVERNED_FEATURES directly
860 * when "struct kvm_vcpu_arch" is no longer defined in an
861 * arch/x86/include/asm header. The max is mostly arbitrary, i.e.
862 * can be increased as necessary.
863 */
864 #define KVM_MAX_NR_GOVERNED_FEATURES BITS_PER_LONG
865
866 /*
867 * Track whether or not the guest is allowed to use features that are
868 * governed by KVM, where "governed" means KVM needs to manage state
869 * and/or explicitly enable the feature in hardware. Typically, but
870 * not always, governed features can be used by the guest if and only
871 * if both KVM and userspace want to expose the feature to the guest.
872 */
873 struct {
874 DECLARE_BITMAP(enabled, KVM_MAX_NR_GOVERNED_FEATURES);
875 } governed_features;
876
877 u64 reserved_gpa_bits;
878 int maxphyaddr;
879
880 /* emulate context */
881
882 struct x86_emulate_ctxt *emulate_ctxt;
883 bool emulate_regs_need_sync_to_vcpu;
884 bool emulate_regs_need_sync_from_vcpu;
885 int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
886
887 gpa_t time;
888 struct pvclock_vcpu_time_info hv_clock;
889 unsigned int hw_tsc_khz;
890 struct gfn_to_pfn_cache pv_time;
891 /* set guest stopped flag in pvclock flags field */
892 bool pvclock_set_guest_stopped_request;
893
894 struct {
895 u8 preempted;
896 u64 msr_val;
897 u64 last_steal;
898 struct gfn_to_hva_cache cache;
899 } st;
900
901 u64 l1_tsc_offset;
902 u64 tsc_offset; /* current tsc offset */
903 u64 last_guest_tsc;
904 u64 last_host_tsc;
905 u64 tsc_offset_adjustment;
906 u64 this_tsc_nsec;
907 u64 this_tsc_write;
908 u64 this_tsc_generation;
909 bool tsc_catchup;
910 bool tsc_always_catchup;
911 s8 virtual_tsc_shift;
912 u32 virtual_tsc_mult;
913 u32 virtual_tsc_khz;
914 s64 ia32_tsc_adjust_msr;
915 u64 msr_ia32_power_ctl;
916 u64 l1_tsc_scaling_ratio;
917 u64 tsc_scaling_ratio; /* current scaling ratio */
918
919 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
920 /* Number of NMIs pending injection, not including hardware vNMIs. */
921 unsigned int nmi_pending;
922 bool nmi_injected; /* Trying to inject an NMI this entry */
923 bool smi_pending; /* SMI queued after currently running handler */
924 u8 handling_intr_from_guest;
925
926 struct kvm_mtrr mtrr_state;
927 u64 pat;
928
929 unsigned switch_db_regs;
930 unsigned long db[KVM_NR_DB_REGS];
931 unsigned long dr6;
932 unsigned long dr7;
933 unsigned long eff_db[KVM_NR_DB_REGS];
934 unsigned long guest_debug_dr7;
935 u64 msr_platform_info;
936 u64 msr_misc_features_enables;
937
938 u64 mcg_cap;
939 u64 mcg_status;
940 u64 mcg_ctl;
941 u64 mcg_ext_ctl;
942 u64 *mce_banks;
943 u64 *mci_ctl2_banks;
944
945 /* Cache MMIO info */
946 u64 mmio_gva;
947 unsigned mmio_access;
948 gfn_t mmio_gfn;
949 u64 mmio_gen;
950
951 struct kvm_pmu pmu;
952
953 /* used for guest single stepping over the given code position */
954 unsigned long singlestep_rip;
955
956 #ifdef CONFIG_KVM_HYPERV
957 bool hyperv_enabled;
958 struct kvm_vcpu_hv *hyperv;
959 #endif
960 #ifdef CONFIG_KVM_XEN
961 struct kvm_vcpu_xen xen;
962 #endif
963 cpumask_var_t wbinvd_dirty_mask;
964
965 unsigned long last_retry_eip;
966 unsigned long last_retry_addr;
967
968 struct {
969 bool halted;
970 gfn_t gfns[ASYNC_PF_PER_VCPU];
971 struct gfn_to_hva_cache data;
972 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */
973 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */
974 u16 vec;
975 u32 id;
976 bool send_user_only;
977 u32 host_apf_flags;
978 bool delivery_as_pf_vmexit;
979 bool pageready_pending;
980 } apf;
981
982 /* OSVW MSRs (AMD only) */
983 struct {
984 u64 length;
985 u64 status;
986 } osvw;
987
988 struct {
989 u64 msr_val;
990 struct gfn_to_hva_cache data;
991 } pv_eoi;
992
993 u64 msr_kvm_poll_control;
994
995 /* set at EPT violation at this point */
996 unsigned long exit_qualification;
997
998 /* pv related host specific info */
999 struct {
1000 bool pv_unhalted;
1001 } pv;
1002
1003 int pending_ioapic_eoi;
1004 int pending_external_vector;
1005
1006 /* be preempted when it's in kernel-mode(cpl=0) */
1007 bool preempted_in_kernel;
1008
1009 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */
1010 bool l1tf_flush_l1d;
1011
1012 /* Host CPU on which VM-entry was most recently attempted */
1013 int last_vmentry_cpu;
1014
1015 /* AMD MSRC001_0015 Hardware Configuration */
1016 u64 msr_hwcr;
1017
1018 /* pv related cpuid info */
1019 struct {
1020 /*
1021 * value of the eax register in the KVM_CPUID_FEATURES CPUID
1022 * leaf.
1023 */
1024 u32 features;
1025
1026 /*
1027 * indicates whether pv emulation should be disabled if features
1028 * are not present in the guest's cpuid
1029 */
1030 bool enforce;
1031 } pv_cpuid;
1032
1033 /* Protected Guests */
1034 bool guest_state_protected;
1035
1036 /*
1037 * Set when PDPTS were loaded directly by the userspace without
1038 * reading the guest memory
1039 */
1040 bool pdptrs_from_userspace;
1041
1042 #if IS_ENABLED(CONFIG_HYPERV)
1043 hpa_t hv_root_tdp;
1044 #endif
1045 };
1046
1047 struct kvm_lpage_info {
1048 int disallow_lpage;
1049 };
1050
1051 struct kvm_arch_memory_slot {
1052 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
1053 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
1054 unsigned short *gfn_write_track;
1055 };
1056
1057 /*
1058 * Track the mode of the optimized logical map, as the rules for decoding the
1059 * destination vary per mode. Enabling the optimized logical map requires all
1060 * software-enabled local APIs to be in the same mode, each addressable APIC to
1061 * be mapped to only one MDA, and each MDA to map to at most one APIC.
1062 */
1063 enum kvm_apic_logical_mode {
1064 /* All local APICs are software disabled. */
1065 KVM_APIC_MODE_SW_DISABLED,
1066 /* All software enabled local APICs in xAPIC cluster addressing mode. */
1067 KVM_APIC_MODE_XAPIC_CLUSTER,
1068 /* All software enabled local APICs in xAPIC flat addressing mode. */
1069 KVM_APIC_MODE_XAPIC_FLAT,
1070 /* All software enabled local APICs in x2APIC mode. */
1071 KVM_APIC_MODE_X2APIC,
1072 /*
1073 * Optimized map disabled, e.g. not all local APICs in the same logical
1074 * mode, same logical ID assigned to multiple APICs, etc.
1075 */
1076 KVM_APIC_MODE_MAP_DISABLED,
1077 };
1078
1079 struct kvm_apic_map {
1080 struct rcu_head rcu;
1081 enum kvm_apic_logical_mode logical_mode;
1082 u32 max_apic_id;
1083 union {
1084 struct kvm_lapic *xapic_flat_map[8];
1085 struct kvm_lapic *xapic_cluster_map[16][4];
1086 };
1087 struct kvm_lapic *phys_map[];
1088 };
1089
1090 /* Hyper-V synthetic debugger (SynDbg)*/
1091 struct kvm_hv_syndbg {
1092 struct {
1093 u64 control;
1094 u64 status;
1095 u64 send_page;
1096 u64 recv_page;
1097 u64 pending_page;
1098 } control;
1099 u64 options;
1100 };
1101
1102 /* Current state of Hyper-V TSC page clocksource */
1103 enum hv_tsc_page_status {
1104 /* TSC page was not set up or disabled */
1105 HV_TSC_PAGE_UNSET = 0,
1106 /* TSC page MSR was written by the guest, update pending */
1107 HV_TSC_PAGE_GUEST_CHANGED,
1108 /* TSC page update was triggered from the host side */
1109 HV_TSC_PAGE_HOST_CHANGED,
1110 /* TSC page was properly set up and is currently active */
1111 HV_TSC_PAGE_SET,
1112 /* TSC page was set up with an inaccessible GPA */
1113 HV_TSC_PAGE_BROKEN,
1114 };
1115
1116 #ifdef CONFIG_KVM_HYPERV
1117 /* Hyper-V emulation context */
1118 struct kvm_hv {
1119 struct mutex hv_lock;
1120 u64 hv_guest_os_id;
1121 u64 hv_hypercall;
1122 u64 hv_tsc_page;
1123 enum hv_tsc_page_status hv_tsc_page_status;
1124
1125 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */
1126 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS];
1127 u64 hv_crash_ctl;
1128
1129 struct ms_hyperv_tsc_page tsc_ref;
1130
1131 struct idr conn_to_evt;
1132
1133 u64 hv_reenlightenment_control;
1134 u64 hv_tsc_emulation_control;
1135 u64 hv_tsc_emulation_status;
1136 u64 hv_invtsc_control;
1137
1138 /* How many vCPUs have VP index != vCPU index */
1139 atomic_t num_mismatched_vp_indexes;
1140
1141 /*
1142 * How many SynICs use 'AutoEOI' feature
1143 * (protected by arch.apicv_update_lock)
1144 */
1145 unsigned int synic_auto_eoi_used;
1146
1147 struct kvm_hv_syndbg hv_syndbg;
1148
1149 bool xsaves_xsavec_checked;
1150 };
1151 #endif
1152
1153 struct msr_bitmap_range {
1154 u32 flags;
1155 u32 nmsrs;
1156 u32 base;
1157 unsigned long *bitmap;
1158 };
1159
1160 #ifdef CONFIG_KVM_XEN
1161 /* Xen emulation context */
1162 struct kvm_xen {
1163 struct mutex xen_lock;
1164 u32 xen_version;
1165 bool long_mode;
1166 bool runstate_update_flag;
1167 u8 upcall_vector;
1168 struct gfn_to_pfn_cache shinfo_cache;
1169 struct idr evtchn_ports;
1170 unsigned long poll_mask[BITS_TO_LONGS(KVM_MAX_VCPUS)];
1171 };
1172 #endif
1173
1174 enum kvm_irqchip_mode {
1175 KVM_IRQCHIP_NONE,
1176 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */
1177 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */
1178 };
1179
1180 struct kvm_x86_msr_filter {
1181 u8 count;
1182 bool default_allow:1;
1183 struct msr_bitmap_range ranges[16];
1184 };
1185
1186 struct kvm_x86_pmu_event_filter {
1187 __u32 action;
1188 __u32 nevents;
1189 __u32 fixed_counter_bitmap;
1190 __u32 flags;
1191 __u32 nr_includes;
1192 __u32 nr_excludes;
1193 __u64 *includes;
1194 __u64 *excludes;
1195 __u64 events[];
1196 };
1197
1198 enum kvm_apicv_inhibit {
1199
1200 /********************************************************************/
1201 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
1202 /********************************************************************/
1203
1204 /*
1205 * APIC acceleration is disabled by a module parameter
1206 * and/or not supported in hardware.
1207 */
1208 APICV_INHIBIT_REASON_DISABLE,
1209
1210 /*
1211 * APIC acceleration is inhibited because AutoEOI feature is
1212 * being used by a HyperV guest.
1213 */
1214 APICV_INHIBIT_REASON_HYPERV,
1215
1216 /*
1217 * APIC acceleration is inhibited because the userspace didn't yet
1218 * enable the kernel/split irqchip.
1219 */
1220 APICV_INHIBIT_REASON_ABSENT,
1221
1222 /* APIC acceleration is inhibited because KVM_GUESTDBG_BLOCKIRQ
1223 * (out of band, debug measure of blocking all interrupts on this vCPU)
1224 * was enabled, to avoid AVIC/APICv bypassing it.
1225 */
1226 APICV_INHIBIT_REASON_BLOCKIRQ,
1227
1228 /*
1229 * APICv is disabled because not all vCPUs have a 1:1 mapping between
1230 * APIC ID and vCPU, _and_ KVM is not applying its x2APIC hotplug hack.
1231 */
1232 APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED,
1233
1234 /*
1235 * For simplicity, the APIC acceleration is inhibited
1236 * first time either APIC ID or APIC base are changed by the guest
1237 * from their reset values.
1238 */
1239 APICV_INHIBIT_REASON_APIC_ID_MODIFIED,
1240 APICV_INHIBIT_REASON_APIC_BASE_MODIFIED,
1241
1242 /******************************************************/
1243 /* INHIBITs that are relevant only to the AMD's AVIC. */
1244 /******************************************************/
1245
1246 /*
1247 * AVIC is inhibited on a vCPU because it runs a nested guest.
1248 *
1249 * This is needed because unlike APICv, the peers of this vCPU
1250 * cannot use the doorbell mechanism to signal interrupts via AVIC when
1251 * a vCPU runs nested.
1252 */
1253 APICV_INHIBIT_REASON_NESTED,
1254
1255 /*
1256 * On SVM, the wait for the IRQ window is implemented with pending vIRQ,
1257 * which cannot be injected when the AVIC is enabled, thus AVIC
1258 * is inhibited while KVM waits for IRQ window.
1259 */
1260 APICV_INHIBIT_REASON_IRQWIN,
1261
1262 /*
1263 * PIT (i8254) 're-inject' mode, relies on EOI intercept,
1264 * which AVIC doesn't support for edge triggered interrupts.
1265 */
1266 APICV_INHIBIT_REASON_PIT_REINJ,
1267
1268 /*
1269 * AVIC is disabled because SEV doesn't support it.
1270 */
1271 APICV_INHIBIT_REASON_SEV,
1272
1273 /*
1274 * AVIC is disabled because not all vCPUs with a valid LDR have a 1:1
1275 * mapping between logical ID and vCPU.
1276 */
1277 APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED,
1278 };
1279
1280 struct kvm_arch {
1281 unsigned long vm_type;
1282 unsigned long n_used_mmu_pages;
1283 unsigned long n_requested_mmu_pages;
1284 unsigned long n_max_mmu_pages;
1285 unsigned int indirect_shadow_pages;
1286 u8 mmu_valid_gen;
1287 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
1288 struct list_head active_mmu_pages;
1289 struct list_head zapped_obsolete_pages;
1290 /*
1291 * A list of kvm_mmu_page structs that, if zapped, could possibly be
1292 * replaced by an NX huge page. A shadow page is on this list if its
1293 * existence disallows an NX huge page (nx_huge_page_disallowed is set)
1294 * and there are no other conditions that prevent a huge page, e.g.
1295 * the backing host page is huge, dirtly logging is not enabled for its
1296 * memslot, etc... Note, zapping shadow pages on this list doesn't
1297 * guarantee an NX huge page will be created in its stead, e.g. if the
1298 * guest attempts to execute from the region then KVM obviously can't
1299 * create an NX huge page (without hanging the guest).
1300 */
1301 struct list_head possible_nx_huge_pages;
1302 #ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
1303 struct kvm_page_track_notifier_head track_notifier_head;
1304 #endif
1305 /*
1306 * Protects marking pages unsync during page faults, as TDP MMU page
1307 * faults only take mmu_lock for read. For simplicity, the unsync
1308 * pages lock is always taken when marking pages unsync regardless of
1309 * whether mmu_lock is held for read or write.
1310 */
1311 spinlock_t mmu_unsync_pages_lock;
1312
1313 struct iommu_domain *iommu_domain;
1314 bool iommu_noncoherent;
1315 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA
1316 atomic_t noncoherent_dma_count;
1317 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE
1318 atomic_t assigned_device_count;
1319 struct kvm_pic *vpic;
1320 struct kvm_ioapic *vioapic;
1321 struct kvm_pit *vpit;
1322 atomic_t vapics_in_nmi_mode;
1323 struct mutex apic_map_lock;
1324 struct kvm_apic_map __rcu *apic_map;
1325 atomic_t apic_map_dirty;
1326
1327 bool apic_access_memslot_enabled;
1328 bool apic_access_memslot_inhibited;
1329
1330 /* Protects apicv_inhibit_reasons */
1331 struct rw_semaphore apicv_update_lock;
1332 unsigned long apicv_inhibit_reasons;
1333
1334 gpa_t wall_clock;
1335
1336 bool mwait_in_guest;
1337 bool hlt_in_guest;
1338 bool pause_in_guest;
1339 bool cstate_in_guest;
1340
1341 unsigned long irq_sources_bitmap;
1342 s64 kvmclock_offset;
1343
1344 /*
1345 * This also protects nr_vcpus_matched_tsc which is read from a
1346 * preemption-disabled region, so it must be a raw spinlock.
1347 */
1348 raw_spinlock_t tsc_write_lock;
1349 u64 last_tsc_nsec;
1350 u64 last_tsc_write;
1351 u32 last_tsc_khz;
1352 u64 last_tsc_offset;
1353 u64 cur_tsc_nsec;
1354 u64 cur_tsc_write;
1355 u64 cur_tsc_offset;
1356 u64 cur_tsc_generation;
1357 int nr_vcpus_matched_tsc;
1358
1359 u32 default_tsc_khz;
1360 bool user_set_tsc;
1361
1362 seqcount_raw_spinlock_t pvclock_sc;
1363 bool use_master_clock;
1364 u64 master_kernel_ns;
1365 u64 master_cycle_now;
1366 struct delayed_work kvmclock_update_work;
1367 struct delayed_work kvmclock_sync_work;
1368
1369 struct kvm_xen_hvm_config xen_hvm_config;
1370
1371 /* reads protected by irq_srcu, writes by irq_lock */
1372 struct hlist_head mask_notifier_list;
1373
1374 #ifdef CONFIG_KVM_HYPERV
1375 struct kvm_hv hyperv;
1376 #endif
1377
1378 #ifdef CONFIG_KVM_XEN
1379 struct kvm_xen xen;
1380 #endif
1381
1382 bool backwards_tsc_observed;
1383 bool boot_vcpu_runs_old_kvmclock;
1384 u32 bsp_vcpu_id;
1385
1386 u64 disabled_quirks;
1387
1388 enum kvm_irqchip_mode irqchip_mode;
1389 u8 nr_reserved_ioapic_pins;
1390
1391 bool disabled_lapic_found;
1392
1393 bool x2apic_format;
1394 bool x2apic_broadcast_quirk_disabled;
1395
1396 bool guest_can_read_msr_platform_info;
1397 bool exception_payload_enabled;
1398
1399 bool triple_fault_event;
1400
1401 bool bus_lock_detection_enabled;
1402 bool enable_pmu;
1403
1404 u32 notify_window;
1405 u32 notify_vmexit_flags;
1406 /*
1407 * If exit_on_emulation_error is set, and the in-kernel instruction
1408 * emulator fails to emulate an instruction, allow userspace
1409 * the opportunity to look at it.
1410 */
1411 bool exit_on_emulation_error;
1412
1413 /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */
1414 u32 user_space_msr_mask;
1415 struct kvm_x86_msr_filter __rcu *msr_filter;
1416
1417 u32 hypercall_exit_enabled;
1418
1419 /* Guest can access the SGX PROVISIONKEY. */
1420 bool sgx_provisioning_allowed;
1421
1422 struct kvm_x86_pmu_event_filter __rcu *pmu_event_filter;
1423 struct task_struct *nx_huge_page_recovery_thread;
1424
1425 #ifdef CONFIG_X86_64
1426 /* The number of TDP MMU pages across all roots. */
1427 atomic64_t tdp_mmu_pages;
1428
1429 /*
1430 * List of struct kvm_mmu_pages being used as roots.
1431 * All struct kvm_mmu_pages in the list should have
1432 * tdp_mmu_page set.
1433 *
1434 * For reads, this list is protected by:
1435 * the MMU lock in read mode + RCU or
1436 * the MMU lock in write mode
1437 *
1438 * For writes, this list is protected by tdp_mmu_pages_lock; see
1439 * below for the details.
1440 *
1441 * Roots will remain in the list until their tdp_mmu_root_count
1442 * drops to zero, at which point the thread that decremented the
1443 * count to zero should removed the root from the list and clean
1444 * it up, freeing the root after an RCU grace period.
1445 */
1446 struct list_head tdp_mmu_roots;
1447
1448 /*
1449 * Protects accesses to the following fields when the MMU lock
1450 * is held in read mode:
1451 * - tdp_mmu_roots (above)
1452 * - the link field of kvm_mmu_page structs used by the TDP MMU
1453 * - possible_nx_huge_pages;
1454 * - the possible_nx_huge_page_link field of kvm_mmu_page structs used
1455 * by the TDP MMU
1456 * Because the lock is only taken within the MMU lock, strictly
1457 * speaking it is redundant to acquire this lock when the thread
1458 * holds the MMU lock in write mode. However it often simplifies
1459 * the code to do so.
1460 */
1461 spinlock_t tdp_mmu_pages_lock;
1462 #endif /* CONFIG_X86_64 */
1463
1464 /*
1465 * If set, at least one shadow root has been allocated. This flag
1466 * is used as one input when determining whether certain memslot
1467 * related allocations are necessary.
1468 */
1469 bool shadow_root_allocated;
1470
1471 #if IS_ENABLED(CONFIG_HYPERV)
1472 hpa_t hv_root_tdp;
1473 spinlock_t hv_root_tdp_lock;
1474 struct hv_partition_assist_pg *hv_pa_pg;
1475 #endif
1476 /*
1477 * VM-scope maximum vCPU ID. Used to determine the size of structures
1478 * that increase along with the maximum vCPU ID, in which case, using
1479 * the global KVM_MAX_VCPU_IDS may lead to significant memory waste.
1480 */
1481 u32 max_vcpu_ids;
1482
1483 bool disable_nx_huge_pages;
1484
1485 /*
1486 * Memory caches used to allocate shadow pages when performing eager
1487 * page splitting. No need for a shadowed_info_cache since eager page
1488 * splitting only allocates direct shadow pages.
1489 *
1490 * Protected by kvm->slots_lock.
1491 */
1492 struct kvm_mmu_memory_cache split_shadow_page_cache;
1493 struct kvm_mmu_memory_cache split_page_header_cache;
1494
1495 /*
1496 * Memory cache used to allocate pte_list_desc structs while splitting
1497 * huge pages. In the worst case, to split one huge page, 512
1498 * pte_list_desc structs are needed to add each lower level leaf sptep
1499 * to the rmap plus 1 to extend the parent_ptes rmap of the lower level
1500 * page table.
1501 *
1502 * Protected by kvm->slots_lock.
1503 */
1504 #define SPLIT_DESC_CACHE_MIN_NR_OBJECTS (SPTE_ENT_PER_PAGE + 1)
1505 struct kvm_mmu_memory_cache split_desc_cache;
1506 };
1507
1508 struct kvm_vm_stat {
1509 struct kvm_vm_stat_generic generic;
1510 u64 mmu_shadow_zapped;
1511 u64 mmu_pte_write;
1512 u64 mmu_pde_zapped;
1513 u64 mmu_flooded;
1514 u64 mmu_recycled;
1515 u64 mmu_cache_miss;
1516 u64 mmu_unsync;
1517 union {
1518 struct {
1519 atomic64_t pages_4k;
1520 atomic64_t pages_2m;
1521 atomic64_t pages_1g;
1522 };
1523 atomic64_t pages[KVM_NR_PAGE_SIZES];
1524 };
1525 u64 nx_lpage_splits;
1526 u64 max_mmu_page_hash_collisions;
1527 u64 max_mmu_rmap_size;
1528 };
1529
1530 struct kvm_vcpu_stat {
1531 struct kvm_vcpu_stat_generic generic;
1532 u64 pf_taken;
1533 u64 pf_fixed;
1534 u64 pf_emulate;
1535 u64 pf_spurious;
1536 u64 pf_fast;
1537 u64 pf_mmio_spte_created;
1538 u64 pf_guest;
1539 u64 tlb_flush;
1540 u64 invlpg;
1541
1542 u64 exits;
1543 u64 io_exits;
1544 u64 mmio_exits;
1545 u64 signal_exits;
1546 u64 irq_window_exits;
1547 u64 nmi_window_exits;
1548 u64 l1d_flush;
1549 u64 halt_exits;
1550 u64 request_irq_exits;
1551 u64 irq_exits;
1552 u64 host_state_reload;
1553 u64 fpu_reload;
1554 u64 insn_emulation;
1555 u64 insn_emulation_fail;
1556 u64 hypercalls;
1557 u64 irq_injections;
1558 u64 nmi_injections;
1559 u64 req_event;
1560 u64 nested_run;
1561 u64 directed_yield_attempted;
1562 u64 directed_yield_successful;
1563 u64 preemption_reported;
1564 u64 preemption_other;
1565 u64 guest_mode;
1566 u64 notify_window_exits;
1567 };
1568
1569 struct x86_instruction_info;
1570
1571 struct msr_data {
1572 bool host_initiated;
1573 u32 index;
1574 u64 data;
1575 };
1576
1577 struct kvm_lapic_irq {
1578 u32 vector;
1579 u16 delivery_mode;
1580 u16 dest_mode;
1581 bool level;
1582 u16 trig_mode;
1583 u32 shorthand;
1584 u32 dest_id;
1585 bool msi_redir_hint;
1586 };
1587
kvm_lapic_irq_dest_mode(bool dest_mode_logical)1588 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical)
1589 {
1590 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
1591 }
1592
1593 struct kvm_x86_ops {
1594 const char *name;
1595
1596 int (*check_processor_compatibility)(void);
1597
1598 int (*hardware_enable)(void);
1599 void (*hardware_disable)(void);
1600 void (*hardware_unsetup)(void);
1601 bool (*has_emulated_msr)(struct kvm *kvm, u32 index);
1602 void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu);
1603
1604 unsigned int vm_size;
1605 int (*vm_init)(struct kvm *kvm);
1606 void (*vm_destroy)(struct kvm *kvm);
1607
1608 /* Create, but do not attach this VCPU */
1609 int (*vcpu_precreate)(struct kvm *kvm);
1610 int (*vcpu_create)(struct kvm_vcpu *vcpu);
1611 void (*vcpu_free)(struct kvm_vcpu *vcpu);
1612 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
1613
1614 void (*prepare_switch_to_guest)(struct kvm_vcpu *vcpu);
1615 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
1616 void (*vcpu_put)(struct kvm_vcpu *vcpu);
1617
1618 void (*update_exception_bitmap)(struct kvm_vcpu *vcpu);
1619 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1620 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1621 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
1622 void (*get_segment)(struct kvm_vcpu *vcpu,
1623 struct kvm_segment *var, int seg);
1624 int (*get_cpl)(struct kvm_vcpu *vcpu);
1625 void (*set_segment)(struct kvm_vcpu *vcpu,
1626 struct kvm_segment *var, int seg);
1627 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
1628 bool (*is_valid_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
1629 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
1630 void (*post_set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
1631 bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
1632 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
1633 int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
1634 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1635 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1636 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1637 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1638 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
1639 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
1640 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
1641 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
1642 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
1643 bool (*get_if_flag)(struct kvm_vcpu *vcpu);
1644
1645 void (*flush_tlb_all)(struct kvm_vcpu *vcpu);
1646 void (*flush_tlb_current)(struct kvm_vcpu *vcpu);
1647 #if IS_ENABLED(CONFIG_HYPERV)
1648 int (*flush_remote_tlbs)(struct kvm *kvm);
1649 int (*flush_remote_tlbs_range)(struct kvm *kvm, gfn_t gfn,
1650 gfn_t nr_pages);
1651 #endif
1652
1653 /*
1654 * Flush any TLB entries associated with the given GVA.
1655 * Does not need to flush GPA->HPA mappings.
1656 * Can potentially get non-canonical addresses through INVLPGs, which
1657 * the implementation may choose to ignore if appropriate.
1658 */
1659 void (*flush_tlb_gva)(struct kvm_vcpu *vcpu, gva_t addr);
1660
1661 /*
1662 * Flush any TLB entries created by the guest. Like tlb_flush_gva(),
1663 * does not need to flush GPA->HPA mappings.
1664 */
1665 void (*flush_tlb_guest)(struct kvm_vcpu *vcpu);
1666
1667 int (*vcpu_pre_run)(struct kvm_vcpu *vcpu);
1668 enum exit_fastpath_completion (*vcpu_run)(struct kvm_vcpu *vcpu);
1669 int (*handle_exit)(struct kvm_vcpu *vcpu,
1670 enum exit_fastpath_completion exit_fastpath);
1671 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
1672 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu);
1673 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
1674 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
1675 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
1676 unsigned char *hypercall_addr);
1677 void (*inject_irq)(struct kvm_vcpu *vcpu, bool reinjected);
1678 void (*inject_nmi)(struct kvm_vcpu *vcpu);
1679 void (*inject_exception)(struct kvm_vcpu *vcpu);
1680 void (*cancel_injection)(struct kvm_vcpu *vcpu);
1681 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1682 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1683 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
1684 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
1685 /* Whether or not a virtual NMI is pending in hardware. */
1686 bool (*is_vnmi_pending)(struct kvm_vcpu *vcpu);
1687 /*
1688 * Attempt to pend a virtual NMI in hardware. Returns %true on success
1689 * to allow using static_call_ret0 as the fallback.
1690 */
1691 bool (*set_vnmi_pending)(struct kvm_vcpu *vcpu);
1692 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
1693 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
1694 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
1695 bool (*check_apicv_inhibit_reasons)(enum kvm_apicv_inhibit reason);
1696 const unsigned long required_apicv_inhibits;
1697 bool allow_apicv_in_x2apic_without_x2apic_virtualization;
1698 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
1699 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
1700 void (*hwapic_isr_update)(int isr);
1701 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu);
1702 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
1703 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
1704 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu);
1705 void (*deliver_interrupt)(struct kvm_lapic *apic, int delivery_mode,
1706 int trig_mode, int vector);
1707 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
1708 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
1709 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);
1710 u8 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
1711
1712 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa,
1713 int root_level);
1714
1715 bool (*has_wbinvd_exit)(void);
1716
1717 u64 (*get_l2_tsc_offset)(struct kvm_vcpu *vcpu);
1718 u64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *vcpu);
1719 void (*write_tsc_offset)(struct kvm_vcpu *vcpu);
1720 void (*write_tsc_multiplier)(struct kvm_vcpu *vcpu);
1721
1722 /*
1723 * Retrieve somewhat arbitrary exit information. Intended to
1724 * be used only from within tracepoints or error paths.
1725 */
1726 void (*get_exit_info)(struct kvm_vcpu *vcpu, u32 *reason,
1727 u64 *info1, u64 *info2,
1728 u32 *exit_int_info, u32 *exit_int_info_err_code);
1729
1730 int (*check_intercept)(struct kvm_vcpu *vcpu,
1731 struct x86_instruction_info *info,
1732 enum x86_intercept_stage stage,
1733 struct x86_exception *exception);
1734 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu);
1735
1736 void (*request_immediate_exit)(struct kvm_vcpu *vcpu);
1737
1738 void (*sched_in)(struct kvm_vcpu *vcpu, int cpu);
1739
1740 /*
1741 * Size of the CPU's dirty log buffer, i.e. VMX's PML buffer. A zero
1742 * value indicates CPU dirty logging is unsupported or disabled.
1743 */
1744 int cpu_dirty_log_size;
1745 void (*update_cpu_dirty_logging)(struct kvm_vcpu *vcpu);
1746
1747 const struct kvm_x86_nested_ops *nested_ops;
1748
1749 void (*vcpu_blocking)(struct kvm_vcpu *vcpu);
1750 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu);
1751
1752 int (*pi_update_irte)(struct kvm *kvm, unsigned int host_irq,
1753 uint32_t guest_irq, bool set);
1754 void (*pi_start_assignment)(struct kvm *kvm);
1755 void (*apicv_pre_state_restore)(struct kvm_vcpu *vcpu);
1756 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu);
1757 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu);
1758
1759 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
1760 bool *expired);
1761 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu);
1762
1763 void (*setup_mce)(struct kvm_vcpu *vcpu);
1764
1765 #ifdef CONFIG_KVM_SMM
1766 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1767 int (*enter_smm)(struct kvm_vcpu *vcpu, union kvm_smram *smram);
1768 int (*leave_smm)(struct kvm_vcpu *vcpu, const union kvm_smram *smram);
1769 void (*enable_smi_window)(struct kvm_vcpu *vcpu);
1770 #endif
1771
1772 int (*mem_enc_ioctl)(struct kvm *kvm, void __user *argp);
1773 int (*mem_enc_register_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1774 int (*mem_enc_unregister_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1775 int (*vm_copy_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
1776 int (*vm_move_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
1777 void (*guest_memory_reclaimed)(struct kvm *kvm);
1778
1779 int (*get_msr_feature)(struct kvm_msr_entry *entry);
1780
1781 int (*check_emulate_instruction)(struct kvm_vcpu *vcpu, int emul_type,
1782 void *insn, int insn_len);
1783
1784 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu);
1785 int (*enable_l2_tlb_flush)(struct kvm_vcpu *vcpu);
1786
1787 void (*migrate_timers)(struct kvm_vcpu *vcpu);
1788 void (*msr_filter_changed)(struct kvm_vcpu *vcpu);
1789 int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err);
1790
1791 void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector);
1792
1793 /*
1794 * Returns vCPU specific APICv inhibit reasons
1795 */
1796 unsigned long (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *vcpu);
1797
1798 gva_t (*get_untagged_addr)(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags);
1799 };
1800
1801 struct kvm_x86_nested_ops {
1802 void (*leave_nested)(struct kvm_vcpu *vcpu);
1803 bool (*is_exception_vmexit)(struct kvm_vcpu *vcpu, u8 vector,
1804 u32 error_code);
1805 int (*check_events)(struct kvm_vcpu *vcpu);
1806 bool (*has_events)(struct kvm_vcpu *vcpu);
1807 void (*triple_fault)(struct kvm_vcpu *vcpu);
1808 int (*get_state)(struct kvm_vcpu *vcpu,
1809 struct kvm_nested_state __user *user_kvm_nested_state,
1810 unsigned user_data_size);
1811 int (*set_state)(struct kvm_vcpu *vcpu,
1812 struct kvm_nested_state __user *user_kvm_nested_state,
1813 struct kvm_nested_state *kvm_state);
1814 bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu);
1815 int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa);
1816
1817 int (*enable_evmcs)(struct kvm_vcpu *vcpu,
1818 uint16_t *vmcs_version);
1819 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu);
1820 void (*hv_inject_synthetic_vmexit_post_tlb_flush)(struct kvm_vcpu *vcpu);
1821 };
1822
1823 struct kvm_x86_init_ops {
1824 int (*hardware_setup)(void);
1825 unsigned int (*handle_intel_pt_intr)(void);
1826
1827 struct kvm_x86_ops *runtime_ops;
1828 struct kvm_pmu_ops *pmu_ops;
1829 };
1830
1831 struct kvm_arch_async_pf {
1832 u32 token;
1833 gfn_t gfn;
1834 unsigned long cr3;
1835 bool direct_map;
1836 };
1837
1838 extern u32 __read_mostly kvm_nr_uret_msrs;
1839 extern u64 __read_mostly host_efer;
1840 extern bool __read_mostly allow_smaller_maxphyaddr;
1841 extern bool __read_mostly enable_apicv;
1842 extern struct kvm_x86_ops kvm_x86_ops;
1843
1844 #define KVM_X86_OP(func) \
1845 DECLARE_STATIC_CALL(kvm_x86_##func, *(((struct kvm_x86_ops *)0)->func));
1846 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
1847 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
1848 #include <asm/kvm-x86-ops.h>
1849
1850 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops);
1851 void kvm_x86_vendor_exit(void);
1852
1853 #define __KVM_HAVE_ARCH_VM_ALLOC
kvm_arch_alloc_vm(void)1854 static inline struct kvm *kvm_arch_alloc_vm(void)
1855 {
1856 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1857 }
1858
1859 #define __KVM_HAVE_ARCH_VM_FREE
1860 void kvm_arch_free_vm(struct kvm *kvm);
1861
1862 #if IS_ENABLED(CONFIG_HYPERV)
1863 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
kvm_arch_flush_remote_tlbs(struct kvm * kvm)1864 static inline int kvm_arch_flush_remote_tlbs(struct kvm *kvm)
1865 {
1866 if (kvm_x86_ops.flush_remote_tlbs &&
1867 !static_call(kvm_x86_flush_remote_tlbs)(kvm))
1868 return 0;
1869 else
1870 return -ENOTSUPP;
1871 }
1872
1873 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
kvm_arch_flush_remote_tlbs_range(struct kvm * kvm,gfn_t gfn,u64 nr_pages)1874 static inline int kvm_arch_flush_remote_tlbs_range(struct kvm *kvm, gfn_t gfn,
1875 u64 nr_pages)
1876 {
1877 if (!kvm_x86_ops.flush_remote_tlbs_range)
1878 return -EOPNOTSUPP;
1879
1880 return static_call(kvm_x86_flush_remote_tlbs_range)(kvm, gfn, nr_pages);
1881 }
1882 #endif /* CONFIG_HYPERV */
1883
1884 #define kvm_arch_pmi_in_guest(vcpu) \
1885 ((vcpu) && (vcpu)->arch.handling_intr_from_guest)
1886
1887 void __init kvm_mmu_x86_module_init(void);
1888 int kvm_mmu_vendor_module_init(void);
1889 void kvm_mmu_vendor_module_exit(void);
1890
1891 void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
1892 int kvm_mmu_create(struct kvm_vcpu *vcpu);
1893 void kvm_mmu_init_vm(struct kvm *kvm);
1894 void kvm_mmu_uninit_vm(struct kvm *kvm);
1895
1896 void kvm_mmu_init_memslot_memory_attributes(struct kvm *kvm,
1897 struct kvm_memory_slot *slot);
1898
1899 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu);
1900 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
1901 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
1902 const struct kvm_memory_slot *memslot,
1903 int start_level);
1904 void kvm_mmu_slot_try_split_huge_pages(struct kvm *kvm,
1905 const struct kvm_memory_slot *memslot,
1906 int target_level);
1907 void kvm_mmu_try_split_huge_pages(struct kvm *kvm,
1908 const struct kvm_memory_slot *memslot,
1909 u64 start, u64 end,
1910 int target_level);
1911 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
1912 const struct kvm_memory_slot *memslot);
1913 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
1914 const struct kvm_memory_slot *memslot);
1915 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
1916 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages);
1917
1918 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
1919
1920 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
1921 const void *val, int bytes);
1922
1923 struct kvm_irq_mask_notifier {
1924 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked);
1925 int irq;
1926 struct hlist_node link;
1927 };
1928
1929 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
1930 struct kvm_irq_mask_notifier *kimn);
1931 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
1932 struct kvm_irq_mask_notifier *kimn);
1933 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
1934 bool mask);
1935
1936 extern bool tdp_enabled;
1937
1938 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
1939
1940 /*
1941 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing
1942 * userspace I/O) to indicate that the emulation context
1943 * should be reused as is, i.e. skip initialization of
1944 * emulation context, instruction fetch and decode.
1945 *
1946 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware.
1947 * Indicates that only select instructions (tagged with
1948 * EmulateOnUD) should be emulated (to minimize the emulator
1949 * attack surface). See also EMULTYPE_TRAP_UD_FORCED.
1950 *
1951 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to
1952 * decode the instruction length. For use *only* by
1953 * kvm_x86_ops.skip_emulated_instruction() implementations if
1954 * EMULTYPE_COMPLETE_USER_EXIT is not set.
1955 *
1956 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to
1957 * retry native execution under certain conditions,
1958 * Can only be set in conjunction with EMULTYPE_PF.
1959 *
1960 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was
1961 * triggered by KVM's magic "force emulation" prefix,
1962 * which is opt in via module param (off by default).
1963 * Bypasses EmulateOnUD restriction despite emulating
1964 * due to an intercepted #UD (see EMULTYPE_TRAP_UD).
1965 * Used to test the full emulator from userspace.
1966 *
1967 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware
1968 * backdoor emulation, which is opt in via module param.
1969 * VMware backdoor emulation handles select instructions
1970 * and reinjects the #GP for all other cases.
1971 *
1972 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which
1973 * case the CR2/GPA value pass on the stack is valid.
1974 *
1975 * EMULTYPE_COMPLETE_USER_EXIT - Set when the emulator should update interruptibility
1976 * state and inject single-step #DBs after skipping
1977 * an instruction (after completing userspace I/O).
1978 *
1979 * EMULTYPE_WRITE_PF_TO_SP - Set when emulating an intercepted page fault that
1980 * is attempting to write a gfn that contains one or
1981 * more of the PTEs used to translate the write itself,
1982 * and the owning page table is being shadowed by KVM.
1983 * If emulation of the faulting instruction fails and
1984 * this flag is set, KVM will exit to userspace instead
1985 * of retrying emulation as KVM cannot make forward
1986 * progress.
1987 *
1988 * If emulation fails for a write to guest page tables,
1989 * KVM unprotects (zaps) the shadow page for the target
1990 * gfn and resumes the guest to retry the non-emulatable
1991 * instruction (on hardware). Unprotecting the gfn
1992 * doesn't allow forward progress for a self-changing
1993 * access because doing so also zaps the translation for
1994 * the gfn, i.e. retrying the instruction will hit a
1995 * !PRESENT fault, which results in a new shadow page
1996 * and sends KVM back to square one.
1997 */
1998 #define EMULTYPE_NO_DECODE (1 << 0)
1999 #define EMULTYPE_TRAP_UD (1 << 1)
2000 #define EMULTYPE_SKIP (1 << 2)
2001 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3)
2002 #define EMULTYPE_TRAP_UD_FORCED (1 << 4)
2003 #define EMULTYPE_VMWARE_GP (1 << 5)
2004 #define EMULTYPE_PF (1 << 6)
2005 #define EMULTYPE_COMPLETE_USER_EXIT (1 << 7)
2006 #define EMULTYPE_WRITE_PF_TO_SP (1 << 8)
2007
2008 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type);
2009 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
2010 void *insn, int insn_len);
2011 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu,
2012 u64 *data, u8 ndata);
2013 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu);
2014
2015 void kvm_enable_efer_bits(u64);
2016 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
2017 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated);
2018 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data);
2019 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data);
2020 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu);
2021 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu);
2022 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu);
2023 int kvm_emulate_invd(struct kvm_vcpu *vcpu);
2024 int kvm_emulate_mwait(struct kvm_vcpu *vcpu);
2025 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu);
2026 int kvm_emulate_monitor(struct kvm_vcpu *vcpu);
2027
2028 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in);
2029 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
2030 int kvm_emulate_halt(struct kvm_vcpu *vcpu);
2031 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu);
2032 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu);
2033 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
2034
2035 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
2036 void kvm_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
2037 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
2038 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
2039
2040 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
2041 int reason, bool has_error_code, u32 error_code);
2042
2043 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0);
2044 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4);
2045 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
2046 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
2047 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2048 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
2049 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
2050 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
2051 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
2052 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
2053 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu);
2054
2055 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
2056 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
2057
2058 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
2059 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
2060 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu);
2061
2062 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
2063 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
2064 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload);
2065 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
2066 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
2067 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
2068 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
2069 struct x86_exception *fault);
2070 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
2071 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
2072
__kvm_irq_line_state(unsigned long * irq_state,int irq_source_id,int level)2073 static inline int __kvm_irq_line_state(unsigned long *irq_state,
2074 int irq_source_id, int level)
2075 {
2076 /* Logical OR for level trig interrupt */
2077 if (level)
2078 __set_bit(irq_source_id, irq_state);
2079 else
2080 __clear_bit(irq_source_id, irq_state);
2081
2082 return !!(*irq_state);
2083 }
2084
2085 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
2086 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
2087
2088 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
2089 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu);
2090
2091 void kvm_update_dr7(struct kvm_vcpu *vcpu);
2092
2093 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
2094 void kvm_mmu_free_roots(struct kvm *kvm, struct kvm_mmu *mmu,
2095 ulong roots_to_free);
2096 void kvm_mmu_free_guest_mode_roots(struct kvm *kvm, struct kvm_mmu *mmu);
2097 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
2098 struct x86_exception *exception);
2099 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
2100 struct x86_exception *exception);
2101 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
2102 struct x86_exception *exception);
2103
2104 bool kvm_apicv_activated(struct kvm *kvm);
2105 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu);
2106 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu);
2107 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
2108 enum kvm_apicv_inhibit reason, bool set);
2109 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
2110 enum kvm_apicv_inhibit reason, bool set);
2111
kvm_set_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)2112 static inline void kvm_set_apicv_inhibit(struct kvm *kvm,
2113 enum kvm_apicv_inhibit reason)
2114 {
2115 kvm_set_or_clear_apicv_inhibit(kvm, reason, true);
2116 }
2117
kvm_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)2118 static inline void kvm_clear_apicv_inhibit(struct kvm *kvm,
2119 enum kvm_apicv_inhibit reason)
2120 {
2121 kvm_set_or_clear_apicv_inhibit(kvm, reason, false);
2122 }
2123
2124 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
2125
2126 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
2127 void *insn, int insn_len);
2128 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
2129 void kvm_mmu_invalidate_addr(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
2130 u64 addr, unsigned long roots);
2131 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid);
2132 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd);
2133
2134 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level,
2135 int tdp_max_root_level, int tdp_huge_page_level);
2136
2137 #ifdef CONFIG_KVM_PRIVATE_MEM
2138 #define kvm_arch_has_private_mem(kvm) ((kvm)->arch.vm_type != KVM_X86_DEFAULT_VM)
2139 #else
2140 #define kvm_arch_has_private_mem(kvm) false
2141 #endif
2142
kvm_read_ldt(void)2143 static inline u16 kvm_read_ldt(void)
2144 {
2145 u16 ldt;
2146 asm("sldt %0" : "=g"(ldt));
2147 return ldt;
2148 }
2149
kvm_load_ldt(u16 sel)2150 static inline void kvm_load_ldt(u16 sel)
2151 {
2152 asm("lldt %0" : : "rm"(sel));
2153 }
2154
2155 #ifdef CONFIG_X86_64
read_msr(unsigned long msr)2156 static inline unsigned long read_msr(unsigned long msr)
2157 {
2158 u64 value;
2159
2160 rdmsrl(msr, value);
2161 return value;
2162 }
2163 #endif
2164
kvm_inject_gp(struct kvm_vcpu * vcpu,u32 error_code)2165 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
2166 {
2167 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2168 }
2169
2170 #define TSS_IOPB_BASE_OFFSET 0x66
2171 #define TSS_BASE_SIZE 0x68
2172 #define TSS_IOPB_SIZE (65536 / 8)
2173 #define TSS_REDIRECTION_SIZE (256 / 8)
2174 #define RMODE_TSS_SIZE \
2175 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
2176
2177 enum {
2178 TASK_SWITCH_CALL = 0,
2179 TASK_SWITCH_IRET = 1,
2180 TASK_SWITCH_JMP = 2,
2181 TASK_SWITCH_GATE = 3,
2182 };
2183
2184 #define HF_GUEST_MASK (1 << 0) /* VCPU is in guest-mode */
2185
2186 #ifdef CONFIG_KVM_SMM
2187 #define HF_SMM_MASK (1 << 1)
2188 #define HF_SMM_INSIDE_NMI_MASK (1 << 2)
2189
2190 # define KVM_MAX_NR_ADDRESS_SPACES 2
2191 /* SMM is currently unsupported for guests with private memory. */
2192 # define kvm_arch_nr_memslot_as_ids(kvm) (kvm_arch_has_private_mem(kvm) ? 1 : 2)
2193 # define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0)
2194 # define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm)
2195 #else
2196 # define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, 0)
2197 #endif
2198
2199 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
2200 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
2201 int kvm_cpu_has_extint(struct kvm_vcpu *v);
2202 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
2203 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
2204 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
2205
2206 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
2207 unsigned long ipi_bitmap_high, u32 min,
2208 unsigned long icr, int op_64_bit);
2209
2210 int kvm_add_user_return_msr(u32 msr);
2211 int kvm_find_user_return_msr(u32 msr);
2212 int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask);
2213
kvm_is_supported_user_return_msr(u32 msr)2214 static inline bool kvm_is_supported_user_return_msr(u32 msr)
2215 {
2216 return kvm_find_user_return_msr(msr) >= 0;
2217 }
2218
2219 u64 kvm_scale_tsc(u64 tsc, u64 ratio);
2220 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
2221 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier);
2222 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier);
2223
2224 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu);
2225 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
2226
2227 void kvm_make_scan_ioapic_request(struct kvm *kvm);
2228 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
2229 unsigned long *vcpu_bitmap);
2230
2231 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
2232 struct kvm_async_pf *work);
2233 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
2234 struct kvm_async_pf *work);
2235 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
2236 struct kvm_async_pf *work);
2237 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu);
2238 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu);
2239 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
2240
2241 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
2242 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
2243 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu);
2244
2245 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
2246 u32 size);
2247 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu);
2248 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu);
2249
2250 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
2251 struct kvm_vcpu **dest_vcpu);
2252
2253 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
2254 struct kvm_lapic_irq *irq);
2255
kvm_irq_is_postable(struct kvm_lapic_irq * irq)2256 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq)
2257 {
2258 /* We can only post Fixed and LowPrio IRQs */
2259 return (irq->delivery_mode == APIC_DM_FIXED ||
2260 irq->delivery_mode == APIC_DM_LOWEST);
2261 }
2262
kvm_arch_vcpu_blocking(struct kvm_vcpu * vcpu)2263 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
2264 {
2265 static_call_cond(kvm_x86_vcpu_blocking)(vcpu);
2266 }
2267
kvm_arch_vcpu_unblocking(struct kvm_vcpu * vcpu)2268 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
2269 {
2270 static_call_cond(kvm_x86_vcpu_unblocking)(vcpu);
2271 }
2272
kvm_cpu_get_apicid(int mps_cpu)2273 static inline int kvm_cpu_get_apicid(int mps_cpu)
2274 {
2275 #ifdef CONFIG_X86_LOCAL_APIC
2276 return default_cpu_present_to_apicid(mps_cpu);
2277 #else
2278 WARN_ON_ONCE(1);
2279 return BAD_APICID;
2280 #endif
2281 }
2282
2283 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages);
2284
2285 #define KVM_CLOCK_VALID_FLAGS \
2286 (KVM_CLOCK_TSC_STABLE | KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC)
2287
2288 #define KVM_X86_VALID_QUIRKS \
2289 (KVM_X86_QUIRK_LINT0_REENABLED | \
2290 KVM_X86_QUIRK_CD_NW_CLEARED | \
2291 KVM_X86_QUIRK_LAPIC_MMIO_HOLE | \
2292 KVM_X86_QUIRK_OUT_7E_INC_RIP | \
2293 KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT | \
2294 KVM_X86_QUIRK_FIX_HYPERCALL_INSN | \
2295 KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS)
2296
2297 /*
2298 * KVM previously used a u32 field in kvm_run to indicate the hypercall was
2299 * initiated from long mode. KVM now sets bit 0 to indicate long mode, but the
2300 * remaining 31 lower bits must be 0 to preserve ABI.
2301 */
2302 #define KVM_EXIT_HYPERCALL_MBZ GENMASK_ULL(31, 1)
2303
2304 #endif /* _ASM_X86_KVM_HOST_H */
2305