1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dcn30_hubp.h"
27
28 #include "dm_services.h"
29 #include "dce_calcs.h"
30 #include "reg_helper.h"
31 #include "basics/conversion.h"
32 #include "dcn20/dcn20_hubp.h"
33 #include "dcn21/dcn21_hubp.h"
34
35 #define REG(reg)\
36 hubp2->hubp_regs->reg
37
38 #define CTX \
39 hubp2->base.ctx
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
44
hubp3_set_vm_system_aperture_settings(struct hubp * hubp,struct vm_system_aperture_param * apt)45 void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
46 struct vm_system_aperture_param *apt)
47 {
48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
49
50 PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
51 PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
52
53 // The format of high/low are 48:18 of the 48 bit addr
54 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
55 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
56
57 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
58 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
59
60 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
61 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
62
63 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
64 ENABLE_L1_TLB, 1,
65 SYSTEM_ACCESS_MODE, 0x3);
66 }
67
hubp3_program_surface_flip_and_addr(struct hubp * hubp,const struct dc_plane_address * address,bool flip_immediate)68 bool hubp3_program_surface_flip_and_addr(
69 struct hubp *hubp,
70 const struct dc_plane_address *address,
71 bool flip_immediate)
72 {
73 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
74
75 //program flip type
76 REG_UPDATE(DCSURF_FLIP_CONTROL,
77 SURFACE_FLIP_TYPE, flip_immediate);
78
79 // Program VMID reg
80 if (flip_immediate == 0)
81 REG_UPDATE(VMID_SETTINGS_0,
82 VMID, address->vmid);
83
84 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
85 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);
86 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
87
88 } else {
89 // turn off stereo if not in stereo
90 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
91 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
92 }
93
94 /* HW automatically latch rest of address register on write to
95 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
96 *
97 * program high first and then the low addr, order matters!
98 */
99 switch (address->type) {
100 case PLN_ADDR_TYPE_GRAPHICS:
101 /* DCN1.0 does not support const color
102 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
103 * base on address->grph.dcc_const_color
104 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
105 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
106 */
107
108 if (address->grph.addr.quad_part == 0)
109 break;
110
111 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
112 PRIMARY_SURFACE_TMZ, address->tmz_surface,
113 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
114
115 if (address->grph.meta_addr.quad_part != 0) {
116 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
117 PRIMARY_META_SURFACE_ADDRESS_HIGH,
118 address->grph.meta_addr.high_part);
119
120 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
121 PRIMARY_META_SURFACE_ADDRESS,
122 address->grph.meta_addr.low_part);
123 }
124
125 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
126 PRIMARY_SURFACE_ADDRESS_HIGH,
127 address->grph.addr.high_part);
128
129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
130 PRIMARY_SURFACE_ADDRESS,
131 address->grph.addr.low_part);
132 break;
133 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
134 if (address->video_progressive.luma_addr.quad_part == 0
135 || address->video_progressive.chroma_addr.quad_part == 0)
136 break;
137
138 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
139 PRIMARY_SURFACE_TMZ, address->tmz_surface,
140 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
141 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
142 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
143
144 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
145 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
146 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
147 address->video_progressive.chroma_meta_addr.high_part);
148
149 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
150 PRIMARY_META_SURFACE_ADDRESS_C,
151 address->video_progressive.chroma_meta_addr.low_part);
152
153 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
154 PRIMARY_META_SURFACE_ADDRESS_HIGH,
155 address->video_progressive.luma_meta_addr.high_part);
156
157 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
158 PRIMARY_META_SURFACE_ADDRESS,
159 address->video_progressive.luma_meta_addr.low_part);
160 }
161
162 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
163 PRIMARY_SURFACE_ADDRESS_HIGH_C,
164 address->video_progressive.chroma_addr.high_part);
165
166 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
167 PRIMARY_SURFACE_ADDRESS_C,
168 address->video_progressive.chroma_addr.low_part);
169
170 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
171 PRIMARY_SURFACE_ADDRESS_HIGH,
172 address->video_progressive.luma_addr.high_part);
173
174 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
175 PRIMARY_SURFACE_ADDRESS,
176 address->video_progressive.luma_addr.low_part);
177 break;
178 case PLN_ADDR_TYPE_GRPH_STEREO:
179 if (address->grph_stereo.left_addr.quad_part == 0)
180 break;
181 if (address->grph_stereo.right_addr.quad_part == 0)
182 break;
183
184 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
185 PRIMARY_SURFACE_TMZ, address->tmz_surface,
186 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
187 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
188 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
189 SECONDARY_SURFACE_TMZ, address->tmz_surface,
190 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
191 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
192 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
193
194 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
195
196 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,
197 SECONDARY_META_SURFACE_ADDRESS_HIGH_C,
198 address->grph_stereo.right_alpha_meta_addr.high_part);
199
200 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,
201 SECONDARY_META_SURFACE_ADDRESS_C,
202 address->grph_stereo.right_alpha_meta_addr.low_part);
203
204 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
205 SECONDARY_META_SURFACE_ADDRESS_HIGH,
206 address->grph_stereo.right_meta_addr.high_part);
207
208 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
209 SECONDARY_META_SURFACE_ADDRESS,
210 address->grph_stereo.right_meta_addr.low_part);
211 }
212 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
213
214 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
215 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
216 address->grph_stereo.left_alpha_meta_addr.high_part);
217
218 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
219 PRIMARY_META_SURFACE_ADDRESS_C,
220 address->grph_stereo.left_alpha_meta_addr.low_part);
221
222 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
223 PRIMARY_META_SURFACE_ADDRESS_HIGH,
224 address->grph_stereo.left_meta_addr.high_part);
225
226 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
227 PRIMARY_META_SURFACE_ADDRESS,
228 address->grph_stereo.left_meta_addr.low_part);
229 }
230
231 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,
232 SECONDARY_SURFACE_ADDRESS_HIGH_C,
233 address->grph_stereo.right_alpha_addr.high_part);
234
235 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,
236 SECONDARY_SURFACE_ADDRESS_C,
237 address->grph_stereo.right_alpha_addr.low_part);
238
239 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
240 SECONDARY_SURFACE_ADDRESS_HIGH,
241 address->grph_stereo.right_addr.high_part);
242
243 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
244 SECONDARY_SURFACE_ADDRESS,
245 address->grph_stereo.right_addr.low_part);
246
247 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
248 PRIMARY_SURFACE_ADDRESS_HIGH_C,
249 address->grph_stereo.left_alpha_addr.high_part);
250
251 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
252 PRIMARY_SURFACE_ADDRESS_C,
253 address->grph_stereo.left_alpha_addr.low_part);
254
255 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
256 PRIMARY_SURFACE_ADDRESS_HIGH,
257 address->grph_stereo.left_addr.high_part);
258
259 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
260 PRIMARY_SURFACE_ADDRESS,
261 address->grph_stereo.left_addr.low_part);
262 break;
263 case PLN_ADDR_TYPE_RGBEA:
264 if (address->rgbea.addr.quad_part == 0
265 || address->rgbea.alpha_addr.quad_part == 0)
266 break;
267
268 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
269 PRIMARY_SURFACE_TMZ, address->tmz_surface,
270 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
271 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
272 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
273
274 if (address->rgbea.meta_addr.quad_part != 0) {
275
276 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
277 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
278 address->rgbea.alpha_meta_addr.high_part);
279
280 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
281 PRIMARY_META_SURFACE_ADDRESS_C,
282 address->rgbea.alpha_meta_addr.low_part);
283
284 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
285 PRIMARY_META_SURFACE_ADDRESS_HIGH,
286 address->rgbea.meta_addr.high_part);
287
288 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
289 PRIMARY_META_SURFACE_ADDRESS,
290 address->rgbea.meta_addr.low_part);
291 }
292
293 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
294 PRIMARY_SURFACE_ADDRESS_HIGH_C,
295 address->rgbea.alpha_addr.high_part);
296
297 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
298 PRIMARY_SURFACE_ADDRESS_C,
299 address->rgbea.alpha_addr.low_part);
300
301 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
302 PRIMARY_SURFACE_ADDRESS_HIGH,
303 address->rgbea.addr.high_part);
304
305 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
306 PRIMARY_SURFACE_ADDRESS,
307 address->rgbea.addr.low_part);
308 break;
309 default:
310 BREAK_TO_DEBUGGER();
311 break;
312 }
313
314 hubp->request_address = *address;
315
316 return true;
317 }
318
hubp3_program_tiling(struct dcn20_hubp * hubp2,const struct dc_tiling_info * info,const enum surface_pixel_format pixel_format)319 void hubp3_program_tiling(
320 struct dcn20_hubp *hubp2,
321 const struct dc_tiling_info *info,
322 const enum surface_pixel_format pixel_format)
323 {
324 REG_UPDATE_4(DCSURF_ADDR_CONFIG,
325 NUM_PIPES, log_2(info->gfx9.num_pipes),
326 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
327 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
328 NUM_PKRS, log_2(info->gfx9.num_pkrs));
329
330 REG_UPDATE_3(DCSURF_TILING_CONFIG,
331 SW_MODE, info->gfx9.swizzle,
332 META_LINEAR, info->gfx9.meta_linear,
333 PIPE_ALIGNED, info->gfx9.pipe_aligned);
334
335 }
336
hubp3_clear_tiling(struct hubp * hubp)337 void hubp3_clear_tiling(struct hubp *hubp)
338 {
339 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
340
341 REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
342 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
343
344 REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
345 PRIMARY_SURFACE_DCC_EN, 0,
346 PRIMARY_SURFACE_DCC_IND_BLK, 0,
347 PRIMARY_SURFACE_DCC_IND_BLK_C, 0,
348 SECONDARY_SURFACE_DCC_EN, 0,
349 SECONDARY_SURFACE_DCC_IND_BLK, 0,
350 SECONDARY_SURFACE_DCC_IND_BLK_C, 0);
351 }
352
hubp3_dcc_control(struct hubp * hubp,bool enable,enum hubp_ind_block_size blk_size)353 void hubp3_dcc_control(struct hubp *hubp, bool enable,
354 enum hubp_ind_block_size blk_size)
355 {
356 uint32_t dcc_en = enable ? 1 : 0;
357 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
358
359 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
360 PRIMARY_SURFACE_DCC_EN, dcc_en,
361 PRIMARY_SURFACE_DCC_IND_BLK, blk_size,
362 SECONDARY_SURFACE_DCC_EN, dcc_en,
363 SECONDARY_SURFACE_DCC_IND_BLK, blk_size);
364 }
365
hubp3_dcc_control_sienna_cichlid(struct hubp * hubp,struct dc_plane_dcc_param * dcc)366 void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
367 struct dc_plane_dcc_param *dcc)
368 {
369 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
370
371 REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
372 PRIMARY_SURFACE_DCC_EN, dcc->enable,
373 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
374 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c,
375 SECONDARY_SURFACE_DCC_EN, dcc->enable,
376 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
377 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c);
378 }
379
hubp3_dmdata_set_attributes(struct hubp * hubp,const struct dc_dmdata_attributes * attr)380 void hubp3_dmdata_set_attributes(
381 struct hubp *hubp,
382 const struct dc_dmdata_attributes *attr)
383 {
384 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
385
386 /*always HW mode */
387 REG_UPDATE(DMDATA_CNTL,
388 DMDATA_MODE, 1);
389
390 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
391 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
392
393 /* toggle DMDATA_UPDATED and set repeat and size */
394 REG_UPDATE(DMDATA_CNTL,
395 DMDATA_UPDATED, 0);
396 REG_UPDATE_3(DMDATA_CNTL,
397 DMDATA_UPDATED, 1,
398 DMDATA_REPEAT, attr->dmdata_repeat,
399 DMDATA_SIZE, attr->dmdata_size);
400
401 /* set DMDATA address */
402 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
403 REG_UPDATE(DMDATA_ADDRESS_HIGH,
404 DMDATA_ADDRESS_HIGH, attr->address.high_part);
405
406 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
407
408 }
409
410
hubp3_program_surface_config(struct hubp * hubp,enum surface_pixel_format format,struct dc_tiling_info * tiling_info,struct plane_size * plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror,unsigned int compat_level)411 void hubp3_program_surface_config(
412 struct hubp *hubp,
413 enum surface_pixel_format format,
414 struct dc_tiling_info *tiling_info,
415 struct plane_size *plane_size,
416 enum dc_rotation_angle rotation,
417 struct dc_plane_dcc_param *dcc,
418 bool horizontal_mirror,
419 unsigned int compat_level)
420 {
421 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
422
423 hubp3_dcc_control_sienna_cichlid(hubp, dcc);
424 hubp3_program_tiling(hubp2, tiling_info, format);
425 hubp2_program_size(hubp, format, plane_size, dcc);
426 hubp2_program_rotation(hubp, rotation, horizontal_mirror);
427 hubp2_program_pixel_format(hubp, format);
428 }
429
hubp3_program_deadline(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)430 static void hubp3_program_deadline(
431 struct hubp *hubp,
432 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
433 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
434 {
435 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
436
437 hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
438 REG_UPDATE(DCN_DMDATA_VM_CNTL,
439 REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);
440 }
441
hubp3_read_state(struct hubp * hubp)442 void hubp3_read_state(struct hubp *hubp)
443 {
444 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
445 struct dcn_hubp_state *s = &hubp2->state;
446 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
447
448 hubp2_read_state_common(hubp);
449
450 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG,
451 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
452 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
453 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
454 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
455 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
456 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
457 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
458
459 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
460 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
461 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
462 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
463 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
464 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
465 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
466 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
467
468 if (REG(UCLK_PSTATE_FORCE))
469 s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);
470
471 if (REG(DCHUBP_CNTL))
472 s->hubp_cntl = REG_READ(DCHUBP_CNTL);
473
474 if (REG(DCSURF_FLIP_CONTROL))
475 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
476
477 }
478
hubp3_read_reg_state(struct hubp * hubp,struct dcn_hubp_reg_state * reg_state)479 void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state)
480 {
481 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
482
483 reg_state->hubp_cntl = REG_READ(DCHUBP_CNTL);
484 reg_state->mall_config = REG_READ(DCHUBP_MALL_CONFIG);
485 reg_state->mall_sub_vp = REG_READ(DCHUBP_MALL_SUB_VP);
486 reg_state->hubp_req_size_config = REG_READ(DCHUBP_REQ_SIZE_CONFIG);
487 reg_state->hubp_req_size_config_c = REG_READ(DCHUBP_REQ_SIZE_CONFIG_C);
488 reg_state->vmpg_config = REG_READ(DCHUBP_VMPG_CONFIG);
489 reg_state->addr_config = REG_READ(DCSURF_ADDR_CONFIG);
490 reg_state->pri_viewport_dimension = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION);
491 reg_state->pri_viewport_dimension_c = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION_C);
492 reg_state->pri_viewport_start = REG_READ(DCSURF_PRI_VIEWPORT_START);
493 reg_state->pri_viewport_start_c = REG_READ(DCSURF_PRI_VIEWPORT_START_C);
494 reg_state->sec_viewport_dimension = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION);
495 reg_state->sec_viewport_dimension_c = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION_C);
496 reg_state->sec_viewport_start = REG_READ(DCSURF_SEC_VIEWPORT_START);
497 reg_state->sec_viewport_start_c = REG_READ(DCSURF_SEC_VIEWPORT_START_C);
498 reg_state->surface_config = REG_READ(DCSURF_SURFACE_CONFIG);
499 reg_state->tiling_config = REG_READ(DCSURF_TILING_CONFIG);
500 reg_state->clk_cntl = REG_READ(HUBP_CLK_CNTL);
501 reg_state->mall_status = REG_READ(HUBP_MALL_STATUS);
502 reg_state->measure_win_ctrl_dcfclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DCFCLK);
503 reg_state->measure_win_ctrl_dppclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DPPCLK);
504
505 reg_state->blank_offset_0 = REG_READ(BLANK_OFFSET_0);
506 reg_state->blank_offset_1 = REG_READ(BLANK_OFFSET_1);
507 reg_state->cursor_settings = REG_READ(CURSOR_SETTINGS);
508 reg_state->dcn_cur0_ttu_cntl0 = REG_READ(DCN_CUR0_TTU_CNTL0);
509 reg_state->dcn_cur0_ttu_cntl1 = REG_READ(DCN_CUR0_TTU_CNTL1);
510 reg_state->dcn_cur1_ttu_cntl0 = REG_READ(DCN_CUR1_TTU_CNTL0);
511 reg_state->dcn_cur1_ttu_cntl1 = REG_READ(DCN_CUR1_TTU_CNTL1);
512 reg_state->dcn_dmdat_vm_cntl = REG_READ(DCN_DMDATA_VM_CNTL);
513 reg_state->dcn_expansion_mode = REG_READ(DCN_EXPANSION_MODE);
514 reg_state->dcn_global_ttu_cntl = REG_READ(DCN_GLOBAL_TTU_CNTL);
515 reg_state->dcn_surf0_ttu_cntl0 = REG_READ(DCN_SURF0_TTU_CNTL0);
516 reg_state->dcn_surf0_ttu_cntl1 = REG_READ(DCN_SURF0_TTU_CNTL1);
517 reg_state->dcn_surf1_ttu_cntl0 = REG_READ(DCN_SURF1_TTU_CNTL0);
518 reg_state->dcn_surf1_ttu_cntl1 = REG_READ(DCN_SURF1_TTU_CNTL1);
519 reg_state->dcn_ttu_qos_wm = REG_READ(DCN_TTU_QOS_WM);
520 reg_state->dcn_vm_mx_l1_tlb_cntl = REG_READ(DCN_VM_MX_L1_TLB_CNTL);
521 reg_state->dcn_vm_system_aperture_high_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR);
522 reg_state->dcn_vm_system_aperture_low_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_LOW_ADDR);
523 reg_state->dcsurf_flip_control = REG_READ(DCSURF_FLIP_CONTROL);
524 reg_state->dcsurf_flip_control2 = REG_READ(DCSURF_FLIP_CONTROL2);
525 reg_state->dcsurf_primary_meta_surface_address = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS);
526 reg_state->dcsurf_primary_meta_surface_address_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C);
527 reg_state->dcsurf_primary_meta_surface_address_high = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH);
528 reg_state->dcsurf_primary_meta_surface_address_high_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C);
529 reg_state->dcsurf_primary_surface_address = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS);
530 reg_state->dcsurf_primary_surface_address_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_C);
531 reg_state->dcsurf_primary_surface_address_high = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH);
532 reg_state->dcsurf_primary_surface_address_high_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C);
533 reg_state->dcsurf_secondary_meta_surface_address = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS);
534 reg_state->dcsurf_secondary_meta_surface_address_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C);
535 reg_state->dcsurf_secondary_meta_surface_address_high = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH);
536 reg_state->dcsurf_secondary_meta_surface_address_high_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C);
537 reg_state->dcsurf_secondary_surface_address = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS);
538 reg_state->dcsurf_secondary_surface_address_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_C);
539 reg_state->dcsurf_secondary_surface_address_high = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH);
540 reg_state->dcsurf_secondary_surface_address_high_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C);
541 reg_state->dcsurf_surface_control = REG_READ(DCSURF_SURFACE_CONTROL);
542 reg_state->dcsurf_surface_earliest_inuse = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE);
543 reg_state->dcsurf_surface_earliest_inuse_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_C);
544 reg_state->dcsurf_surface_earliest_inuse_high = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH);
545 reg_state->dcsurf_surface_earliest_inuse_high_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C);
546 reg_state->dcsurf_surface_flip_interrupt = REG_READ(DCSURF_SURFACE_FLIP_INTERRUPT);
547 reg_state->dcsurf_surface_inuse = REG_READ(DCSURF_SURFACE_INUSE);
548 reg_state->dcsurf_surface_inuse_c = REG_READ(DCSURF_SURFACE_INUSE_C);
549 reg_state->dcsurf_surface_inuse_high = REG_READ(DCSURF_SURFACE_INUSE_HIGH);
550 reg_state->dcsurf_surface_inuse_high_c = REG_READ(DCSURF_SURFACE_INUSE_HIGH_C);
551 reg_state->dcsurf_surface_pitch = REG_READ(DCSURF_SURFACE_PITCH);
552 reg_state->dcsurf_surface_pitch_c = REG_READ(DCSURF_SURFACE_PITCH_C);
553 reg_state->dst_after_scaler = REG_READ(DST_AFTER_SCALER);
554 reg_state->dst_dimensions = REG_READ(DST_DIMENSIONS);
555 reg_state->dst_y_delta_drq_limit = REG_READ(DST_Y_DELTA_DRQ_LIMIT);
556 reg_state->flip_parameters_0 = REG_READ(FLIP_PARAMETERS_0);
557 reg_state->flip_parameters_1 = REG_READ(FLIP_PARAMETERS_1);
558 reg_state->flip_parameters_2 = REG_READ(FLIP_PARAMETERS_2);
559 reg_state->flip_parameters_3 = REG_READ(FLIP_PARAMETERS_3);
560 reg_state->flip_parameters_4 = REG_READ(FLIP_PARAMETERS_4);
561 reg_state->flip_parameters_5 = REG_READ(FLIP_PARAMETERS_5);
562 reg_state->flip_parameters_6 = REG_READ(FLIP_PARAMETERS_6);
563 reg_state->hubpreq_mem_pwr_ctrl = REG_READ(HUBPREQ_MEM_PWR_CTRL);
564 reg_state->hubpreq_mem_pwr_status = REG_READ(HUBPREQ_MEM_PWR_STATUS);
565 reg_state->nom_parameters_0 = REG_READ(NOM_PARAMETERS_0);
566 reg_state->nom_parameters_1 = REG_READ(NOM_PARAMETERS_1);
567 reg_state->nom_parameters_2 = REG_READ(NOM_PARAMETERS_2);
568 reg_state->nom_parameters_3 = REG_READ(NOM_PARAMETERS_3);
569 reg_state->nom_parameters_4 = REG_READ(NOM_PARAMETERS_4);
570 reg_state->nom_parameters_5 = REG_READ(NOM_PARAMETERS_5);
571 reg_state->nom_parameters_6 = REG_READ(NOM_PARAMETERS_6);
572 reg_state->nom_parameters_7 = REG_READ(NOM_PARAMETERS_7);
573 reg_state->per_line_delivery = REG_READ(PER_LINE_DELIVERY);
574 reg_state->per_line_delivery_pre = REG_READ(PER_LINE_DELIVERY_PRE);
575 reg_state->prefetch_settings = REG_READ(PREFETCH_SETTINGS);
576 reg_state->prefetch_settings_c = REG_READ(PREFETCH_SETTINGS_C);
577 reg_state->ref_freq_to_pix_freq = REG_READ(REF_FREQ_TO_PIX_FREQ);
578 reg_state->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);
579 reg_state->vblank_parameters_0 = REG_READ(VBLANK_PARAMETERS_0);
580 reg_state->vblank_parameters_1 = REG_READ(VBLANK_PARAMETERS_1);
581 reg_state->vblank_parameters_2 = REG_READ(VBLANK_PARAMETERS_2);
582 reg_state->vblank_parameters_3 = REG_READ(VBLANK_PARAMETERS_3);
583 reg_state->vblank_parameters_4 = REG_READ(VBLANK_PARAMETERS_4);
584 reg_state->vblank_parameters_5 = REG_READ(VBLANK_PARAMETERS_5);
585 reg_state->vblank_parameters_6 = REG_READ(VBLANK_PARAMETERS_6);
586 reg_state->vmid_settings_0 = REG_READ(VMID_SETTINGS_0);
587 reg_state->hubpret_control = REG_READ(HUBPRET_CONTROL);
588 reg_state->hubpret_interrupt = REG_READ(HUBPRET_INTERRUPT);
589 reg_state->hubpret_mem_pwr_ctrl = REG_READ(HUBPRET_MEM_PWR_CTRL);
590 reg_state->hubpret_mem_pwr_status = REG_READ(HUBPRET_MEM_PWR_STATUS);
591 reg_state->hubpret_read_line_ctrl0 = REG_READ(HUBPRET_READ_LINE_CTRL0);
592 reg_state->hubpret_read_line_ctrl1 = REG_READ(HUBPRET_READ_LINE_CTRL1);
593 reg_state->hubpret_read_line_status = REG_READ(HUBPRET_READ_LINE_STATUS);
594 reg_state->hubpret_read_line_value = REG_READ(HUBPRET_READ_LINE_VALUE);
595 reg_state->hubpret_read_line0 = REG_READ(HUBPRET_READ_LINE0);
596 reg_state->hubpret_read_line1 = REG_READ(HUBPRET_READ_LINE1);
597 }
598
hubp3_setup(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)599 void hubp3_setup(
600 struct hubp *hubp,
601 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
602 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
603 struct _vcs_dpi_display_rq_regs_st *rq_regs,
604 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
605 {
606 /* otg is locked when this func is called. Register are double buffered.
607 * disable the requestors is not needed
608 */
609 hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
610 hubp21_program_requestor(hubp, rq_regs);
611 hubp3_program_deadline(hubp, dlg_attr, ttu_attr);
612 }
613
hubp3_init(struct hubp * hubp)614 void hubp3_init(struct hubp *hubp)
615 {
616 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
617 // This is a chicken bit to enable the ECO fix.
618
619 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
620 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
621 REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
622
623 REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);
624
625 hubp_reset(hubp);
626 }
627
628 static struct hubp_funcs dcn30_hubp_funcs = {
629 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
630 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
631 .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
632 .hubp_program_surface_config = hubp3_program_surface_config,
633 .hubp_is_flip_pending = hubp2_is_flip_pending,
634 .hubp_setup = hubp3_setup,
635 .hubp_setup_interdependent = hubp2_setup_interdependent,
636 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
637 .set_blank = hubp2_set_blank,
638 .set_blank_regs = hubp2_set_blank_regs,
639 .dcc_control = hubp3_dcc_control,
640 .hubp_reset = hubp_reset,
641 .mem_program_viewport = min_set_viewport,
642 .set_cursor_attributes = hubp2_cursor_set_attributes,
643 .set_cursor_position = hubp2_cursor_set_position,
644 .hubp_clk_cntl = hubp2_clk_cntl,
645 .hubp_vtg_sel = hubp2_vtg_sel,
646 .dmdata_set_attributes = hubp3_dmdata_set_attributes,
647 .dmdata_load = hubp2_dmdata_load,
648 .dmdata_status_done = hubp2_dmdata_status_done,
649 .hubp_read_state = hubp3_read_state,
650 .hubp_clear_underflow = hubp2_clear_underflow,
651 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
652 .hubp_init = hubp3_init,
653 .hubp_in_blank = hubp1_in_blank,
654 .hubp_soft_reset = hubp1_soft_reset,
655 .hubp_set_flip_int = hubp1_set_flip_int,
656 .hubp_clear_tiling = hubp3_clear_tiling,
657 .hubp_read_reg_state = hubp3_read_reg_state
658 };
659
hubp3_construct(struct dcn20_hubp * hubp2,struct dc_context * ctx,uint32_t inst,const struct dcn_hubp2_registers * hubp_regs,const struct dcn_hubp2_shift * hubp_shift,const struct dcn_hubp2_mask * hubp_mask)660 bool hubp3_construct(
661 struct dcn20_hubp *hubp2,
662 struct dc_context *ctx,
663 uint32_t inst,
664 const struct dcn_hubp2_registers *hubp_regs,
665 const struct dcn_hubp2_shift *hubp_shift,
666 const struct dcn_hubp2_mask *hubp_mask)
667 {
668 hubp2->base.funcs = &dcn30_hubp_funcs;
669 hubp2->base.ctx = ctx;
670 hubp2->hubp_regs = hubp_regs;
671 hubp2->hubp_shift = hubp_shift;
672 hubp2->hubp_mask = hubp_mask;
673 hubp2->base.inst = inst;
674 hubp2->base.opp_id = OPP_ID_INVALID;
675 hubp2->base.mpcc_id = 0xf;
676
677 return true;
678 }
679