1 /*
2 * PowerPC emulation special registers manipulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "qemu/main-loop.h"
23 #include "exec/cputlb.h"
24 #include "system/kvm.h"
25 #include "system/tcg.h"
26 #include "helper_regs.h"
27 #include "power8-pmu.h"
28 #include "cpu-models.h"
29 #include "spr_common.h"
30 #include "accel/tcg/cpu-ops.h"
31 #include "internal.h"
32
33 /* Swap temporary saved registers with GPRs */
hreg_swap_gpr_tgpr(CPUPPCState * env)34 void hreg_swap_gpr_tgpr(CPUPPCState *env)
35 {
36 target_ulong tmp;
37
38 tmp = env->gpr[0];
39 env->gpr[0] = env->tgpr[0];
40 env->tgpr[0] = tmp;
41 tmp = env->gpr[1];
42 env->gpr[1] = env->tgpr[1];
43 env->tgpr[1] = tmp;
44 tmp = env->gpr[2];
45 env->gpr[2] = env->tgpr[2];
46 env->tgpr[2] = tmp;
47 tmp = env->gpr[3];
48 env->gpr[3] = env->tgpr[3];
49 env->tgpr[3] = tmp;
50 }
51
52 #if defined(TARGET_PPC64)
hreg_check_bhrb_enable(CPUPPCState * env)53 static bool hreg_check_bhrb_enable(CPUPPCState *env)
54 {
55 bool pr = !!(env->msr & (1 << MSR_PR));
56 target_long mmcr0;
57 bool fcp;
58 bool hv;
59
60 /* ISA 3.1 adds the PMCRA[BRHBRD] and problem state checks */
61 if ((env->insns_flags2 & PPC2_ISA310) &&
62 ((env->spr[SPR_POWER_MMCRA] & MMCRA_BHRBRD) || !pr)) {
63 return false;
64 }
65
66 /* Check for BHRB "frozen" conditions */
67 mmcr0 = env->spr[SPR_POWER_MMCR0];
68 fcp = !!(mmcr0 & MMCR0_FCP);
69 if (mmcr0 & MMCR0_FCPC) {
70 hv = !!(env->msr & (1ull << MSR_HV));
71 if (fcp) {
72 if (hv && pr) {
73 return false;
74 }
75 } else if (!hv && pr) {
76 return false;
77 }
78 } else if (fcp && pr) {
79 return false;
80 }
81 return true;
82 }
83 #endif
84
hreg_compute_pmu_hflags_value(CPUPPCState * env)85 static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env)
86 {
87 uint32_t hflags = 0;
88 #if defined(TARGET_PPC64)
89 target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0];
90
91 if (mmcr0 & MMCR0_PMCC0) {
92 hflags |= 1 << HFLAGS_PMCC0;
93 }
94 if (mmcr0 & MMCR0_PMCC1) {
95 hflags |= 1 << HFLAGS_PMCC1;
96 }
97 if (mmcr0 & MMCR0_PMCjCE) {
98 hflags |= 1 << HFLAGS_PMCJCE;
99 }
100 if (hreg_check_bhrb_enable(env)) {
101 hflags |= 1 << HFLAGS_BHRB_ENABLE;
102 }
103
104 #ifndef CONFIG_USER_ONLY
105 if (env->pmc_ins_cnt) {
106 hflags |= 1 << HFLAGS_INSN_CNT;
107 if (env->pmc_ins_cnt & 0x1e) {
108 hflags |= 1 << HFLAGS_PMC_OTHER;
109 }
110 }
111 #endif
112 #endif
113
114 return hflags;
115 }
116
117 /* Mask of all PMU hflags */
hreg_compute_pmu_hflags_mask(CPUPPCState * env)118 static uint32_t hreg_compute_pmu_hflags_mask(CPUPPCState *env)
119 {
120 uint32_t hflags_mask = 0;
121 #if defined(TARGET_PPC64)
122 hflags_mask |= 1 << HFLAGS_PMCC0;
123 hflags_mask |= 1 << HFLAGS_PMCC1;
124 hflags_mask |= 1 << HFLAGS_PMCJCE;
125 hflags_mask |= 1 << HFLAGS_INSN_CNT;
126 hflags_mask |= 1 << HFLAGS_PMC_OTHER;
127 hflags_mask |= 1 << HFLAGS_BHRB_ENABLE;
128 #endif
129 return hflags_mask;
130 }
131
hreg_compute_hflags_value(CPUPPCState * env)132 static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
133 {
134 target_ulong msr = env->msr;
135 uint32_t ppc_flags = env->flags;
136 uint32_t hflags = 0;
137 uint32_t msr_mask;
138
139 /* Some bits come straight across from MSR. */
140 QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
141 QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
142 QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
143 QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
144 msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
145 (1 << MSR_DR) | (1 << MSR_FP));
146
147 if (ppc_flags & POWERPC_FLAG_DE) {
148 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
149 if ((dbcr0 & DBCR0_ICMP) && FIELD_EX64(msr, MSR, DE)) {
150 hflags |= 1 << HFLAGS_SE;
151 }
152 if ((dbcr0 & DBCR0_BRT) && FIELD_EX64(msr, MSR, DE)) {
153 hflags |= 1 << HFLAGS_BE;
154 }
155 } else {
156 if (ppc_flags & POWERPC_FLAG_BE) {
157 QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
158 msr_mask |= 1 << MSR_BE;
159 }
160 if (ppc_flags & POWERPC_FLAG_SE) {
161 QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
162 msr_mask |= 1 << MSR_SE;
163 }
164 }
165
166 if (msr_is_64bit(env, msr)) {
167 hflags |= 1 << HFLAGS_64;
168 }
169 if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
170 hflags |= 1 << HFLAGS_SPE;
171 }
172 if (ppc_flags & POWERPC_FLAG_VRE) {
173 QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
174 msr_mask |= 1 << MSR_VR;
175 }
176 if (ppc_flags & POWERPC_FLAG_VSX) {
177 QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
178 msr_mask |= 1 << MSR_VSX;
179 }
180 if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
181 hflags |= 1 << HFLAGS_TM;
182 }
183 if (env->spr[SPR_LPCR] & LPCR_GTSE) {
184 hflags |= 1 << HFLAGS_GTSE;
185 }
186 if (env->spr[SPR_LPCR] & LPCR_HR) {
187 hflags |= 1 << HFLAGS_HR;
188 }
189
190 #ifndef CONFIG_USER_ONLY
191 if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
192 hflags |= 1 << HFLAGS_HV;
193 }
194
195 /*
196 * This is our encoding for server processors. The architecture
197 * specifies that there is no such thing as userspace with
198 * translation off, however it appears that MacOS does it and some
199 * 32-bit CPUs support it. Weird...
200 *
201 * 0 = Guest User space virtual mode
202 * 1 = Guest Kernel space virtual mode
203 * 2 = Guest User space real mode
204 * 3 = Guest Kernel space real mode
205 * 4 = HV User space virtual mode
206 * 5 = HV Kernel space virtual mode
207 * 6 = HV User space real mode
208 * 7 = HV Kernel space real mode
209 *
210 * For BookE, we need 8 MMU modes as follow:
211 *
212 * 0 = AS 0 HV User space
213 * 1 = AS 0 HV Kernel space
214 * 2 = AS 1 HV User space
215 * 3 = AS 1 HV Kernel space
216 * 4 = AS 0 Guest User space
217 * 5 = AS 0 Guest Kernel space
218 * 6 = AS 1 Guest User space
219 * 7 = AS 1 Guest Kernel space
220 */
221 unsigned immu_idx, dmmu_idx;
222 dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1;
223 if (env->mmu_model == POWERPC_MMU_BOOKE ||
224 env->mmu_model == POWERPC_MMU_BOOKE206) {
225 dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0;
226 immu_idx = dmmu_idx;
227 immu_idx |= msr & (1 << MSR_IS) ? 2 : 0;
228 dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0;
229 } else {
230 dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0;
231 immu_idx = dmmu_idx;
232 immu_idx |= msr & (1 << MSR_IR) ? 0 : 2;
233 dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2;
234 }
235 hflags |= immu_idx << HFLAGS_IMMU_IDX;
236 hflags |= dmmu_idx << HFLAGS_DMMU_IDX;
237 #endif
238
239 hflags |= hreg_compute_pmu_hflags_value(env);
240
241 return hflags | (msr & msr_mask);
242 }
243
hreg_compute_hflags(CPUPPCState * env)244 void hreg_compute_hflags(CPUPPCState *env)
245 {
246 env->hflags = hreg_compute_hflags_value(env);
247 }
248
249 /*
250 * This can be used as a lighter-weight alternative to hreg_compute_hflags
251 * when PMU MMCR0 or pmc_ins_cnt changes. pmc_ins_cnt is changed by
252 * pmu_update_summaries.
253 */
hreg_update_pmu_hflags(CPUPPCState * env)254 void hreg_update_pmu_hflags(CPUPPCState *env)
255 {
256 env->hflags &= ~hreg_compute_pmu_hflags_mask(env);
257 env->hflags |= hreg_compute_pmu_hflags_value(env);
258 }
259
ppc_get_tb_cpu_state(CPUState * cs)260 TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs)
261 {
262 CPUPPCState *env = cpu_env(cs);
263 uint32_t hflags_current = env->hflags;
264
265 #ifdef CONFIG_DEBUG_TCG
266 uint32_t hflags_rebuilt = hreg_compute_hflags_value(env);
267 if (unlikely(hflags_current != hflags_rebuilt)) {
268 cpu_abort(env_cpu(env),
269 "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
270 hflags_current, hflags_rebuilt);
271 }
272 #endif
273
274 return (TCGTBCPUState){ .pc = env->nip, .flags = hflags_current };
275 }
276
cpu_interrupt_exittb(CPUState * cs)277 void cpu_interrupt_exittb(CPUState *cs)
278 {
279 /*
280 * We don't need to worry about translation blocks
281 * unless running with TCG.
282 */
283 if (tcg_enabled()) {
284 BQL_LOCK_GUARD();
285 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
286 }
287 }
288
hreg_store_msr(CPUPPCState * env,target_ulong value,int alter_hv)289 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
290 {
291 int excp;
292 #if !defined(CONFIG_USER_ONLY)
293 CPUState *cs = env_cpu(env);
294 #endif
295
296 excp = 0;
297 value &= env->msr_mask;
298 #if !defined(CONFIG_USER_ONLY)
299 /* Neither mtmsr nor guest state can alter HV */
300 if (!alter_hv || !(env->msr & MSR_HVB)) {
301 value &= ~MSR_HVB;
302 value |= env->msr & MSR_HVB;
303 }
304 /* Attempt to modify MSR[ME] in guest state is ignored */
305 if (is_book3s_arch2x(env) && !(env->msr & MSR_HVB)) {
306 value &= ~(1 << MSR_ME);
307 value |= env->msr & (1 << MSR_ME);
308 }
309 if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
310 cpu_interrupt_exittb(cs);
311 }
312 if ((env->mmu_model == POWERPC_MMU_BOOKE ||
313 env->mmu_model == POWERPC_MMU_BOOKE206) &&
314 ((value ^ env->msr) & R_MSR_GS_MASK)) {
315 cpu_interrupt_exittb(cs);
316 }
317 if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
318 ((value ^ env->msr) & (1 << MSR_TGPR)))) {
319 /* Swap temporary saved registers with GPRs */
320 hreg_swap_gpr_tgpr(env);
321 }
322 if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) {
323 env->excp_prefix = FIELD_EX64(value, MSR, EP) * 0xFFF00000;
324 }
325 /*
326 * If PR=1 then EE, IR and DR must be 1
327 *
328 * Note: We only enforce this on 64-bit server processors.
329 * It appears that:
330 * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
331 * exploits it.
332 * - 64-bit embedded implementations do not need any operation to be
333 * performed when PR is set.
334 */
335 if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
336 value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
337 }
338 #endif
339 env->msr = value;
340 hreg_compute_hflags(env);
341 #if !defined(CONFIG_USER_ONLY)
342 ppc_maybe_interrupt(env);
343
344 if (unlikely(FIELD_EX64(env->msr, MSR, POW))) {
345 if (!env->pending_interrupts && (*env->check_pow)(env)) {
346 cs->halted = 1;
347 excp = EXCP_HALTED;
348 }
349 }
350 #endif
351
352 return excp;
353 }
354
355 #ifndef CONFIG_USER_ONLY
store_40x_sler(CPUPPCState * env,uint32_t val)356 void store_40x_sler(CPUPPCState *env, uint32_t val)
357 {
358 /* XXX: TO BE FIXED */
359 if (val != 0x00000000) {
360 cpu_abort(env_cpu(env),
361 "Little-endian regions are not supported by now\n");
362 }
363 env->spr[SPR_405_SLER] = val;
364 }
365
check_tlb_flush(CPUPPCState * env,bool global)366 void check_tlb_flush(CPUPPCState *env, bool global)
367 {
368 CPUState *cs = env_cpu(env);
369
370 /* Handle global flushes first */
371 if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
372 env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
373 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
374 tlb_flush_all_cpus_synced(cs);
375 return;
376 }
377
378 /* Then handle local ones */
379 if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
380 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
381 tlb_flush(cs);
382 }
383 }
384 #endif /* !CONFIG_USER_ONLY */
385
386 /**
387 * _spr_register
388 *
389 * Register an SPR with all the callbacks required for tcg,
390 * and the ID number for KVM.
391 *
392 * The reason for the conditional compilation is that the tcg functions
393 * may be compiled out, and the system kvm header may not be available
394 * for supplying the ID numbers. This is ugly, but the best we can do.
395 */
_spr_register(CPUPPCState * env,int num,const char * name,USR_ARG (spr_callback * uea_read)USR_ARG (spr_callback * uea_write)SYS_ARG (spr_callback * oea_read)SYS_ARG (spr_callback * oea_write)SYS_ARG (spr_callback * hea_read)SYS_ARG (spr_callback * hea_write)KVM_ARG (uint64_t one_reg_id)target_ulong initial_value)396 void _spr_register(CPUPPCState *env, int num, const char *name,
397 USR_ARG(spr_callback *uea_read)
398 USR_ARG(spr_callback *uea_write)
399 SYS_ARG(spr_callback *oea_read)
400 SYS_ARG(spr_callback *oea_write)
401 SYS_ARG(spr_callback *hea_read)
402 SYS_ARG(spr_callback *hea_write)
403 KVM_ARG(uint64_t one_reg_id)
404 target_ulong initial_value)
405 {
406 ppc_spr_t *spr = &env->spr_cb[num];
407
408 /* No SPR should be registered twice. */
409 assert(spr->name == NULL);
410 assert(name != NULL);
411
412 spr->name = name;
413 spr->default_value = initial_value;
414 env->spr[num] = initial_value;
415
416 #ifdef CONFIG_TCG
417 spr->uea_read = uea_read;
418 spr->uea_write = uea_write;
419 # ifndef CONFIG_USER_ONLY
420 spr->oea_read = oea_read;
421 spr->oea_write = oea_write;
422 spr->hea_read = hea_read;
423 spr->hea_write = hea_write;
424 # endif
425 #endif
426 #ifdef CONFIG_KVM
427 spr->one_reg_id = one_reg_id;
428 #endif
429 }
430
431 /* Generic PowerPC SPRs */
register_generic_sprs(PowerPCCPU * cpu)432 void register_generic_sprs(PowerPCCPU *cpu)
433 {
434 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
435 CPUPPCState *env = &cpu->env;
436
437 /* Integer processing */
438 spr_register(env, SPR_XER, "XER",
439 &spr_read_xer, &spr_write_xer,
440 &spr_read_xer, &spr_write_xer,
441 0x00000000);
442 /* Branch control */
443 spr_register(env, SPR_LR, "LR",
444 &spr_read_lr, &spr_write_lr,
445 &spr_read_lr, &spr_write_lr,
446 0x00000000);
447 spr_register(env, SPR_CTR, "CTR",
448 &spr_read_ctr, &spr_write_ctr,
449 &spr_read_ctr, &spr_write_ctr,
450 0x00000000);
451 /* Interrupt processing */
452 spr_register(env, SPR_SRR0, "SRR0",
453 SPR_NOACCESS, SPR_NOACCESS,
454 &spr_read_generic, &spr_write_generic,
455 0x00000000);
456 spr_register(env, SPR_SRR1, "SRR1",
457 SPR_NOACCESS, SPR_NOACCESS,
458 &spr_read_generic, &spr_write_generic,
459 0x00000000);
460 /* Processor control */
461 spr_register(env, SPR_SPRG0, "SPRG0",
462 SPR_NOACCESS, SPR_NOACCESS,
463 &spr_read_generic, &spr_write_generic,
464 0x00000000);
465 spr_register(env, SPR_SPRG1, "SPRG1",
466 SPR_NOACCESS, SPR_NOACCESS,
467 &spr_read_generic, &spr_write_generic,
468 0x00000000);
469 spr_register(env, SPR_SPRG2, "SPRG2",
470 SPR_NOACCESS, SPR_NOACCESS,
471 &spr_read_generic, &spr_write_generic,
472 0x00000000);
473 spr_register(env, SPR_SPRG3, "SPRG3",
474 SPR_NOACCESS, SPR_NOACCESS,
475 &spr_read_generic, &spr_write_generic,
476 0x00000000);
477
478 spr_register(env, SPR_PVR, "PVR",
479 /* Linux permits userspace to read PVR */
480 #if defined(CONFIG_LINUX_USER)
481 &spr_read_generic,
482 #else
483 SPR_NOACCESS,
484 #endif
485 SPR_NOACCESS,
486 &spr_read_generic, SPR_NOACCESS,
487 pcc->pvr);
488
489 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
490 if (pcc->svr != POWERPC_SVR_NONE) {
491 if (pcc->svr & POWERPC_SVR_E500) {
492 spr_register(env, SPR_E500_SVR, "SVR",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, SPR_NOACCESS,
495 pcc->svr & ~POWERPC_SVR_E500);
496 } else {
497 spr_register(env, SPR_SVR, "SVR",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, SPR_NOACCESS,
500 pcc->svr);
501 }
502 }
503
504 /* Time base */
505 #if defined(TARGET_PPC64)
506 spr_register(env, SPR_TBL, "TB",
507 #else
508 spr_register(env, SPR_TBL, "TBL",
509 #endif
510 &spr_read_tbl, SPR_NOACCESS,
511 &spr_read_tbl, SPR_NOACCESS,
512 0x00000000);
513 spr_register(env, SPR_TBU, "TBU",
514 &spr_read_tbu, SPR_NOACCESS,
515 &spr_read_tbu, SPR_NOACCESS,
516 0x00000000);
517 #ifndef CONFIG_USER_ONLY
518 if (env->has_hv_mode) {
519 spr_register_hv(env, SPR_WR_TBL, "TBL",
520 SPR_NOACCESS, SPR_NOACCESS,
521 SPR_NOACCESS, SPR_NOACCESS,
522 SPR_NOACCESS, &spr_write_tbl,
523 0x00000000);
524 spr_register_hv(env, SPR_WR_TBU, "TBU",
525 SPR_NOACCESS, SPR_NOACCESS,
526 SPR_NOACCESS, SPR_NOACCESS,
527 SPR_NOACCESS, &spr_write_tbu,
528 0x00000000);
529 } else {
530 spr_register(env, SPR_WR_TBL, "TBL",
531 SPR_NOACCESS, SPR_NOACCESS,
532 SPR_NOACCESS, &spr_write_tbl,
533 0x00000000);
534 spr_register(env, SPR_WR_TBU, "TBU",
535 SPR_NOACCESS, SPR_NOACCESS,
536 SPR_NOACCESS, &spr_write_tbu,
537 0x00000000);
538 }
539 #endif
540 }
541
register_non_embedded_sprs(CPUPPCState * env)542 void register_non_embedded_sprs(CPUPPCState *env)
543 {
544 /* Exception processing */
545 spr_register_kvm(env, SPR_DSISR, "DSISR",
546 SPR_NOACCESS, SPR_NOACCESS,
547 &spr_read_generic, &spr_write_generic32,
548 KVM_REG_PPC_DSISR, 0x00000000);
549 spr_register_kvm(env, SPR_DAR, "DAR",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_generic, &spr_write_generic,
552 KVM_REG_PPC_DAR, 0x00000000);
553 /* Timer */
554 spr_register(env, SPR_DECR, "DEC",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_decr, &spr_write_decr,
557 0x00000000);
558 }
559
560 /* Storage Description Register 1 */
register_sdr1_sprs(CPUPPCState * env)561 void register_sdr1_sprs(CPUPPCState *env)
562 {
563 #ifndef CONFIG_USER_ONLY
564 if (env->has_hv_mode) {
565 /*
566 * SDR1 is a hypervisor resource on CPUs which have a
567 * hypervisor mode
568 */
569 spr_register_hv(env, SPR_SDR1, "SDR1",
570 SPR_NOACCESS, SPR_NOACCESS,
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_generic, &spr_write_sdr1,
573 0x00000000);
574 } else {
575 spr_register(env, SPR_SDR1, "SDR1",
576 SPR_NOACCESS, SPR_NOACCESS,
577 &spr_read_generic, &spr_write_sdr1,
578 0x00000000);
579 }
580 #endif
581 }
582
583 /* BATs 0-3 */
register_low_BATs(CPUPPCState * env)584 void register_low_BATs(CPUPPCState *env)
585 {
586 #if !defined(CONFIG_USER_ONLY)
587 spr_register(env, SPR_IBAT0U, "IBAT0U",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_ibat, &spr_write_ibatu,
590 0x00000000);
591 spr_register(env, SPR_IBAT0L, "IBAT0L",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_ibat, &spr_write_ibatl,
594 0x00000000);
595 spr_register(env, SPR_IBAT1U, "IBAT1U",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_ibat, &spr_write_ibatu,
598 0x00000000);
599 spr_register(env, SPR_IBAT1L, "IBAT1L",
600 SPR_NOACCESS, SPR_NOACCESS,
601 &spr_read_ibat, &spr_write_ibatl,
602 0x00000000);
603 spr_register(env, SPR_IBAT2U, "IBAT2U",
604 SPR_NOACCESS, SPR_NOACCESS,
605 &spr_read_ibat, &spr_write_ibatu,
606 0x00000000);
607 spr_register(env, SPR_IBAT2L, "IBAT2L",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_ibat, &spr_write_ibatl,
610 0x00000000);
611 spr_register(env, SPR_IBAT3U, "IBAT3U",
612 SPR_NOACCESS, SPR_NOACCESS,
613 &spr_read_ibat, &spr_write_ibatu,
614 0x00000000);
615 spr_register(env, SPR_IBAT3L, "IBAT3L",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_ibat, &spr_write_ibatl,
618 0x00000000);
619 spr_register(env, SPR_DBAT0U, "DBAT0U",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_dbat, &spr_write_dbatu,
622 0x00000000);
623 spr_register(env, SPR_DBAT0L, "DBAT0L",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_dbat, &spr_write_dbatl,
626 0x00000000);
627 spr_register(env, SPR_DBAT1U, "DBAT1U",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_dbat, &spr_write_dbatu,
630 0x00000000);
631 spr_register(env, SPR_DBAT1L, "DBAT1L",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_dbat, &spr_write_dbatl,
634 0x00000000);
635 spr_register(env, SPR_DBAT2U, "DBAT2U",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_dbat, &spr_write_dbatu,
638 0x00000000);
639 spr_register(env, SPR_DBAT2L, "DBAT2L",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_dbat, &spr_write_dbatl,
642 0x00000000);
643 spr_register(env, SPR_DBAT3U, "DBAT3U",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_dbat, &spr_write_dbatu,
646 0x00000000);
647 spr_register(env, SPR_DBAT3L, "DBAT3L",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_dbat, &spr_write_dbatl,
650 0x00000000);
651 env->nb_BATs += 4;
652 #endif
653 }
654
655 /* BATs 4-7 */
register_high_BATs(CPUPPCState * env)656 void register_high_BATs(CPUPPCState *env)
657 {
658 #if !defined(CONFIG_USER_ONLY)
659 spr_register(env, SPR_IBAT4U, "IBAT4U",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_ibat_h, &spr_write_ibatu_h,
662 0x00000000);
663 spr_register(env, SPR_IBAT4L, "IBAT4L",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_ibat_h, &spr_write_ibatl_h,
666 0x00000000);
667 spr_register(env, SPR_IBAT5U, "IBAT5U",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_ibat_h, &spr_write_ibatu_h,
670 0x00000000);
671 spr_register(env, SPR_IBAT5L, "IBAT5L",
672 SPR_NOACCESS, SPR_NOACCESS,
673 &spr_read_ibat_h, &spr_write_ibatl_h,
674 0x00000000);
675 spr_register(env, SPR_IBAT6U, "IBAT6U",
676 SPR_NOACCESS, SPR_NOACCESS,
677 &spr_read_ibat_h, &spr_write_ibatu_h,
678 0x00000000);
679 spr_register(env, SPR_IBAT6L, "IBAT6L",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat_h, &spr_write_ibatl_h,
682 0x00000000);
683 spr_register(env, SPR_IBAT7U, "IBAT7U",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat_h, &spr_write_ibatu_h,
686 0x00000000);
687 spr_register(env, SPR_IBAT7L, "IBAT7L",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat_h, &spr_write_ibatl_h,
690 0x00000000);
691 spr_register(env, SPR_DBAT4U, "DBAT4U",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_dbat_h, &spr_write_dbatu_h,
694 0x00000000);
695 spr_register(env, SPR_DBAT4L, "DBAT4L",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_dbat_h, &spr_write_dbatl_h,
698 0x00000000);
699 spr_register(env, SPR_DBAT5U, "DBAT5U",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_dbat_h, &spr_write_dbatu_h,
702 0x00000000);
703 spr_register(env, SPR_DBAT5L, "DBAT5L",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_dbat_h, &spr_write_dbatl_h,
706 0x00000000);
707 spr_register(env, SPR_DBAT6U, "DBAT6U",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_dbat_h, &spr_write_dbatu_h,
710 0x00000000);
711 spr_register(env, SPR_DBAT6L, "DBAT6L",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat_h, &spr_write_dbatl_h,
714 0x00000000);
715 spr_register(env, SPR_DBAT7U, "DBAT7U",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat_h, &spr_write_dbatu_h,
718 0x00000000);
719 spr_register(env, SPR_DBAT7L, "DBAT7L",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat_h, &spr_write_dbatl_h,
722 0x00000000);
723 env->nb_BATs += 4;
724 #endif
725 }
726
727 /* Softare table search registers */
register_6xx_7xx_soft_tlb(CPUPPCState * env,int nb_tlbs,int nb_ways)728 void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
729 {
730 #if !defined(CONFIG_USER_ONLY)
731 env->nb_tlb = nb_tlbs;
732 env->nb_ways = nb_ways;
733 env->tlb_type = TLB_6XX;
734 spr_register(env, SPR_DMISS, "DMISS",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, SPR_NOACCESS,
737 0x00000000);
738 spr_register(env, SPR_DCMP, "DCMP",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, SPR_NOACCESS,
741 0x00000000);
742 spr_register(env, SPR_HASH1, "HASH1",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, SPR_NOACCESS,
745 0x00000000);
746 spr_register(env, SPR_HASH2, "HASH2",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_generic, SPR_NOACCESS,
749 0x00000000);
750 spr_register(env, SPR_IMISS, "IMISS",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_generic, SPR_NOACCESS,
753 0x00000000);
754 spr_register(env, SPR_ICMP, "ICMP",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_generic, SPR_NOACCESS,
757 0x00000000);
758 spr_register(env, SPR_RPA, "RPA",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762 #endif
763 }
764
register_thrm_sprs(CPUPPCState * env)765 void register_thrm_sprs(CPUPPCState *env)
766 {
767 /* Thermal management */
768 spr_register(env, SPR_THRM1, "THRM1",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_thrm, &spr_write_generic,
771 0x00000000);
772
773 spr_register(env, SPR_THRM2, "THRM2",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_thrm, &spr_write_generic,
776 0x00000000);
777
778 spr_register(env, SPR_THRM3, "THRM3",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_thrm, &spr_write_generic,
781 0x00000000);
782 }
783
register_usprgh_sprs(CPUPPCState * env)784 void register_usprgh_sprs(CPUPPCState *env)
785 {
786 spr_register(env, SPR_USPRG4, "USPRG4",
787 &spr_read_ureg, SPR_NOACCESS,
788 &spr_read_ureg, SPR_NOACCESS,
789 0x00000000);
790 spr_register(env, SPR_USPRG5, "USPRG5",
791 &spr_read_ureg, SPR_NOACCESS,
792 &spr_read_ureg, SPR_NOACCESS,
793 0x00000000);
794 spr_register(env, SPR_USPRG6, "USPRG6",
795 &spr_read_ureg, SPR_NOACCESS,
796 &spr_read_ureg, SPR_NOACCESS,
797 0x00000000);
798 spr_register(env, SPR_USPRG7, "USPRG7",
799 &spr_read_ureg, SPR_NOACCESS,
800 &spr_read_ureg, SPR_NOACCESS,
801 0x00000000);
802 }
803