1 /*
2 * HPPA interrupt helper routines
3 *
4 * Copyright (c) 2017 Richard Henderson
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
22 #include "qemu/log.h"
23 #include "cpu.h"
24 #include "exec/helper-proto.h"
25 #include "hw/core/cpu.h"
26 #include "hw/hppa/hppa_hardware.h"
27
eval_interrupt(HPPACPU * cpu)28 static void eval_interrupt(HPPACPU *cpu)
29 {
30 CPUState *cs = CPU(cpu);
31 if (cpu->env.cr[CR_EIRR]) {
32 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
33 } else {
34 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
35 }
36 }
37
38 /* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus
39 * can write to this word to raise an external interrupt on the target CPU.
40 * This includes the system controller (DINO) for regular devices, or
41 * another CPU for SMP interprocessor interrupts.
42 */
io_eir_read(void * opaque,hwaddr addr,unsigned size)43 static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size)
44 {
45 HPPACPU *cpu = opaque;
46
47 /* ??? What does a read of this register over the GSC bus do? */
48 return cpu->env.cr[CR_EIRR];
49 }
50
io_eir_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)51 static void io_eir_write(void *opaque, hwaddr addr,
52 uint64_t data, unsigned size)
53 {
54 HPPACPU *cpu = opaque;
55 CPUHPPAState *env = &cpu->env;
56 int widthm1 = 31;
57 int le_bit;
58
59 /* The default PSW.W controls the width of EIRR. */
60 if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) {
61 widthm1 = 63;
62 }
63 le_bit = ~data & widthm1;
64
65 env->cr[CR_EIRR] |= 1ull << le_bit;
66 eval_interrupt(cpu);
67 }
68
69 const MemoryRegionOps hppa_io_eir_ops = {
70 .read = io_eir_read,
71 .write = io_eir_write,
72 .valid.min_access_size = 4,
73 .valid.max_access_size = 4,
74 .impl.min_access_size = 4,
75 .impl.max_access_size = 4,
76 };
77
hppa_cpu_alarm_timer(void * opaque)78 void hppa_cpu_alarm_timer(void *opaque)
79 {
80 /* Raise interrupt 0. */
81 io_eir_write(opaque, 0, 0, 4);
82 }
83
HELPER(write_eirr)84 void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val)
85 {
86 env->cr[CR_EIRR] &= ~val;
87 bql_lock();
88 eval_interrupt(env_archcpu(env));
89 bql_unlock();
90 }
91
hppa_cpu_do_interrupt(CPUState * cs)92 void hppa_cpu_do_interrupt(CPUState *cs)
93 {
94 HPPACPU *cpu = HPPA_CPU(cs);
95 CPUHPPAState *env = &cpu->env;
96 int i = cs->exception_index;
97 uint64_t old_psw, old_gva_offset_mask;
98
99 /* As documented in pa2.0 -- interruption handling. */
100 /* step 1 */
101 env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);
102 old_gva_offset_mask = env->gva_offset_mask;
103
104 /* step 2 -- Note PSW_W is masked out again for pa1.x */
105 cpu_hppa_put_psw(env,
106 (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W : 0) |
107 (i == EXCP_HPMC ? PSW_M : 0));
108
109 /* step 3 */
110 /*
111 * IIASQ is the top bits of the virtual address, or zero if translation
112 * is disabled -- with PSW_W == 0, this will reduce to the space.
113 */
114 if (old_psw & PSW_C) {
115 env->cr[CR_IIASQ] =
116 hppa_form_gva_mask(old_gva_offset_mask, env->iasq_f, env->iaoq_f) >> 32;
117 env->cr_back[0] =
118 hppa_form_gva_mask(old_gva_offset_mask, env->iasq_b, env->iaoq_b) >> 32;
119 } else {
120 env->cr[CR_IIASQ] = 0;
121 env->cr_back[0] = 0;
122 }
123 /* IIAOQ is the full offset for wide mode, or 32 bits for narrow mode. */
124 if (old_psw & PSW_W) {
125 env->cr[CR_IIAOQ] = env->iaoq_f;
126 env->cr_back[1] = env->iaoq_b;
127 } else {
128 env->cr[CR_IIAOQ] = (uint32_t)env->iaoq_f;
129 env->cr_back[1] = (uint32_t)env->iaoq_b;
130 }
131
132 if (old_psw & PSW_Q) {
133 /* step 5 */
134 /* ISR and IOR will be set elsewhere. */
135 switch (i) {
136 case EXCP_ILL:
137 case EXCP_BREAK:
138 case EXCP_OVERFLOW:
139 case EXCP_COND:
140 case EXCP_PRIV_REG:
141 case EXCP_PRIV_OPR:
142 /* IIR set via translate.c. */
143 break;
144
145 case EXCP_ASSIST:
146 case EXCP_DTLB_MISS:
147 case EXCP_NA_ITLB_MISS:
148 case EXCP_NA_DTLB_MISS:
149 case EXCP_DMAR:
150 case EXCP_DMPI:
151 case EXCP_UNALIGN:
152 case EXCP_DMP:
153 case EXCP_DMB:
154 case EXCP_TLB_DIRTY:
155 case EXCP_PAGE_REF:
156 case EXCP_ASSIST_EMU:
157 {
158 /* Avoid reading directly from the virtual address, lest we
159 raise another exception from some sort of TLB issue. */
160 /* ??? An alternate fool-proof method would be to store the
161 instruction data into the unwind info. That's probably
162 a bit too much in the way of extra storage required. */
163 vaddr vaddr = env->iaoq_f & -4;
164 hwaddr paddr = vaddr;
165
166 if (old_psw & PSW_C) {
167 int prot, t;
168
169 vaddr = hppa_form_gva_mask(old_gva_offset_mask,
170 env->iasq_f, vaddr);
171 t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX,
172 0, 0, &paddr, &prot);
173 if (t >= 0) {
174 /* We can't re-load the instruction. */
175 env->cr[CR_IIR] = 0;
176 break;
177 }
178 }
179 env->cr[CR_IIR] = ldl_phys(cs->as, paddr);
180 if (i == EXCP_ASSIST) {
181 /* stuff insn code into bits of FP exception register #1 */
182 env->fr[0] |= (env->cr[CR_IIR] & 0x03ffffff);
183 }
184 }
185 break;
186
187 default:
188 /* Other exceptions do not set IIR. */
189 break;
190 }
191
192 /* step 6 */
193 env->shadow[0] = env->gr[1];
194 env->shadow[1] = env->gr[8];
195 env->shadow[2] = env->gr[9];
196 env->shadow[3] = env->gr[16];
197 env->shadow[4] = env->gr[17];
198 env->shadow[5] = env->gr[24];
199 env->shadow[6] = env->gr[25];
200 }
201
202 /* step 7 */
203 if (i == EXCP_TOC) {
204 env->iaoq_f = hppa_form_gva(env, 0, FIRMWARE_START);
205 /* help SeaBIOS and provide iaoq_b and iasq_back in shadow regs */
206 env->gr[24] = env->cr_back[0];
207 env->gr[25] = env->cr_back[1];
208 } else {
209 env->iaoq_f = hppa_form_gva(env, 0, env->cr[CR_IVA] + 32 * i);
210 }
211 env->iaoq_b = hppa_form_gva(env, 0, env->iaoq_f + 4);
212 env->iasq_f = 0;
213 env->iasq_b = 0;
214
215 if (qemu_loglevel_mask(CPU_LOG_INT)) {
216 static const char * const names[] = {
217 [EXCP_HPMC] = "high priority machine check",
218 [EXCP_POWER_FAIL] = "power fail interrupt",
219 [EXCP_RC] = "recovery counter trap",
220 [EXCP_EXT_INTERRUPT] = "external interrupt",
221 [EXCP_LPMC] = "low priority machine check",
222 [EXCP_ITLB_MISS] = "instruction tlb miss fault",
223 [EXCP_IMP] = "instruction memory protection trap",
224 [EXCP_ILL] = "illegal instruction trap",
225 [EXCP_BREAK] = "break instruction trap",
226 [EXCP_PRIV_OPR] = "privileged operation trap",
227 [EXCP_PRIV_REG] = "privileged register trap",
228 [EXCP_OVERFLOW] = "overflow trap",
229 [EXCP_COND] = "conditional trap",
230 [EXCP_ASSIST] = "assist exception trap",
231 [EXCP_DTLB_MISS] = "data tlb miss fault",
232 [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss",
233 [EXCP_NA_DTLB_MISS] = "non-access data tlb miss",
234 [EXCP_DMP] = "data memory protection trap",
235 [EXCP_DMB] = "data memory break trap",
236 [EXCP_TLB_DIRTY] = "tlb dirty bit trap",
237 [EXCP_PAGE_REF] = "page reference trap",
238 [EXCP_ASSIST_EMU] = "assist emulation trap",
239 [EXCP_HPT] = "high-privilege transfer trap",
240 [EXCP_LPT] = "low-privilege transfer trap",
241 [EXCP_TB] = "taken branch trap",
242 [EXCP_DMAR] = "data memory access rights trap",
243 [EXCP_DMPI] = "data memory protection id trap",
244 [EXCP_UNALIGN] = "unaligned data reference trap",
245 [EXCP_PER_INTERRUPT] = "performance monitor interrupt",
246 [EXCP_SYSCALL] = "syscall",
247 [EXCP_SYSCALL_LWS] = "syscall-lws",
248 [EXCP_TOC] = "TOC (transfer of control)",
249 };
250
251 FILE *logfile = qemu_log_trylock();
252 if (logfile) {
253 const char *name = NULL;
254
255 if (i >= 0 && i < ARRAY_SIZE(names)) {
256 name = names[i];
257 }
258 if (name) {
259 fprintf(logfile, "INT: cpu %d %s\n", cs->cpu_index, name);
260 } else {
261 fprintf(logfile, "INT: cpu %d unknown %d\n", cs->cpu_index, i);
262 }
263 hppa_cpu_dump_state(cs, logfile, 0);
264 qemu_log_unlock(logfile);
265 }
266 }
267 cs->exception_index = -1;
268 }
269
hppa_cpu_exec_interrupt(CPUState * cs,int interrupt_request)270 bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
271 {
272 HPPACPU *cpu = HPPA_CPU(cs);
273 CPUHPPAState *env = &cpu->env;
274
275 if (interrupt_request & CPU_INTERRUPT_NMI) {
276 /* Raise TOC (NMI) interrupt */
277 cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI);
278 cs->exception_index = EXCP_TOC;
279 hppa_cpu_do_interrupt(cs);
280 return true;
281 }
282
283 /* If interrupts are requested and enabled, raise them. */
284 if ((interrupt_request & CPU_INTERRUPT_HARD)
285 && (env->psw & PSW_I)
286 && (env->cr[CR_EIRR] & env->cr[CR_EIEM])) {
287 cs->exception_index = EXCP_EXT_INTERRUPT;
288 hppa_cpu_do_interrupt(cs);
289 return true;
290 }
291 return false;
292 }
293