1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
3 *
4 * Based on the bochs drm driver.
5 *
6 * Copyright (c) 2016 Huawei Limited.
7 *
8 * Author:
9 * Rongrong Zou <zourongrong@huawei.com>
10 * Rongrong Zou <zourongrong@gmail.com>
11 * Jianhua Li <lijianhua@huawei.com>
12 */
13
14 #include <linux/aperture.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17
18 #include <drm/clients/drm_client_setup.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_drv.h>
21 #include <drm/drm_fbdev_ttm.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_gem_vram_helper.h>
24 #include <drm/drm_managed.h>
25 #include <drm/drm_module.h>
26 #include <drm/drm_vblank.h>
27
28 #include "hibmc_drm_drv.h"
29 #include "hibmc_drm_regs.h"
30
31 #include "dp/dp_reg.h"
32
33 DEFINE_DRM_GEM_FOPS(hibmc_fops);
34
35 static const char *g_irqs_names_map[HIBMC_MAX_VECTORS] = { "vblank", "hpd" };
36
hibmc_interrupt(int irq,void * arg)37 static irqreturn_t hibmc_interrupt(int irq, void *arg)
38 {
39 struct drm_device *dev = (struct drm_device *)arg;
40 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
41 u32 status;
42
43 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT);
44
45 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) {
46 writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
47 priv->mmio + HIBMC_RAW_INTERRUPT);
48 drm_handle_vblank(dev, 0);
49 }
50
51 return IRQ_HANDLED;
52 }
53
hibmc_dp_interrupt(int irq,void * arg)54 static irqreturn_t hibmc_dp_interrupt(int irq, void *arg)
55 {
56 struct drm_device *dev = (struct drm_device *)arg;
57 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
58 u32 status;
59
60 status = readl(priv->mmio + HIBMC_DP_INTSTAT);
61 if (status) {
62 priv->dp.irq_status = status;
63 writel(status, priv->mmio + HIBMC_DP_INTCLR);
64 return IRQ_WAKE_THREAD;
65 }
66
67 return IRQ_HANDLED;
68 }
69
hibmc_dumb_create(struct drm_file * file,struct drm_device * dev,struct drm_mode_create_dumb * args)70 static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev,
71 struct drm_mode_create_dumb *args)
72 {
73 return drm_gem_vram_fill_create_dumb(file, dev, 0, 128, args);
74 }
75
76 static const struct drm_driver hibmc_driver = {
77 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
78 .fops = &hibmc_fops,
79 .name = "hibmc",
80 .desc = "hibmc drm driver",
81 .major = 1,
82 .minor = 0,
83 .debugfs_init = drm_vram_mm_debugfs_init,
84 .dumb_create = hibmc_dumb_create,
85 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
86 DRM_FBDEV_TTM_DRIVER_OPS,
87 };
88
hibmc_pm_suspend(struct device * dev)89 static int __maybe_unused hibmc_pm_suspend(struct device *dev)
90 {
91 struct drm_device *drm_dev = dev_get_drvdata(dev);
92
93 return drm_mode_config_helper_suspend(drm_dev);
94 }
95
hibmc_pm_resume(struct device * dev)96 static int __maybe_unused hibmc_pm_resume(struct device *dev)
97 {
98 struct drm_device *drm_dev = dev_get_drvdata(dev);
99
100 return drm_mode_config_helper_resume(drm_dev);
101 }
102
103 static const struct dev_pm_ops hibmc_pm_ops = {
104 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
105 hibmc_pm_resume)
106 };
107
108 static const struct drm_mode_config_funcs hibmc_mode_funcs = {
109 .mode_valid = drm_vram_helper_mode_valid,
110 .atomic_check = drm_atomic_helper_check,
111 .atomic_commit = drm_atomic_helper_commit,
112 .fb_create = drm_gem_fb_create,
113 };
114
hibmc_kms_init(struct hibmc_drm_private * priv)115 static int hibmc_kms_init(struct hibmc_drm_private *priv)
116 {
117 struct drm_device *dev = &priv->dev;
118 int ret;
119
120 ret = drmm_mode_config_init(dev);
121 if (ret)
122 return ret;
123
124 dev->mode_config.min_width = 0;
125 dev->mode_config.min_height = 0;
126 dev->mode_config.max_width = 1920;
127 dev->mode_config.max_height = 1200;
128
129 dev->mode_config.preferred_depth = 24;
130 dev->mode_config.prefer_shadow = 1;
131
132 dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
133
134 ret = hibmc_de_init(priv);
135 if (ret) {
136 drm_err(dev, "failed to init de: %d\n", ret);
137 return ret;
138 }
139
140 /*
141 * If the serdes reg is readable and is not equal to 0,
142 * DP block exists and initializes it.
143 */
144 ret = readl(priv->mmio + HIBMC_DP_HOST_SERDES_CTRL);
145 if (ret) {
146 ret = hibmc_dp_init(priv);
147 if (ret)
148 drm_err(dev, "failed to init dp: %d\n", ret);
149 }
150
151 ret = hibmc_vdac_init(priv);
152 if (ret) {
153 drm_err(dev, "failed to init vdac: %d\n", ret);
154 return ret;
155 }
156
157 return 0;
158 }
159
160 /*
161 * It can operate in one of three modes: 0, 1 or Sleep.
162 */
hibmc_set_power_mode(struct hibmc_drm_private * priv,u32 power_mode)163 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode)
164 {
165 u32 control_value = 0;
166 void __iomem *mmio = priv->mmio;
167 u32 input = 1;
168
169 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
170 return;
171
172 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
173 input = 0;
174
175 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
176 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
177 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
178 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
179 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
180 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
181 }
182
hibmc_set_current_gate(struct hibmc_drm_private * priv,unsigned int gate)183 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
184 {
185 u32 gate_reg;
186 u32 mode;
187 void __iomem *mmio = priv->mmio;
188
189 /* Get current power mode. */
190 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
191 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
192
193 switch (mode) {
194 case HIBMC_PW_MODE_CTL_MODE_MODE0:
195 gate_reg = HIBMC_MODE0_GATE;
196 break;
197
198 case HIBMC_PW_MODE_CTL_MODE_MODE1:
199 gate_reg = HIBMC_MODE1_GATE;
200 break;
201
202 default:
203 gate_reg = HIBMC_MODE0_GATE;
204 break;
205 }
206 writel(gate, mmio + gate_reg);
207 }
208
hibmc_hw_config(struct hibmc_drm_private * priv)209 static void hibmc_hw_config(struct hibmc_drm_private *priv)
210 {
211 u32 reg;
212
213 /* On hardware reset, power mode 0 is default. */
214 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
215
216 /* Enable display power gate & LOCALMEM power gate*/
217 reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
218 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
219 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
220 reg |= HIBMC_CURR_GATE_DISPLAY(1);
221 reg |= HIBMC_CURR_GATE_LOCALMEM(1);
222
223 hibmc_set_current_gate(priv, reg);
224
225 /*
226 * Reset the memory controller. If the memory controller
227 * is not reset in chip,the system might hang when sw accesses
228 * the memory.The memory should be resetted after
229 * changing the MXCLK.
230 */
231 reg = readl(priv->mmio + HIBMC_MISC_CTRL);
232 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
233 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
234 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
235
236 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
237 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
238
239 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
240 }
241
hibmc_hw_map(struct hibmc_drm_private * priv)242 static int hibmc_hw_map(struct hibmc_drm_private *priv)
243 {
244 struct drm_device *dev = &priv->dev;
245 struct pci_dev *pdev = to_pci_dev(dev->dev);
246 resource_size_t ioaddr, iosize;
247
248 ioaddr = pci_resource_start(pdev, 1);
249 iosize = pci_resource_len(pdev, 1);
250 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize);
251 if (!priv->mmio) {
252 drm_err(dev, "Cannot map mmio region\n");
253 return -ENOMEM;
254 }
255
256 return 0;
257 }
258
hibmc_hw_init(struct hibmc_drm_private * priv)259 static int hibmc_hw_init(struct hibmc_drm_private *priv)
260 {
261 int ret;
262
263 ret = hibmc_hw_map(priv);
264 if (ret)
265 return ret;
266
267 hibmc_hw_config(priv);
268
269 return 0;
270 }
271
hibmc_unload(struct drm_device * dev)272 static void hibmc_unload(struct drm_device *dev)
273 {
274 drm_atomic_helper_shutdown(dev);
275 }
276
hibmc_msi_init(struct drm_device * dev)277 static int hibmc_msi_init(struct drm_device *dev)
278 {
279 struct pci_dev *pdev = to_pci_dev(dev->dev);
280 char name[32] = {0};
281 int valid_irq_num;
282 int irq;
283 int ret;
284
285 ret = pci_alloc_irq_vectors(pdev, HIBMC_MIN_VECTORS,
286 HIBMC_MAX_VECTORS, PCI_IRQ_MSI);
287 if (ret < 0) {
288 drm_err(dev, "enabling MSI failed: %d\n", ret);
289 return ret;
290 }
291
292 valid_irq_num = ret;
293
294 for (int i = 0; i < valid_irq_num; i++) {
295 snprintf(name, ARRAY_SIZE(name) - 1, "%s-%s-%s",
296 dev->driver->name, pci_name(pdev), g_irqs_names_map[i]);
297
298 irq = pci_irq_vector(pdev, i);
299
300 if (i)
301 /* PCI devices require shared interrupts. */
302 ret = devm_request_threaded_irq(&pdev->dev, irq,
303 hibmc_dp_interrupt,
304 hibmc_dp_hpd_isr,
305 IRQF_SHARED, name, dev);
306 else
307 ret = devm_request_irq(&pdev->dev, irq, hibmc_interrupt,
308 IRQF_SHARED, name, dev);
309 if (ret) {
310 drm_err(dev, "install irq failed: %d\n", ret);
311 return ret;
312 }
313 }
314
315 return 0;
316 }
317
hibmc_load(struct drm_device * dev)318 static int hibmc_load(struct drm_device *dev)
319 {
320 struct pci_dev *pdev = to_pci_dev(dev->dev);
321 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
322 int ret;
323
324 ret = hibmc_hw_init(priv);
325 if (ret)
326 goto err;
327
328 ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0),
329 pci_resource_len(pdev, 0));
330 if (ret) {
331 drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
332 goto err;
333 }
334
335 ret = hibmc_kms_init(priv);
336 if (ret)
337 goto err;
338
339 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
340 if (ret) {
341 drm_err(dev, "failed to initialize vblank: %d\n", ret);
342 goto err;
343 }
344
345 ret = hibmc_msi_init(dev);
346 if (ret) {
347 drm_err(dev, "hibmc msi init failed, ret:%d\n", ret);
348 goto err;
349 }
350
351 /* reset all the states of crtc/plane/encoder/connector */
352 drm_mode_config_reset(dev);
353
354 return 0;
355
356 err:
357 hibmc_unload(dev);
358 drm_err(dev, "failed to initialize drm driver: %d\n", ret);
359 return ret;
360 }
361
hibmc_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)362 static int hibmc_pci_probe(struct pci_dev *pdev,
363 const struct pci_device_id *ent)
364 {
365 struct hibmc_drm_private *priv;
366 struct drm_device *dev;
367 int ret;
368
369 ret = aperture_remove_conflicting_pci_devices(pdev, hibmc_driver.name);
370 if (ret)
371 return ret;
372
373 priv = devm_drm_dev_alloc(&pdev->dev, &hibmc_driver,
374 struct hibmc_drm_private, dev);
375 if (IS_ERR(priv)) {
376 DRM_ERROR("failed to allocate drm_device\n");
377 return PTR_ERR(priv);
378 }
379
380 dev = &priv->dev;
381 pci_set_drvdata(pdev, dev);
382
383 ret = pcim_enable_device(pdev);
384 if (ret) {
385 drm_err(dev, "failed to enable pci device: %d\n", ret);
386 goto err_return;
387 }
388
389 pci_set_master(pdev);
390
391 ret = hibmc_load(dev);
392 if (ret) {
393 drm_err(dev, "failed to load hibmc: %d\n", ret);
394 goto err_return;
395 }
396
397 ret = drm_dev_register(dev, 0);
398 if (ret) {
399 drm_err(dev, "failed to register drv for userspace access: %d\n",
400 ret);
401 goto err_unload;
402 }
403
404 drm_client_setup(dev, NULL);
405
406 return 0;
407
408 err_unload:
409 hibmc_unload(dev);
410 err_return:
411 return ret;
412 }
413
hibmc_pci_remove(struct pci_dev * pdev)414 static void hibmc_pci_remove(struct pci_dev *pdev)
415 {
416 struct drm_device *dev = pci_get_drvdata(pdev);
417
418 drm_dev_unregister(dev);
419 hibmc_unload(dev);
420 }
421
hibmc_pci_shutdown(struct pci_dev * pdev)422 static void hibmc_pci_shutdown(struct pci_dev *pdev)
423 {
424 hibmc_pci_remove(pdev);
425 }
426
427 static const struct pci_device_id hibmc_pci_table[] = {
428 { PCI_VDEVICE(HUAWEI, 0x1711) },
429 {0,}
430 };
431
432 static struct pci_driver hibmc_pci_driver = {
433 .name = "hibmc-drm",
434 .id_table = hibmc_pci_table,
435 .probe = hibmc_pci_probe,
436 .remove = hibmc_pci_remove,
437 .shutdown = hibmc_pci_shutdown,
438 .driver.pm = &hibmc_pm_ops,
439 };
440
441 drm_module_pci_driver(hibmc_pci_driver);
442
443 MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
444 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
445 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
446 MODULE_LICENSE("GPL v2");
447