1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-common.h" 28 #include "exec/cpu-defs.h" 29 #include "exec/cpu-interrupt.h" 30 #include "exec/gdbstub.h" 31 #include "exec/page-protection.h" 32 #include "qapi/qapi-types-common.h" 33 #include "target/arm/multiprocessing.h" 34 #include "target/arm/gtimer.h" 35 #include "target/arm/cpu-sysregs.h" 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 61 #define EXCP_NMI 26 62 #define EXCP_VINMI 27 63 #define EXCP_VFNMI 28 64 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ 65 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 66 67 #define ARMV7M_EXCP_RESET 1 68 #define ARMV7M_EXCP_NMI 2 69 #define ARMV7M_EXCP_HARD 3 70 #define ARMV7M_EXCP_MEM 4 71 #define ARMV7M_EXCP_BUS 5 72 #define ARMV7M_EXCP_USAGE 6 73 #define ARMV7M_EXCP_SECURE 7 74 #define ARMV7M_EXCP_SVC 11 75 #define ARMV7M_EXCP_DEBUG 12 76 #define ARMV7M_EXCP_PENDSV 14 77 #define ARMV7M_EXCP_SYSTICK 15 78 79 /* ARM-specific interrupt pending bits. */ 80 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 81 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 82 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 83 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 84 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 85 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 86 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 87 88 /* The usual mapping for an AArch64 system register to its AArch32 89 * counterpart is for the 32 bit world to have access to the lower 90 * half only (with writes leaving the upper half untouched). It's 91 * therefore useful to be able to pass TCG the offset of the least 92 * significant half of a uint64_t struct member. 93 */ 94 #if HOST_BIG_ENDIAN 95 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 96 #define offsetofhigh32(S, M) offsetof(S, M) 97 #else 98 #define offsetoflow32(S, M) offsetof(S, M) 99 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 100 #endif 101 102 /* The 2nd extra word holding syndrome info for data aborts does not use 103 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 104 * help the sleb128 encoder do a better job. 105 * When restoring the CPU state, we shift it back up. 106 */ 107 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 108 #define ARM_INSN_START_WORD2_SHIFT 13 109 110 /* We currently assume float and double are IEEE single and double 111 precision respectively. 112 Doing runtime conversions is tricky because VFP registers may contain 113 integer values (eg. as the result of a FTOSI instruction). 114 s<2n> maps to the least significant half of d<n> 115 s<2n+1> maps to the most significant half of d<n> 116 */ 117 118 /** 119 * DynamicGDBFeatureInfo: 120 * @desc: Contains the feature descriptions. 121 * @data: A union with data specific to the set of registers 122 * @cpregs_keys: Array that contains the corresponding Key of 123 * a given cpreg with the same order of the cpreg 124 * in the XML description. 125 */ 126 typedef struct DynamicGDBFeatureInfo { 127 GDBFeature desc; 128 union { 129 struct { 130 uint32_t *keys; 131 } cpregs; 132 } data; 133 } DynamicGDBFeatureInfo; 134 135 /* CPU state for each instance of a generic timer (in cp15 c14) */ 136 typedef struct ARMGenericTimer { 137 uint64_t cval; /* Timer CompareValue register */ 138 uint64_t ctl; /* Timer Control register */ 139 } ARMGenericTimer; 140 141 /* Define a maximum sized vector register. 142 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 143 * For 64-bit, this is a 2048-bit SVE register. 144 * 145 * Note that the mapping between S, D, and Q views of the register bank 146 * differs between AArch64 and AArch32. 147 * In AArch32: 148 * Qn = regs[n].d[1]:regs[n].d[0] 149 * Dn = regs[n / 2].d[n & 1] 150 * Sn = regs[n / 4].d[n % 4 / 2], 151 * bits 31..0 for even n, and bits 63..32 for odd n 152 * (and regs[16] to regs[31] are inaccessible) 153 * In AArch64: 154 * Zn = regs[n].d[*] 155 * Qn = regs[n].d[1]:regs[n].d[0] 156 * Dn = regs[n].d[0] 157 * Sn = regs[n].d[0] bits 31..0 158 * Hn = regs[n].d[0] bits 15..0 159 * 160 * This corresponds to the architecturally defined mapping between 161 * the two execution states, and means we do not need to explicitly 162 * map these registers when changing states. 163 * 164 * Align the data for use with TCG host vector operations. 165 */ 166 167 #define ARM_MAX_VQ 16 168 169 typedef struct ARMVectorReg { 170 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 171 } ARMVectorReg; 172 173 /* In AArch32 mode, predicate registers do not exist at all. */ 174 typedef struct ARMPredicateReg { 175 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 176 } ARMPredicateReg; 177 178 /* In AArch32 mode, PAC keys do not exist at all. */ 179 typedef struct ARMPACKey { 180 uint64_t lo, hi; 181 } ARMPACKey; 182 183 /* See the commentary above the TBFLAG field definitions. */ 184 typedef struct CPUARMTBFlags { 185 uint32_t flags; 186 uint64_t flags2; 187 } CPUARMTBFlags; 188 189 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 190 191 typedef struct NVICState NVICState; 192 193 /* 194 * Enum for indexing vfp.fp_status[]. 195 * 196 * FPST_A32: is the "normal" fp status for AArch32 insns 197 * FPST_A64: is the "normal" fp status for AArch64 insns 198 * FPST_A32_F16: used for AArch32 half-precision calculations 199 * FPST_A64_F16: used for AArch64 half-precision calculations 200 * FPST_STD: the ARM "Standard FPSCR Value" 201 * FPST_STD_F16: used for half-precision 202 * calculations with the ARM "Standard FPSCR Value" 203 * FPST_AH: used for the A64 insns which change behaviour 204 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 205 * and the reciprocal and square root estimate/step insns) 206 * FPST_AH_F16: used for the A64 insns which change behaviour 207 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 208 * and the reciprocal and square root estimate/step insns); 209 * for half-precision 210 * ZA: the "streaming sve" fp status. 211 * ZA_F16: likewise for half-precision. 212 * 213 * Half-precision operations are governed by a separate 214 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 215 * status structure to control this. 216 * 217 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 218 * round-to-nearest and is used by any operations (generally 219 * Neon) which the architecture defines as controlled by the 220 * standard FPSCR value rather than the FPSCR. 221 * 222 * The "standard FPSCR but for fp16 ops" is needed because 223 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 224 * using a fixed value for it. 225 * 226 * FPST_AH is needed because some insns have different 227 * behaviour when FPCR.AH == 1: they don't update cumulative 228 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and 229 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, 230 * which means we need an FPST_AH_F16 as well. 231 * 232 * The "ZA" float_status are for Streaming SVE operations which use 233 * default-NaN and do not generate fp exceptions, which means that they 234 * do not accumulate exception bits back into FPCR. 235 * See e.g. FPAdd vs FPAdd_ZA pseudocode functions, and the setting 236 * of fpcr.DN and fpexec parameters. 237 * 238 * To avoid having to transfer exception bits around, we simply 239 * say that the FPSCR cumulative exception flags are the logical 240 * OR of the flags in the four fp statuses. This relies on the 241 * only thing which needs to read the exception flags being 242 * an explicit FPSCR read. 243 */ 244 typedef enum ARMFPStatusFlavour { 245 FPST_A32, 246 FPST_A64, 247 FPST_A32_F16, 248 FPST_A64_F16, 249 FPST_AH, 250 FPST_AH_F16, 251 FPST_ZA, 252 FPST_ZA_F16, 253 FPST_STD, 254 FPST_STD_F16, 255 } ARMFPStatusFlavour; 256 #define FPST_COUNT 10 257 258 typedef struct CPUArchState { 259 /* Regs for current mode. */ 260 uint32_t regs[16]; 261 262 /* 32/64 switch only happens when taking and returning from 263 * exceptions so the overlap semantics are taken care of then 264 * instead of having a complicated union. 265 */ 266 /* Regs for A64 mode. */ 267 uint64_t xregs[32]; 268 uint64_t pc; 269 /* PSTATE isn't an architectural register for ARMv8. However, it is 270 * convenient for us to assemble the underlying state into a 32 bit format 271 * identical to the architectural format used for the SPSR. (This is also 272 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 273 * 'pstate' register are.) Of the PSTATE bits: 274 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 275 * semantics as for AArch32, as described in the comments on each field) 276 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 277 * DAIF (exception masks) are kept in env->daif 278 * BTYPE is kept in env->btype 279 * SM and ZA are kept in env->svcr 280 * all other bits are stored in their correct places in env->pstate 281 */ 282 uint32_t pstate; 283 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 284 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 285 286 /* Cached TBFLAGS state. See below for which bits are included. */ 287 CPUARMTBFlags hflags; 288 289 /* Frequently accessed CPSR bits are stored separately for efficiency. 290 This contains all the other bits. Use cpsr_{read,write} to access 291 the whole CPSR. */ 292 uint32_t uncached_cpsr; 293 uint32_t spsr; 294 295 /* Banked registers. */ 296 uint64_t banked_spsr[8]; 297 uint32_t banked_r13[8]; 298 uint32_t banked_r14[8]; 299 300 /* These hold r8-r12. */ 301 uint32_t usr_regs[5]; 302 uint32_t fiq_regs[5]; 303 304 /* cpsr flag cache for faster execution */ 305 uint32_t CF; /* 0 or 1 */ 306 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 307 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 308 uint32_t ZF; /* Z set if zero. */ 309 uint32_t QF; /* 0 or 1 */ 310 uint32_t GE; /* cpsr[19:16] */ 311 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 312 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 313 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 314 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 315 316 uint64_t elr_el[4]; /* AArch64 exception link regs */ 317 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 318 319 /* System control coprocessor (cp15) */ 320 struct { 321 uint32_t c0_cpuid; 322 union { /* Cache size selection */ 323 struct { 324 uint64_t _unused_csselr0; 325 uint64_t csselr_ns; 326 uint64_t _unused_csselr1; 327 uint64_t csselr_s; 328 }; 329 uint64_t csselr_el[4]; 330 }; 331 union { /* System control register. */ 332 struct { 333 uint64_t _unused_sctlr; 334 uint64_t sctlr_ns; 335 uint64_t hsctlr; 336 uint64_t sctlr_s; 337 }; 338 uint64_t sctlr_el[4]; 339 }; 340 uint64_t vsctlr; /* Virtualization System control register. */ 341 uint64_t cpacr_el1; /* Architectural feature access control register */ 342 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 343 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 344 uint64_t sder; /* Secure debug enable register. */ 345 uint32_t nsacr; /* Non-secure access control register. */ 346 union { /* MMU translation table base 0. */ 347 struct { 348 uint64_t _unused_ttbr0_0; 349 uint64_t ttbr0_ns; 350 uint64_t _unused_ttbr0_1; 351 uint64_t ttbr0_s; 352 }; 353 uint64_t ttbr0_el[4]; 354 }; 355 union { /* MMU translation table base 1. */ 356 struct { 357 uint64_t _unused_ttbr1_0; 358 uint64_t ttbr1_ns; 359 uint64_t _unused_ttbr1_1; 360 uint64_t ttbr1_s; 361 }; 362 uint64_t ttbr1_el[4]; 363 }; 364 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 365 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 366 /* MMU translation table base control. */ 367 uint64_t tcr_el[4]; 368 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 369 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 370 uint32_t c2_data; /* MPU data cacheable bits. */ 371 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 372 union { /* MMU domain access control register 373 * MPU write buffer control. 374 */ 375 struct { 376 uint64_t dacr_ns; 377 uint64_t dacr_s; 378 }; 379 struct { 380 uint64_t dacr32_el2; 381 }; 382 }; 383 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 384 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 385 uint64_t hcr_el2; /* Hypervisor configuration register */ 386 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 387 uint64_t scr_el3; /* Secure configuration register. */ 388 union { /* Fault status registers. */ 389 struct { 390 uint64_t ifsr_ns; 391 uint64_t ifsr_s; 392 }; 393 struct { 394 uint64_t ifsr32_el2; 395 }; 396 }; 397 union { 398 struct { 399 uint64_t _unused_dfsr; 400 uint64_t dfsr_ns; 401 uint64_t hsr; 402 uint64_t dfsr_s; 403 }; 404 uint64_t esr_el[4]; 405 }; 406 uint32_t c6_region[8]; /* MPU base/size registers. */ 407 union { /* Fault address registers. */ 408 struct { 409 uint64_t _unused_far0; 410 #if HOST_BIG_ENDIAN 411 uint32_t ifar_ns; 412 uint32_t dfar_ns; 413 uint32_t ifar_s; 414 uint32_t dfar_s; 415 #else 416 uint32_t dfar_ns; 417 uint32_t ifar_ns; 418 uint32_t dfar_s; 419 uint32_t ifar_s; 420 #endif 421 uint64_t _unused_far3; 422 }; 423 uint64_t far_el[4]; 424 }; 425 uint64_t hpfar_el2; 426 uint64_t hstr_el2; 427 union { /* Translation result. */ 428 struct { 429 uint64_t _unused_par_0; 430 uint64_t par_ns; 431 uint64_t _unused_par_1; 432 uint64_t par_s; 433 }; 434 uint64_t par_el[4]; 435 }; 436 437 uint32_t c9_insn; /* Cache lockdown registers. */ 438 uint32_t c9_data; 439 uint64_t c9_pmcr; /* performance monitor control register */ 440 uint64_t c9_pmcnten; /* perf monitor counter enables */ 441 uint64_t c9_pmovsr; /* perf monitor overflow status */ 442 uint64_t c9_pmuserenr; /* perf monitor user enable */ 443 uint64_t c9_pmselr; /* perf monitor counter selection register */ 444 uint64_t c9_pminten; /* perf monitor interrupt enables */ 445 union { /* Memory attribute redirection */ 446 struct { 447 #if HOST_BIG_ENDIAN 448 uint64_t _unused_mair_0; 449 uint32_t mair1_ns; 450 uint32_t mair0_ns; 451 uint64_t _unused_mair_1; 452 uint32_t mair1_s; 453 uint32_t mair0_s; 454 #else 455 uint64_t _unused_mair_0; 456 uint32_t mair0_ns; 457 uint32_t mair1_ns; 458 uint64_t _unused_mair_1; 459 uint32_t mair0_s; 460 uint32_t mair1_s; 461 #endif 462 }; 463 uint64_t mair_el[4]; 464 }; 465 union { /* vector base address register */ 466 struct { 467 uint64_t _unused_vbar; 468 uint64_t vbar_ns; 469 uint64_t hvbar; 470 uint64_t vbar_s; 471 }; 472 uint64_t vbar_el[4]; 473 }; 474 uint32_t mvbar; /* (monitor) vector base address register */ 475 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 476 struct { /* FCSE PID. */ 477 uint32_t fcseidr_ns; 478 uint32_t fcseidr_s; 479 }; 480 union { /* Context ID. */ 481 struct { 482 uint64_t _unused_contextidr_0; 483 uint64_t contextidr_ns; 484 uint64_t _unused_contextidr_1; 485 uint64_t contextidr_s; 486 }; 487 uint64_t contextidr_el[4]; 488 }; 489 union { /* User RW Thread register. */ 490 struct { 491 uint64_t tpidrurw_ns; 492 uint64_t tpidrprw_ns; 493 uint64_t htpidr; 494 uint64_t _tpidr_el3; 495 }; 496 uint64_t tpidr_el[4]; 497 }; 498 uint64_t tpidr2_el0; 499 /* The secure banks of these registers don't map anywhere */ 500 uint64_t tpidrurw_s; 501 uint64_t tpidrprw_s; 502 uint64_t tpidruro_s; 503 504 union { /* User RO Thread register. */ 505 uint64_t tpidruro_ns; 506 uint64_t tpidrro_el[1]; 507 }; 508 uint64_t c14_cntfrq; /* Counter Frequency register */ 509 uint64_t c14_cntkctl; /* Timer Control register */ 510 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 511 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 512 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 513 ARMGenericTimer c14_timer[NUM_GTIMERS]; 514 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 515 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 516 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 517 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 518 uint32_t c15_threadid; /* TI debugger thread-ID. */ 519 uint32_t c15_config_base_address; /* SCU base address. */ 520 uint32_t c15_diagnostic; /* diagnostic register */ 521 uint32_t c15_power_diagnostic; 522 uint32_t c15_power_control; /* power control */ 523 uint64_t dbgbvr[16]; /* breakpoint value registers */ 524 uint64_t dbgbcr[16]; /* breakpoint control registers */ 525 uint64_t dbgwvr[16]; /* watchpoint value registers */ 526 uint64_t dbgwcr[16]; /* watchpoint control registers */ 527 uint64_t dbgclaim; /* DBGCLAIM bits */ 528 uint64_t mdscr_el1; 529 uint64_t oslsr_el1; /* OS Lock Status */ 530 uint64_t osdlr_el1; /* OS DoubleLock status */ 531 uint64_t mdcr_el2; 532 uint64_t mdcr_el3; 533 /* Stores the architectural value of the counter *the last time it was 534 * updated* by pmccntr_op_start. Accesses should always be surrounded 535 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 536 * architecturally-correct value is being read/set. 537 */ 538 uint64_t c15_ccnt; 539 /* Stores the delta between the architectural value and the underlying 540 * cycle count during normal operation. It is used to update c15_ccnt 541 * to be the correct architectural value before accesses. During 542 * accesses, c15_ccnt_delta contains the underlying count being used 543 * for the access, after which it reverts to the delta value in 544 * pmccntr_op_finish. 545 */ 546 uint64_t c15_ccnt_delta; 547 uint64_t c14_pmevcntr[31]; 548 uint64_t c14_pmevcntr_delta[31]; 549 uint64_t c14_pmevtyper[31]; 550 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 551 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 552 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 553 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 554 uint64_t gcr_el1; 555 uint64_t rgsr_el1; 556 557 /* Minimal RAS registers */ 558 uint64_t disr_el1; 559 uint64_t vdisr_el2; 560 uint64_t vsesr_el2; 561 562 /* 563 * Fine-Grained Trap registers. We store these as arrays so the 564 * access checking code doesn't have to manually select 565 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 566 * FEAT_FGT2 will add more elements to these arrays. 567 */ 568 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 569 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 570 uint64_t fgt_exec[1]; /* HFGITR */ 571 572 /* RME registers */ 573 uint64_t gpccr_el3; 574 uint64_t gptbr_el3; 575 uint64_t mfar_el3; 576 577 /* NV2 register */ 578 uint64_t vncr_el2; 579 } cp15; 580 581 struct { 582 /* M profile has up to 4 stack pointers: 583 * a Main Stack Pointer and a Process Stack Pointer for each 584 * of the Secure and Non-Secure states. (If the CPU doesn't support 585 * the security extension then it has only two SPs.) 586 * In QEMU we always store the currently active SP in regs[13], 587 * and the non-active SP for the current security state in 588 * v7m.other_sp. The stack pointers for the inactive security state 589 * are stored in other_ss_msp and other_ss_psp. 590 * switch_v7m_security_state() is responsible for rearranging them 591 * when we change security state. 592 */ 593 uint32_t other_sp; 594 uint32_t other_ss_msp; 595 uint32_t other_ss_psp; 596 uint32_t vecbase[M_REG_NUM_BANKS]; 597 uint32_t basepri[M_REG_NUM_BANKS]; 598 uint32_t control[M_REG_NUM_BANKS]; 599 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 600 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 601 uint32_t hfsr; /* HardFault Status */ 602 uint32_t dfsr; /* Debug Fault Status Register */ 603 uint32_t sfsr; /* Secure Fault Status Register */ 604 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 605 uint32_t bfar; /* BusFault Address */ 606 uint32_t sfar; /* Secure Fault Address Register */ 607 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 608 int exception; 609 uint32_t primask[M_REG_NUM_BANKS]; 610 uint32_t faultmask[M_REG_NUM_BANKS]; 611 uint32_t aircr; /* only holds r/w state if security extn implemented */ 612 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 613 uint32_t csselr[M_REG_NUM_BANKS]; 614 uint32_t scr[M_REG_NUM_BANKS]; 615 uint32_t msplim[M_REG_NUM_BANKS]; 616 uint32_t psplim[M_REG_NUM_BANKS]; 617 uint32_t fpcar[M_REG_NUM_BANKS]; 618 uint32_t fpccr[M_REG_NUM_BANKS]; 619 uint32_t fpdscr[M_REG_NUM_BANKS]; 620 uint32_t cpacr[M_REG_NUM_BANKS]; 621 uint32_t nsacr; 622 uint32_t ltpsize; 623 uint32_t vpr; 624 } v7m; 625 626 /* Information associated with an exception about to be taken: 627 * code which raises an exception must set cs->exception_index and 628 * the relevant parts of this structure; the cpu_do_interrupt function 629 * will then set the guest-visible registers as part of the exception 630 * entry process. 631 */ 632 struct { 633 uint32_t syndrome; /* AArch64 format syndrome register */ 634 uint32_t fsr; /* AArch32 format fault status register info */ 635 uint64_t vaddress; /* virtual addr associated with exception, if any */ 636 uint32_t target_el; /* EL the exception should be targeted for */ 637 /* If we implement EL2 we will also need to store information 638 * about the intermediate physical address for stage 2 faults. 639 */ 640 } exception; 641 642 /* Information associated with an SError */ 643 struct { 644 uint8_t pending; 645 uint8_t has_esr; 646 uint64_t esr; 647 } serror; 648 649 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 650 651 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 652 uint32_t irq_line_state; 653 654 /* Thumb-2 EE state. */ 655 uint32_t teecr; 656 uint32_t teehbr; 657 658 /* VFP coprocessor state. */ 659 struct { 660 ARMVectorReg zregs[32]; 661 662 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 663 #define FFR_PRED_NUM 16 664 ARMPredicateReg pregs[17]; 665 /* Scratch space for aa64 sve predicate temporary. */ 666 ARMPredicateReg preg_tmp; 667 668 /* We store these fpcsr fields separately for convenience. */ 669 uint32_t qc[4] QEMU_ALIGNED(16); 670 int vec_len; 671 int vec_stride; 672 673 /* 674 * Floating point status and control registers. Some bits are 675 * stored separately in other fields or in the float_status below. 676 */ 677 uint64_t fpsr; 678 uint64_t fpcr; 679 680 uint32_t xregs[16]; 681 682 /* There are a number of distinct float control structures. */ 683 float_status fp_status[FPST_COUNT]; 684 685 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 686 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 687 } vfp; 688 689 uint64_t exclusive_addr; 690 uint64_t exclusive_val; 691 /* 692 * Contains the 'val' for the second 64-bit register of LDXP, which comes 693 * from the higher address, not the high part of a complete 128-bit value. 694 * In some ways it might be more convenient to record the exclusive value 695 * as the low and high halves of a 128 bit data value, but the current 696 * semantics of these fields are baked into the migration format. 697 */ 698 uint64_t exclusive_high; 699 700 /* iwMMXt coprocessor state. */ 701 struct { 702 uint64_t regs[16]; 703 uint64_t val; 704 705 uint32_t cregs[16]; 706 } iwmmxt; 707 708 struct { 709 ARMPACKey apia; 710 ARMPACKey apib; 711 ARMPACKey apda; 712 ARMPACKey apdb; 713 ARMPACKey apga; 714 } keys; 715 716 uint64_t scxtnum_el[4]; 717 718 struct { 719 /* SME2 ZT0 -- 512 bit array, with data ordered like ARMVectorReg. */ 720 uint64_t zt0[512 / 64] QEMU_ALIGNED(16); 721 722 /* 723 * SME ZA storage -- 256 x 256 byte array, with bytes in host 724 * word order, as we do with vfp.zregs[]. This corresponds to 725 * the architectural ZA array, where ZA[N] is in the least 726 * significant bytes of env->za_state.za[N]. 727 * 728 * When SVL is less than the architectural maximum, the accessible 729 * storage is restricted, such that if the SVL is X bytes the guest 730 * can see only the bottom X elements of zarray[], and only the least 731 * significant X bytes of each element of the array. (In other words, 732 * the observable part is always square.) 733 * 734 * The ZA storage can also be considered as a set of square tiles of 735 * elements of different sizes. The mapping from tiles to the ZA array 736 * is architecturally defined, such that for tiles of elements of esz 737 * bytes, the Nth row (or "horizontal slice") of tile T is in 738 * ZA[T + N * esz]. Note that this means that each tile is not 739 * contiguous in the ZA storage, because its rows are striped through 740 * the ZA array. 741 * 742 * Because this is so large, keep this toward the end of the 743 * reset area, to keep the offsets into the rest of the structure 744 * smaller. 745 */ 746 ARMVectorReg za[ARM_MAX_VQ * 16]; 747 } za_state; 748 749 struct CPUBreakpoint *cpu_breakpoint[16]; 750 struct CPUWatchpoint *cpu_watchpoint[16]; 751 752 /* Optional fault info across tlb lookup. */ 753 ARMMMUFaultInfo *tlb_fi; 754 755 /* Fields up to this point are cleared by a CPU reset */ 756 struct {} end_reset_fields; 757 758 /* Fields after this point are preserved across CPU reset. */ 759 760 /* Internal CPU feature flags. */ 761 uint64_t features; 762 763 /* PMSAv7 MPU */ 764 struct { 765 uint32_t *drbar; 766 uint32_t *drsr; 767 uint32_t *dracr; 768 uint32_t rnr[M_REG_NUM_BANKS]; 769 } pmsav7; 770 771 /* PMSAv8 MPU */ 772 struct { 773 /* The PMSAv8 implementation also shares some PMSAv7 config 774 * and state: 775 * pmsav7.rnr (region number register) 776 * pmsav7_dregion (number of configured regions) 777 */ 778 uint32_t *rbar[M_REG_NUM_BANKS]; 779 uint32_t *rlar[M_REG_NUM_BANKS]; 780 uint32_t *hprbar; 781 uint32_t *hprlar; 782 uint32_t mair0[M_REG_NUM_BANKS]; 783 uint32_t mair1[M_REG_NUM_BANKS]; 784 uint32_t hprselr; 785 } pmsav8; 786 787 /* v8M SAU */ 788 struct { 789 uint32_t *rbar; 790 uint32_t *rlar; 791 uint32_t rnr; 792 uint32_t ctrl; 793 } sau; 794 795 #if !defined(CONFIG_USER_ONLY) 796 NVICState *nvic; 797 const struct arm_boot_info *boot_info; 798 /* Store GICv3CPUState to access from this struct */ 799 void *gicv3state; 800 #else /* CONFIG_USER_ONLY */ 801 /* For usermode syscall translation. */ 802 bool eabi; 803 /* Linux syscall tagged address support */ 804 bool tagged_addr_enable; 805 #endif /* CONFIG_USER_ONLY */ 806 } CPUARMState; 807 808 static inline void set_feature(CPUARMState *env, int feature) 809 { 810 env->features |= 1ULL << feature; 811 } 812 813 static inline void unset_feature(CPUARMState *env, int feature) 814 { 815 env->features &= ~(1ULL << feature); 816 } 817 818 /** 819 * ARMELChangeHookFn: 820 * type of a function which can be registered via arm_register_el_change_hook() 821 * to get callbacks when the CPU changes its exception level or mode. 822 */ 823 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 824 typedef struct ARMELChangeHook ARMELChangeHook; 825 struct ARMELChangeHook { 826 ARMELChangeHookFn *hook; 827 void *opaque; 828 QLIST_ENTRY(ARMELChangeHook) node; 829 }; 830 831 /* These values map onto the return values for 832 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 833 typedef enum ARMPSCIState { 834 PSCI_ON = 0, 835 PSCI_OFF = 1, 836 PSCI_ON_PENDING = 2 837 } ARMPSCIState; 838 839 typedef struct ARMISARegisters ARMISARegisters; 840 841 /* 842 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 843 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 844 * 845 * While processing properties during initialization, corresponding init bits 846 * are set for bits in sve_vq_map that have been set by properties. 847 * 848 * Bits set in supported represent valid vector lengths for the CPU type. 849 */ 850 typedef struct { 851 uint32_t map, init, supported; 852 } ARMVQMap; 853 854 /* REG is ID_XXX */ 855 #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ 856 ({ \ 857 ARMISARegisters *i_ = (ISAR); \ 858 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \ 859 regval = FIELD_DP64(regval, REG, FIELD, VALUE); \ 860 i_->idregs[REG ## _EL1_IDX] = regval; \ 861 }) 862 863 #define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \ 864 ({ \ 865 ARMISARegisters *i_ = (ISAR); \ 866 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \ 867 regval = FIELD_DP32(regval, REG, FIELD, VALUE); \ 868 i_->idregs[REG ## _EL1_IDX] = regval; \ 869 }) 870 871 #define FIELD_EX64_IDREG(ISAR, REG, FIELD) \ 872 ({ \ 873 const ARMISARegisters *i_ = (ISAR); \ 874 FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 875 }) 876 877 #define FIELD_EX32_IDREG(ISAR, REG, FIELD) \ 878 ({ \ 879 const ARMISARegisters *i_ = (ISAR); \ 880 FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 881 }) 882 883 #define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \ 884 ({ \ 885 const ARMISARegisters *i_ = (ISAR); \ 886 FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 887 }) 888 889 #define SET_IDREG(ISAR, REG, VALUE) \ 890 ({ \ 891 ARMISARegisters *i_ = (ISAR); \ 892 i_->idregs[REG ## _EL1_IDX] = VALUE; \ 893 }) 894 895 #define GET_IDREG(ISAR, REG) \ 896 ({ \ 897 const ARMISARegisters *i_ = (ISAR); \ 898 i_->idregs[REG ## _EL1_IDX]; \ 899 }) 900 901 /** 902 * ARMCPU: 903 * @env: #CPUARMState 904 * 905 * An ARM CPU core. 906 */ 907 struct ArchCPU { 908 CPUState parent_obj; 909 910 CPUARMState env; 911 912 /* Coprocessor information */ 913 GHashTable *cp_regs; 914 /* For marshalling (mostly coprocessor) register state between the 915 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 916 * we use these arrays. 917 */ 918 /* List of register indexes managed via these arrays; (full KVM style 919 * 64 bit indexes, not CPRegInfo 32 bit indexes) 920 */ 921 uint64_t *cpreg_indexes; 922 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 923 uint64_t *cpreg_values; 924 /* Length of the indexes, values, reset_values arrays */ 925 int32_t cpreg_array_len; 926 /* These are used only for migration: incoming data arrives in 927 * these fields and is sanity checked in post_load before copying 928 * to the working data structures above. 929 */ 930 uint64_t *cpreg_vmstate_indexes; 931 uint64_t *cpreg_vmstate_values; 932 int32_t cpreg_vmstate_array_len; 933 934 DynamicGDBFeatureInfo dyn_sysreg_feature; 935 DynamicGDBFeatureInfo dyn_svereg_feature; 936 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 937 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 938 939 /* Timers used by the generic (architected) timer */ 940 QEMUTimer *gt_timer[NUM_GTIMERS]; 941 /* 942 * Timer used by the PMU. Its state is restored after migration by 943 * pmu_op_finish() - it does not need other handling during migration 944 */ 945 QEMUTimer *pmu_timer; 946 /* Timer used for WFxT timeouts */ 947 QEMUTimer *wfxt_timer; 948 949 /* GPIO outputs for generic timer */ 950 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 951 /* GPIO output for GICv3 maintenance interrupt signal */ 952 qemu_irq gicv3_maintenance_interrupt; 953 /* GPIO output for the PMU interrupt */ 954 qemu_irq pmu_interrupt; 955 956 /* MemoryRegion to use for secure physical accesses */ 957 MemoryRegion *secure_memory; 958 959 /* MemoryRegion to use for allocation tag accesses */ 960 MemoryRegion *tag_memory; 961 MemoryRegion *secure_tag_memory; 962 963 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 964 Object *idau; 965 966 /* 'compatible' string for this CPU for Linux device trees */ 967 const char *dtb_compatible; 968 969 /* PSCI version for this CPU 970 * Bits[31:16] = Major Version 971 * Bits[15:0] = Minor Version 972 */ 973 uint32_t psci_version; 974 975 /* Current power state, access guarded by BQL */ 976 ARMPSCIState power_state; 977 978 /* CPU has virtualization extension */ 979 bool has_el2; 980 /* CPU has security extension */ 981 bool has_el3; 982 /* CPU has PMU (Performance Monitor Unit) */ 983 bool has_pmu; 984 /* CPU has VFP */ 985 bool has_vfp; 986 /* CPU has 32 VFP registers */ 987 bool has_vfp_d32; 988 /* CPU has Neon */ 989 bool has_neon; 990 /* CPU has M-profile DSP extension */ 991 bool has_dsp; 992 993 /* CPU has memory protection unit */ 994 bool has_mpu; 995 /* CPU has MTE enabled in KVM mode */ 996 bool kvm_mte; 997 /* PMSAv7 MPU number of supported regions */ 998 uint32_t pmsav7_dregion; 999 /* PMSAv8 MPU number of supported hyp regions */ 1000 uint32_t pmsav8r_hdregion; 1001 /* v8M SAU number of supported regions */ 1002 uint32_t sau_sregion; 1003 1004 /* PSCI conduit used to invoke PSCI methods 1005 * 0 - disabled, 1 - smc, 2 - hvc 1006 */ 1007 uint32_t psci_conduit; 1008 1009 /* For v8M, initial value of the Secure VTOR */ 1010 uint32_t init_svtor; 1011 /* For v8M, initial value of the Non-secure VTOR */ 1012 uint32_t init_nsvtor; 1013 1014 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 1015 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 1016 */ 1017 uint32_t kvm_target; 1018 1019 /* KVM init features for this CPU */ 1020 uint32_t kvm_init_features[7]; 1021 1022 /* KVM CPU state */ 1023 1024 /* KVM virtual time adjustment */ 1025 bool kvm_adjvtime; 1026 bool kvm_vtime_dirty; 1027 uint64_t kvm_vtime; 1028 1029 /* KVM steal time */ 1030 OnOffAuto kvm_steal_time; 1031 1032 /* Uniprocessor system with MP extensions */ 1033 bool mp_is_up; 1034 1035 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 1036 * and the probe failed (so we need to report the error in realize) 1037 */ 1038 bool host_cpu_probe_failed; 1039 1040 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 1041 bool backcompat_cntfrq; 1042 1043 /* QOM property to indicate we should use the back-compat QARMA5 default */ 1044 bool backcompat_pauth_default_use_qarma5; 1045 1046 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 1047 * register. 1048 */ 1049 int32_t core_count; 1050 1051 /* The instance init functions for implementation-specific subclasses 1052 * set these fields to specify the implementation-dependent values of 1053 * various constant registers and reset values of non-constant 1054 * registers. 1055 * Some of these might become QOM properties eventually. 1056 * Field names match the official register names as defined in the 1057 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 1058 * is used for reset values of non-constant registers; no reset_ 1059 * prefix means a constant register. 1060 * Some of these registers are split out into a substructure that 1061 * is shared with the translators to control the ISA. 1062 * 1063 * Note that if you add an ID register to the ARMISARegisters struct 1064 * you need to also update the 32-bit and 64-bit versions of the 1065 * kvm_arm_get_host_cpu_features() function to correctly populate the 1066 * field by reading the value from the KVM vCPU. 1067 */ 1068 struct ARMISARegisters { 1069 uint32_t mvfr0; 1070 uint32_t mvfr1; 1071 uint32_t mvfr2; 1072 uint32_t dbgdidr; 1073 uint32_t dbgdevid; 1074 uint32_t dbgdevid1; 1075 uint64_t reset_pmcr_el0; 1076 uint64_t idregs[NUM_ID_IDX]; 1077 } isar; 1078 uint64_t midr; 1079 uint32_t revidr; 1080 uint32_t reset_fpsid; 1081 uint64_t ctr; 1082 uint32_t reset_sctlr; 1083 uint64_t pmceid0; 1084 uint64_t pmceid1; 1085 uint32_t id_afr0; 1086 uint64_t id_aa64afr0; 1087 uint64_t id_aa64afr1; 1088 uint64_t clidr; 1089 uint64_t mp_affinity; /* MP ID without feature bits */ 1090 /* The elements of this array are the CCSIDR values for each cache, 1091 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1092 */ 1093 uint64_t ccsidr[16]; 1094 uint64_t reset_cbar; 1095 uint32_t reset_auxcr; 1096 bool reset_hivecs; 1097 uint8_t reset_l0gptsz; 1098 1099 /* 1100 * Intermediate values used during property parsing. 1101 * Once finalized, the values should be read from ID_AA64*. 1102 */ 1103 bool prop_pauth; 1104 bool prop_pauth_impdef; 1105 bool prop_pauth_qarma3; 1106 bool prop_pauth_qarma5; 1107 bool prop_lpa2; 1108 1109 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1110 uint8_t dcz_blocksize; 1111 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1112 uint8_t gm_blocksize; 1113 1114 uint64_t rvbar_prop; /* Property/input signals. */ 1115 1116 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1117 int gic_num_lrs; /* number of list registers */ 1118 int gic_vpribits; /* number of virtual priority bits */ 1119 int gic_vprebits; /* number of virtual preemption bits */ 1120 int gic_pribits; /* number of physical priority bits */ 1121 1122 /* Whether the cfgend input is high (i.e. this CPU should reset into 1123 * big-endian mode). This setting isn't used directly: instead it modifies 1124 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1125 * architecture version. 1126 */ 1127 bool cfgend; 1128 1129 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1130 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1131 1132 int32_t node_id; /* NUMA node this CPU belongs to */ 1133 1134 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1135 uint8_t device_irq_level; 1136 1137 /* Used to set the maximum vector length the cpu will support. */ 1138 uint32_t sve_max_vq; 1139 uint32_t sme_max_vq; 1140 1141 #ifdef CONFIG_USER_ONLY 1142 /* Used to set the default vector length at process start. */ 1143 uint32_t sve_default_vq; 1144 uint32_t sme_default_vq; 1145 #endif 1146 1147 ARMVQMap sve_vq; 1148 ARMVQMap sme_vq; 1149 1150 /* Generic timer counter frequency, in Hz */ 1151 uint64_t gt_cntfrq_hz; 1152 }; 1153 1154 typedef struct ARMCPUInfo { 1155 const char *name; 1156 const char *deprecation_note; 1157 void (*initfn)(Object *obj); 1158 void (*class_init)(ObjectClass *oc, const void *data); 1159 } ARMCPUInfo; 1160 1161 /** 1162 * ARMCPUClass: 1163 * @parent_realize: The parent class' realize handler. 1164 * @parent_phases: The parent class' reset phase handlers. 1165 * 1166 * An ARM CPU model. 1167 */ 1168 struct ARMCPUClass { 1169 CPUClass parent_class; 1170 1171 const ARMCPUInfo *info; 1172 DeviceRealize parent_realize; 1173 ResettablePhases parent_phases; 1174 }; 1175 1176 /* Callback functions for the generic timer's timers. */ 1177 void arm_gt_ptimer_cb(void *opaque); 1178 void arm_gt_vtimer_cb(void *opaque); 1179 void arm_gt_htimer_cb(void *opaque); 1180 void arm_gt_stimer_cb(void *opaque); 1181 void arm_gt_hvtimer_cb(void *opaque); 1182 void arm_gt_sel2timer_cb(void *opaque); 1183 void arm_gt_sel2vtimer_cb(void *opaque); 1184 1185 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1186 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1187 1188 #define ARM_AFF0_SHIFT 0 1189 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1190 #define ARM_AFF1_SHIFT 8 1191 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1192 #define ARM_AFF2_SHIFT 16 1193 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1194 #define ARM_AFF3_SHIFT 32 1195 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1196 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1197 1198 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1199 #define ARM64_AFFINITY_MASK \ 1200 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1201 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1202 1203 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1204 1205 #ifndef CONFIG_USER_ONLY 1206 extern const VMStateDescription vmstate_arm_cpu; 1207 1208 void arm_cpu_do_interrupt(CPUState *cpu); 1209 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1210 1211 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1212 MemTxAttrs *attrs); 1213 #endif /* !CONFIG_USER_ONLY */ 1214 1215 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1216 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1217 1218 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1219 int cpuid, DumpState *s); 1220 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1221 int cpuid, DumpState *s); 1222 1223 /** 1224 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1225 * @cpu: CPU (which must have been freshly reset) 1226 * @target_el: exception level to put the CPU into 1227 * @secure: whether to put the CPU in secure state 1228 * 1229 * When QEMU is directly running a guest kernel at a lower level than 1230 * EL3 it implicitly emulates some aspects of the guest firmware. 1231 * This includes that on reset we need to configure the parts of the 1232 * CPU corresponding to EL3 so that the real guest code can run at its 1233 * lower exception level. This function does that post-reset CPU setup, 1234 * for when we do direct boot of a guest kernel, and for when we 1235 * emulate PSCI and similar firmware interfaces starting a CPU at a 1236 * lower exception level. 1237 * 1238 * @target_el must be an EL implemented by the CPU between 1 and 3. 1239 * We do not support dropping into a Secure EL other than 3. 1240 * 1241 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1242 */ 1243 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1244 1245 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1246 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1247 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1248 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1249 int new_el, bool el0_a64); 1250 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1251 1252 /* 1253 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1254 * The byte at offset i from the start of the in-memory representation contains 1255 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1256 * lowest offsets are stored in the lowest memory addresses, then that nearly 1257 * matches QEMU's representation, which is to use an array of host-endian 1258 * uint64_t's, where the lower offsets are at the lower indices. To complete 1259 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1260 */ 1261 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1262 { 1263 #if HOST_BIG_ENDIAN 1264 int i; 1265 1266 for (i = 0; i < nr; ++i) { 1267 dst[i] = bswap64(src[i]); 1268 } 1269 1270 return dst; 1271 #else 1272 return src; 1273 #endif 1274 } 1275 1276 void aarch64_sync_32_to_64(CPUARMState *env); 1277 void aarch64_sync_64_to_32(CPUARMState *env); 1278 1279 int fp_exception_el(CPUARMState *env, int cur_el); 1280 int sve_exception_el(CPUARMState *env, int cur_el); 1281 int sme_exception_el(CPUARMState *env, int cur_el); 1282 1283 /** 1284 * sve_vqm1_for_el_sm: 1285 * @env: CPUARMState 1286 * @el: exception level 1287 * @sm: streaming mode 1288 * 1289 * Compute the current vector length for @el & @sm, in units of 1290 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1291 * If @sm, compute for SVL, otherwise NVL. 1292 */ 1293 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1294 1295 /* Likewise, but using @sm = PSTATE.SM. */ 1296 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1297 1298 static inline bool is_a64(CPUARMState *env) 1299 { 1300 return env->aarch64; 1301 } 1302 1303 /** 1304 * pmu_op_start/finish 1305 * @env: CPUARMState 1306 * 1307 * Convert all PMU counters between their delta form (the typical mode when 1308 * they are enabled) and the guest-visible values. These two calls must 1309 * surround any action which might affect the counters. 1310 */ 1311 void pmu_op_start(CPUARMState *env); 1312 void pmu_op_finish(CPUARMState *env); 1313 1314 /* 1315 * Called when a PMU counter is due to overflow 1316 */ 1317 void arm_pmu_timer_cb(void *opaque); 1318 1319 /** 1320 * Functions to register as EL change hooks for PMU mode filtering 1321 */ 1322 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1323 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1324 1325 /* 1326 * pmu_init 1327 * @cpu: ARMCPU 1328 * 1329 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1330 * for the current configuration 1331 */ 1332 void pmu_init(ARMCPU *cpu); 1333 1334 /* SCTLR bit meanings. Several bits have been reused in newer 1335 * versions of the architecture; in that case we define constants 1336 * for both old and new bit meanings. Code which tests against those 1337 * bits should probably check or otherwise arrange that the CPU 1338 * is the architectural version it expects. 1339 */ 1340 #define SCTLR_M (1U << 0) 1341 #define SCTLR_A (1U << 1) 1342 #define SCTLR_C (1U << 2) 1343 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1344 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1345 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1346 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1347 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1348 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1349 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1350 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1351 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1352 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1353 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1354 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1355 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1356 #define SCTLR_SED (1U << 8) /* v8 onward */ 1357 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1358 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1359 #define SCTLR_F (1U << 10) /* up to v6 */ 1360 #define SCTLR_SW (1U << 10) /* v7 */ 1361 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1362 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1363 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1364 #define SCTLR_I (1U << 12) 1365 #define SCTLR_V (1U << 13) /* AArch32 only */ 1366 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1367 #define SCTLR_RR (1U << 14) /* up to v7 */ 1368 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1369 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1370 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1371 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1372 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1373 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1374 #define SCTLR_BR (1U << 17) /* PMSA only */ 1375 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1376 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1377 #define SCTLR_WXN (1U << 19) 1378 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1379 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1380 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1381 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1382 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1383 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1384 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1385 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1386 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1387 #define SCTLR_VE (1U << 24) /* up to v7 */ 1388 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1389 #define SCTLR_EE (1U << 25) 1390 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1391 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1392 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1393 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1394 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1395 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1396 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1397 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1398 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1399 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1400 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1401 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1402 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */ 1403 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1404 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1405 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1406 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1407 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1408 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1409 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1410 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1411 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1412 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1413 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1414 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1415 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1416 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1417 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1418 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1419 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1420 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1421 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1422 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1423 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1424 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1425 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1426 1427 #define CPSR_M (0x1fU) 1428 #define CPSR_T (1U << 5) 1429 #define CPSR_F (1U << 6) 1430 #define CPSR_I (1U << 7) 1431 #define CPSR_A (1U << 8) 1432 #define CPSR_E (1U << 9) 1433 #define CPSR_IT_2_7 (0xfc00U) 1434 #define CPSR_GE (0xfU << 16) 1435 #define CPSR_IL (1U << 20) 1436 #define CPSR_DIT (1U << 21) 1437 #define CPSR_PAN (1U << 22) 1438 #define CPSR_SSBS (1U << 23) 1439 #define CPSR_J (1U << 24) 1440 #define CPSR_IT_0_1 (3U << 25) 1441 #define CPSR_Q (1U << 27) 1442 #define CPSR_V (1U << 28) 1443 #define CPSR_C (1U << 29) 1444 #define CPSR_Z (1U << 30) 1445 #define CPSR_N (1U << 31) 1446 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1447 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1448 #define ISR_FS (1U << 9) 1449 #define ISR_IS (1U << 10) 1450 1451 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1452 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1453 | CPSR_NZCV) 1454 /* Bits writable in user mode. */ 1455 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1456 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1457 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1458 1459 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1460 #define XPSR_EXCP 0x1ffU 1461 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1462 #define XPSR_IT_2_7 CPSR_IT_2_7 1463 #define XPSR_GE CPSR_GE 1464 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1465 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1466 #define XPSR_IT_0_1 CPSR_IT_0_1 1467 #define XPSR_Q CPSR_Q 1468 #define XPSR_V CPSR_V 1469 #define XPSR_C CPSR_C 1470 #define XPSR_Z CPSR_Z 1471 #define XPSR_N CPSR_N 1472 #define XPSR_NZCV CPSR_NZCV 1473 #define XPSR_IT CPSR_IT 1474 1475 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1476 * Only these are valid when in AArch64 mode; in 1477 * AArch32 mode SPSRs are basically CPSR-format. 1478 */ 1479 #define PSTATE_SP (1U) 1480 #define PSTATE_M (0xFU) 1481 #define PSTATE_nRW (1U << 4) 1482 #define PSTATE_F (1U << 6) 1483 #define PSTATE_I (1U << 7) 1484 #define PSTATE_A (1U << 8) 1485 #define PSTATE_D (1U << 9) 1486 #define PSTATE_BTYPE (3U << 10) 1487 #define PSTATE_SSBS (1U << 12) 1488 #define PSTATE_ALLINT (1U << 13) 1489 #define PSTATE_IL (1U << 20) 1490 #define PSTATE_SS (1U << 21) 1491 #define PSTATE_PAN (1U << 22) 1492 #define PSTATE_UAO (1U << 23) 1493 #define PSTATE_DIT (1U << 24) 1494 #define PSTATE_TCO (1U << 25) 1495 #define PSTATE_V (1U << 28) 1496 #define PSTATE_C (1U << 29) 1497 #define PSTATE_Z (1U << 30) 1498 #define PSTATE_N (1U << 31) 1499 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1500 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1501 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1502 /* Mode values for AArch64 */ 1503 #define PSTATE_MODE_EL3h 13 1504 #define PSTATE_MODE_EL3t 12 1505 #define PSTATE_MODE_EL2h 9 1506 #define PSTATE_MODE_EL2t 8 1507 #define PSTATE_MODE_EL1h 5 1508 #define PSTATE_MODE_EL1t 4 1509 #define PSTATE_MODE_EL0t 0 1510 1511 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1512 FIELD(SVCR, SM, 0, 1) 1513 FIELD(SVCR, ZA, 1, 1) 1514 1515 /* Fields for SMCR_ELx. */ 1516 FIELD(SMCR, LEN, 0, 4) 1517 FIELD(SMCR, EZT0, 30, 1) 1518 FIELD(SMCR, FA64, 31, 1) 1519 1520 /* Write a new value to v7m.exception, thus transitioning into or out 1521 * of Handler mode; this may result in a change of active stack pointer. 1522 */ 1523 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1524 1525 /* Map EL and handler into a PSTATE_MODE. */ 1526 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1527 { 1528 return (el << 2) | handler; 1529 } 1530 1531 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1532 * interprocessing, so we don't attempt to sync with the cpsr state used by 1533 * the 32 bit decoder. 1534 */ 1535 static inline uint32_t pstate_read(CPUARMState *env) 1536 { 1537 int ZF; 1538 1539 ZF = (env->ZF == 0); 1540 return (env->NF & 0x80000000) | (ZF << 30) 1541 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1542 | env->pstate | env->daif | (env->btype << 10); 1543 } 1544 1545 static inline void pstate_write(CPUARMState *env, uint32_t val) 1546 { 1547 env->ZF = (~val) & PSTATE_Z; 1548 env->NF = val; 1549 env->CF = (val >> 29) & 1; 1550 env->VF = (val << 3) & 0x80000000; 1551 env->daif = val & PSTATE_DAIF; 1552 env->btype = (val >> 10) & 3; 1553 env->pstate = val & ~CACHED_PSTATE_BITS; 1554 } 1555 1556 /* Return the current CPSR value. */ 1557 uint32_t cpsr_read(CPUARMState *env); 1558 1559 typedef enum CPSRWriteType { 1560 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1561 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1562 CPSRWriteRaw = 2, 1563 /* trust values, no reg bank switch, no hflags rebuild */ 1564 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1565 } CPSRWriteType; 1566 1567 /* 1568 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1569 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1570 * correspond to TB flags bits cached in the hflags, unless @write_type 1571 * is CPSRWriteRaw. 1572 */ 1573 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1574 CPSRWriteType write_type); 1575 1576 /* Return the current xPSR value. */ 1577 static inline uint32_t xpsr_read(CPUARMState *env) 1578 { 1579 int ZF; 1580 ZF = (env->ZF == 0); 1581 return (env->NF & 0x80000000) | (ZF << 30) 1582 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1583 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1584 | ((env->condexec_bits & 0xfc) << 8) 1585 | (env->GE << 16) 1586 | env->v7m.exception; 1587 } 1588 1589 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1590 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1591 { 1592 if (mask & XPSR_NZCV) { 1593 env->ZF = (~val) & XPSR_Z; 1594 env->NF = val; 1595 env->CF = (val >> 29) & 1; 1596 env->VF = (val << 3) & 0x80000000; 1597 } 1598 if (mask & XPSR_Q) { 1599 env->QF = ((val & XPSR_Q) != 0); 1600 } 1601 if (mask & XPSR_GE) { 1602 env->GE = (val & XPSR_GE) >> 16; 1603 } 1604 #ifndef CONFIG_USER_ONLY 1605 if (mask & XPSR_T) { 1606 env->thumb = ((val & XPSR_T) != 0); 1607 } 1608 if (mask & XPSR_IT_0_1) { 1609 env->condexec_bits &= ~3; 1610 env->condexec_bits |= (val >> 25) & 3; 1611 } 1612 if (mask & XPSR_IT_2_7) { 1613 env->condexec_bits &= 3; 1614 env->condexec_bits |= (val >> 8) & 0xfc; 1615 } 1616 if (mask & XPSR_EXCP) { 1617 /* Note that this only happens on exception exit */ 1618 write_v7m_exception(env, val & XPSR_EXCP); 1619 } 1620 #endif 1621 } 1622 1623 #define HCR_VM (1ULL << 0) 1624 #define HCR_SWIO (1ULL << 1) 1625 #define HCR_PTW (1ULL << 2) 1626 #define HCR_FMO (1ULL << 3) 1627 #define HCR_IMO (1ULL << 4) 1628 #define HCR_AMO (1ULL << 5) 1629 #define HCR_VF (1ULL << 6) 1630 #define HCR_VI (1ULL << 7) 1631 #define HCR_VSE (1ULL << 8) 1632 #define HCR_FB (1ULL << 9) 1633 #define HCR_BSU_MASK (3ULL << 10) 1634 #define HCR_DC (1ULL << 12) 1635 #define HCR_TWI (1ULL << 13) 1636 #define HCR_TWE (1ULL << 14) 1637 #define HCR_TID0 (1ULL << 15) 1638 #define HCR_TID1 (1ULL << 16) 1639 #define HCR_TID2 (1ULL << 17) 1640 #define HCR_TID3 (1ULL << 18) 1641 #define HCR_TSC (1ULL << 19) 1642 #define HCR_TIDCP (1ULL << 20) 1643 #define HCR_TACR (1ULL << 21) 1644 #define HCR_TSW (1ULL << 22) 1645 #define HCR_TPCP (1ULL << 23) 1646 #define HCR_TPU (1ULL << 24) 1647 #define HCR_TTLB (1ULL << 25) 1648 #define HCR_TVM (1ULL << 26) 1649 #define HCR_TGE (1ULL << 27) 1650 #define HCR_TDZ (1ULL << 28) 1651 #define HCR_HCD (1ULL << 29) 1652 #define HCR_TRVM (1ULL << 30) 1653 #define HCR_RW (1ULL << 31) 1654 #define HCR_CD (1ULL << 32) 1655 #define HCR_ID (1ULL << 33) 1656 #define HCR_E2H (1ULL << 34) 1657 #define HCR_TLOR (1ULL << 35) 1658 #define HCR_TERR (1ULL << 36) 1659 #define HCR_TEA (1ULL << 37) 1660 #define HCR_MIOCNCE (1ULL << 38) 1661 #define HCR_TME (1ULL << 39) 1662 #define HCR_APK (1ULL << 40) 1663 #define HCR_API (1ULL << 41) 1664 #define HCR_NV (1ULL << 42) 1665 #define HCR_NV1 (1ULL << 43) 1666 #define HCR_AT (1ULL << 44) 1667 #define HCR_NV2 (1ULL << 45) 1668 #define HCR_FWB (1ULL << 46) 1669 #define HCR_FIEN (1ULL << 47) 1670 #define HCR_GPF (1ULL << 48) 1671 #define HCR_TID4 (1ULL << 49) 1672 #define HCR_TICAB (1ULL << 50) 1673 #define HCR_AMVOFFEN (1ULL << 51) 1674 #define HCR_TOCU (1ULL << 52) 1675 #define HCR_ENSCXT (1ULL << 53) 1676 #define HCR_TTLBIS (1ULL << 54) 1677 #define HCR_TTLBOS (1ULL << 55) 1678 #define HCR_ATA (1ULL << 56) 1679 #define HCR_DCT (1ULL << 57) 1680 #define HCR_TID5 (1ULL << 58) 1681 #define HCR_TWEDEN (1ULL << 59) 1682 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1683 1684 #define SCR_NS (1ULL << 0) 1685 #define SCR_IRQ (1ULL << 1) 1686 #define SCR_FIQ (1ULL << 2) 1687 #define SCR_EA (1ULL << 3) 1688 #define SCR_FW (1ULL << 4) 1689 #define SCR_AW (1ULL << 5) 1690 #define SCR_NET (1ULL << 6) 1691 #define SCR_SMD (1ULL << 7) 1692 #define SCR_HCE (1ULL << 8) 1693 #define SCR_SIF (1ULL << 9) 1694 #define SCR_RW (1ULL << 10) 1695 #define SCR_ST (1ULL << 11) 1696 #define SCR_TWI (1ULL << 12) 1697 #define SCR_TWE (1ULL << 13) 1698 #define SCR_TLOR (1ULL << 14) 1699 #define SCR_TERR (1ULL << 15) 1700 #define SCR_APK (1ULL << 16) 1701 #define SCR_API (1ULL << 17) 1702 #define SCR_EEL2 (1ULL << 18) 1703 #define SCR_EASE (1ULL << 19) 1704 #define SCR_NMEA (1ULL << 20) 1705 #define SCR_FIEN (1ULL << 21) 1706 #define SCR_ENSCXT (1ULL << 25) 1707 #define SCR_ATA (1ULL << 26) 1708 #define SCR_FGTEN (1ULL << 27) 1709 #define SCR_ECVEN (1ULL << 28) 1710 #define SCR_TWEDEN (1ULL << 29) 1711 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1712 #define SCR_TME (1ULL << 34) 1713 #define SCR_AMVOFFEN (1ULL << 35) 1714 #define SCR_ENAS0 (1ULL << 36) 1715 #define SCR_ADEN (1ULL << 37) 1716 #define SCR_HXEN (1ULL << 38) 1717 #define SCR_TRNDR (1ULL << 40) 1718 #define SCR_ENTP2 (1ULL << 41) 1719 #define SCR_GPF (1ULL << 48) 1720 #define SCR_NSE (1ULL << 62) 1721 1722 /* Return the current FPSCR value. */ 1723 uint32_t vfp_get_fpscr(CPUARMState *env); 1724 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1725 1726 /* 1727 * FPCR, Floating Point Control Register 1728 * FPSR, Floating Point Status Register 1729 * 1730 * For A64 floating point control and status bits are stored in 1731 * two logically distinct registers, FPCR and FPSR. We store these 1732 * in QEMU in vfp.fpcr and vfp.fpsr. 1733 * For A32 there was only one register, FPSCR. The bits are arranged 1734 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions, 1735 * so we can use appropriate masking to handle FPSCR reads and writes. 1736 * Note that the FPCR has some bits which are not visible in the 1737 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged. 1738 */ 1739 1740 /* FPCR bits */ 1741 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */ 1742 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */ 1743 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */ 1744 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1745 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1746 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1747 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1748 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1749 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ 1750 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1751 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ 1752 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1753 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */ 1754 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1755 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1756 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1757 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1758 1759 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1760 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1761 #define FPCR_LTPSIZE_LENGTH 3 1762 1763 /* Cumulative exception trap enable bits */ 1764 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE) 1765 1766 /* FPSR bits */ 1767 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */ 1768 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */ 1769 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */ 1770 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */ 1771 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */ 1772 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */ 1773 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */ 1774 #define FPSR_V (1 << 28) /* FP overflow flag */ 1775 #define FPSR_C (1 << 29) /* FP carry flag */ 1776 #define FPSR_Z (1 << 30) /* FP zero flag */ 1777 #define FPSR_N (1 << 31) /* FP negative flag */ 1778 1779 /* Cumulative exception status bits */ 1780 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC) 1781 1782 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) 1783 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) 1784 1785 /* A32 FPSCR bits which architecturally map to FPSR bits */ 1786 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK) 1787 /* A32 FPSCR bits which architecturally map to FPCR bits */ 1788 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \ 1789 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \ 1790 FPCR_FZ | FPCR_DN | FPCR_AHP) 1791 /* These masks don't overlap: each bit lives in only one place */ 1792 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK); 1793 1794 /** 1795 * vfp_get_fpsr: read the AArch64 FPSR 1796 * @env: CPU context 1797 * 1798 * Return the current AArch64 FPSR value 1799 */ 1800 uint32_t vfp_get_fpsr(CPUARMState *env); 1801 1802 /** 1803 * vfp_get_fpcr: read the AArch64 FPCR 1804 * @env: CPU context 1805 * 1806 * Return the current AArch64 FPCR value 1807 */ 1808 uint32_t vfp_get_fpcr(CPUARMState *env); 1809 1810 /** 1811 * vfp_set_fpsr: write the AArch64 FPSR 1812 * @env: CPU context 1813 * @value: new value 1814 */ 1815 void vfp_set_fpsr(CPUARMState *env, uint32_t value); 1816 1817 /** 1818 * vfp_set_fpcr: write the AArch64 FPCR 1819 * @env: CPU context 1820 * @value: new value 1821 */ 1822 void vfp_set_fpcr(CPUARMState *env, uint32_t value); 1823 1824 enum arm_cpu_mode { 1825 ARM_CPU_MODE_USR = 0x10, 1826 ARM_CPU_MODE_FIQ = 0x11, 1827 ARM_CPU_MODE_IRQ = 0x12, 1828 ARM_CPU_MODE_SVC = 0x13, 1829 ARM_CPU_MODE_MON = 0x16, 1830 ARM_CPU_MODE_ABT = 0x17, 1831 ARM_CPU_MODE_HYP = 0x1a, 1832 ARM_CPU_MODE_UND = 0x1b, 1833 ARM_CPU_MODE_SYS = 0x1f 1834 }; 1835 1836 /* VFP system registers. */ 1837 #define ARM_VFP_FPSID 0 1838 #define ARM_VFP_FPSCR 1 1839 #define ARM_VFP_MVFR2 5 1840 #define ARM_VFP_MVFR1 6 1841 #define ARM_VFP_MVFR0 7 1842 #define ARM_VFP_FPEXC 8 1843 #define ARM_VFP_FPINST 9 1844 #define ARM_VFP_FPINST2 10 1845 /* These ones are M-profile only */ 1846 #define ARM_VFP_FPSCR_NZCVQC 2 1847 #define ARM_VFP_VPR 12 1848 #define ARM_VFP_P0 13 1849 #define ARM_VFP_FPCXT_NS 14 1850 #define ARM_VFP_FPCXT_S 15 1851 1852 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1853 #define QEMU_VFP_FPSCR_NZCV 0xffff 1854 1855 /* iwMMXt coprocessor control registers. */ 1856 #define ARM_IWMMXT_wCID 0 1857 #define ARM_IWMMXT_wCon 1 1858 #define ARM_IWMMXT_wCSSF 2 1859 #define ARM_IWMMXT_wCASF 3 1860 #define ARM_IWMMXT_wCGR0 8 1861 #define ARM_IWMMXT_wCGR1 9 1862 #define ARM_IWMMXT_wCGR2 10 1863 #define ARM_IWMMXT_wCGR3 11 1864 1865 /* V7M CCR bits */ 1866 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1867 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1868 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1869 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1870 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1871 FIELD(V7M_CCR, STKALIGN, 9, 1) 1872 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1873 FIELD(V7M_CCR, DC, 16, 1) 1874 FIELD(V7M_CCR, IC, 17, 1) 1875 FIELD(V7M_CCR, BP, 18, 1) 1876 FIELD(V7M_CCR, LOB, 19, 1) 1877 FIELD(V7M_CCR, TRD, 20, 1) 1878 1879 /* V7M SCR bits */ 1880 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1881 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1882 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1883 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1884 1885 /* V7M AIRCR bits */ 1886 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1887 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1888 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1889 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1890 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1891 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1892 FIELD(V7M_AIRCR, PRIS, 14, 1) 1893 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1894 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1895 1896 /* V7M CFSR bits for MMFSR */ 1897 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1898 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1899 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1900 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1901 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1902 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1903 1904 /* V7M CFSR bits for BFSR */ 1905 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1906 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1907 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1908 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1909 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1910 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1911 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1912 1913 /* V7M CFSR bits for UFSR */ 1914 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1915 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1916 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1917 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1918 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1919 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1920 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1921 1922 /* V7M CFSR bit masks covering all of the subregister bits */ 1923 FIELD(V7M_CFSR, MMFSR, 0, 8) 1924 FIELD(V7M_CFSR, BFSR, 8, 8) 1925 FIELD(V7M_CFSR, UFSR, 16, 16) 1926 1927 /* V7M HFSR bits */ 1928 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1929 FIELD(V7M_HFSR, FORCED, 30, 1) 1930 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1931 1932 /* V7M DFSR bits */ 1933 FIELD(V7M_DFSR, HALTED, 0, 1) 1934 FIELD(V7M_DFSR, BKPT, 1, 1) 1935 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1936 FIELD(V7M_DFSR, VCATCH, 3, 1) 1937 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1938 1939 /* V7M SFSR bits */ 1940 FIELD(V7M_SFSR, INVEP, 0, 1) 1941 FIELD(V7M_SFSR, INVIS, 1, 1) 1942 FIELD(V7M_SFSR, INVER, 2, 1) 1943 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1944 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1945 FIELD(V7M_SFSR, LSPERR, 5, 1) 1946 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1947 FIELD(V7M_SFSR, LSERR, 7, 1) 1948 1949 /* v7M MPU_CTRL bits */ 1950 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1951 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1952 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1953 1954 /* v7M CLIDR bits */ 1955 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1956 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1957 FIELD(V7M_CLIDR, LOC, 24, 3) 1958 FIELD(V7M_CLIDR, LOUU, 27, 3) 1959 FIELD(V7M_CLIDR, ICB, 30, 2) 1960 1961 FIELD(V7M_CSSELR, IND, 0, 1) 1962 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1963 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1964 * define a mask for this and check that it doesn't permit running off 1965 * the end of the array. 1966 */ 1967 FIELD(V7M_CSSELR, INDEX, 0, 4) 1968 1969 /* v7M FPCCR bits */ 1970 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1971 FIELD(V7M_FPCCR, USER, 1, 1) 1972 FIELD(V7M_FPCCR, S, 2, 1) 1973 FIELD(V7M_FPCCR, THREAD, 3, 1) 1974 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1975 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1976 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1977 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1978 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1979 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1980 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1981 FIELD(V7M_FPCCR, RES0, 11, 15) 1982 FIELD(V7M_FPCCR, TS, 26, 1) 1983 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1984 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1985 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1986 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1987 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1988 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1989 #define R_V7M_FPCCR_BANKED_MASK \ 1990 (R_V7M_FPCCR_LSPACT_MASK | \ 1991 R_V7M_FPCCR_USER_MASK | \ 1992 R_V7M_FPCCR_THREAD_MASK | \ 1993 R_V7M_FPCCR_MMRDY_MASK | \ 1994 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1995 R_V7M_FPCCR_UFRDY_MASK | \ 1996 R_V7M_FPCCR_ASPEN_MASK) 1997 1998 /* v7M VPR bits */ 1999 FIELD(V7M_VPR, P0, 0, 16) 2000 FIELD(V7M_VPR, MASK01, 16, 4) 2001 FIELD(V7M_VPR, MASK23, 20, 4) 2002 2003 /* 2004 * System register ID fields. 2005 */ 2006 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2007 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2008 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2009 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2010 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2011 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2012 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2013 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2014 FIELD(CLIDR_EL1, LOC, 24, 3) 2015 FIELD(CLIDR_EL1, LOUU, 27, 3) 2016 FIELD(CLIDR_EL1, ICB, 30, 3) 2017 2018 /* When FEAT_CCIDX is implemented */ 2019 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2020 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2021 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2022 2023 /* When FEAT_CCIDX is not implemented */ 2024 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2025 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2026 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2027 2028 FIELD(CTR_EL0, IMINLINE, 0, 4) 2029 FIELD(CTR_EL0, L1IP, 14, 2) 2030 FIELD(CTR_EL0, DMINLINE, 16, 4) 2031 FIELD(CTR_EL0, ERG, 20, 4) 2032 FIELD(CTR_EL0, CWG, 24, 4) 2033 FIELD(CTR_EL0, IDC, 28, 1) 2034 FIELD(CTR_EL0, DIC, 29, 1) 2035 FIELD(CTR_EL0, TMINLINE, 32, 6) 2036 2037 FIELD(MIDR_EL1, REVISION, 0, 4) 2038 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2039 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2040 FIELD(MIDR_EL1, VARIANT, 20, 4) 2041 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2042 2043 FIELD(ID_ISAR0, SWAP, 0, 4) 2044 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2045 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2046 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2047 FIELD(ID_ISAR0, COPROC, 16, 4) 2048 FIELD(ID_ISAR0, DEBUG, 20, 4) 2049 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2050 2051 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2052 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2053 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2054 FIELD(ID_ISAR1, EXTEND, 12, 4) 2055 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2056 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2057 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2058 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2059 2060 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2061 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2062 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2063 FIELD(ID_ISAR2, MULT, 12, 4) 2064 FIELD(ID_ISAR2, MULTS, 16, 4) 2065 FIELD(ID_ISAR2, MULTU, 20, 4) 2066 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2067 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2068 2069 FIELD(ID_ISAR3, SATURATE, 0, 4) 2070 FIELD(ID_ISAR3, SIMD, 4, 4) 2071 FIELD(ID_ISAR3, SVC, 8, 4) 2072 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2073 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2074 FIELD(ID_ISAR3, T32COPY, 20, 4) 2075 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2076 FIELD(ID_ISAR3, T32EE, 28, 4) 2077 2078 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2079 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2080 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2081 FIELD(ID_ISAR4, SMC, 12, 4) 2082 FIELD(ID_ISAR4, BARRIER, 16, 4) 2083 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2084 FIELD(ID_ISAR4, PSR_M, 24, 4) 2085 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2086 2087 FIELD(ID_ISAR5, SEVL, 0, 4) 2088 FIELD(ID_ISAR5, AES, 4, 4) 2089 FIELD(ID_ISAR5, SHA1, 8, 4) 2090 FIELD(ID_ISAR5, SHA2, 12, 4) 2091 FIELD(ID_ISAR5, CRC32, 16, 4) 2092 FIELD(ID_ISAR5, RDM, 24, 4) 2093 FIELD(ID_ISAR5, VCMA, 28, 4) 2094 2095 FIELD(ID_ISAR6, JSCVT, 0, 4) 2096 FIELD(ID_ISAR6, DP, 4, 4) 2097 FIELD(ID_ISAR6, FHM, 8, 4) 2098 FIELD(ID_ISAR6, SB, 12, 4) 2099 FIELD(ID_ISAR6, SPECRES, 16, 4) 2100 FIELD(ID_ISAR6, BF16, 20, 4) 2101 FIELD(ID_ISAR6, I8MM, 24, 4) 2102 2103 FIELD(ID_MMFR0, VMSA, 0, 4) 2104 FIELD(ID_MMFR0, PMSA, 4, 4) 2105 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2106 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2107 FIELD(ID_MMFR0, TCM, 16, 4) 2108 FIELD(ID_MMFR0, AUXREG, 20, 4) 2109 FIELD(ID_MMFR0, FCSE, 24, 4) 2110 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2111 2112 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2113 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2114 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2115 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2116 FIELD(ID_MMFR1, L1HVD, 16, 4) 2117 FIELD(ID_MMFR1, L1UNI, 20, 4) 2118 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2119 FIELD(ID_MMFR1, BPRED, 28, 4) 2120 2121 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2122 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2123 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2124 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2125 FIELD(ID_MMFR2, UNITLB, 16, 4) 2126 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2127 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2128 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2129 2130 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2131 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2132 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2133 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2134 FIELD(ID_MMFR3, PAN, 16, 4) 2135 FIELD(ID_MMFR3, COHWALK, 20, 4) 2136 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2137 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2138 2139 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2140 FIELD(ID_MMFR4, AC2, 4, 4) 2141 FIELD(ID_MMFR4, XNX, 8, 4) 2142 FIELD(ID_MMFR4, CNP, 12, 4) 2143 FIELD(ID_MMFR4, HPDS, 16, 4) 2144 FIELD(ID_MMFR4, LSM, 20, 4) 2145 FIELD(ID_MMFR4, CCIDX, 24, 4) 2146 FIELD(ID_MMFR4, EVT, 28, 4) 2147 2148 FIELD(ID_MMFR5, ETS, 0, 4) 2149 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2150 2151 FIELD(ID_PFR0, STATE0, 0, 4) 2152 FIELD(ID_PFR0, STATE1, 4, 4) 2153 FIELD(ID_PFR0, STATE2, 8, 4) 2154 FIELD(ID_PFR0, STATE3, 12, 4) 2155 FIELD(ID_PFR0, CSV2, 16, 4) 2156 FIELD(ID_PFR0, AMU, 20, 4) 2157 FIELD(ID_PFR0, DIT, 24, 4) 2158 FIELD(ID_PFR0, RAS, 28, 4) 2159 2160 FIELD(ID_PFR1, PROGMOD, 0, 4) 2161 FIELD(ID_PFR1, SECURITY, 4, 4) 2162 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2163 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2164 FIELD(ID_PFR1, GENTIMER, 16, 4) 2165 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2166 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2167 FIELD(ID_PFR1, GIC, 28, 4) 2168 2169 FIELD(ID_PFR2, CSV3, 0, 4) 2170 FIELD(ID_PFR2, SSBS, 4, 4) 2171 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2172 2173 FIELD(ID_AA64ISAR0, AES, 4, 4) 2174 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2175 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2176 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2177 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2178 FIELD(ID_AA64ISAR0, TME, 24, 4) 2179 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2180 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2181 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2182 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2183 FIELD(ID_AA64ISAR0, DP, 44, 4) 2184 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2185 FIELD(ID_AA64ISAR0, TS, 52, 4) 2186 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2187 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2188 2189 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2190 FIELD(ID_AA64ISAR1, APA, 4, 4) 2191 FIELD(ID_AA64ISAR1, API, 8, 4) 2192 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2193 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2194 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2195 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2196 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2197 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2198 FIELD(ID_AA64ISAR1, SB, 36, 4) 2199 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2200 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2201 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2202 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2203 FIELD(ID_AA64ISAR1, XS, 56, 4) 2204 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2205 2206 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2207 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2208 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2209 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2210 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2211 FIELD(ID_AA64ISAR2, BC, 20, 4) 2212 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2213 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2214 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2215 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2216 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2217 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2218 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2219 FIELD(ID_AA64ISAR2, LUT, 56, 4) 2220 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2221 2222 FIELD(ID_AA64PFR0, EL0, 0, 4) 2223 FIELD(ID_AA64PFR0, EL1, 4, 4) 2224 FIELD(ID_AA64PFR0, EL2, 8, 4) 2225 FIELD(ID_AA64PFR0, EL3, 12, 4) 2226 FIELD(ID_AA64PFR0, FP, 16, 4) 2227 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2228 FIELD(ID_AA64PFR0, GIC, 24, 4) 2229 FIELD(ID_AA64PFR0, RAS, 28, 4) 2230 FIELD(ID_AA64PFR0, SVE, 32, 4) 2231 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2232 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2233 FIELD(ID_AA64PFR0, AMU, 44, 4) 2234 FIELD(ID_AA64PFR0, DIT, 48, 4) 2235 FIELD(ID_AA64PFR0, RME, 52, 4) 2236 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2237 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2238 2239 FIELD(ID_AA64PFR1, BT, 0, 4) 2240 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2241 FIELD(ID_AA64PFR1, MTE, 8, 4) 2242 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2243 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2244 FIELD(ID_AA64PFR1, SME, 24, 4) 2245 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2246 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2247 FIELD(ID_AA64PFR1, NMI, 36, 4) 2248 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2249 FIELD(ID_AA64PFR1, GCS, 44, 4) 2250 FIELD(ID_AA64PFR1, THE, 48, 4) 2251 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2252 FIELD(ID_AA64PFR1, DF2, 56, 4) 2253 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2254 2255 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2256 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2257 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2258 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2259 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2260 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2261 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2262 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2263 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2264 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2265 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2266 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2267 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2268 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2269 2270 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2271 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2272 FIELD(ID_AA64MMFR1, VH, 8, 4) 2273 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2274 FIELD(ID_AA64MMFR1, LO, 16, 4) 2275 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2276 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2277 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2278 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2279 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2280 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2281 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2282 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2283 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2284 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2285 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2286 2287 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2288 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2289 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2290 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2291 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2292 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2293 FIELD(ID_AA64MMFR2, NV, 24, 4) 2294 FIELD(ID_AA64MMFR2, ST, 28, 4) 2295 FIELD(ID_AA64MMFR2, AT, 32, 4) 2296 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2297 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2298 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2299 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2300 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2301 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2302 2303 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2304 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2305 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2306 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2307 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2308 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2309 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2310 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2311 FIELD(ID_AA64MMFR3, D128, 32, 4) 2312 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2313 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2314 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2315 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2316 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2317 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2318 2319 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2320 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2321 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2322 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2323 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2324 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2325 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2326 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2327 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2328 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2329 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2330 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2331 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2332 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2333 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2334 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2335 2336 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2337 FIELD(ID_AA64ZFR0, AES, 4, 4) 2338 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2339 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2340 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2341 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2342 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2343 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2344 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2345 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2346 2347 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2348 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2349 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2350 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2351 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2352 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2353 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2354 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2355 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2356 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2357 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2358 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2359 2360 FIELD(ID_DFR0, COPDBG, 0, 4) 2361 FIELD(ID_DFR0, COPSDBG, 4, 4) 2362 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2363 FIELD(ID_DFR0, COPTRC, 12, 4) 2364 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2365 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2366 FIELD(ID_DFR0, PERFMON, 24, 4) 2367 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2368 2369 FIELD(ID_DFR1, MTPMU, 0, 4) 2370 FIELD(ID_DFR1, HPMN0, 4, 4) 2371 2372 FIELD(DBGDIDR, SE_IMP, 12, 1) 2373 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2374 FIELD(DBGDIDR, VERSION, 16, 4) 2375 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2376 FIELD(DBGDIDR, BRPS, 24, 4) 2377 FIELD(DBGDIDR, WRPS, 28, 4) 2378 2379 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2380 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2381 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2382 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2383 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2384 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2385 FIELD(DBGDEVID, AUXREGS, 24, 4) 2386 FIELD(DBGDEVID, CIDMASK, 28, 4) 2387 2388 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 2389 2390 FIELD(MVFR0, SIMDREG, 0, 4) 2391 FIELD(MVFR0, FPSP, 4, 4) 2392 FIELD(MVFR0, FPDP, 8, 4) 2393 FIELD(MVFR0, FPTRAP, 12, 4) 2394 FIELD(MVFR0, FPDIVIDE, 16, 4) 2395 FIELD(MVFR0, FPSQRT, 20, 4) 2396 FIELD(MVFR0, FPSHVEC, 24, 4) 2397 FIELD(MVFR0, FPROUND, 28, 4) 2398 2399 FIELD(MVFR1, FPFTZ, 0, 4) 2400 FIELD(MVFR1, FPDNAN, 4, 4) 2401 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2402 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2403 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2404 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2405 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2406 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2407 FIELD(MVFR1, FPHP, 24, 4) 2408 FIELD(MVFR1, SIMDFMAC, 28, 4) 2409 2410 FIELD(MVFR2, SIMDMISC, 0, 4) 2411 FIELD(MVFR2, FPMISC, 4, 4) 2412 2413 FIELD(GPCCR, PPS, 0, 3) 2414 FIELD(GPCCR, IRGN, 8, 2) 2415 FIELD(GPCCR, ORGN, 10, 2) 2416 FIELD(GPCCR, SH, 12, 2) 2417 FIELD(GPCCR, PGS, 14, 2) 2418 FIELD(GPCCR, GPC, 16, 1) 2419 FIELD(GPCCR, GPCP, 17, 1) 2420 FIELD(GPCCR, L0GPTSZ, 20, 4) 2421 2422 FIELD(MFAR, FPA, 12, 40) 2423 FIELD(MFAR, NSE, 62, 1) 2424 FIELD(MFAR, NS, 63, 1) 2425 2426 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2427 2428 /* If adding a feature bit which corresponds to a Linux ELF 2429 * HWCAP bit, remember to update the feature-bit-to-hwcap 2430 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2431 */ 2432 enum arm_features { 2433 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2434 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2435 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2436 ARM_FEATURE_V6, 2437 ARM_FEATURE_V6K, 2438 ARM_FEATURE_V7, 2439 ARM_FEATURE_THUMB2, 2440 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2441 ARM_FEATURE_NEON, 2442 ARM_FEATURE_M, /* Microcontroller profile. */ 2443 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2444 ARM_FEATURE_THUMB2EE, 2445 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2446 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2447 ARM_FEATURE_V4T, 2448 ARM_FEATURE_V5, 2449 ARM_FEATURE_STRONGARM, 2450 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2451 ARM_FEATURE_GENERIC_TIMER, 2452 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2453 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2454 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2455 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2456 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2457 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2458 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2459 ARM_FEATURE_V8, 2460 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2461 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2462 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2463 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2464 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2465 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2466 ARM_FEATURE_PMU, /* has PMU support */ 2467 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2468 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2469 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2470 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2471 /* 2472 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2473 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2474 * compatibility and used only with CPU definitions that were already 2475 * in QEMU before we changed the default. It should not be set on any 2476 * CPU types added in future. 2477 */ 2478 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2479 }; 2480 2481 static inline int arm_feature(CPUARMState *env, int feature) 2482 { 2483 return (env->features & (1ULL << feature)) != 0; 2484 } 2485 2486 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2487 2488 /* 2489 * ARM v9 security states. 2490 * The ordering of the enumeration corresponds to the low 2 bits 2491 * of the GPI value, and (except for Root) the concat of NSE:NS. 2492 */ 2493 2494 typedef enum ARMSecuritySpace { 2495 ARMSS_Secure = 0, 2496 ARMSS_NonSecure = 1, 2497 ARMSS_Root = 2, 2498 ARMSS_Realm = 3, 2499 } ARMSecuritySpace; 2500 2501 /* Return true if @space is secure, in the pre-v9 sense. */ 2502 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2503 { 2504 return space == ARMSS_Secure || space == ARMSS_Root; 2505 } 2506 2507 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2508 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2509 { 2510 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2511 } 2512 2513 #if !defined(CONFIG_USER_ONLY) 2514 /** 2515 * arm_security_space_below_el3: 2516 * @env: cpu context 2517 * 2518 * Return the security space of exception levels below EL3, following 2519 * an exception return to those levels. Unlike arm_security_space, 2520 * this doesn't care about the current EL. 2521 */ 2522 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2523 2524 /** 2525 * arm_is_secure_below_el3: 2526 * @env: cpu context 2527 * 2528 * Return true if exception levels below EL3 are in secure state, 2529 * or would be following an exception return to those levels. 2530 */ 2531 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2532 { 2533 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2534 return ss == ARMSS_Secure; 2535 } 2536 2537 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2538 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2539 { 2540 assert(!arm_feature(env, ARM_FEATURE_M)); 2541 if (arm_feature(env, ARM_FEATURE_EL3)) { 2542 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2543 /* CPU currently in AArch64 state and EL3 */ 2544 return true; 2545 } else if (!is_a64(env) && 2546 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2547 /* CPU currently in AArch32 state and monitor mode */ 2548 return true; 2549 } 2550 } 2551 return false; 2552 } 2553 2554 /** 2555 * arm_security_space: 2556 * @env: cpu context 2557 * 2558 * Return the current security space of the cpu. 2559 */ 2560 ARMSecuritySpace arm_security_space(CPUARMState *env); 2561 2562 /** 2563 * arm_is_secure: 2564 * @env: cpu context 2565 * 2566 * Return true if the processor is in secure state. 2567 */ 2568 static inline bool arm_is_secure(CPUARMState *env) 2569 { 2570 return arm_space_is_secure(arm_security_space(env)); 2571 } 2572 2573 /* 2574 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2575 * This corresponds to the pseudocode EL2Enabled(). 2576 */ 2577 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2578 ARMSecuritySpace space) 2579 { 2580 assert(space != ARMSS_Root); 2581 return arm_feature(env, ARM_FEATURE_EL2) 2582 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2583 } 2584 2585 static inline bool arm_is_el2_enabled(CPUARMState *env) 2586 { 2587 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2588 } 2589 2590 #else 2591 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2592 { 2593 return ARMSS_NonSecure; 2594 } 2595 2596 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2597 { 2598 return false; 2599 } 2600 2601 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2602 { 2603 return false; 2604 } 2605 2606 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2607 { 2608 return ARMSS_NonSecure; 2609 } 2610 2611 static inline bool arm_is_secure(CPUARMState *env) 2612 { 2613 return false; 2614 } 2615 2616 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2617 ARMSecuritySpace space) 2618 { 2619 return false; 2620 } 2621 2622 static inline bool arm_is_el2_enabled(CPUARMState *env) 2623 { 2624 return false; 2625 } 2626 #endif 2627 2628 /** 2629 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2630 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2631 * "for all purposes other than a direct read or write access of HCR_EL2." 2632 * Not included here is HCR_RW. 2633 */ 2634 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2635 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2636 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2637 2638 /* 2639 * Function for determining whether guest cp register reads and writes should 2640 * access the secure or non-secure bank of a cp register. When EL3 is 2641 * operating in AArch32 state, the NS-bit determines whether the secure 2642 * instance of a cp register should be used. When EL3 is AArch64 (or if 2643 * it doesn't exist at all) then there is no register banking, and all 2644 * accesses are to the non-secure version. 2645 */ 2646 bool access_secure_reg(CPUARMState *env); 2647 2648 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2649 uint32_t cur_el, bool secure); 2650 2651 /* Return the highest implemented Exception Level */ 2652 static inline int arm_highest_el(CPUARMState *env) 2653 { 2654 if (arm_feature(env, ARM_FEATURE_EL3)) { 2655 return 3; 2656 } 2657 if (arm_feature(env, ARM_FEATURE_EL2)) { 2658 return 2; 2659 } 2660 return 1; 2661 } 2662 2663 /* Return true if a v7M CPU is in Handler mode */ 2664 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2665 { 2666 return env->v7m.exception != 0; 2667 } 2668 2669 /** 2670 * write_list_to_cpustate 2671 * @cpu: ARMCPU 2672 * 2673 * For each register listed in the ARMCPU cpreg_indexes list, write 2674 * its value from the cpreg_values list into the ARMCPUState structure. 2675 * This updates TCG's working data structures from KVM data or 2676 * from incoming migration state. 2677 * 2678 * Returns: true if all register values were updated correctly, 2679 * false if some register was unknown or could not be written. 2680 * Note that we do not stop early on failure -- we will attempt 2681 * writing all registers in the list. 2682 */ 2683 bool write_list_to_cpustate(ARMCPU *cpu); 2684 2685 /** 2686 * write_cpustate_to_list: 2687 * @cpu: ARMCPU 2688 * @kvm_sync: true if this is for syncing back to KVM 2689 * 2690 * For each register listed in the ARMCPU cpreg_indexes list, write 2691 * its value from the ARMCPUState structure into the cpreg_values list. 2692 * This is used to copy info from TCG's working data structures into 2693 * KVM or for outbound migration. 2694 * 2695 * @kvm_sync is true if we are doing this in order to sync the 2696 * register state back to KVM. In this case we will only update 2697 * values in the list if the previous list->cpustate sync actually 2698 * successfully wrote the CPU state. Otherwise we will keep the value 2699 * that is in the list. 2700 * 2701 * Returns: true if all register values were read correctly, 2702 * false if some register was unknown or could not be read. 2703 * Note that we do not stop early on failure -- we will attempt 2704 * reading all registers in the list. 2705 */ 2706 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2707 2708 #define ARM_CPUID_TI915T 0x54029152 2709 #define ARM_CPUID_TI925T 0x54029252 2710 2711 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2712 2713 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2714 2715 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2716 * 2717 * If EL3 is 64-bit: 2718 * + NonSecure EL1 & 0 stage 1 2719 * + NonSecure EL1 & 0 stage 2 2720 * + NonSecure EL2 2721 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2722 * + Secure EL1 & 0 stage 1 2723 * + Secure EL1 & 0 stage 2 (FEAT_SEL2) 2724 * + Secure EL2 (FEAT_SEL2) 2725 * + Secure EL2 & 0 (FEAT_SEL2) 2726 * + Realm EL1 & 0 stage 1 (FEAT_RME) 2727 * + Realm EL1 & 0 stage 2 (FEAT_RME) 2728 * + Realm EL2 (FEAT_RME) 2729 * + EL3 2730 * If EL3 is 32-bit: 2731 * + NonSecure PL1 & 0 stage 1 2732 * + NonSecure PL1 & 0 stage 2 2733 * + NonSecure PL2 2734 * + Secure PL1 & 0 2735 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2736 * 2737 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2738 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2739 * because they may differ in access permissions even if the VA->PA map is 2740 * the same 2741 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2742 * translation, which means that we have one mmu_idx that deals with two 2743 * concatenated translation regimes [this sort of combined s1+2 TLB is 2744 * architecturally permitted] 2745 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2746 * handling via the TLB. The only way to do a stage 1 translation without 2747 * the immediate stage 2 translation is via the ATS or AT system insns, 2748 * which can be slow-pathed and always do a page table walk. 2749 * The only use of stage 2 translations is either as part of an s1+2 2750 * lookup or when loading the descriptors during a stage 1 page table walk, 2751 * and in both those cases we don't use the TLB. 2752 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2753 * translation regimes, because they map reasonably well to each other 2754 * and they can't both be active at the same time. 2755 * 5. we want to be able to use the TLB for accesses done as part of a 2756 * stage1 page table walk, rather than having to walk the stage2 page 2757 * table over and over. 2758 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2759 * Never (PAN) bit within PSTATE. 2760 * 7. we fold together most secure and non-secure regimes for A-profile, 2761 * because there are no banked system registers for aarch64, so the 2762 * process of switching between secure and non-secure is 2763 * already heavyweight. 2764 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, 2765 * because both are in use simultaneously for Secure EL2. 2766 * 2767 * This gives us the following list of cases: 2768 * 2769 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) 2770 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) 2771 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) 2772 * EL0 EL2&0 2773 * EL2 EL2&0 2774 * EL2 EL2&0 +PAN 2775 * EL2 (aka NS PL2) 2776 * EL3 (aka AArch32 S PL1 PL1&0) 2777 * AArch32 S PL0 PL1&0 (we call this EL30_0) 2778 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) 2779 * Stage2 Secure 2780 * Stage2 NonSecure 2781 * plus one TLB per Physical address space: S, NS, Realm, Root 2782 * 2783 * for a total of 16 different mmu_idx. 2784 * 2785 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2786 * as A profile. They only need to distinguish EL0 and EL1 (and 2787 * EL2 for cores like the Cortex-R52). 2788 * 2789 * M profile CPUs are rather different as they do not have a true MMU. 2790 * They have the following different MMU indexes: 2791 * User 2792 * Privileged 2793 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2794 * Privileged, execution priority negative (ditto) 2795 * If the CPU supports the v8M Security Extension then there are also: 2796 * Secure User 2797 * Secure Privileged 2798 * Secure User, execution priority negative 2799 * Secure Privileged, execution priority negative 2800 * 2801 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2802 * are not quite the same -- different CPU types (most notably M profile 2803 * vs A/R profile) would like to use MMU indexes with different semantics, 2804 * but since we don't ever need to use all of those in a single CPU we 2805 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2806 * modes + total number of M profile MMU modes". The lower bits of 2807 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2808 * the same for any particular CPU. 2809 * Variables of type ARMMUIdx are always full values, and the core 2810 * index values are in variables of type 'int'. 2811 * 2812 * Our enumeration includes at the end some entries which are not "true" 2813 * mmu_idx values in that they don't have corresponding TLBs and are only 2814 * valid for doing slow path page table walks. 2815 * 2816 * The constant names here are patterned after the general style of the names 2817 * of the AT/ATS operations. 2818 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2819 * For M profile we arrange them to have a bit for priv, a bit for negpri 2820 * and a bit for secure. 2821 */ 2822 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2823 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2824 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2825 2826 /* Meanings of the bits for M profile mmu idx values */ 2827 #define ARM_MMU_IDX_M_PRIV 0x1 2828 #define ARM_MMU_IDX_M_NEGPRI 0x2 2829 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2830 2831 #define ARM_MMU_IDX_TYPE_MASK \ 2832 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2833 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2834 2835 typedef enum ARMMMUIdx { 2836 /* 2837 * A-profile. 2838 */ 2839 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2840 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2841 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2842 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2843 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2844 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2845 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2846 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2847 ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A, 2848 ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A, 2849 2850 /* 2851 * Used for second stage of an S12 page table walk, or for descriptor 2852 * loads during first stage of an S1 page table walk. Note that both 2853 * are in use simultaneously for SecureEL2: the security state for 2854 * the S2 ptw is selected by the NS bit from the S1 ptw. 2855 */ 2856 ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A, 2857 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, 2858 2859 /* TLBs with 1-1 mapping to the physical address spaces. */ 2860 ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A, 2861 ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A, 2862 ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A, 2863 ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A, 2864 2865 /* 2866 * These are not allocated TLBs and are used only for AT system 2867 * instructions or for the first stage of an S12 page table walk. 2868 */ 2869 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2870 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2871 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2872 2873 /* 2874 * M-profile. 2875 */ 2876 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2877 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2878 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2879 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2880 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2881 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2882 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2883 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2884 } ARMMMUIdx; 2885 2886 /* 2887 * Bit macros for the core-mmu-index values for each index, 2888 * for use when calling tlb_flush_by_mmuidx() and friends. 2889 */ 2890 #define TO_CORE_BIT(NAME) \ 2891 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2892 2893 typedef enum ARMMMUIdxBit { 2894 TO_CORE_BIT(E10_0), 2895 TO_CORE_BIT(E20_0), 2896 TO_CORE_BIT(E10_1), 2897 TO_CORE_BIT(E10_1_PAN), 2898 TO_CORE_BIT(E2), 2899 TO_CORE_BIT(E20_2), 2900 TO_CORE_BIT(E20_2_PAN), 2901 TO_CORE_BIT(E3), 2902 TO_CORE_BIT(E30_0), 2903 TO_CORE_BIT(E30_3_PAN), 2904 TO_CORE_BIT(Stage2), 2905 TO_CORE_BIT(Stage2_S), 2906 2907 TO_CORE_BIT(MUser), 2908 TO_CORE_BIT(MPriv), 2909 TO_CORE_BIT(MUserNegPri), 2910 TO_CORE_BIT(MPrivNegPri), 2911 TO_CORE_BIT(MSUser), 2912 TO_CORE_BIT(MSPriv), 2913 TO_CORE_BIT(MSUserNegPri), 2914 TO_CORE_BIT(MSPrivNegPri), 2915 } ARMMMUIdxBit; 2916 2917 #undef TO_CORE_BIT 2918 2919 #define MMU_USER_IDX 0 2920 2921 /* Indexes used when registering address spaces with cpu_address_space_init */ 2922 typedef enum ARMASIdx { 2923 ARMASIdx_NS = 0, 2924 ARMASIdx_S = 1, 2925 ARMASIdx_TagNS = 2, 2926 ARMASIdx_TagS = 3, 2927 } ARMASIdx; 2928 2929 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2930 { 2931 /* Assert the relative order of the physical mmu indexes. */ 2932 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2933 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2934 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2935 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2936 2937 return ARMMMUIdx_Phys_S + space; 2938 } 2939 2940 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2941 { 2942 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2943 return idx - ARMMMUIdx_Phys_S; 2944 } 2945 2946 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2947 { 2948 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2949 * CSSELR is RAZ/WI. 2950 */ 2951 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2952 } 2953 2954 static inline bool arm_sctlr_b(CPUARMState *env) 2955 { 2956 return 2957 /* We need not implement SCTLR.ITD in user-mode emulation, so 2958 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2959 * This lets people run BE32 binaries with "-cpu any". 2960 */ 2961 #ifndef CONFIG_USER_ONLY 2962 !arm_feature(env, ARM_FEATURE_V7) && 2963 #endif 2964 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2965 } 2966 2967 uint64_t arm_sctlr(CPUARMState *env, int el); 2968 2969 /* 2970 * We have more than 32-bits worth of state per TB, so we split the data 2971 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2972 * We collect these two parts in CPUARMTBFlags where they are named 2973 * flags and flags2 respectively. 2974 * 2975 * The flags that are shared between all execution modes, TBFLAG_ANY, are stored 2976 * in flags. The flags that are specific to a given mode are stored in flags2. 2977 * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32. 2978 * 2979 * The bits for 32-bit A-profile and M-profile partially overlap: 2980 * 2981 * 31 23 11 10 0 2982 * +-------------+----------+----------------+ 2983 * | | | TBFLAG_A32 | 2984 * | TBFLAG_AM32 | +-----+----------+ 2985 * | | |TBFLAG_M32| 2986 * +-------------+----------------+----------+ 2987 * 31 23 6 5 0 2988 * 2989 * Unless otherwise noted, these bits are cached in env->hflags. 2990 */ 2991 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2992 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2993 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2994 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2995 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 2996 /* Target EL if we take a floating-point-disabled exception */ 2997 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 2998 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 2999 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3000 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3001 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3002 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3003 3004 /* 3005 * Bit usage when in AArch32 state, both A- and M-profile. 3006 */ 3007 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3008 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3009 3010 /* 3011 * Bit usage when in AArch32 state, for A-profile only. 3012 */ 3013 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3014 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3015 /* 3016 * We store the bottom two bits of the CPAR as TB flags and handle 3017 * checks on the other bits at runtime. This shares the same bits as 3018 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3019 * Not cached, because VECLEN+VECSTRIDE are not cached. 3020 */ 3021 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3022 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3023 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3024 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3025 /* 3026 * Indicates whether cp register reads and writes by guest code should access 3027 * the secure or nonsecure bank of banked registers; note that this is not 3028 * the same thing as the current security state of the processor! 3029 */ 3030 FIELD(TBFLAG_A32, NS, 10, 1) 3031 /* 3032 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3033 * This requires an SME trap from AArch32 mode when using NEON. 3034 */ 3035 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3036 3037 /* 3038 * Bit usage when in AArch32 state, for M-profile only. 3039 */ 3040 /* Handler (ie not Thread) mode */ 3041 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3042 /* Whether we should generate stack-limit checks */ 3043 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3044 /* Set if FPCCR.LSPACT is set */ 3045 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3046 /* Set if we must create a new FP context */ 3047 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3048 /* Set if FPCCR.S does not match current security state */ 3049 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3050 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3051 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3052 /* Set if in secure mode */ 3053 FIELD(TBFLAG_M32, SECURE, 6, 1) 3054 3055 /* 3056 * Bit usage when in AArch64 state 3057 */ 3058 FIELD(TBFLAG_A64, TBII, 0, 2) 3059 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3060 /* The current vector length, either NVL or SVL. */ 3061 FIELD(TBFLAG_A64, VL, 4, 4) 3062 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3063 FIELD(TBFLAG_A64, BT, 9, 1) 3064 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3065 FIELD(TBFLAG_A64, TBID, 12, 2) 3066 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3067 FIELD(TBFLAG_A64, ATA, 15, 1) 3068 FIELD(TBFLAG_A64, TCMA, 16, 2) 3069 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3070 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3071 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3072 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3073 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3074 FIELD(TBFLAG_A64, SVL, 24, 4) 3075 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3076 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3077 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3078 FIELD(TBFLAG_A64, NAA, 30, 1) 3079 FIELD(TBFLAG_A64, ATA0, 31, 1) 3080 FIELD(TBFLAG_A64, NV, 32, 1) 3081 FIELD(TBFLAG_A64, NV1, 33, 1) 3082 FIELD(TBFLAG_A64, NV2, 34, 1) 3083 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3084 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3085 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3086 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3087 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ 3088 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ 3089 FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2) 3090 3091 /* 3092 * Helpers for using the above. Note that only the A64 accessors use 3093 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3094 * word either is or might be 32 bits only. 3095 */ 3096 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3097 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3098 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3099 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3100 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3101 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3102 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3103 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3104 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3105 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3106 3107 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3108 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3109 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3110 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3111 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3112 3113 /** 3114 * sve_vq 3115 * @env: the cpu context 3116 * 3117 * Return the VL cached within env->hflags, in units of quadwords. 3118 */ 3119 static inline int sve_vq(CPUARMState *env) 3120 { 3121 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3122 } 3123 3124 /** 3125 * sme_vq 3126 * @env: the cpu context 3127 * 3128 * Return the SVL cached within env->hflags, in units of quadwords. 3129 */ 3130 static inline int sme_vq(CPUARMState *env) 3131 { 3132 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3133 } 3134 3135 static inline bool bswap_code(bool sctlr_b) 3136 { 3137 #ifdef CONFIG_USER_ONLY 3138 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3139 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3140 * would also end up as a mixed-endian mode with BE code, LE data. 3141 */ 3142 return TARGET_BIG_ENDIAN ^ sctlr_b; 3143 #else 3144 /* All code access in ARM is little endian, and there are no loaders 3145 * doing swaps that need to be reversed 3146 */ 3147 return 0; 3148 #endif 3149 } 3150 3151 enum { 3152 QEMU_PSCI_CONDUIT_DISABLED = 0, 3153 QEMU_PSCI_CONDUIT_SMC = 1, 3154 QEMU_PSCI_CONDUIT_HVC = 2, 3155 }; 3156 3157 #ifndef CONFIG_USER_ONLY 3158 /* Return the address space index to use for a memory access */ 3159 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3160 { 3161 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3162 } 3163 3164 /* Return the AddressSpace to use for a memory access 3165 * (which depends on whether the access is S or NS, and whether 3166 * the board gave us a separate AddressSpace for S accesses). 3167 */ 3168 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3169 { 3170 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3171 } 3172 #endif 3173 3174 /** 3175 * arm_register_pre_el_change_hook: 3176 * Register a hook function which will be called immediately before this 3177 * CPU changes exception level or mode. The hook function will be 3178 * passed a pointer to the ARMCPU and the opaque data pointer passed 3179 * to this function when the hook was registered. 3180 * 3181 * Note that if a pre-change hook is called, any registered post-change hooks 3182 * are guaranteed to subsequently be called. 3183 */ 3184 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3185 void *opaque); 3186 /** 3187 * arm_register_el_change_hook: 3188 * Register a hook function which will be called immediately after this 3189 * CPU changes exception level or mode. The hook function will be 3190 * passed a pointer to the ARMCPU and the opaque data pointer passed 3191 * to this function when the hook was registered. 3192 * 3193 * Note that any registered hooks registered here are guaranteed to be called 3194 * if pre-change hooks have been. 3195 */ 3196 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3197 *opaque); 3198 3199 /** 3200 * arm_rebuild_hflags: 3201 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3202 */ 3203 void arm_rebuild_hflags(CPUARMState *env); 3204 3205 /** 3206 * aa32_vfp_dreg: 3207 * Return a pointer to the Dn register within env in 32-bit mode. 3208 */ 3209 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3210 { 3211 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3212 } 3213 3214 /** 3215 * aa32_vfp_qreg: 3216 * Return a pointer to the Qn register within env in 32-bit mode. 3217 */ 3218 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3219 { 3220 return &env->vfp.zregs[regno].d[0]; 3221 } 3222 3223 /** 3224 * aa64_vfp_qreg: 3225 * Return a pointer to the Qn register within env in 64-bit mode. 3226 */ 3227 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3228 { 3229 return &env->vfp.zregs[regno].d[0]; 3230 } 3231 3232 /* Shared between translate-sve.c and sve_helper.c. */ 3233 extern const uint64_t pred_esz_masks[5]; 3234 3235 /* 3236 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3237 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3238 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3239 */ 3240 #define PAGE_BTI PAGE_TARGET_1 3241 #define PAGE_MTE PAGE_TARGET_2 3242 #define PAGE_TARGET_STICKY PAGE_MTE 3243 3244 /* We associate one allocation tag per 16 bytes, the minimum. */ 3245 #define LOG2_TAG_GRANULE 4 3246 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3247 3248 #endif 3249