1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <asm/unaligned.h>
9 #include <linux/bitfield.h>
10 #include <media/v4l2-mem2mem.h>
11 #include "hantro.h"
12 #include "hantro_hw.h"
13
14 #define G1_SWREG(nr) ((nr) * 4)
15
16 #define G1_REG_RLC_VLC_BASE G1_SWREG(12)
17 #define G1_REG_DEC_OUT_BASE G1_SWREG(13)
18 #define G1_REG_REFER0_BASE G1_SWREG(14)
19 #define G1_REG_REFER1_BASE G1_SWREG(15)
20 #define G1_REG_REFER2_BASE G1_SWREG(16)
21 #define G1_REG_REFER3_BASE G1_SWREG(17)
22 #define G1_REG_QTABLE_BASE G1_SWREG(40)
23 #define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0)
24
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0)
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0)
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0)
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0)
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0)
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0)
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11))
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0)
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0)
35 #define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0)
36 #define G1_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(6) : 0)
37 #define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0)
38 #define G1_REG_DEC_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))
39
40 #define G1_REG_DEC_MODE(v) (((v) << 28) & GENMASK(31, 28))
41 #define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0)
42 #define G1_REG_PIC_INTERLACE_E(v) ((v) ? BIT(23) : 0)
43 #define G1_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(22) : 0)
44 #define G1_REG_PIC_B_E(v) ((v) ? BIT(21) : 0)
45 #define G1_REG_PIC_INTER_E(v) ((v) ? BIT(20) : 0)
46 #define G1_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(19) : 0)
47 #define G1_REG_FWD_INTERLACE_E(v) ((v) ? BIT(18) : 0)
48 #define G1_REG_FILTERING_DIS(v) ((v) ? BIT(14) : 0)
49 #define G1_REG_WRITE_MVS_E(v) ((v) ? BIT(12) : 0)
50 #define G1_REG_DEC_AXI_WR_ID(v) (((v) << 0) & GENMASK(7, 0))
51
52 #define G1_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
53 #define G1_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))
54 #define G1_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0)
55 #define G1_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0)
56
57 #define G1_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))
58 #define G1_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0)
59 #define G1_REG_CON_MV_E(v) ((v) ? BIT(4) : 0)
60 #define G1_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))
61 #define G1_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0)
62 #define G1_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0)
63
64 #define G1_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
65 #define G1_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
66
67 #define G1_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0)
68 #define G1_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))
69 #define G1_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))
70 #define G1_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))
71 #define G1_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))
72 #define G1_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0)
73 #define G1_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0)
74
75 #define G1_REG_STARTMB_X(v) (((v) << 23) & GENMASK(31, 23))
76 #define G1_REG_STARTMB_Y(v) (((v) << 15) & GENMASK(22, 15))
77
78 #define G1_REG_APF_THRESHOLD(v) (((v) << 0) & GENMASK(13, 0))
79
80 #define PICT_TOP_FIELD 1
81 #define PICT_BOTTOM_FIELD 2
82 #define PICT_FRAME 3
83
84 static void
hantro_g1_mpeg2_dec_set_quantization(struct hantro_dev * vpu,struct hantro_ctx * ctx)85 hantro_g1_mpeg2_dec_set_quantization(struct hantro_dev *vpu,
86 struct hantro_ctx *ctx)
87 {
88 struct v4l2_ctrl_mpeg2_quantization *quantization;
89
90 quantization = hantro_get_ctrl(ctx,
91 V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
92 hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu,
93 quantization);
94 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma,
95 G1_REG_QTABLE_BASE);
96 }
97
98 static void
hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev * vpu,struct hantro_ctx * ctx,struct vb2_buffer * src_buf,struct vb2_buffer * dst_buf,const struct v4l2_mpeg2_sequence * sequence,const struct v4l2_mpeg2_picture * picture,const struct v4l2_ctrl_mpeg2_slice_params * slice_params)99 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx,
100 struct vb2_buffer *src_buf,
101 struct vb2_buffer *dst_buf,
102 const struct v4l2_mpeg2_sequence *sequence,
103 const struct v4l2_mpeg2_picture *picture,
104 const struct v4l2_ctrl_mpeg2_slice_params *slice_params)
105 {
106 dma_addr_t forward_addr = 0, backward_addr = 0;
107 dma_addr_t current_addr, addr;
108
109 switch (picture->picture_coding_type) {
110 case V4L2_MPEG2_PICTURE_CODING_TYPE_B:
111 backward_addr = hantro_get_ref(ctx,
112 slice_params->backward_ref_ts);
113 fallthrough;
114 case V4L2_MPEG2_PICTURE_CODING_TYPE_P:
115 forward_addr = hantro_get_ref(ctx,
116 slice_params->forward_ref_ts);
117 }
118
119 /* Source bitstream buffer */
120 addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
121 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);
122
123 /* Destination frame buffer */
124 addr = hantro_get_dec_buf_addr(ctx, dst_buf);
125 current_addr = addr;
126
127 if (picture->picture_structure == PICT_BOTTOM_FIELD)
128 addr += ALIGN(ctx->dst_fmt.width, 16);
129 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE);
130
131 if (!forward_addr)
132 forward_addr = current_addr;
133 if (!backward_addr)
134 backward_addr = current_addr;
135
136 /* Set forward ref frame (top/bottom field) */
137 if (picture->picture_structure == PICT_FRAME ||
138 picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B ||
139 (picture->picture_structure == PICT_TOP_FIELD &&
140 picture->top_field_first) ||
141 (picture->picture_structure == PICT_BOTTOM_FIELD &&
142 !picture->top_field_first)) {
143 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
144 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
145 } else if (picture->picture_structure == PICT_TOP_FIELD) {
146 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
147 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE);
148 } else if (picture->picture_structure == PICT_BOTTOM_FIELD) {
149 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE);
150 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
151 }
152
153 /* Set backward ref frame (top/bottom field) */
154 vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER2_BASE);
155 vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER3_BASE);
156 }
157
hantro_g1_mpeg2_dec_run(struct hantro_ctx * ctx)158 void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx)
159 {
160 struct hantro_dev *vpu = ctx->dev;
161 struct vb2_v4l2_buffer *src_buf, *dst_buf;
162 const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
163 const struct v4l2_mpeg2_sequence *sequence;
164 const struct v4l2_mpeg2_picture *picture;
165 u32 reg;
166
167 src_buf = hantro_get_src_buf(ctx);
168 dst_buf = hantro_get_dst_buf(ctx);
169
170 /* Apply request controls if any */
171 hantro_start_prepare_run(ctx);
172
173 slice_params = hantro_get_ctrl(ctx,
174 V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
175 sequence = &slice_params->sequence;
176 picture = &slice_params->picture;
177
178 reg = G1_REG_DEC_AXI_RD_ID(0) |
179 G1_REG_DEC_TIMEOUT_E(1) |
180 G1_REG_DEC_STRSWAP32_E(1) |
181 G1_REG_DEC_STRENDIAN_E(1) |
182 G1_REG_DEC_INSWAP32_E(1) |
183 G1_REG_DEC_OUTSWAP32_E(1) |
184 G1_REG_DEC_DATA_DISC_E(0) |
185 G1_REG_DEC_LATENCY(0) |
186 G1_REG_DEC_CLK_GATE_E(1) |
187 G1_REG_DEC_IN_ENDIAN(1) |
188 G1_REG_DEC_OUT_ENDIAN(1) |
189 G1_REG_DEC_ADV_PRE_DIS(0) |
190 G1_REG_DEC_SCMD_DIS(0) |
191 G1_REG_DEC_MAX_BURST(16);
192 vdpu_write_relaxed(vpu, reg, G1_SWREG(2));
193
194 reg = G1_REG_DEC_MODE(5) |
195 G1_REG_RLC_MODE_E(0) |
196 G1_REG_PIC_INTERLACE_E(!sequence->progressive_sequence) |
197 G1_REG_PIC_FIELDMODE_E(picture->picture_structure != PICT_FRAME) |
198 G1_REG_PIC_B_E(picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B) |
199 G1_REG_PIC_INTER_E(picture->picture_coding_type != V4L2_MPEG2_PICTURE_CODING_TYPE_I) |
200 G1_REG_PIC_TOPFIELD_E(picture->picture_structure == PICT_TOP_FIELD) |
201 G1_REG_FWD_INTERLACE_E(0) |
202 G1_REG_FILTERING_DIS(1) |
203 G1_REG_WRITE_MVS_E(0) |
204 G1_REG_DEC_AXI_WR_ID(0);
205 vdpu_write_relaxed(vpu, reg, G1_SWREG(3));
206
207 reg = G1_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->dst_fmt.width)) |
208 G1_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->dst_fmt.height)) |
209 G1_REG_ALT_SCAN_E(picture->alternate_scan) |
210 G1_REG_TOPFIELDFIRST_E(picture->top_field_first);
211 vdpu_write_relaxed(vpu, reg, G1_SWREG(4));
212
213 reg = G1_REG_STRM_START_BIT(slice_params->data_bit_offset) |
214 G1_REG_QSCALE_TYPE(picture->q_scale_type) |
215 G1_REG_CON_MV_E(picture->concealment_motion_vectors) |
216 G1_REG_INTRA_DC_PREC(picture->intra_dc_precision) |
217 G1_REG_INTRA_VLC_TAB(picture->intra_vlc_format) |
218 G1_REG_FRAME_PRED_DCT(picture->frame_pred_frame_dct);
219 vdpu_write_relaxed(vpu, reg, G1_SWREG(5));
220
221 reg = G1_REG_INIT_QP(1) |
222 G1_REG_STREAM_LEN(slice_params->bit_size >> 3);
223 vdpu_write_relaxed(vpu, reg, G1_SWREG(6));
224
225 reg = G1_REG_ALT_SCAN_FLAG_E(picture->alternate_scan) |
226 G1_REG_FCODE_FWD_HOR(picture->f_code[0][0]) |
227 G1_REG_FCODE_FWD_VER(picture->f_code[0][1]) |
228 G1_REG_FCODE_BWD_HOR(picture->f_code[1][0]) |
229 G1_REG_FCODE_BWD_VER(picture->f_code[1][1]) |
230 G1_REG_MV_ACCURACY_FWD(1) |
231 G1_REG_MV_ACCURACY_BWD(1);
232 vdpu_write_relaxed(vpu, reg, G1_SWREG(18));
233
234 reg = G1_REG_STARTMB_X(0) |
235 G1_REG_STARTMB_Y(0);
236 vdpu_write_relaxed(vpu, reg, G1_SWREG(48));
237
238 reg = G1_REG_APF_THRESHOLD(8);
239 vdpu_write_relaxed(vpu, reg, G1_SWREG(55));
240
241 hantro_g1_mpeg2_dec_set_quantization(vpu, ctx);
242
243 hantro_g1_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
244 &dst_buf->vb2_buf,
245 sequence, picture, slice_params);
246
247 hantro_end_prepare_run(ctx);
248
249 reg = G1_REG_DEC_E(1);
250 vdpu_write(vpu, reg, G1_SWREG(1));
251 }
252