1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2014-2019 Intel Corporation
4 */
5
6 #ifndef _INTEL_GUC_FWIF_H
7 #define _INTEL_GUC_FWIF_H
8
9 #include <linux/bits.h>
10 #include <linux/compiler.h>
11 #include <linux/types.h>
12 #include "gt/intel_engine_types.h"
13
14 #include "abi/guc_actions_abi.h"
15 #include "abi/guc_actions_slpc_abi.h"
16 #include "abi/guc_errors_abi.h"
17 #include "abi/guc_communication_mmio_abi.h"
18 #include "abi/guc_communication_ctb_abi.h"
19 #include "abi/guc_klvs_abi.h"
20 #include "abi/guc_messages_abi.h"
21
22 /* Payload length only i.e. don't include G2H header length */
23 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2
24 #define G2H_LEN_DW_DEREGISTER_CONTEXT 1
25 #define G2H_LEN_DW_INVALIDATE_TLB 1
26
27 #define GUC_CONTEXT_DISABLE 0
28 #define GUC_CONTEXT_ENABLE 1
29
30 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0
31 #define GUC_CLIENT_PRIORITY_HIGH 1
32 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
33 #define GUC_CLIENT_PRIORITY_NORMAL 3
34 #define GUC_CLIENT_PRIORITY_NUM 4
35
36 #define GUC_MAX_CONTEXT_ID 65535
37 #define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID
38
39 #define GUC_RENDER_CLASS 0
40 #define GUC_VIDEO_CLASS 1
41 #define GUC_VIDEOENHANCE_CLASS 2
42 #define GUC_BLITTER_CLASS 3
43 #define GUC_COMPUTE_CLASS 4
44 #define GUC_GSC_OTHER_CLASS 5
45 #define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
46 #define GUC_MAX_ENGINE_CLASSES 16
47 #define GUC_MAX_INSTANCES_PER_CLASS 32
48
49 #define GUC_DOORBELL_INVALID 256
50
51 /*
52 * Work queue item header definitions
53 *
54 * Work queue is circular buffer used to submit complex (multi-lrc) submissions
55 * to the GuC. A work queue item is an entry in the circular buffer.
56 */
57 #define WQ_STATUS_ACTIVE 1
58 #define WQ_STATUS_SUSPENDED 2
59 #define WQ_STATUS_CMD_ERROR 3
60 #define WQ_STATUS_ENGINE_ID_NOT_USED 4
61 #define WQ_STATUS_SUSPENDED_FROM_RESET 5
62 #define WQ_TYPE_BATCH_BUF 0x1
63 #define WQ_TYPE_PSEUDO 0x2
64 #define WQ_TYPE_INORDER 0x3
65 #define WQ_TYPE_NOOP 0x4
66 #define WQ_TYPE_MULTI_LRC 0x5
67 #define WQ_TYPE_MASK GENMASK(7, 0)
68 #define WQ_LEN_MASK GENMASK(26, 16)
69
70 #define WQ_GUC_ID_MASK GENMASK(15, 0)
71 #define WQ_RING_TAIL_MASK GENMASK(28, 18)
72
73 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
74 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
75 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
76 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
77 #define GUC_STAGE_DESC_ATTR_RESET BIT(4)
78 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
79 #define GUC_STAGE_DESC_ATTR_PCH BIT(6)
80 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
81
82 #define GUC_CTL_LOG_PARAMS 0
83 #define GUC_LOG_VALID BIT(0)
84 #define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)
85 #define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)
86 #define GUC_LOG_LOG_ALLOC_UNITS BIT(3)
87 #define GUC_LOG_CRASH_SHIFT 4
88 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
89 #define GUC_LOG_DEBUG_SHIFT 6
90 #define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)
91 #define GUC_LOG_CAPTURE_SHIFT 10
92 #define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT)
93 #define GUC_LOG_BUF_ADDR_SHIFT 12
94
95 #define GUC_CTL_WA 1
96 #define GUC_WA_GAM_CREDITS BIT(10)
97 #define GUC_WA_DUAL_QUEUE BIT(11)
98 #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
99 #define GUC_WA_CONTEXT_ISOLATION BIT(15)
100 #define GUC_WA_PRE_PARSER BIT(14)
101 #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
102 #define GUC_WA_POLLCS BIT(18)
103 #define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
104 #define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)
105
106 #define GUC_CTL_FEATURE 2
107 #define GUC_CTL_ENABLE_SLPC BIT(2)
108 #define GUC_CTL_DISABLE_SCHEDULER BIT(14)
109
110 #define GUC_CTL_DEBUG 3
111 #define GUC_LOG_VERBOSITY_SHIFT 0
112 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
113 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
114 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
115 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
116 /* Verbosity range-check limits, without the shift */
117 #define GUC_LOG_VERBOSITY_MIN 0
118 #define GUC_LOG_VERBOSITY_MAX 3
119 #define GUC_LOG_VERBOSITY_MASK 0x0000000f
120 #define GUC_LOG_DESTINATION_MASK (3 << 4)
121 #define GUC_LOG_DISABLED (1 << 6)
122 #define GUC_PROFILE_ENABLED (1 << 7)
123
124 #define GUC_CTL_ADS 4
125 #define GUC_ADS_ADDR_SHIFT 1
126 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
127
128 #define GUC_CTL_DEVID 5
129
130 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
131
132 /* Generic GT SysInfo data types */
133 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0
134 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1
135 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2
136 #define GUC_GENERIC_GT_SYSINFO_MAX 16
137
138 /*
139 * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6].
140 * Bit 7 can be used for operations that apply to all engine classes&instances.
141 */
142 #define GUC_ENGINE_CLASS_SHIFT 0
143 #define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT)
144 #define GUC_ENGINE_INSTANCE_SHIFT 3
145 #define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT)
146 #define GUC_ENGINE_ALL_INSTANCES BIT(7)
147
148 #define MAKE_GUC_ID(class, instance) \
149 (((class) << GUC_ENGINE_CLASS_SHIFT) | \
150 ((instance) << GUC_ENGINE_INSTANCE_SHIFT))
151
152 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \
153 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT)
154 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
155 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
156
157 #define SLPC_EVENT(id, c) (\
158 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \
159 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \
160 )
161
162 /* the GuC arrays don't include OTHER_CLASS */
163 static u8 engine_class_guc_class_map[] = {
164 [RENDER_CLASS] = GUC_RENDER_CLASS,
165 [COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS,
166 [VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS,
167 [VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
168 [OTHER_CLASS] = GUC_GSC_OTHER_CLASS,
169 [COMPUTE_CLASS] = GUC_COMPUTE_CLASS,
170 };
171
172 static u8 guc_class_engine_class_map[] = {
173 [GUC_RENDER_CLASS] = RENDER_CLASS,
174 [GUC_BLITTER_CLASS] = COPY_ENGINE_CLASS,
175 [GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS,
176 [GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
177 [GUC_COMPUTE_CLASS] = COMPUTE_CLASS,
178 [GUC_GSC_OTHER_CLASS] = OTHER_CLASS,
179 };
180
engine_class_to_guc_class(u8 class)181 static inline u8 engine_class_to_guc_class(u8 class)
182 {
183 BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
184 GEM_BUG_ON(class > MAX_ENGINE_CLASS);
185
186 return engine_class_guc_class_map[class];
187 }
188
guc_class_to_engine_class(u8 guc_class)189 static inline u8 guc_class_to_engine_class(u8 guc_class)
190 {
191 BUILD_BUG_ON(ARRAY_SIZE(guc_class_engine_class_map) != GUC_LAST_ENGINE_CLASS + 1);
192 GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
193
194 return guc_class_engine_class_map[guc_class];
195 }
196
197 /* Work item for submitting workloads into work queue of GuC. */
198 struct guc_wq_item {
199 u32 header;
200 u32 context_desc;
201 u32 submit_element_info;
202 u32 fence_id;
203 } __packed;
204
205 struct guc_process_desc_v69 {
206 u32 stage_id;
207 u64 db_base_addr;
208 u32 head;
209 u32 tail;
210 u32 error_offset;
211 u64 wq_base_addr;
212 u32 wq_size_bytes;
213 u32 wq_status;
214 u32 engine_presence;
215 u32 priority;
216 u32 reserved[36];
217 } __packed;
218
219 struct guc_sched_wq_desc {
220 u32 head;
221 u32 tail;
222 u32 error_offset;
223 u32 wq_status;
224 u32 reserved[28];
225 } __packed;
226
227 /* Helper for context registration H2G */
228 struct guc_ctxt_registration_info {
229 u32 flags;
230 u32 context_idx;
231 u32 engine_class;
232 u32 engine_submit_mask;
233 u32 wq_desc_lo;
234 u32 wq_desc_hi;
235 u32 wq_base_lo;
236 u32 wq_base_hi;
237 u32 wq_size;
238 u32 hwlrca_lo;
239 u32 hwlrca_hi;
240 };
241 #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
242
243 /* Preempt to idle on quantum expiry */
244 #define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE_V69 BIT(0)
245
246 /*
247 * GuC Context registration descriptor.
248 * FIXME: This is only required to exist during context registration.
249 * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
250 * is not required.
251 */
252 struct guc_lrc_desc_v69 {
253 u32 hw_context_desc;
254 u32 slpm_perf_mode_hint; /* SPLC v1 only */
255 u32 slpm_freq_hint;
256 u32 engine_submit_mask; /* In logical space */
257 u8 engine_class;
258 u8 reserved0[3];
259 u32 priority;
260 u32 process_desc;
261 u32 wq_addr;
262 u32 wq_size;
263 u32 context_flags; /* CONTEXT_REGISTRATION_* */
264 /* Time for one workload to execute. (in micro seconds) */
265 u32 execution_quantum;
266 /* Time to wait for a preemption request to complete before issuing a
267 * reset. (in micro seconds).
268 */
269 u32 preemption_timeout;
270 u32 policy_flags; /* CONTEXT_POLICY_* */
271 u32 reserved1[19];
272 } __packed;
273
274 /* 32-bit KLV structure as used by policy updates and others */
275 struct guc_klv_generic_dw_t {
276 u32 kl;
277 u32 value;
278 } __packed;
279
280 /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
281 struct guc_update_context_policy_header {
282 u32 action;
283 u32 ctx_id;
284 } __packed;
285
286 struct guc_update_context_policy {
287 struct guc_update_context_policy_header header;
288 struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
289 } __packed;
290
291 /* Format of the UPDATE_SCHEDULING_POLICIES H2G data packet */
292 struct guc_update_scheduling_policy_header {
293 u32 action;
294 } __packed;
295
296 /*
297 * Can't dynmically allocate memory for the scheduling policy KLV because
298 * it will be sent from within the reset path. Need a fixed size lump on
299 * the stack instead :(.
300 *
301 * Currently, there is only one KLV defined, which has 1 word of KL + 2 words of V.
302 */
303 #define MAX_SCHEDULING_POLICY_SIZE 3
304
305 struct guc_update_scheduling_policy {
306 struct guc_update_scheduling_policy_header header;
307 u32 data[MAX_SCHEDULING_POLICY_SIZE];
308 } __packed;
309
310 #define GUC_POWER_UNSPECIFIED 0
311 #define GUC_POWER_D0 1
312 #define GUC_POWER_D1 2
313 #define GUC_POWER_D2 3
314 #define GUC_POWER_D3 4
315
316 /* Scheduling policy settings */
317
318 #define GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION 100 /* in ms */
319 #define GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO 50 /* in percent */
320
321 #define GLOBAL_POLICY_MAX_NUM_WI 15
322
323 /* Don't reset an engine upon preemption failure */
324 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
325
326 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
327
328 /*
329 * GuC converts the timeout to clock ticks internally. Different platforms have
330 * different GuC clocks. Thus, the maximum value before overflow is platform
331 * dependent. Current worst case scenario is about 110s. So, the spec says to
332 * limit to 100s to be safe.
333 */
334 #define GUC_POLICY_MAX_EXEC_QUANTUM_US (100 * 1000 * 1000UL)
335 #define GUC_POLICY_MAX_PREEMPT_TIMEOUT_US (100 * 1000 * 1000UL)
336
guc_policy_max_exec_quantum_ms(void)337 static inline u32 guc_policy_max_exec_quantum_ms(void)
338 {
339 BUILD_BUG_ON(GUC_POLICY_MAX_EXEC_QUANTUM_US >= UINT_MAX);
340 return GUC_POLICY_MAX_EXEC_QUANTUM_US / 1000;
341 }
342
guc_policy_max_preempt_timeout_ms(void)343 static inline u32 guc_policy_max_preempt_timeout_ms(void)
344 {
345 BUILD_BUG_ON(GUC_POLICY_MAX_PREEMPT_TIMEOUT_US >= UINT_MAX);
346 return GUC_POLICY_MAX_PREEMPT_TIMEOUT_US / 1000;
347 }
348
349 struct guc_policies {
350 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
351 /* In micro seconds. How much time to allow before DPC processing is
352 * called back via interrupt (to prevent DPC queue drain starving).
353 * Typically 1000s of micro seconds (example only, not granularity). */
354 u32 dpc_promote_time;
355
356 /* Must be set to take these new values. */
357 u32 is_valid;
358
359 /* Max number of WIs to process per call. A large value may keep CS
360 * idle. */
361 u32 max_num_work_items;
362
363 u32 global_flags;
364 u32 reserved[4];
365 } __packed;
366
367 /* GuC MMIO reg state struct */
368 struct guc_mmio_reg {
369 u32 offset;
370 u32 value;
371 u32 flags;
372 #define GUC_REGSET_MASKED BIT(0)
373 #define GUC_REGSET_NEEDS_STEERING BIT(1)
374 #define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
375 #define GUC_REGSET_RESTORE_ONLY BIT(3)
376 #define GUC_REGSET_STEERING_GROUP GENMASK(15, 12)
377 #define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)
378 u32 mask;
379 } __packed;
380
381 /* GuC register sets */
382 struct guc_mmio_reg_set {
383 u32 address;
384 u16 count;
385 u16 reserved;
386 } __packed;
387
388 /* HW info */
389 struct guc_gt_system_info {
390 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
391 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
392 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
393 } __packed;
394
395 enum {
396 GUC_CAPTURE_LIST_INDEX_PF = 0,
397 GUC_CAPTURE_LIST_INDEX_VF = 1,
398 GUC_CAPTURE_LIST_INDEX_MAX = 2,
399 };
400
401 /*Register-types of GuC capture register lists */
402 enum guc_capture_type {
403 GUC_CAPTURE_LIST_TYPE_GLOBAL = 0,
404 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
405 GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
406 GUC_CAPTURE_LIST_TYPE_MAX,
407 };
408
409 /* Class indecies for capture_class and capture_instance arrays */
410 enum {
411 GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0,
412 GUC_CAPTURE_LIST_CLASS_VIDEO = 1,
413 GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2,
414 GUC_CAPTURE_LIST_CLASS_BLITTER = 3,
415 GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4,
416 };
417
418 /* GuC Additional Data Struct */
419 struct guc_ads {
420 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
421 u32 reserved0;
422 u32 scheduler_policies;
423 u32 gt_system_info;
424 u32 reserved1;
425 u32 control_data;
426 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
427 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
428 u32 private_data;
429 u32 reserved2;
430 u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
431 u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
432 u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
433 u32 reserved[14];
434 } __packed;
435
436 /* Engine usage stats */
437 struct guc_engine_usage_record {
438 u32 current_context_index;
439 u32 last_switch_in_stamp;
440 u32 reserved0;
441 u32 total_runtime;
442 u32 reserved1[4];
443 } __packed;
444
445 struct guc_engine_usage {
446 struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
447 } __packed;
448
449 /* GuC logging structures */
450
451 enum guc_log_buffer_type {
452 GUC_DEBUG_LOG_BUFFER,
453 GUC_CRASH_DUMP_LOG_BUFFER,
454 GUC_CAPTURE_LOG_BUFFER,
455 GUC_MAX_LOG_BUFFER
456 };
457
458 /*
459 * struct guc_log_buffer_state - GuC log buffer state
460 *
461 * Below state structure is used for coordination of retrieval of GuC firmware
462 * logs. Separate state is maintained for each log buffer type.
463 * read_ptr points to the location where i915 read last in log buffer and
464 * is read only for GuC firmware. write_ptr is incremented by GuC with number
465 * of bytes written for each log entry and is read only for i915.
466 * When any type of log buffer becomes half full, GuC sends a flush interrupt.
467 * GuC firmware expects that while it is writing to 2nd half of the buffer,
468 * first half would get consumed by Host and then get a flush completed
469 * acknowledgment from Host, so that it does not end up doing any overwrite
470 * causing loss of logs. So when buffer gets half filled & i915 has requested
471 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
472 * to the value of write_ptr and raise the interrupt.
473 * On receiving the interrupt i915 should read the buffer, clear flush_to_file
474 * field and also update read_ptr with the value of sample_write_ptr, before
475 * sending an acknowledgment to GuC. marker & version fields are for internal
476 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
477 * time GuC detects the log buffer overflow.
478 */
479 struct guc_log_buffer_state {
480 u32 marker[2];
481 u32 read_ptr;
482 u32 write_ptr;
483 u32 size;
484 u32 sampled_write_ptr;
485 u32 wrap_offset;
486 union {
487 struct {
488 u32 flush_to_file:1;
489 u32 buffer_full_cnt:4;
490 u32 reserved:27;
491 };
492 u32 flags;
493 };
494 u32 version;
495 } __packed;
496
497 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
498 enum intel_guc_recv_message {
499 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
500 INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30),
501 };
502
503 #endif
504