1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__ 27 #define __DAL_TIMING_GENERATOR_TYPES_H__ 28 29 #include "hw_shared.h" 30 31 struct dc_bios; 32 33 /* Contains CRTC vertical/horizontal pixel counters */ 34 struct crtc_position { 35 int32_t vertical_count; 36 int32_t horizontal_count; 37 int32_t nominal_vcount; 38 }; 39 40 struct dcp_gsl_params { 41 int gsl_group; 42 int gsl_master; 43 }; 44 45 struct gsl_params { 46 int gsl0_en; 47 int gsl1_en; 48 int gsl2_en; 49 int gsl_master_en; 50 int gsl_master_mode; 51 int master_update_lock_gsl_en; 52 int gsl_window_start_x; 53 int gsl_window_end_x; 54 int gsl_window_start_y; 55 int gsl_window_end_y; 56 }; 57 58 /* define the structure of Dynamic Refresh Mode */ 59 struct drr_params { 60 uint32_t vertical_total_min; 61 uint32_t vertical_total_max; 62 uint32_t vertical_total_mid; 63 uint32_t vertical_total_mid_frame_num; 64 bool immediate_flip; 65 }; 66 67 struct long_vtotal_params { 68 uint32_t vertical_total_min; 69 uint32_t vertical_total_max; 70 uint32_t vertical_blank_start; 71 }; 72 73 #define LEFT_EYE_3D_PRIMARY_SURFACE 1 74 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0 75 76 enum crtc_state { 77 CRTC_STATE_VBLANK = 0, 78 CRTC_STATE_VACTIVE 79 }; 80 81 struct vupdate_keepout_params { 82 int start_offset; 83 int end_offset; 84 int enable; 85 }; 86 87 struct crtc_stereo_flags { 88 uint8_t PROGRAM_STEREO : 1; 89 uint8_t PROGRAM_POLARITY : 1; 90 uint8_t RIGHT_EYE_POLARITY : 1; 91 uint8_t FRAME_PACKED : 1; 92 uint8_t DISABLE_STEREO_DP_SYNC : 1; 93 }; 94 95 enum crc_selection { 96 /* Order must match values expected by hardware */ 97 UNION_WINDOW_A_B = 0, 98 UNION_WINDOW_A_NOT_B, 99 UNION_WINDOW_NOT_A_B, 100 UNION_WINDOW_NOT_A_NOT_B, 101 INTERSECT_WINDOW_A_B, 102 INTERSECT_WINDOW_A_NOT_B, 103 INTERSECT_WINDOW_NOT_A_B, 104 INTERSECT_WINDOW_NOT_A_NOT_B, 105 }; 106 107 enum otg_out_mux_dest { 108 OUT_MUX_DIO = 0, 109 OUT_MUX_HPO_DP = 2, 110 }; 111 112 enum h_timing_div_mode { 113 H_TIMING_NO_DIV, 114 H_TIMING_DIV_BY2, 115 H_TIMING_RESERVED, 116 H_TIMING_DIV_BY4, 117 }; 118 119 enum timing_synchronization_type { 120 NOT_SYNCHRONIZABLE, 121 TIMING_SYNCHRONIZABLE, 122 VBLANK_SYNCHRONIZABLE 123 }; 124 125 struct crc_params { 126 /* Regions used to calculate CRC*/ 127 uint16_t windowa_x_start; 128 uint16_t windowa_x_end; 129 uint16_t windowa_y_start; 130 uint16_t windowa_y_end; 131 132 uint16_t windowb_x_start; 133 uint16_t windowb_x_end; 134 uint16_t windowb_y_start; 135 uint16_t windowb_y_end; 136 137 enum crc_selection selection; 138 139 uint8_t dsc_mode; 140 uint8_t odm_mode; 141 142 bool continuous_mode; 143 bool enable; 144 145 uint8_t crc_eng_inst; 146 bool reset; 147 }; 148 149 struct dcn_otg_state { 150 uint32_t v_blank_start; 151 uint32_t v_blank_end; 152 uint32_t v_sync_a_pol; 153 uint32_t v_total; 154 uint32_t v_total_max; 155 uint32_t v_total_min; 156 uint32_t v_total_min_sel; 157 uint32_t v_total_max_sel; 158 uint32_t v_sync_a_start; 159 uint32_t v_sync_a_end; 160 uint32_t h_blank_start; 161 uint32_t h_blank_end; 162 uint32_t h_sync_a_start; 163 uint32_t h_sync_a_end; 164 uint32_t h_sync_a_pol; 165 uint32_t h_total; 166 uint32_t underflow_occurred_status; 167 uint32_t otg_enabled; 168 uint32_t blank_enabled; 169 uint32_t vertical_interrupt1_en; 170 uint32_t vertical_interrupt1_line; 171 uint32_t vertical_interrupt2_en; 172 uint32_t vertical_interrupt2_line; 173 uint32_t vertical_interrupt2_dest; 174 uint32_t otg_master_update_lock; 175 uint32_t otg_double_buffer_control; 176 }; 177 178 /** 179 * struct timing_generator - Entry point to Output Timing Generator feature. 180 */ 181 struct timing_generator { 182 /** 183 * @funcs: Timing generator control functions 184 */ 185 const struct timing_generator_funcs *funcs; 186 struct dc_bios *bp; 187 struct dc_context *ctx; 188 int inst; 189 }; 190 191 struct dc_crtc_timing; 192 193 struct drr_params; 194 195 /** 196 * struct timing_generator_funcs - Control timing generator on a given device. 197 */ 198 struct timing_generator_funcs { 199 bool (*validate_timing)(struct timing_generator *tg, 200 const struct dc_crtc_timing *timing); 201 void (*program_timing)(struct timing_generator *tg, 202 const struct dc_crtc_timing *timing, 203 int vready_offset, 204 int vstartup_start, 205 int vupdate_offset, 206 int vupdate_width, 207 int pstate_keepout, 208 const enum signal_type signal, 209 bool use_vbios 210 ); 211 void (*setup_vertical_interrupt0)( 212 struct timing_generator *optc, 213 uint32_t start_line, 214 uint32_t end_line); 215 void (*setup_vertical_interrupt1)( 216 struct timing_generator *optc, 217 uint32_t start_line); 218 void (*setup_vertical_interrupt2)( 219 struct timing_generator *optc, 220 uint32_t start_line); 221 222 bool (*enable_crtc)(struct timing_generator *tg); 223 bool (*disable_crtc)(struct timing_generator *tg); 224 void (*phantom_crtc_post_enable)(struct timing_generator *tg); 225 void (*disable_phantom_crtc)(struct timing_generator *tg); 226 bool (*immediate_disable_crtc)(struct timing_generator *tg); 227 bool (*is_counter_moving)(struct timing_generator *tg); 228 void (*get_position)(struct timing_generator *tg, 229 struct crtc_position *position); 230 231 uint32_t (*get_frame_count)(struct timing_generator *tg); 232 void (*get_scanoutpos)( 233 struct timing_generator *tg, 234 uint32_t *v_blank_start, 235 uint32_t *v_blank_end, 236 uint32_t *h_position, 237 uint32_t *v_position); 238 bool (*get_otg_active_size)(struct timing_generator *optc, 239 uint32_t *otg_active_width, 240 uint32_t *otg_active_height); 241 bool (*is_matching_timing)(struct timing_generator *tg, 242 const struct dc_crtc_timing *otg_timing); 243 void (*set_early_control)(struct timing_generator *tg, 244 uint32_t early_cntl); 245 void (*wait_for_state)(struct timing_generator *tg, 246 enum crtc_state state); 247 void (*set_blank)(struct timing_generator *tg, 248 bool enable_blanking); 249 bool (*is_blanked)(struct timing_generator *tg); 250 void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); 251 void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color); 252 void (*set_colors)(struct timing_generator *tg, 253 const struct tg_color *blank_color, 254 const struct tg_color *overscan_color); 255 256 void (*disable_vga)(struct timing_generator *tg); 257 bool (*did_triggered_reset_occur)(struct timing_generator *tg); 258 void (*setup_global_swap_lock)(struct timing_generator *tg, 259 const struct dcp_gsl_params *gsl_params); 260 void (*unlock)(struct timing_generator *tg); 261 void (*lock)(struct timing_generator *tg); 262 void (*lock_doublebuffer_disable)(struct timing_generator *tg); 263 void (*lock_doublebuffer_enable)(struct timing_generator *tg); 264 void(*triplebuffer_unlock)(struct timing_generator *tg); 265 void(*triplebuffer_lock)(struct timing_generator *tg); 266 void (*enable_reset_trigger)(struct timing_generator *tg, 267 int source_tg_inst); 268 void (*enable_crtc_reset)(struct timing_generator *tg, 269 int source_tg_inst, 270 struct crtc_trigger_info *crtc_tp); 271 void (*disable_reset_trigger)(struct timing_generator *tg); 272 void (*tear_down_global_swap_lock)(struct timing_generator *tg); 273 void (*enable_advanced_request)(struct timing_generator *tg, 274 bool enable, const struct dc_crtc_timing *timing); 275 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); 276 void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max); 277 void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate); 278 void (*set_static_screen_control)(struct timing_generator *tg, 279 uint32_t event_triggers, 280 uint32_t num_frames); 281 void (*set_test_pattern)( 282 struct timing_generator *tg, 283 enum controller_dp_test_pattern test_pattern, 284 enum dc_color_depth color_depth); 285 286 bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); 287 288 void (*program_global_sync)(struct timing_generator *tg, 289 int vready_offset, 290 int vstartup_start, 291 int vupdate_offset, 292 int vupdate_width, 293 int pstate_keepout); 294 void (*enable_optc_clock)(struct timing_generator *tg, bool enable); 295 void (*program_stereo)(struct timing_generator *tg, 296 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 297 bool (*is_stereo_left_eye)(struct timing_generator *tg); 298 299 void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); 300 301 void (*tg_init)(struct timing_generator *tg); 302 bool (*is_tg_enabled)(struct timing_generator *tg); 303 bool (*is_optc_underflow_occurred)(struct timing_generator *tg); 304 void (*clear_optc_underflow)(struct timing_generator *tg); 305 306 void (*set_dwb_source)(struct timing_generator *optc, 307 uint32_t dwb_pipe_inst); 308 309 void (*get_optc_source)(struct timing_generator *optc, 310 uint32_t *num_of_input_segments, 311 uint32_t *seg0_src_sel, 312 uint32_t *seg1_src_sel); 313 bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing); 314 315 /** 316 * Configure CRCs for the given timing generator. Return false if TG is 317 * not on. 318 */ 319 bool (*configure_crc)(struct timing_generator *tg, 320 const struct crc_params *params); 321 322 /** 323 * @get_crc: Get CRCs for the given timing generator. Return false if 324 * CRCs are not enabled (via configure_crc). 325 */ 326 bool (*get_crc)(struct timing_generator *tg, uint8_t idx, 327 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 328 329 void (*program_manual_trigger)(struct timing_generator *optc); 330 void (*setup_manual_trigger)(struct timing_generator *optc); 331 bool (*get_hw_timing)(struct timing_generator *optc, 332 struct dc_crtc_timing *hw_crtc_timing); 333 334 void (*set_vtg_params)(struct timing_generator *optc, 335 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 336 337 void (*set_dsc_config)(struct timing_generator *optc, 338 enum optc_dsc_mode dsc_mode, 339 uint32_t dsc_bytes_per_pixel, 340 uint32_t dsc_slice_width); 341 void (*get_dsc_status)(struct timing_generator *optc, 342 uint32_t *dsc_mode); 343 void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); 344 345 /** 346 * @set_odm_combine: Set up the ODM block to read from the correct 347 * OPP(s) and turn on/off ODM memory. 348 */ 349 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, 350 int segment_width, int last_segment_width); 351 void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments); 352 void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode); 353 void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); 354 void (*set_gsl_source_select)(struct timing_generator *optc, 355 int group_idx, 356 uint32_t gsl_ready_signal); 357 void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest); 358 void (*set_drr_trigger_window)(struct timing_generator *optc, 359 uint32_t window_start, uint32_t window_end); 360 void (*set_vtotal_change_limit)(struct timing_generator *optc, 361 uint32_t limit); 362 void (*align_vblanks)(struct timing_generator *master_optc, 363 struct timing_generator *slave_optc, 364 uint32_t master_pixel_clock_100Hz, 365 uint32_t slave_pixel_clock_100Hz, 366 uint8_t master_clock_divider, 367 uint8_t slave_clock_divider); 368 bool (*validate_vmin_vmax)(struct timing_generator *optc, 369 int vmin, int vmax); 370 bool (*validate_vtotal_change_limit)(struct timing_generator *optc, 371 uint32_t vtotal_change_limit); 372 373 void (*init_odm)(struct timing_generator *tg); 374 void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); 375 void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); 376 void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); 377 bool (*get_optc_double_buffer_pending)(struct timing_generator *tg); 378 bool (*get_otg_double_buffer_pending)(struct timing_generator *tg); 379 bool (*get_pipe_update_pending)(struct timing_generator *tg); 380 void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable); 381 bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked); 382 void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s); 383 }; 384 385 #endif 386