1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_EN_STATS_H__
34 #define __MLX5_EN_STATS_H__
35
36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
44
45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
53
54 #define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
55 #define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
56 #define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
57 #define MLX5E_DECLARE_PTP_RQ_STAT(type, fld) "ptp_rq%d_"#fld, offsetof(type, fld)
58
59 #define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)
60
61 struct counter_desc {
62 char format[ETH_GSTRING_LEN];
63 size_t offset; /* Byte offset */
64 };
65
66 enum {
67 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
68 };
69
70 struct mlx5e_priv;
71 struct mlx5e_stats_grp {
72 u16 update_stats_mask;
73 int (*get_num_stats)(struct mlx5e_priv *priv);
74 void (*fill_strings)(struct mlx5e_priv *priv, u8 **data);
75 void (*fill_stats)(struct mlx5e_priv *priv, u64 **data);
76 void (*update_stats)(struct mlx5e_priv *priv);
77 };
78
79 void mlx5e_ethtool_put_stat(u64 **data, u64 val);
80
81 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
82
83 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
84
85 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
86 int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
87
88 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
89 void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
90
91 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
92 void MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 **data)
93
94 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
95 void MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 **data)
96
97 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
98
99 #define MLX5E_DECLARE_STATS_GRP(grp) \
100 const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
101
102 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \
103 MLX5E_DECLARE_STATS_GRP(grp) = { \
104 .get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
105 .fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \
106 .fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \
107 .update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \
108 .update_stats_mask = mask, \
109 }
110
111 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
112 void mlx5e_stats_update(struct mlx5e_priv *priv);
113 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
114 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
115 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
116
117 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
118 struct ethtool_pause_stats *pause_stats);
119 void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
120 struct ethtool_fec_stats *fec_stats);
121
122 void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
123 struct ethtool_eth_phy_stats *phy_stats);
124 void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
125 struct ethtool_eth_mac_stats *mac_stats);
126 void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
127 struct ethtool_eth_ctrl_stats *ctrl_stats);
128 void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
129 struct ethtool_rmon_stats *rmon,
130 const struct ethtool_rmon_hist_range **ranges);
131 void mlx5e_stats_ts_get(struct mlx5e_priv *priv,
132 struct ethtool_ts_stats *ts_stats);
133 void mlx5e_get_link_ext_stats(struct net_device *dev,
134 struct ethtool_link_ext_stats *stats);
135
136 /* Concrete NIC Stats */
137
138 struct mlx5e_sw_stats {
139 u64 rx_packets;
140 u64 rx_bytes;
141 u64 tx_packets;
142 u64 tx_bytes;
143 u64 tx_tso_packets;
144 u64 tx_tso_bytes;
145 u64 tx_tso_inner_packets;
146 u64 tx_tso_inner_bytes;
147 u64 tx_added_vlan_packets;
148 u64 tx_nop;
149 u64 tx_mpwqe_blks;
150 u64 tx_mpwqe_pkts;
151 u64 rx_lro_packets;
152 u64 rx_lro_bytes;
153 u64 rx_gro_packets;
154 u64 rx_gro_bytes;
155 u64 rx_gro_skbs;
156 u64 rx_gro_large_hds;
157 u64 rx_hds_nodata_packets;
158 u64 rx_hds_nodata_bytes;
159 u64 rx_hds_nosplit_packets;
160 u64 rx_hds_nosplit_bytes;
161 u64 rx_mcast_packets;
162 u64 rx_ecn_mark;
163 u64 rx_removed_vlan_packets;
164 u64 rx_csum_unnecessary;
165 u64 rx_csum_none;
166 u64 rx_csum_complete;
167 u64 rx_csum_complete_tail;
168 u64 rx_csum_complete_tail_slow;
169 u64 rx_csum_unnecessary_inner;
170 u64 rx_xdp_drop;
171 u64 rx_xdp_redirect;
172 u64 rx_xdp_tx_xmit;
173 u64 rx_xdp_tx_mpwqe;
174 u64 rx_xdp_tx_inlnw;
175 u64 rx_xdp_tx_nops;
176 u64 rx_xdp_tx_full;
177 u64 rx_xdp_tx_err;
178 u64 rx_xdp_tx_cqe;
179 u64 tx_csum_none;
180 u64 tx_csum_partial;
181 u64 tx_csum_partial_inner;
182 u64 tx_queue_stopped;
183 u64 tx_queue_dropped;
184 u64 tx_xmit_more;
185 u64 tx_recover;
186 u64 tx_cqes;
187 u64 tx_queue_wake;
188 u64 tx_cqe_err;
189 u64 tx_xdp_xmit;
190 u64 tx_xdp_mpwqe;
191 u64 tx_xdp_inlnw;
192 u64 tx_xdp_nops;
193 u64 tx_xdp_full;
194 u64 tx_xdp_err;
195 u64 tx_xdp_cqes;
196 u64 rx_wqe_err;
197 u64 rx_mpwqe_filler_cqes;
198 u64 rx_mpwqe_filler_strides;
199 u64 rx_oversize_pkts_sw_drop;
200 u64 rx_buff_alloc_err;
201 u64 rx_cqe_compress_blks;
202 u64 rx_cqe_compress_pkts;
203 u64 rx_congst_umr;
204 #ifdef CONFIG_MLX5_EN_ARFS
205 u64 rx_arfs_add;
206 u64 rx_arfs_request_in;
207 u64 rx_arfs_request_out;
208 u64 rx_arfs_expired;
209 u64 rx_arfs_err;
210 #endif
211 u64 rx_recover;
212 u64 ch_events;
213 u64 ch_poll;
214 u64 ch_arm;
215 u64 ch_aff_change;
216 u64 ch_force_irq;
217 u64 ch_eq_rearm;
218 u64 rx_pp_alloc_fast;
219 u64 rx_pp_alloc_slow;
220 u64 rx_pp_alloc_slow_high_order;
221 u64 rx_pp_alloc_empty;
222 u64 rx_pp_alloc_refill;
223 u64 rx_pp_alloc_waive;
224 u64 rx_pp_recycle_cached;
225 u64 rx_pp_recycle_cache_full;
226 u64 rx_pp_recycle_ring;
227 u64 rx_pp_recycle_ring_full;
228 u64 rx_pp_recycle_released_ref;
229 #ifdef CONFIG_MLX5_EN_TLS
230 u64 tx_tls_encrypted_packets;
231 u64 tx_tls_encrypted_bytes;
232 u64 tx_tls_ooo;
233 u64 tx_tls_dump_packets;
234 u64 tx_tls_dump_bytes;
235 u64 tx_tls_resync_bytes;
236 u64 tx_tls_skip_no_sync_data;
237 u64 tx_tls_drop_no_sync_data;
238 u64 tx_tls_drop_bypass_req;
239
240 u64 rx_tls_decrypted_packets;
241 u64 rx_tls_decrypted_bytes;
242 u64 rx_tls_resync_req_pkt;
243 u64 rx_tls_resync_req_start;
244 u64 rx_tls_resync_req_end;
245 u64 rx_tls_resync_req_skip;
246 u64 rx_tls_resync_res_ok;
247 u64 rx_tls_resync_res_retry;
248 u64 rx_tls_resync_res_skip;
249 u64 rx_tls_err;
250 #endif
251
252 u64 rx_xsk_packets;
253 u64 rx_xsk_bytes;
254 u64 rx_xsk_csum_complete;
255 u64 rx_xsk_csum_unnecessary;
256 u64 rx_xsk_csum_unnecessary_inner;
257 u64 rx_xsk_csum_none;
258 u64 rx_xsk_ecn_mark;
259 u64 rx_xsk_removed_vlan_packets;
260 u64 rx_xsk_xdp_drop;
261 u64 rx_xsk_xdp_redirect;
262 u64 rx_xsk_wqe_err;
263 u64 rx_xsk_mpwqe_filler_cqes;
264 u64 rx_xsk_mpwqe_filler_strides;
265 u64 rx_xsk_oversize_pkts_sw_drop;
266 u64 rx_xsk_buff_alloc_err;
267 u64 rx_xsk_cqe_compress_blks;
268 u64 rx_xsk_cqe_compress_pkts;
269 u64 rx_xsk_congst_umr;
270 u64 tx_xsk_xmit;
271 u64 tx_xsk_mpwqe;
272 u64 tx_xsk_inlnw;
273 u64 tx_xsk_full;
274 u64 tx_xsk_err;
275 u64 tx_xsk_cqes;
276 };
277
278 struct mlx5e_qcounter_stats {
279 u32 rx_out_of_buffer;
280 u32 rx_if_down_packets;
281 };
282
283 #define VNIC_ENV_GET(vnic_env_stats, c) \
284 MLX5_GET(query_vnic_env_out, (vnic_env_stats)->query_vnic_env_out, \
285 vport_env.c)
286
287 struct mlx5e_vnic_env_stats {
288 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
289 };
290
291 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
292 vstats->query_vport_out, c)
293
294 struct mlx5e_vport_stats {
295 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
296 };
297
298 #define PPORT_802_3_GET(pstats, c) \
299 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
300 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
301 #define PPORT_2863_GET(pstats, c) \
302 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
303 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
304 #define PPORT_2819_GET(pstats, c) \
305 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
306 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
307 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
308 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
309 counter_set.phys_layer_statistical_cntrs.c##_high)
310 #define PPORT_PHY_RECOVERY_GET(pstats, c) \
311 MLX5_GET64(ppcnt_reg, (pstats)->phy_recovery_counters, \
312 counter_set.phys_layer_recovery_cntrs.c)
313 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
314 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
315 counter_set.eth_per_prio_grp_data_layout.c##_high)
316 #define NUM_PPORT_PRIO 8
317 #define PPORT_ETH_EXT_GET(pstats, c) \
318 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
319 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
320
321 struct mlx5e_pport_stats {
322 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
323 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
324 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
325 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
326 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
327 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
328 __be64 phy_recovery_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
329 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
330 __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
331 __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
332 };
333
334 #define PCIE_PERF_GET(pcie_stats, c) \
335 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
336 counter_set.pcie_perf_cntrs_grp_data_layout.c)
337
338 #define PCIE_PERF_GET64(pcie_stats, c) \
339 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
340 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
341
342 struct mlx5e_pcie_stats {
343 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
344 };
345
346 struct mlx5e_rq_stats {
347 u64 packets;
348 u64 bytes;
349 u64 csum_complete;
350 u64 csum_complete_tail;
351 u64 csum_complete_tail_slow;
352 u64 csum_unnecessary;
353 u64 csum_unnecessary_inner;
354 u64 csum_none;
355 u64 lro_packets;
356 u64 lro_bytes;
357 u64 gro_packets;
358 u64 gro_bytes;
359 u64 gro_skbs;
360 u64 gro_large_hds;
361 u64 hds_nodata_packets;
362 u64 hds_nodata_bytes;
363 u64 hds_nosplit_packets;
364 u64 hds_nosplit_bytes;
365 u64 mcast_packets;
366 u64 ecn_mark;
367 u64 removed_vlan_packets;
368 u64 xdp_drop;
369 u64 xdp_redirect;
370 u64 wqe_err;
371 u64 mpwqe_filler_cqes;
372 u64 mpwqe_filler_strides;
373 u64 oversize_pkts_sw_drop;
374 u64 buff_alloc_err;
375 u64 cqe_compress_blks;
376 u64 cqe_compress_pkts;
377 u64 congst_umr;
378 #ifdef CONFIG_MLX5_EN_ARFS
379 u64 arfs_add;
380 u64 arfs_request_in;
381 u64 arfs_request_out;
382 u64 arfs_expired;
383 u64 arfs_err;
384 #endif
385 u64 recover;
386 u64 pp_alloc_fast;
387 u64 pp_alloc_slow;
388 u64 pp_alloc_slow_high_order;
389 u64 pp_alloc_empty;
390 u64 pp_alloc_refill;
391 u64 pp_alloc_waive;
392 u64 pp_recycle_cached;
393 u64 pp_recycle_cache_full;
394 u64 pp_recycle_ring;
395 u64 pp_recycle_ring_full;
396 u64 pp_recycle_released_ref;
397 #ifdef CONFIG_MLX5_EN_TLS
398 u64 tls_decrypted_packets;
399 u64 tls_decrypted_bytes;
400 u64 tls_resync_req_pkt;
401 u64 tls_resync_req_start;
402 u64 tls_resync_req_end;
403 u64 tls_resync_req_skip;
404 u64 tls_resync_res_ok;
405 u64 tls_resync_res_retry;
406 u64 tls_resync_res_skip;
407 u64 tls_err;
408 #endif
409 };
410
411 struct mlx5e_sq_stats {
412 /* commonly accessed in data path */
413 u64 packets;
414 u64 bytes;
415 u64 xmit_more;
416 u64 tso_packets;
417 u64 tso_bytes;
418 u64 tso_inner_packets;
419 u64 tso_inner_bytes;
420 u64 csum_partial;
421 u64 csum_partial_inner;
422 u64 added_vlan_packets;
423 u64 nop;
424 u64 mpwqe_blks;
425 u64 mpwqe_pkts;
426 #ifdef CONFIG_MLX5_EN_TLS
427 u64 tls_encrypted_packets;
428 u64 tls_encrypted_bytes;
429 u64 tls_ooo;
430 u64 tls_dump_packets;
431 u64 tls_dump_bytes;
432 u64 tls_resync_bytes;
433 u64 tls_skip_no_sync_data;
434 u64 tls_drop_no_sync_data;
435 u64 tls_drop_bypass_req;
436 #endif
437 /* less likely accessed in data path */
438 u64 csum_none;
439 u64 stopped;
440 u64 dropped;
441 u64 recover;
442 u64 timestamps;
443 /* dirtied @completion */
444 u64 cqes ____cacheline_aligned_in_smp;
445 u64 wake;
446 u64 cqe_err;
447 };
448
449 struct mlx5e_xdpsq_stats {
450 u64 xmit;
451 u64 mpwqe;
452 u64 inlnw;
453 u64 nops;
454 u64 full;
455 u64 err;
456 /* dirtied @completion */
457 u64 cqes ____cacheline_aligned_in_smp;
458 };
459
460 struct mlx5e_ch_stats {
461 u64 events;
462 u64 poll;
463 u64 arm;
464 u64 aff_change;
465 u64 force_irq;
466 u64 eq_rearm;
467 };
468
469 struct mlx5e_ptp_cq_stats {
470 u64 cqe;
471 u64 err_cqe;
472 u64 abort;
473 u64 abort_abs_diff_ns;
474 u64 late_cqe;
475 u64 lost_cqe;
476 };
477
478 struct mlx5e_rep_stats {
479 u64 vport_rx_packets;
480 u64 vport_tx_packets;
481 u64 vport_rx_bytes;
482 u64 vport_tx_bytes;
483 u64 rx_vport_rdma_unicast_packets;
484 u64 tx_vport_rdma_unicast_packets;
485 u64 rx_vport_rdma_unicast_bytes;
486 u64 tx_vport_rdma_unicast_bytes;
487 u64 rx_vport_rdma_multicast_packets;
488 u64 tx_vport_rdma_multicast_packets;
489 u64 rx_vport_rdma_multicast_bytes;
490 u64 tx_vport_rdma_multicast_bytes;
491 u64 vport_loopback_packets;
492 u64 vport_loopback_bytes;
493 u64 rx_vport_out_of_buffer;
494 };
495
496 struct mlx5e_stats {
497 struct mlx5e_sw_stats sw;
498 struct mlx5e_qcounter_stats qcnt;
499 struct mlx5e_vnic_env_stats vnic;
500 struct mlx5e_vport_stats vport;
501 struct mlx5e_pport_stats pport;
502 struct mlx5e_pcie_stats pcie;
503 struct mlx5e_rep_stats rep_stats;
504 };
505
mlx5e_stats_copy_rep_stats(struct rtnl_link_stats64 * vf_vport,struct mlx5e_rep_stats * rep_stats)506 static inline void mlx5e_stats_copy_rep_stats(struct rtnl_link_stats64 *vf_vport,
507 struct mlx5e_rep_stats *rep_stats)
508 {
509 memset(vf_vport, 0, sizeof(*vf_vport));
510 vf_vport->rx_packets = rep_stats->vport_rx_packets;
511 vf_vport->tx_packets = rep_stats->vport_tx_packets;
512 vf_vport->rx_bytes = rep_stats->vport_rx_bytes;
513 vf_vport->tx_bytes = rep_stats->vport_tx_bytes;
514 vf_vport->rx_missed_errors = rep_stats->rx_vport_out_of_buffer;
515 }
516
517 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
518 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
519
520 extern MLX5E_DECLARE_STATS_GRP(sw);
521 extern MLX5E_DECLARE_STATS_GRP(qcnt);
522 extern MLX5E_DECLARE_STATS_GRP(vnic_env);
523 extern MLX5E_DECLARE_STATS_GRP(vport);
524 extern MLX5E_DECLARE_STATS_GRP(802_3);
525 extern MLX5E_DECLARE_STATS_GRP(2863);
526 extern MLX5E_DECLARE_STATS_GRP(2819);
527 extern MLX5E_DECLARE_STATS_GRP(phy);
528 extern MLX5E_DECLARE_STATS_GRP(eth_ext);
529 extern MLX5E_DECLARE_STATS_GRP(pcie);
530 extern MLX5E_DECLARE_STATS_GRP(per_prio);
531 extern MLX5E_DECLARE_STATS_GRP(pme);
532 extern MLX5E_DECLARE_STATS_GRP(channels);
533 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
534 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
535 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
536 extern MLX5E_DECLARE_STATS_GRP(ptp);
537 extern MLX5E_DECLARE_STATS_GRP(macsec_hw);
538
539 #endif /* __MLX5_EN_STATS_H__ */
540