1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/agp_backend.h>
64 #include <linux/atomic.h>
65 #include <linux/wait.h>
66 #include <linux/list.h>
67 #include <linux/kref.h>
68 #include <linux/interval_tree.h>
69 #include <linux/hashtable.h>
70 #include <linux/dma-fence.h>
71
72 #ifdef CONFIG_MMU_NOTIFIER
73 #include <linux/mmu_notifier.h>
74 #endif
75
76 #include <drm/ttm/ttm_bo.h>
77 #include <drm/ttm/ttm_placement.h>
78
79 #include <drm/drm_exec.h>
80 #include <drm/drm_gem.h>
81 #include <drm/drm_audio_component.h>
82 #include <drm/drm_suballoc.h>
83 #include <drm/drm_print.h>
84
85 #include "radeon_family.h"
86 #include "radeon_mode.h"
87 #include "radeon_reg.h"
88
89 /*
90 * Modules parameters.
91 */
92 extern int radeon_no_wb;
93 extern int radeon_modeset;
94 extern int radeon_dynclks;
95 extern int radeon_r4xx_atom;
96 extern int radeon_agpmode;
97 extern int radeon_vram_limit;
98 extern int radeon_gart_size;
99 extern int radeon_benchmarking;
100 extern int radeon_testing;
101 extern int radeon_connector_table;
102 extern int radeon_tv;
103 extern int radeon_audio;
104 extern int radeon_disp_priority;
105 extern int radeon_hw_i2c;
106 extern int radeon_pcie_gen2;
107 extern int radeon_msi;
108 extern int radeon_lockup_timeout;
109 extern int radeon_fastfb;
110 extern int radeon_dpm;
111 extern int radeon_aspm;
112 extern int radeon_runtime_pm;
113 extern int radeon_hard_reset;
114 extern int radeon_vm_size;
115 extern int radeon_vm_block_size;
116 extern int radeon_deep_color;
117 extern int radeon_use_pflipirq;
118 extern int radeon_bapm;
119 extern int radeon_backlight;
120 extern int radeon_auxch;
121 extern int radeon_uvd;
122 extern int radeon_vce;
123 extern int radeon_si_support;
124 extern int radeon_cik_support;
125
126 /*
127 * Copy from radeon_drv.h so we don't have to include both and have conflicting
128 * symbol;
129 */
130 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
131 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
132 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
133 /* RADEON_IB_POOL_SIZE must be a power of 2 */
134 #define RADEON_IB_POOL_SIZE 16
135 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
136 #define RADEON_BIOS_NUM_SCRATCH 8
137
138 /* internal ring indices */
139 /* r1xx+ has gfx CP ring */
140 #define RADEON_RING_TYPE_GFX_INDEX 0
141
142 /* cayman has 2 compute CP rings */
143 #define CAYMAN_RING_TYPE_CP1_INDEX 1
144 #define CAYMAN_RING_TYPE_CP2_INDEX 2
145
146 /* R600+ has an async dma ring */
147 #define R600_RING_TYPE_DMA_INDEX 3
148 /* cayman add a second async dma ring */
149 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
150
151 /* R600+ */
152 #define R600_RING_TYPE_UVD_INDEX 5
153
154 /* TN+ */
155 #define TN_RING_TYPE_VCE1_INDEX 6
156 #define TN_RING_TYPE_VCE2_INDEX 7
157
158 /* max number of rings */
159 #define RADEON_NUM_RINGS 8
160
161 /* number of hw syncs before falling back on blocking */
162 #define RADEON_NUM_SYNCS 4
163
164 /* hardcode those limit for now */
165 #define RADEON_VA_IB_OFFSET (1 << 20)
166 #define RADEON_VA_RESERVED_SIZE (8 << 20)
167 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
168
169 /* hard reset data */
170 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
171
172 /* reset flags */
173 #define RADEON_RESET_GFX (1 << 0)
174 #define RADEON_RESET_COMPUTE (1 << 1)
175 #define RADEON_RESET_DMA (1 << 2)
176 #define RADEON_RESET_CP (1 << 3)
177 #define RADEON_RESET_GRBM (1 << 4)
178 #define RADEON_RESET_DMA1 (1 << 5)
179 #define RADEON_RESET_RLC (1 << 6)
180 #define RADEON_RESET_SEM (1 << 7)
181 #define RADEON_RESET_IH (1 << 8)
182 #define RADEON_RESET_VMC (1 << 9)
183 #define RADEON_RESET_MC (1 << 10)
184 #define RADEON_RESET_DISPLAY (1 << 11)
185
186 /* CG block flags */
187 #define RADEON_CG_BLOCK_GFX (1 << 0)
188 #define RADEON_CG_BLOCK_MC (1 << 1)
189 #define RADEON_CG_BLOCK_SDMA (1 << 2)
190 #define RADEON_CG_BLOCK_UVD (1 << 3)
191 #define RADEON_CG_BLOCK_VCE (1 << 4)
192 #define RADEON_CG_BLOCK_HDP (1 << 5)
193 #define RADEON_CG_BLOCK_BIF (1 << 6)
194
195 /* CG flags */
196 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
197 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
198 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
199 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
200 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
201 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
202 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
203 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
204 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
205 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
206 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
207 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
208 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
209 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
210 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
211 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
212 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
213
214 /* PG flags */
215 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
216 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
217 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
218 #define RADEON_PG_SUPPORT_UVD (1 << 3)
219 #define RADEON_PG_SUPPORT_VCE (1 << 4)
220 #define RADEON_PG_SUPPORT_CP (1 << 5)
221 #define RADEON_PG_SUPPORT_GDS (1 << 6)
222 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
223 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
224 #define RADEON_PG_SUPPORT_ACP (1 << 9)
225 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
226
227 /* max cursor sizes (in pixels) */
228 #define CURSOR_WIDTH 64
229 #define CURSOR_HEIGHT 64
230
231 #define CIK_CURSOR_WIDTH 128
232 #define CIK_CURSOR_HEIGHT 128
233
234 /*
235 * Errata workarounds.
236 */
237 enum radeon_pll_errata {
238 CHIP_ERRATA_R300_CG = 0x00000001,
239 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
240 CHIP_ERRATA_PLL_DELAY = 0x00000004
241 };
242
243
244 struct radeon_device;
245
246
247 /*
248 * BIOS.
249 */
250 bool radeon_get_bios(struct radeon_device *rdev);
251
252 /*
253 * Dummy page
254 */
255 struct radeon_dummy_page {
256 uint64_t entry;
257 struct page *page;
258 dma_addr_t addr;
259 };
260 int radeon_dummy_page_init(struct radeon_device *rdev);
261 void radeon_dummy_page_fini(struct radeon_device *rdev);
262
263
264 /*
265 * Clocks
266 */
267 struct radeon_clock {
268 struct radeon_pll p1pll;
269 struct radeon_pll p2pll;
270 struct radeon_pll dcpll;
271 struct radeon_pll spll;
272 struct radeon_pll mpll;
273 /* 10 Khz units */
274 uint32_t default_mclk;
275 uint32_t default_sclk;
276 uint32_t default_dispclk;
277 uint32_t current_dispclk;
278 uint32_t dp_extclk;
279 uint32_t max_pixel_clock;
280 uint32_t vco_freq;
281 };
282
283 /*
284 * Power management
285 */
286 int radeon_pm_init(struct radeon_device *rdev);
287 int radeon_pm_late_init(struct radeon_device *rdev);
288 void radeon_pm_fini(struct radeon_device *rdev);
289 void radeon_pm_compute_clocks(struct radeon_device *rdev);
290 void radeon_pm_suspend(struct radeon_device *rdev);
291 void radeon_pm_resume(struct radeon_device *rdev);
292 void radeon_combios_get_power_modes(struct radeon_device *rdev);
293 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
294 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
295 u8 clock_type,
296 u32 clock,
297 bool strobe_mode,
298 struct atom_clock_dividers *dividers);
299 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
300 u32 clock,
301 bool strobe_mode,
302 struct atom_mpll_param *mpll_param);
303 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
304 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
305 u16 voltage_level, u8 voltage_type,
306 u32 *gpio_value, u32 *gpio_mask);
307 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
308 u32 eng_clock, u32 mem_clock);
309 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
310 u8 voltage_type, u16 *voltage_step);
311 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
312 u16 voltage_id, u16 *voltage);
313 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
314 u16 *voltage,
315 u16 leakage_idx);
316 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
317 u16 *leakage_id);
318 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
319 u16 *vddc, u16 *vddci,
320 u16 virtual_voltage_id,
321 u16 vbios_voltage_id);
322 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
323 u16 virtual_voltage_id,
324 u16 *voltage);
325 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
326 u8 voltage_type,
327 u16 nominal_voltage,
328 u16 *true_voltage);
329 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
330 u8 voltage_type, u16 *min_voltage);
331 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
332 u8 voltage_type, u16 *max_voltage);
333 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
334 u8 voltage_type, u8 voltage_mode,
335 struct atom_voltage_table *voltage_table);
336 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
337 u8 voltage_type, u8 voltage_mode);
338 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
339 u8 voltage_type,
340 u8 *svd_gpio_id, u8 *svc_gpio_id);
341 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
342 u32 mem_clock);
343 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
344 u32 mem_clock);
345 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
346 u8 module_index,
347 struct atom_mc_reg_table *reg_table);
348 int radeon_atom_get_memory_info(struct radeon_device *rdev,
349 u8 module_index, struct atom_memory_info *mem_info);
350 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
351 bool gddr5, u8 module_index,
352 struct atom_memory_clock_range_table *mclk_range_table);
353 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
354 u16 voltage_id, u16 *voltage);
355 void rs690_pm_info(struct radeon_device *rdev);
356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
357 unsigned *bankh, unsigned *mtaspect,
358 unsigned *tile_split);
359
360 /*
361 * Fences.
362 */
363 struct radeon_fence_driver {
364 struct radeon_device *rdev;
365 uint32_t scratch_reg;
366 uint64_t gpu_addr;
367 volatile uint32_t *cpu_addr;
368 /* sync_seq is protected by ring emission lock */
369 uint64_t sync_seq[RADEON_NUM_RINGS];
370 atomic64_t last_seq;
371 bool initialized, delayed_irq;
372 struct delayed_work lockup_work;
373 };
374
375 struct radeon_fence {
376 struct dma_fence base;
377
378 struct radeon_device *rdev;
379 uint64_t seq;
380 /* RB, DMA, etc. */
381 unsigned ring;
382 bool is_vm_update;
383
384 wait_queue_entry_t fence_wake;
385 };
386
387 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
388 void radeon_fence_driver_init(struct radeon_device *rdev);
389 void radeon_fence_driver_fini(struct radeon_device *rdev);
390 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
391 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
392 void radeon_fence_process(struct radeon_device *rdev, int ring);
393 bool radeon_fence_signaled(struct radeon_fence *fence);
394 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
395 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
396 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
397 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
398 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
399 void radeon_fence_unref(struct radeon_fence **fence);
400 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
401 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
402 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)403 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
404 struct radeon_fence *b)
405 {
406 if (!a) {
407 return b;
408 }
409
410 if (!b) {
411 return a;
412 }
413
414 BUG_ON(a->ring != b->ring);
415
416 if (a->seq > b->seq) {
417 return a;
418 } else {
419 return b;
420 }
421 }
422
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)423 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
424 struct radeon_fence *b)
425 {
426 if (!a) {
427 return false;
428 }
429
430 if (!b) {
431 return true;
432 }
433
434 BUG_ON(a->ring != b->ring);
435
436 return a->seq < b->seq;
437 }
438
439 /*
440 * Tiling registers
441 */
442 struct radeon_surface_reg {
443 struct radeon_bo *bo;
444 };
445
446 #define RADEON_GEM_MAX_SURFACES 8
447
448 /*
449 * TTM.
450 */
451 struct radeon_mman {
452 struct ttm_device bdev;
453 bool initialized;
454 };
455
456 struct radeon_bo_list {
457 struct radeon_bo *robj;
458 struct list_head list;
459 bool shared;
460 uint64_t gpu_offset;
461 unsigned preferred_domains;
462 unsigned allowed_domains;
463 uint32_t tiling_flags;
464 };
465
466 /* bo virtual address in a specific vm */
467 struct radeon_bo_va {
468 /* protected by bo being reserved */
469 struct list_head bo_list;
470 uint32_t flags;
471 struct radeon_fence *last_pt_update;
472 unsigned ref_count;
473
474 /* protected by vm mutex */
475 struct interval_tree_node it;
476 struct list_head vm_status;
477
478 /* constant after initialization */
479 struct radeon_vm *vm;
480 struct radeon_bo *bo;
481 };
482
483 struct radeon_bo {
484 /* Protected by gem.mutex */
485 struct list_head list;
486 /* Protected by tbo.reserved */
487 u32 initial_domain;
488 struct ttm_place placements[4];
489 struct ttm_placement placement;
490 struct ttm_buffer_object tbo;
491 struct ttm_bo_kmap_obj kmap;
492 u32 flags;
493 void *kptr;
494 u32 tiling_flags;
495 u32 pitch;
496 int surface_reg;
497 unsigned prime_shared_count;
498 /* list of all virtual address to which this bo
499 * is associated to
500 */
501 struct list_head va;
502 /* Constant after initialization */
503 struct radeon_device *rdev;
504
505 pid_t pid;
506
507 #ifdef CONFIG_MMU_NOTIFIER
508 struct mmu_interval_notifier notifier;
509 #endif
510 };
511 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
512
513 struct radeon_sa_manager {
514 struct drm_suballoc_manager base;
515 struct radeon_bo *bo;
516 uint64_t gpu_addr;
517 void *cpu_ptr;
518 u32 domain;
519 };
520
521 /*
522 * GEM objects.
523 */
524 struct radeon_gem {
525 struct mutex mutex;
526 struct list_head objects;
527 };
528
529 extern const struct drm_gem_object_funcs radeon_gem_object_funcs;
530
531 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled);
532
533 int radeon_gem_init(struct radeon_device *rdev);
534 void radeon_gem_fini(struct radeon_device *rdev);
535 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
536 int alignment, int initial_domain,
537 u32 flags, bool kernel,
538 struct drm_gem_object **obj);
539
540 int radeon_mode_dumb_create(struct drm_file *file_priv,
541 struct drm_device *dev,
542 struct drm_mode_create_dumb *args);
543 int radeon_mode_dumb_mmap(struct drm_file *filp,
544 struct drm_device *dev,
545 uint32_t handle, uint64_t *offset_p);
546
547 /*
548 * Semaphores.
549 */
550 struct radeon_semaphore {
551 struct drm_suballoc *sa_bo;
552 signed waiters;
553 uint64_t gpu_addr;
554 };
555
556 int radeon_semaphore_create(struct radeon_device *rdev,
557 struct radeon_semaphore **semaphore);
558 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
559 struct radeon_semaphore *semaphore);
560 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
561 struct radeon_semaphore *semaphore);
562 void radeon_semaphore_free(struct radeon_device *rdev,
563 struct radeon_semaphore **semaphore,
564 struct radeon_fence *fence);
565
566 /*
567 * Synchronization
568 */
569 struct radeon_sync {
570 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
571 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
572 struct radeon_fence *last_vm_update;
573 };
574
575 void radeon_sync_create(struct radeon_sync *sync);
576 void radeon_sync_fence(struct radeon_sync *sync,
577 struct radeon_fence *fence);
578 int radeon_sync_resv(struct radeon_device *rdev,
579 struct radeon_sync *sync,
580 struct dma_resv *resv,
581 bool shared);
582 int radeon_sync_rings(struct radeon_device *rdev,
583 struct radeon_sync *sync,
584 int waiting_ring);
585 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
586 struct radeon_fence *fence);
587
588 /*
589 * GART structures, functions & helpers
590 */
591 struct radeon_mc;
592
593 #define RADEON_GPU_PAGE_SIZE 4096
594 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
595 #define RADEON_GPU_PAGE_SHIFT 12
596 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
597
598 #define RADEON_GART_PAGE_DUMMY 0
599 #define RADEON_GART_PAGE_VALID (1 << 0)
600 #define RADEON_GART_PAGE_READ (1 << 1)
601 #define RADEON_GART_PAGE_WRITE (1 << 2)
602 #define RADEON_GART_PAGE_SNOOP (1 << 3)
603
604 struct radeon_gart {
605 dma_addr_t table_addr;
606 struct radeon_bo *robj;
607 void *ptr;
608 unsigned num_gpu_pages;
609 unsigned num_cpu_pages;
610 unsigned table_size;
611 struct page **pages;
612 uint64_t *pages_entry;
613 bool ready;
614 };
615
616 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
617 void radeon_gart_table_ram_free(struct radeon_device *rdev);
618 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
619 void radeon_gart_table_vram_free(struct radeon_device *rdev);
620 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
621 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
622 int radeon_gart_init(struct radeon_device *rdev);
623 void radeon_gart_fini(struct radeon_device *rdev);
624 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
625 int pages);
626 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
627 int pages, struct page **pagelist,
628 dma_addr_t *dma_addr, uint32_t flags);
629
630
631 /*
632 * GPU MC structures, functions & helpers
633 */
634 struct radeon_mc {
635 resource_size_t aper_size;
636 resource_size_t aper_base;
637 resource_size_t agp_base;
638 /* for some chips with <= 32MB we need to lie
639 * about vram size near mc fb location */
640 u64 mc_vram_size;
641 u64 visible_vram_size;
642 u64 gtt_size;
643 u64 gtt_start;
644 u64 gtt_end;
645 u64 vram_start;
646 u64 vram_end;
647 unsigned vram_width;
648 u64 real_vram_size;
649 int vram_mtrr;
650 bool vram_is_ddr;
651 bool igp_sideport_enabled;
652 u64 gtt_base_align;
653 u64 mc_mask;
654 };
655
656 bool radeon_combios_sideport_present(struct radeon_device *rdev);
657 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
658
659 /*
660 * GPU scratch registers structures, functions & helpers
661 */
662 struct radeon_scratch {
663 unsigned num_reg;
664 uint32_t reg_base;
665 bool free[32];
666 uint32_t reg[32];
667 };
668
669 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
670 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
671
672 /*
673 * GPU doorbell structures, functions & helpers
674 */
675 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
676
677 struct radeon_doorbell {
678 /* doorbell mmio */
679 resource_size_t base;
680 resource_size_t size;
681 u32 __iomem *ptr;
682 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
683 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
684 };
685
686 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
687 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
688
689 /*
690 * IRQS.
691 */
692
693 struct radeon_flip_work {
694 struct work_struct flip_work;
695 struct work_struct unpin_work;
696 struct radeon_device *rdev;
697 int crtc_id;
698 u32 target_vblank;
699 uint64_t base;
700 struct drm_pending_vblank_event *event;
701 struct radeon_bo *old_rbo;
702 struct dma_fence *fence;
703 bool async;
704 };
705
706 struct r500_irq_stat_regs {
707 u32 disp_int;
708 u32 hdmi0_status;
709 };
710
711 struct r600_irq_stat_regs {
712 u32 disp_int;
713 u32 disp_int_cont;
714 u32 disp_int_cont2;
715 u32 d1grph_int;
716 u32 d2grph_int;
717 u32 hdmi0_status;
718 u32 hdmi1_status;
719 };
720
721 struct evergreen_irq_stat_regs {
722 u32 disp_int[6];
723 u32 grph_int[6];
724 u32 afmt_status[6];
725 };
726
727 struct cik_irq_stat_regs {
728 u32 disp_int;
729 u32 disp_int_cont;
730 u32 disp_int_cont2;
731 u32 disp_int_cont3;
732 u32 disp_int_cont4;
733 u32 disp_int_cont5;
734 u32 disp_int_cont6;
735 u32 d1grph_int;
736 u32 d2grph_int;
737 u32 d3grph_int;
738 u32 d4grph_int;
739 u32 d5grph_int;
740 u32 d6grph_int;
741 };
742
743 union radeon_irq_stat_regs {
744 struct r500_irq_stat_regs r500;
745 struct r600_irq_stat_regs r600;
746 struct evergreen_irq_stat_regs evergreen;
747 struct cik_irq_stat_regs cik;
748 };
749
750 struct radeon_irq {
751 bool installed;
752 spinlock_t lock;
753 atomic_t ring_int[RADEON_NUM_RINGS];
754 bool crtc_vblank_int[RADEON_MAX_CRTCS];
755 atomic_t pflip[RADEON_MAX_CRTCS];
756 wait_queue_head_t vblank_queue;
757 bool hpd[RADEON_MAX_HPD_PINS];
758 bool afmt[RADEON_MAX_AFMT_BLOCKS];
759 union radeon_irq_stat_regs stat_regs;
760 bool dpm_thermal;
761 };
762
763 int radeon_irq_kms_init(struct radeon_device *rdev);
764 void radeon_irq_kms_fini(struct radeon_device *rdev);
765 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
766 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
767 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
768 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
769 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
770 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
771 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
772 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
773 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
774
775 /*
776 * CP & rings.
777 */
778
779 struct radeon_ib {
780 struct drm_suballoc *sa_bo;
781 uint32_t length_dw;
782 uint64_t gpu_addr;
783 uint32_t *ptr;
784 int ring;
785 struct radeon_fence *fence;
786 struct radeon_vm *vm;
787 bool is_const_ib;
788 struct radeon_sync sync;
789 };
790
791 struct radeon_ring {
792 struct radeon_device *rdev;
793 struct radeon_bo *ring_obj;
794 volatile uint32_t *ring;
795 unsigned rptr_offs;
796 unsigned rptr_save_reg;
797 u64 next_rptr_gpu_addr;
798 volatile u32 *next_rptr_cpu_addr;
799 unsigned wptr;
800 unsigned wptr_old;
801 unsigned ring_size;
802 unsigned ring_free_dw;
803 int count_dw;
804 atomic_t last_rptr;
805 atomic64_t last_activity;
806 uint64_t gpu_addr;
807 uint32_t align_mask;
808 uint32_t ptr_mask;
809 bool ready;
810 u32 nop;
811 u32 idx;
812 u64 last_semaphore_signal_addr;
813 u64 last_semaphore_wait_addr;
814 /* for CIK queues */
815 u32 me;
816 u32 pipe;
817 u32 queue;
818 struct radeon_bo *mqd_obj;
819 u32 doorbell_index;
820 unsigned wptr_offs;
821 };
822
823 struct radeon_mec {
824 struct radeon_bo *hpd_eop_obj;
825 u64 hpd_eop_gpu_addr;
826 u32 num_pipe;
827 u32 num_mec;
828 u32 num_queue;
829 };
830
831 /*
832 * VM
833 */
834
835 /* maximum number of VMIDs */
836 #define RADEON_NUM_VM 16
837
838 /* number of entries in page table */
839 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
840
841 /* PTBs (Page Table Blocks) need to be aligned to 32K */
842 #define RADEON_VM_PTB_ALIGN_SIZE 32768
843 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
844 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
845
846 #define R600_PTE_VALID (1 << 0)
847 #define R600_PTE_SYSTEM (1 << 1)
848 #define R600_PTE_SNOOPED (1 << 2)
849 #define R600_PTE_READABLE (1 << 5)
850 #define R600_PTE_WRITEABLE (1 << 6)
851
852 /* PTE (Page Table Entry) fragment field for different page sizes */
853 #define R600_PTE_FRAG_4KB (0 << 7)
854 #define R600_PTE_FRAG_64KB (4 << 7)
855 #define R600_PTE_FRAG_256KB (6 << 7)
856
857 /* flags needed to be set so we can copy directly from the GART table */
858 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
859 R600_PTE_SYSTEM | R600_PTE_VALID )
860
861 struct radeon_vm_pt {
862 struct radeon_bo *bo;
863 uint64_t addr;
864 };
865
866 struct radeon_vm_id {
867 unsigned id;
868 uint64_t pd_gpu_addr;
869 /* last flushed PD/PT update */
870 struct radeon_fence *flushed_updates;
871 /* last use of vmid */
872 struct radeon_fence *last_id_use;
873 };
874
875 struct radeon_vm {
876 struct mutex mutex;
877
878 struct rb_root_cached va;
879
880 /* protecting invalidated and freed */
881 spinlock_t status_lock;
882
883 /* BOs moved, but not yet updated in the PT */
884 struct list_head invalidated;
885
886 /* BOs freed, but not yet updated in the PT */
887 struct list_head freed;
888
889 /* BOs cleared in the PT */
890 struct list_head cleared;
891
892 /* contains the page directory */
893 struct radeon_bo *page_directory;
894 unsigned max_pde_used;
895
896 /* array of page tables, one for each page directory entry */
897 struct radeon_vm_pt *page_tables;
898
899 struct radeon_bo_va *ib_bo_va;
900
901 /* for id and flush management per ring */
902 struct radeon_vm_id ids[RADEON_NUM_RINGS];
903 };
904
905 struct radeon_vm_manager {
906 struct radeon_fence *active[RADEON_NUM_VM];
907 uint32_t max_pfn;
908 /* number of VMIDs */
909 unsigned nvm;
910 /* vram base address for page table entry */
911 u64 vram_base_offset;
912 /* is vm enabled? */
913 bool enabled;
914 /* for hw to save the PD addr on suspend/resume */
915 uint32_t saved_table_addr[RADEON_NUM_VM];
916 };
917
918 /*
919 * file private structure
920 */
921 struct radeon_fpriv {
922 struct radeon_vm vm;
923 };
924
925 /*
926 * R6xx+ IH ring
927 */
928 struct r600_ih {
929 struct radeon_bo *ring_obj;
930 volatile uint32_t *ring;
931 unsigned rptr;
932 unsigned ring_size;
933 uint64_t gpu_addr;
934 uint32_t ptr_mask;
935 atomic_t lock;
936 bool enabled;
937 };
938
939 /*
940 * RLC stuff
941 */
942 #include "clearstate_defs.h"
943
944 struct radeon_rlc {
945 /* for power gating */
946 struct radeon_bo *save_restore_obj;
947 uint64_t save_restore_gpu_addr;
948 volatile uint32_t *sr_ptr;
949 const u32 *reg_list;
950 u32 reg_list_size;
951 /* for clear state */
952 struct radeon_bo *clear_state_obj;
953 uint64_t clear_state_gpu_addr;
954 volatile uint32_t *cs_ptr;
955 const struct cs_section_def *cs_data;
956 u32 clear_state_size;
957 /* for cp tables */
958 struct radeon_bo *cp_table_obj;
959 uint64_t cp_table_gpu_addr;
960 volatile uint32_t *cp_table_ptr;
961 u32 cp_table_size;
962 };
963
964 int radeon_ib_get(struct radeon_device *rdev, int ring,
965 struct radeon_ib *ib, struct radeon_vm *vm,
966 unsigned size);
967 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
968 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
969 struct radeon_ib *const_ib, bool hdp_flush);
970 int radeon_ib_pool_init(struct radeon_device *rdev);
971 void radeon_ib_pool_fini(struct radeon_device *rdev);
972 int radeon_ib_ring_tests(struct radeon_device *rdev);
973 /* Ring access between begin & end cannot sleep */
974 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
975 struct radeon_ring *ring);
976 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
977 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
978 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
979 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
980 bool hdp_flush);
981 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
982 bool hdp_flush);
983 void radeon_ring_undo(struct radeon_ring *ring);
984 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
985 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
986 void radeon_ring_lockup_update(struct radeon_device *rdev,
987 struct radeon_ring *ring);
988 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
989 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
990 uint32_t **data);
991 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
992 unsigned size, uint32_t *data);
993 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
994 unsigned rptr_offs, u32 nop);
995 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
996
997
998 /* r600 async dma */
999 void r600_dma_stop(struct radeon_device *rdev);
1000 int r600_dma_resume(struct radeon_device *rdev);
1001 void r600_dma_fini(struct radeon_device *rdev);
1002
1003 void cayman_dma_stop(struct radeon_device *rdev);
1004 int cayman_dma_resume(struct radeon_device *rdev);
1005 void cayman_dma_fini(struct radeon_device *rdev);
1006
1007 /*
1008 * CS.
1009 */
1010 struct radeon_cs_chunk {
1011 uint32_t length_dw;
1012 uint32_t *kdata;
1013 void __user *user_ptr;
1014 };
1015
1016 struct radeon_cs_parser {
1017 struct device *dev;
1018 struct radeon_device *rdev;
1019 struct drm_file *filp;
1020 /* chunks */
1021 unsigned nchunks;
1022 struct radeon_cs_chunk *chunks;
1023 uint64_t *chunks_array;
1024 /* IB */
1025 unsigned idx;
1026 /* relocations */
1027 unsigned nrelocs;
1028 struct radeon_bo_list *relocs;
1029 struct radeon_bo_list *vm_bos;
1030 struct list_head validated;
1031 unsigned dma_reloc_idx;
1032 struct drm_exec exec;
1033 /* indices of various chunks */
1034 struct radeon_cs_chunk *chunk_ib;
1035 struct radeon_cs_chunk *chunk_relocs;
1036 struct radeon_cs_chunk *chunk_flags;
1037 struct radeon_cs_chunk *chunk_const_ib;
1038 struct radeon_ib ib;
1039 struct radeon_ib const_ib;
1040 void *track;
1041 unsigned family;
1042 int parser_error;
1043 u32 cs_flags;
1044 u32 ring;
1045 s32 priority;
1046 };
1047
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1048 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1049 {
1050 struct radeon_cs_chunk *ibc = p->chunk_ib;
1051
1052 if (ibc->kdata)
1053 return ibc->kdata[idx];
1054 return p->ib.ptr[idx];
1055 }
1056
1057
1058 struct radeon_cs_packet {
1059 unsigned idx;
1060 unsigned type;
1061 unsigned reg;
1062 unsigned opcode;
1063 int count;
1064 unsigned one_reg_wr;
1065 };
1066
1067 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1068 struct radeon_cs_packet *pkt,
1069 unsigned idx, unsigned reg);
1070
1071 /*
1072 * AGP
1073 */
1074
1075 struct radeon_agp_mode {
1076 unsigned long mode; /**< AGP mode */
1077 };
1078
1079 struct radeon_agp_info {
1080 int agp_version_major;
1081 int agp_version_minor;
1082 unsigned long mode;
1083 unsigned long aperture_base; /* physical address */
1084 unsigned long aperture_size; /* bytes */
1085 unsigned long memory_allowed; /* bytes */
1086 unsigned long memory_used;
1087
1088 /* PCI information */
1089 unsigned short id_vendor;
1090 unsigned short id_device;
1091 };
1092
1093 struct radeon_agp_head {
1094 struct agp_kern_info agp_info;
1095 struct list_head memory;
1096 unsigned long mode;
1097 struct agp_bridge_data *bridge;
1098 int enabled;
1099 int acquired;
1100 unsigned long base;
1101 int agp_mtrr;
1102 int cant_use_aperture;
1103 unsigned long page_mask;
1104 };
1105
1106 #if IS_ENABLED(CONFIG_AGP)
1107 struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev);
1108 #else
radeon_agp_head_init(struct drm_device * dev)1109 static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)
1110 {
1111 return NULL;
1112 }
1113 #endif
1114 int radeon_agp_init(struct radeon_device *rdev);
1115 void radeon_agp_resume(struct radeon_device *rdev);
1116 void radeon_agp_suspend(struct radeon_device *rdev);
1117 void radeon_agp_fini(struct radeon_device *rdev);
1118
1119
1120 /*
1121 * Writeback
1122 */
1123 struct radeon_wb {
1124 struct radeon_bo *wb_obj;
1125 volatile uint32_t *wb;
1126 uint64_t gpu_addr;
1127 bool enabled;
1128 bool use_event;
1129 };
1130
1131 #define RADEON_WB_SCRATCH_OFFSET 0
1132 #define RADEON_WB_RING0_NEXT_RPTR 256
1133 #define RADEON_WB_CP_RPTR_OFFSET 1024
1134 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1135 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1136 #define R600_WB_DMA_RPTR_OFFSET 1792
1137 #define R600_WB_IH_WPTR_OFFSET 2048
1138 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1139 #define R600_WB_EVENT_OFFSET 3072
1140 #define CIK_WB_CP1_WPTR_OFFSET 3328
1141 #define CIK_WB_CP2_WPTR_OFFSET 3584
1142 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1143 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1144
1145 /**
1146 * struct radeon_pm - power management datas
1147 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1148 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1149 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1150 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1151 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1152 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1153 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1154 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1155 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1156 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1157 * @needed_bandwidth: current bandwidth needs
1158 *
1159 * It keeps track of various data needed to take powermanagement decision.
1160 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1161 * Equation between gpu/memory clock and available bandwidth is hw dependent
1162 * (type of memory, bus size, efficiency, ...)
1163 */
1164
1165 enum radeon_pm_method {
1166 PM_METHOD_PROFILE,
1167 PM_METHOD_DYNPM,
1168 PM_METHOD_DPM,
1169 };
1170
1171 enum radeon_dynpm_state {
1172 DYNPM_STATE_DISABLED,
1173 DYNPM_STATE_MINIMUM,
1174 DYNPM_STATE_PAUSED,
1175 DYNPM_STATE_ACTIVE,
1176 DYNPM_STATE_SUSPENDED,
1177 };
1178 enum radeon_dynpm_action {
1179 DYNPM_ACTION_NONE,
1180 DYNPM_ACTION_MINIMUM,
1181 DYNPM_ACTION_DOWNCLOCK,
1182 DYNPM_ACTION_UPCLOCK,
1183 DYNPM_ACTION_DEFAULT
1184 };
1185
1186 enum radeon_voltage_type {
1187 VOLTAGE_NONE = 0,
1188 VOLTAGE_GPIO,
1189 VOLTAGE_VDDC,
1190 VOLTAGE_SW
1191 };
1192
1193 enum radeon_pm_state_type {
1194 /* not used for dpm */
1195 POWER_STATE_TYPE_DEFAULT,
1196 POWER_STATE_TYPE_POWERSAVE,
1197 /* user selectable states */
1198 POWER_STATE_TYPE_BATTERY,
1199 POWER_STATE_TYPE_BALANCED,
1200 POWER_STATE_TYPE_PERFORMANCE,
1201 /* internal states */
1202 POWER_STATE_TYPE_INTERNAL_UVD,
1203 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1204 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1205 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1206 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1207 POWER_STATE_TYPE_INTERNAL_BOOT,
1208 POWER_STATE_TYPE_INTERNAL_THERMAL,
1209 POWER_STATE_TYPE_INTERNAL_ACPI,
1210 POWER_STATE_TYPE_INTERNAL_ULV,
1211 POWER_STATE_TYPE_INTERNAL_3DPERF,
1212 };
1213
1214 enum radeon_pm_profile_type {
1215 PM_PROFILE_DEFAULT,
1216 PM_PROFILE_AUTO,
1217 PM_PROFILE_LOW,
1218 PM_PROFILE_MID,
1219 PM_PROFILE_HIGH,
1220 };
1221
1222 #define PM_PROFILE_DEFAULT_IDX 0
1223 #define PM_PROFILE_LOW_SH_IDX 1
1224 #define PM_PROFILE_MID_SH_IDX 2
1225 #define PM_PROFILE_HIGH_SH_IDX 3
1226 #define PM_PROFILE_LOW_MH_IDX 4
1227 #define PM_PROFILE_MID_MH_IDX 5
1228 #define PM_PROFILE_HIGH_MH_IDX 6
1229 #define PM_PROFILE_MAX 7
1230
1231 struct radeon_pm_profile {
1232 int dpms_off_ps_idx;
1233 int dpms_on_ps_idx;
1234 int dpms_off_cm_idx;
1235 int dpms_on_cm_idx;
1236 };
1237
1238 enum radeon_int_thermal_type {
1239 THERMAL_TYPE_NONE,
1240 THERMAL_TYPE_EXTERNAL,
1241 THERMAL_TYPE_EXTERNAL_GPIO,
1242 THERMAL_TYPE_RV6XX,
1243 THERMAL_TYPE_RV770,
1244 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1245 THERMAL_TYPE_EVERGREEN,
1246 THERMAL_TYPE_SUMO,
1247 THERMAL_TYPE_NI,
1248 THERMAL_TYPE_SI,
1249 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1250 THERMAL_TYPE_CI,
1251 THERMAL_TYPE_KV,
1252 };
1253
1254 struct radeon_voltage {
1255 enum radeon_voltage_type type;
1256 /* gpio voltage */
1257 struct radeon_gpio_rec gpio;
1258 u32 delay; /* delay in usec from voltage drop to sclk change */
1259 bool active_high; /* voltage drop is active when bit is high */
1260 /* VDDC voltage */
1261 u8 vddc_id; /* index into vddc voltage table */
1262 u8 vddci_id; /* index into vddci voltage table */
1263 bool vddci_enabled;
1264 /* r6xx+ sw */
1265 u16 voltage;
1266 /* evergreen+ vddci */
1267 u16 vddci;
1268 };
1269
1270 /* clock mode flags */
1271 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1272
1273 struct radeon_pm_clock_info {
1274 /* memory clock */
1275 u32 mclk;
1276 /* engine clock */
1277 u32 sclk;
1278 /* voltage info */
1279 struct radeon_voltage voltage;
1280 /* standardized clock flags */
1281 u32 flags;
1282 };
1283
1284 /* state flags */
1285 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1286
1287 struct radeon_power_state {
1288 enum radeon_pm_state_type type;
1289 struct radeon_pm_clock_info *clock_info;
1290 /* number of valid clock modes in this power state */
1291 int num_clock_modes;
1292 struct radeon_pm_clock_info *default_clock_mode;
1293 /* standardized state flags */
1294 u32 flags;
1295 u32 misc; /* vbios specific flags */
1296 u32 misc2; /* vbios specific flags */
1297 int pcie_lanes; /* pcie lanes */
1298 };
1299
1300 /*
1301 * Some modes are overclocked by very low value, accept them
1302 */
1303 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1304
1305 enum radeon_dpm_auto_throttle_src {
1306 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1307 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1308 };
1309
1310 enum radeon_dpm_event_src {
1311 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1312 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1313 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1314 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1315 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1316 };
1317
1318 #define RADEON_MAX_VCE_LEVELS 6
1319
1320 enum radeon_vce_level {
1321 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1322 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1323 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1324 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1325 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1326 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1327 };
1328
1329 struct radeon_ps {
1330 u32 caps; /* vbios flags */
1331 u32 class; /* vbios flags */
1332 u32 class2; /* vbios flags */
1333 /* UVD clocks */
1334 u32 vclk;
1335 u32 dclk;
1336 /* VCE clocks */
1337 u32 evclk;
1338 u32 ecclk;
1339 bool vce_active;
1340 enum radeon_vce_level vce_level;
1341 /* asic priv */
1342 void *ps_priv;
1343 };
1344
1345 struct radeon_dpm_thermal {
1346 /* thermal interrupt work */
1347 struct work_struct work;
1348 /* low temperature threshold */
1349 int min_temp;
1350 /* high temperature threshold */
1351 int max_temp;
1352 /* was interrupt low to high or high to low */
1353 bool high_to_low;
1354 };
1355
1356 enum radeon_clk_action {
1357 RADEON_SCLK_UP = 1,
1358 RADEON_SCLK_DOWN
1359 };
1360
1361 struct radeon_blacklist_clocks {
1362 u32 sclk;
1363 u32 mclk;
1364 enum radeon_clk_action action;
1365 };
1366
1367 struct radeon_clock_and_voltage_limits {
1368 u32 sclk;
1369 u32 mclk;
1370 u16 vddc;
1371 u16 vddci;
1372 };
1373
1374 struct radeon_clock_array {
1375 u32 count;
1376 u32 *values;
1377 };
1378
1379 struct radeon_clock_voltage_dependency_entry {
1380 u32 clk;
1381 u16 v;
1382 };
1383
1384 struct radeon_clock_voltage_dependency_table {
1385 u32 count;
1386 struct radeon_clock_voltage_dependency_entry *entries;
1387 };
1388
1389 union radeon_cac_leakage_entry {
1390 struct {
1391 u16 vddc;
1392 u32 leakage;
1393 };
1394 struct {
1395 u16 vddc1;
1396 u16 vddc2;
1397 u16 vddc3;
1398 };
1399 };
1400
1401 struct radeon_cac_leakage_table {
1402 u32 count;
1403 union radeon_cac_leakage_entry *entries;
1404 };
1405
1406 struct radeon_phase_shedding_limits_entry {
1407 u16 voltage;
1408 u32 sclk;
1409 u32 mclk;
1410 };
1411
1412 struct radeon_phase_shedding_limits_table {
1413 u32 count;
1414 struct radeon_phase_shedding_limits_entry *entries;
1415 };
1416
1417 struct radeon_uvd_clock_voltage_dependency_entry {
1418 u32 vclk;
1419 u32 dclk;
1420 u16 v;
1421 };
1422
1423 struct radeon_uvd_clock_voltage_dependency_table {
1424 u8 count;
1425 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1426 };
1427
1428 struct radeon_vce_clock_voltage_dependency_entry {
1429 u32 ecclk;
1430 u32 evclk;
1431 u16 v;
1432 };
1433
1434 struct radeon_vce_clock_voltage_dependency_table {
1435 u8 count;
1436 struct radeon_vce_clock_voltage_dependency_entry *entries;
1437 };
1438
1439 struct radeon_ppm_table {
1440 u8 ppm_design;
1441 u16 cpu_core_number;
1442 u32 platform_tdp;
1443 u32 small_ac_platform_tdp;
1444 u32 platform_tdc;
1445 u32 small_ac_platform_tdc;
1446 u32 apu_tdp;
1447 u32 dgpu_tdp;
1448 u32 dgpu_ulv_power;
1449 u32 tj_max;
1450 };
1451
1452 struct radeon_cac_tdp_table {
1453 u16 tdp;
1454 u16 configurable_tdp;
1455 u16 tdc;
1456 u16 battery_power_limit;
1457 u16 small_power_limit;
1458 u16 low_cac_leakage;
1459 u16 high_cac_leakage;
1460 u16 maximum_power_delivery_limit;
1461 };
1462
1463 struct radeon_dpm_dynamic_state {
1464 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1465 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1466 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1467 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1468 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1469 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1470 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1471 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1472 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1473 struct radeon_clock_array valid_sclk_values;
1474 struct radeon_clock_array valid_mclk_values;
1475 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1476 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1477 u32 mclk_sclk_ratio;
1478 u32 sclk_mclk_delta;
1479 u16 vddc_vddci_delta;
1480 u16 min_vddc_for_pcie_gen2;
1481 struct radeon_cac_leakage_table cac_leakage_table;
1482 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1483 struct radeon_ppm_table *ppm_table;
1484 struct radeon_cac_tdp_table *cac_tdp_table;
1485 };
1486
1487 struct radeon_dpm_fan {
1488 u16 t_min;
1489 u16 t_med;
1490 u16 t_high;
1491 u16 pwm_min;
1492 u16 pwm_med;
1493 u16 pwm_high;
1494 u8 t_hyst;
1495 u32 cycle_delay;
1496 u16 t_max;
1497 u8 control_mode;
1498 u16 default_max_fan_pwm;
1499 u16 default_fan_output_sensitivity;
1500 u16 fan_output_sensitivity;
1501 bool ucode_fan_control;
1502 };
1503
1504 enum radeon_pcie_gen {
1505 RADEON_PCIE_GEN1 = 0,
1506 RADEON_PCIE_GEN2 = 1,
1507 RADEON_PCIE_GEN3 = 2,
1508 RADEON_PCIE_GEN_INVALID = 0xffff
1509 };
1510
1511 enum radeon_dpm_forced_level {
1512 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1513 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1514 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1515 };
1516
1517 struct radeon_vce_state {
1518 /* vce clocks */
1519 u32 evclk;
1520 u32 ecclk;
1521 /* gpu clocks */
1522 u32 sclk;
1523 u32 mclk;
1524 u8 clk_idx;
1525 u8 pstate;
1526 };
1527
1528 struct radeon_dpm {
1529 struct radeon_ps *ps;
1530 /* number of valid power states */
1531 int num_ps;
1532 /* current power state that is active */
1533 struct radeon_ps *current_ps;
1534 /* requested power state */
1535 struct radeon_ps *requested_ps;
1536 /* boot up power state */
1537 struct radeon_ps *boot_ps;
1538 /* default uvd power state */
1539 struct radeon_ps *uvd_ps;
1540 /* vce requirements */
1541 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1542 enum radeon_vce_level vce_level;
1543 enum radeon_pm_state_type state;
1544 enum radeon_pm_state_type user_state;
1545 u32 platform_caps;
1546 u32 voltage_response_time;
1547 u32 backbias_response_time;
1548 void *priv;
1549 u32 new_active_crtcs;
1550 int new_active_crtc_count;
1551 int high_pixelclock_count;
1552 u32 current_active_crtcs;
1553 int current_active_crtc_count;
1554 bool single_display;
1555 struct radeon_dpm_dynamic_state dyn_state;
1556 struct radeon_dpm_fan fan;
1557 u32 tdp_limit;
1558 u32 near_tdp_limit;
1559 u32 near_tdp_limit_adjusted;
1560 u32 sq_ramping_threshold;
1561 u32 cac_leakage;
1562 u16 tdp_od_limit;
1563 u32 tdp_adjustment;
1564 u16 load_line_slope;
1565 bool power_control;
1566 bool ac_power;
1567 /* special states active */
1568 bool thermal_active;
1569 bool uvd_active;
1570 bool vce_active;
1571 /* thermal handling */
1572 struct radeon_dpm_thermal thermal;
1573 /* forced levels */
1574 enum radeon_dpm_forced_level forced_level;
1575 /* track UVD streams */
1576 unsigned sd;
1577 unsigned hd;
1578 };
1579
1580 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1581 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1582
1583 struct radeon_pm {
1584 struct mutex mutex;
1585 /* write locked while reprogramming mclk */
1586 struct rw_semaphore mclk_lock;
1587 u32 active_crtcs;
1588 int active_crtc_count;
1589 int req_vblank;
1590 bool vblank_sync;
1591 fixed20_12 max_bandwidth;
1592 fixed20_12 igp_sideport_mclk;
1593 fixed20_12 igp_system_mclk;
1594 fixed20_12 igp_ht_link_clk;
1595 fixed20_12 igp_ht_link_width;
1596 fixed20_12 k8_bandwidth;
1597 fixed20_12 sideport_bandwidth;
1598 fixed20_12 ht_bandwidth;
1599 fixed20_12 core_bandwidth;
1600 fixed20_12 sclk;
1601 fixed20_12 mclk;
1602 fixed20_12 needed_bandwidth;
1603 struct radeon_power_state *power_state;
1604 /* number of valid power states */
1605 int num_power_states;
1606 int current_power_state_index;
1607 int current_clock_mode_index;
1608 int requested_power_state_index;
1609 int requested_clock_mode_index;
1610 int default_power_state_index;
1611 u32 current_sclk;
1612 u32 current_mclk;
1613 u16 current_vddc;
1614 u16 current_vddci;
1615 u32 default_sclk;
1616 u32 default_mclk;
1617 u16 default_vddc;
1618 u16 default_vddci;
1619 struct radeon_i2c_chan *i2c_bus;
1620 /* selected pm method */
1621 enum radeon_pm_method pm_method;
1622 /* dynpm power management */
1623 struct delayed_work dynpm_idle_work;
1624 enum radeon_dynpm_state dynpm_state;
1625 enum radeon_dynpm_action dynpm_planned_action;
1626 unsigned long dynpm_action_timeout;
1627 bool dynpm_can_upclock;
1628 bool dynpm_can_downclock;
1629 /* profile-based power management */
1630 enum radeon_pm_profile_type profile;
1631 int profile_index;
1632 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1633 /* internal thermal controller on rv6xx+ */
1634 enum radeon_int_thermal_type int_thermal_type;
1635 struct device *int_hwmon_dev;
1636 /* fan control parameters */
1637 bool no_fan;
1638 u8 fan_pulses_per_revolution;
1639 u8 fan_min_rpm;
1640 u8 fan_max_rpm;
1641 /* dpm */
1642 bool dpm_enabled;
1643 bool sysfs_initialized;
1644 struct radeon_dpm dpm;
1645 };
1646
1647 #define RADEON_PCIE_SPEED_25 1
1648 #define RADEON_PCIE_SPEED_50 2
1649 #define RADEON_PCIE_SPEED_80 4
1650
1651 int radeon_pm_get_type_index(struct radeon_device *rdev,
1652 enum radeon_pm_state_type ps_type,
1653 int instance);
1654 /*
1655 * UVD
1656 */
1657 #define RADEON_DEFAULT_UVD_HANDLES 10
1658 #define RADEON_MAX_UVD_HANDLES 30
1659 #define RADEON_UVD_STACK_SIZE (200*1024)
1660 #define RADEON_UVD_HEAP_SIZE (256*1024)
1661 #define RADEON_UVD_SESSION_SIZE (50*1024)
1662
1663 struct radeon_uvd {
1664 bool fw_header_present;
1665 struct radeon_bo *vcpu_bo;
1666 void *cpu_addr;
1667 uint64_t gpu_addr;
1668 unsigned max_handles;
1669 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1670 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1671 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1672 struct delayed_work idle_work;
1673 };
1674
1675 int radeon_uvd_init(struct radeon_device *rdev);
1676 void radeon_uvd_fini(struct radeon_device *rdev);
1677 int radeon_uvd_suspend(struct radeon_device *rdev);
1678 int radeon_uvd_resume(struct radeon_device *rdev);
1679 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1680 uint32_t handle, struct radeon_fence **fence);
1681 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1682 uint32_t handle, struct radeon_fence **fence);
1683 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1684 uint32_t allowed_domains);
1685 void radeon_uvd_free_handles(struct radeon_device *rdev,
1686 struct drm_file *filp);
1687 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1688 void radeon_uvd_note_usage(struct radeon_device *rdev);
1689 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1690 unsigned vclk, unsigned dclk,
1691 unsigned vco_min, unsigned vco_max,
1692 unsigned fb_factor, unsigned fb_mask,
1693 unsigned pd_min, unsigned pd_max,
1694 unsigned pd_even,
1695 unsigned *optimal_fb_div,
1696 unsigned *optimal_vclk_div,
1697 unsigned *optimal_dclk_div);
1698 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1699 unsigned cg_upll_func_cntl);
1700
1701 /*
1702 * VCE
1703 */
1704 #define RADEON_MAX_VCE_HANDLES 16
1705
1706 struct radeon_vce {
1707 struct radeon_bo *vcpu_bo;
1708 uint64_t gpu_addr;
1709 unsigned fw_version;
1710 unsigned fb_version;
1711 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1712 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1713 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1714 struct delayed_work idle_work;
1715 uint32_t keyselect;
1716 };
1717
1718 int radeon_vce_init(struct radeon_device *rdev);
1719 void radeon_vce_fini(struct radeon_device *rdev);
1720 int radeon_vce_suspend(struct radeon_device *rdev);
1721 int radeon_vce_resume(struct radeon_device *rdev);
1722 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1723 uint32_t handle, struct radeon_fence **fence);
1724 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1725 uint32_t handle, struct radeon_fence **fence);
1726 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1727 void radeon_vce_note_usage(struct radeon_device *rdev);
1728 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1729 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1730 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1731 struct radeon_ring *ring,
1732 struct radeon_semaphore *semaphore,
1733 bool emit_wait);
1734 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1735 void radeon_vce_fence_emit(struct radeon_device *rdev,
1736 struct radeon_fence *fence);
1737 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1738 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1739
1740 struct r600_audio_pin {
1741 int channels;
1742 int rate;
1743 int bits_per_sample;
1744 u8 status_bits;
1745 u8 category_code;
1746 u32 offset;
1747 bool connected;
1748 u32 id;
1749 };
1750
1751 struct r600_audio {
1752 bool enabled;
1753 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1754 int num_pins;
1755 struct radeon_audio_funcs *hdmi_funcs;
1756 struct radeon_audio_funcs *dp_funcs;
1757 struct radeon_audio_basic_funcs *funcs;
1758 struct drm_audio_component *component;
1759 bool component_registered;
1760 struct mutex component_mutex;
1761 };
1762
1763 /*
1764 * Benchmarking
1765 */
1766 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1767
1768
1769 /*
1770 * Testing
1771 */
1772 void radeon_test_moves(struct radeon_device *rdev);
1773 void radeon_test_ring_sync(struct radeon_device *rdev,
1774 struct radeon_ring *cpA,
1775 struct radeon_ring *cpB);
1776 void radeon_test_syncing(struct radeon_device *rdev);
1777
1778 /*
1779 * MMU Notifier
1780 */
1781 #if defined(CONFIG_MMU_NOTIFIER)
1782 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1783 void radeon_mn_unregister(struct radeon_bo *bo);
1784 #else
radeon_mn_register(struct radeon_bo * bo,unsigned long addr)1785 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1786 {
1787 return -ENODEV;
1788 }
radeon_mn_unregister(struct radeon_bo * bo)1789 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1790 #endif
1791
1792 /*
1793 * Debugfs
1794 */
1795 void radeon_debugfs_fence_init(struct radeon_device *rdev);
1796 void radeon_gem_debugfs_init(struct radeon_device *rdev);
1797
1798 /*
1799 * ASIC ring specific functions.
1800 */
1801 struct radeon_asic_ring {
1802 /* ring read/write ptr handling */
1803 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1804 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1805 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1806
1807 /* validating and patching of IBs */
1808 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1809 int (*cs_parse)(struct radeon_cs_parser *p);
1810
1811 /* command emmit functions */
1812 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1813 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1814 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1815 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1816 struct radeon_semaphore *semaphore, bool emit_wait);
1817 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1818 unsigned vm_id, uint64_t pd_addr);
1819
1820 /* testing functions */
1821 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1822 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1823 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1824
1825 /* deprecated */
1826 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1827 };
1828
1829 /*
1830 * ASIC specific functions.
1831 */
1832 struct radeon_asic {
1833 int (*init)(struct radeon_device *rdev);
1834 void (*fini)(struct radeon_device *rdev);
1835 int (*resume)(struct radeon_device *rdev);
1836 int (*suspend)(struct radeon_device *rdev);
1837 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1838 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1839 /* Flush the HDP cache via MMIO */
1840 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1841 /* check if 3D engine is idle */
1842 bool (*gui_idle)(struct radeon_device *rdev);
1843 /* wait for mc_idle */
1844 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1845 /* get the reference clock */
1846 u32 (*get_xclk)(struct radeon_device *rdev);
1847 /* get the gpu clock counter */
1848 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1849 /* get register for info ioctl */
1850 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1851 /* gart */
1852 struct {
1853 void (*tlb_flush)(struct radeon_device *rdev);
1854 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1855 void (*set_page)(struct radeon_device *rdev, unsigned i,
1856 uint64_t entry);
1857 } gart;
1858 struct {
1859 int (*init)(struct radeon_device *rdev);
1860 void (*fini)(struct radeon_device *rdev);
1861 void (*copy_pages)(struct radeon_device *rdev,
1862 struct radeon_ib *ib,
1863 uint64_t pe, uint64_t src,
1864 unsigned count);
1865 void (*write_pages)(struct radeon_device *rdev,
1866 struct radeon_ib *ib,
1867 uint64_t pe,
1868 uint64_t addr, unsigned count,
1869 uint32_t incr, uint32_t flags);
1870 void (*set_pages)(struct radeon_device *rdev,
1871 struct radeon_ib *ib,
1872 uint64_t pe,
1873 uint64_t addr, unsigned count,
1874 uint32_t incr, uint32_t flags);
1875 void (*pad_ib)(struct radeon_ib *ib);
1876 } vm;
1877 /* ring specific callbacks */
1878 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1879 /* irqs */
1880 struct {
1881 int (*set)(struct radeon_device *rdev);
1882 int (*process)(struct radeon_device *rdev);
1883 } irq;
1884 /* displays */
1885 struct {
1886 /* display watermarks */
1887 void (*bandwidth_update)(struct radeon_device *rdev);
1888 /* get frame count */
1889 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1890 /* wait for vblank */
1891 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1892 /* set backlight level */
1893 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1894 /* get backlight level */
1895 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1896 /* audio callbacks */
1897 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1898 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1899 } display;
1900 /* copy functions for bo handling */
1901 struct {
1902 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1903 uint64_t src_offset,
1904 uint64_t dst_offset,
1905 unsigned num_gpu_pages,
1906 struct dma_resv *resv);
1907 u32 blit_ring_index;
1908 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1909 uint64_t src_offset,
1910 uint64_t dst_offset,
1911 unsigned num_gpu_pages,
1912 struct dma_resv *resv);
1913 u32 dma_ring_index;
1914 /* method used for bo copy */
1915 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1916 uint64_t src_offset,
1917 uint64_t dst_offset,
1918 unsigned num_gpu_pages,
1919 struct dma_resv *resv);
1920 /* ring used for bo copies */
1921 u32 copy_ring_index;
1922 } copy;
1923 /* surfaces */
1924 struct {
1925 int (*set_reg)(struct radeon_device *rdev, int reg,
1926 uint32_t tiling_flags, uint32_t pitch,
1927 uint32_t offset, uint32_t obj_size);
1928 void (*clear_reg)(struct radeon_device *rdev, int reg);
1929 } surface;
1930 /* hotplug detect */
1931 struct {
1932 void (*init)(struct radeon_device *rdev);
1933 void (*fini)(struct radeon_device *rdev);
1934 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1935 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1936 } hpd;
1937 /* static power management */
1938 struct {
1939 void (*misc)(struct radeon_device *rdev);
1940 void (*prepare)(struct radeon_device *rdev);
1941 void (*finish)(struct radeon_device *rdev);
1942 void (*init_profile)(struct radeon_device *rdev);
1943 void (*get_dynpm_state)(struct radeon_device *rdev);
1944 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1945 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1946 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1947 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1948 int (*get_pcie_lanes)(struct radeon_device *rdev);
1949 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1950 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1951 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1952 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1953 int (*get_temperature)(struct radeon_device *rdev);
1954 } pm;
1955 /* dynamic power management */
1956 struct {
1957 int (*init)(struct radeon_device *rdev);
1958 void (*setup_asic)(struct radeon_device *rdev);
1959 int (*enable)(struct radeon_device *rdev);
1960 int (*late_enable)(struct radeon_device *rdev);
1961 void (*disable)(struct radeon_device *rdev);
1962 int (*pre_set_power_state)(struct radeon_device *rdev);
1963 int (*set_power_state)(struct radeon_device *rdev);
1964 void (*post_set_power_state)(struct radeon_device *rdev);
1965 void (*display_configuration_changed)(struct radeon_device *rdev);
1966 void (*fini)(struct radeon_device *rdev);
1967 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1968 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1969 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1970 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1971 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1972 bool (*vblank_too_short)(struct radeon_device *rdev);
1973 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1974 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1975 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1976 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1977 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1978 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1979 u32 (*get_current_sclk)(struct radeon_device *rdev);
1980 u32 (*get_current_mclk)(struct radeon_device *rdev);
1981 u16 (*get_current_vddc)(struct radeon_device *rdev);
1982 } dpm;
1983 /* pageflipping */
1984 struct {
1985 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
1986 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1987 } pflip;
1988 };
1989
1990 /*
1991 * Asic structures
1992 */
1993 struct r100_asic {
1994 const unsigned *reg_safe_bm;
1995 unsigned reg_safe_bm_size;
1996 u32 hdp_cntl;
1997 };
1998
1999 struct r300_asic {
2000 const unsigned *reg_safe_bm;
2001 unsigned reg_safe_bm_size;
2002 u32 resync_scratch;
2003 u32 hdp_cntl;
2004 };
2005
2006 struct r600_asic {
2007 unsigned max_pipes;
2008 unsigned max_tile_pipes;
2009 unsigned max_simds;
2010 unsigned max_backends;
2011 unsigned max_gprs;
2012 unsigned max_threads;
2013 unsigned max_stack_entries;
2014 unsigned max_hw_contexts;
2015 unsigned max_gs_threads;
2016 unsigned sx_max_export_size;
2017 unsigned sx_max_export_pos_size;
2018 unsigned sx_max_export_smx_size;
2019 unsigned sq_num_cf_insts;
2020 unsigned tiling_nbanks;
2021 unsigned tiling_npipes;
2022 unsigned tiling_group_size;
2023 unsigned tile_config;
2024 unsigned backend_map;
2025 unsigned active_simds;
2026 };
2027
2028 struct rv770_asic {
2029 unsigned max_pipes;
2030 unsigned max_tile_pipes;
2031 unsigned max_simds;
2032 unsigned max_backends;
2033 unsigned max_gprs;
2034 unsigned max_threads;
2035 unsigned max_stack_entries;
2036 unsigned max_hw_contexts;
2037 unsigned max_gs_threads;
2038 unsigned sx_max_export_size;
2039 unsigned sx_max_export_pos_size;
2040 unsigned sx_max_export_smx_size;
2041 unsigned sq_num_cf_insts;
2042 unsigned sx_num_of_sets;
2043 unsigned sc_prim_fifo_size;
2044 unsigned sc_hiz_tile_fifo_size;
2045 unsigned sc_earlyz_tile_fifo_fize;
2046 unsigned tiling_nbanks;
2047 unsigned tiling_npipes;
2048 unsigned tiling_group_size;
2049 unsigned tile_config;
2050 unsigned backend_map;
2051 unsigned active_simds;
2052 };
2053
2054 struct evergreen_asic {
2055 unsigned num_ses;
2056 unsigned max_pipes;
2057 unsigned max_tile_pipes;
2058 unsigned max_simds;
2059 unsigned max_backends;
2060 unsigned max_gprs;
2061 unsigned max_threads;
2062 unsigned max_stack_entries;
2063 unsigned max_hw_contexts;
2064 unsigned max_gs_threads;
2065 unsigned sx_max_export_size;
2066 unsigned sx_max_export_pos_size;
2067 unsigned sx_max_export_smx_size;
2068 unsigned sq_num_cf_insts;
2069 unsigned sx_num_of_sets;
2070 unsigned sc_prim_fifo_size;
2071 unsigned sc_hiz_tile_fifo_size;
2072 unsigned sc_earlyz_tile_fifo_size;
2073 unsigned tiling_nbanks;
2074 unsigned tiling_npipes;
2075 unsigned tiling_group_size;
2076 unsigned tile_config;
2077 unsigned backend_map;
2078 unsigned active_simds;
2079 };
2080
2081 struct cayman_asic {
2082 unsigned max_shader_engines;
2083 unsigned max_pipes_per_simd;
2084 unsigned max_tile_pipes;
2085 unsigned max_simds_per_se;
2086 unsigned max_backends_per_se;
2087 unsigned max_texture_channel_caches;
2088 unsigned max_gprs;
2089 unsigned max_threads;
2090 unsigned max_gs_threads;
2091 unsigned max_stack_entries;
2092 unsigned sx_num_of_sets;
2093 unsigned sx_max_export_size;
2094 unsigned sx_max_export_pos_size;
2095 unsigned sx_max_export_smx_size;
2096 unsigned max_hw_contexts;
2097 unsigned sq_num_cf_insts;
2098 unsigned sc_prim_fifo_size;
2099 unsigned sc_hiz_tile_fifo_size;
2100 unsigned sc_earlyz_tile_fifo_size;
2101
2102 unsigned num_shader_engines;
2103 unsigned num_shader_pipes_per_simd;
2104 unsigned num_tile_pipes;
2105 unsigned num_simds_per_se;
2106 unsigned num_backends_per_se;
2107 unsigned backend_disable_mask_per_asic;
2108 unsigned backend_map;
2109 unsigned num_texture_channel_caches;
2110 unsigned mem_max_burst_length_bytes;
2111 unsigned mem_row_size_in_kb;
2112 unsigned shader_engine_tile_size;
2113 unsigned num_gpus;
2114 unsigned multi_gpu_tile_size;
2115
2116 unsigned tile_config;
2117 unsigned active_simds;
2118 };
2119
2120 struct si_asic {
2121 unsigned max_shader_engines;
2122 unsigned max_tile_pipes;
2123 unsigned max_cu_per_sh;
2124 unsigned max_sh_per_se;
2125 unsigned max_backends_per_se;
2126 unsigned max_texture_channel_caches;
2127 unsigned max_gprs;
2128 unsigned max_gs_threads;
2129 unsigned max_hw_contexts;
2130 unsigned sc_prim_fifo_size_frontend;
2131 unsigned sc_prim_fifo_size_backend;
2132 unsigned sc_hiz_tile_fifo_size;
2133 unsigned sc_earlyz_tile_fifo_size;
2134
2135 unsigned num_tile_pipes;
2136 unsigned backend_enable_mask;
2137 unsigned backend_disable_mask_per_asic;
2138 unsigned backend_map;
2139 unsigned num_texture_channel_caches;
2140 unsigned mem_max_burst_length_bytes;
2141 unsigned mem_row_size_in_kb;
2142 unsigned shader_engine_tile_size;
2143 unsigned num_gpus;
2144 unsigned multi_gpu_tile_size;
2145
2146 unsigned tile_config;
2147 uint32_t tile_mode_array[32];
2148 uint32_t active_cus;
2149 };
2150
2151 struct cik_asic {
2152 unsigned max_shader_engines;
2153 unsigned max_tile_pipes;
2154 unsigned max_cu_per_sh;
2155 unsigned max_sh_per_se;
2156 unsigned max_backends_per_se;
2157 unsigned max_texture_channel_caches;
2158 unsigned max_gprs;
2159 unsigned max_gs_threads;
2160 unsigned max_hw_contexts;
2161 unsigned sc_prim_fifo_size_frontend;
2162 unsigned sc_prim_fifo_size_backend;
2163 unsigned sc_hiz_tile_fifo_size;
2164 unsigned sc_earlyz_tile_fifo_size;
2165
2166 unsigned num_tile_pipes;
2167 unsigned backend_enable_mask;
2168 unsigned backend_disable_mask_per_asic;
2169 unsigned backend_map;
2170 unsigned num_texture_channel_caches;
2171 unsigned mem_max_burst_length_bytes;
2172 unsigned mem_row_size_in_kb;
2173 unsigned shader_engine_tile_size;
2174 unsigned num_gpus;
2175 unsigned multi_gpu_tile_size;
2176
2177 unsigned tile_config;
2178 uint32_t tile_mode_array[32];
2179 uint32_t macrotile_mode_array[16];
2180 uint32_t active_cus;
2181 };
2182
2183 union radeon_asic_config {
2184 struct r300_asic r300;
2185 struct r100_asic r100;
2186 struct r600_asic r600;
2187 struct rv770_asic rv770;
2188 struct evergreen_asic evergreen;
2189 struct cayman_asic cayman;
2190 struct si_asic si;
2191 struct cik_asic cik;
2192 };
2193
2194 /*
2195 * asic initizalization from radeon_asic.c
2196 */
2197 void radeon_agp_disable(struct radeon_device *rdev);
2198 int radeon_asic_init(struct radeon_device *rdev);
2199
2200
2201 /*
2202 * IOCTL.
2203 */
2204 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2205 struct drm_file *filp);
2206 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2207 struct drm_file *filp);
2208 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2209 struct drm_file *filp);
2210 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2211 struct drm_file *file_priv);
2212 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2213 struct drm_file *file_priv);
2214 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2215 struct drm_file *filp);
2216 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2217 struct drm_file *filp);
2218 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2219 struct drm_file *filp);
2220 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
2224 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *filp);
2226 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2227 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2228 struct drm_file *filp);
2229 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2230 struct drm_file *filp);
2231 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2232
2233 /* VRAM scratch page for HDP bug, default vram page */
2234 struct r600_vram_scratch {
2235 struct radeon_bo *robj;
2236 volatile uint32_t *ptr;
2237 u64 gpu_addr;
2238 };
2239
2240 /*
2241 * ACPI
2242 */
2243 struct radeon_atif_notification_cfg {
2244 bool enabled;
2245 int command_code;
2246 };
2247
2248 struct radeon_atif_notifications {
2249 bool display_switch;
2250 bool expansion_mode_change;
2251 bool thermal_state;
2252 bool forced_power_state;
2253 bool system_power_state;
2254 bool display_conf_change;
2255 bool px_gfx_switch;
2256 bool brightness_change;
2257 bool dgpu_display_event;
2258 };
2259
2260 struct radeon_atif_functions {
2261 bool system_params;
2262 bool sbios_requests;
2263 bool select_active_disp;
2264 bool lid_state;
2265 bool get_tv_standard;
2266 bool set_tv_standard;
2267 bool get_panel_expansion_mode;
2268 bool set_panel_expansion_mode;
2269 bool temperature_change;
2270 bool graphics_device_types;
2271 };
2272
2273 struct radeon_atif {
2274 struct radeon_atif_notifications notifications;
2275 struct radeon_atif_functions functions;
2276 struct radeon_atif_notification_cfg notification_cfg;
2277 struct radeon_encoder *encoder_for_bl;
2278 };
2279
2280 struct radeon_atcs_functions {
2281 bool get_ext_state;
2282 bool pcie_perf_req;
2283 bool pcie_dev_rdy;
2284 bool pcie_bus_width;
2285 };
2286
2287 struct radeon_atcs {
2288 struct radeon_atcs_functions functions;
2289 };
2290
2291 /*
2292 * Core structure, functions and helpers.
2293 */
2294 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2295 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2296
2297 struct radeon_device {
2298 struct device *dev;
2299 struct drm_device ddev;
2300 struct pci_dev *pdev;
2301 #ifdef __alpha__
2302 struct pci_controller *hose;
2303 #endif
2304 struct radeon_agp_head *agp;
2305 struct rw_semaphore exclusive_lock;
2306 /* ASIC */
2307 union radeon_asic_config config;
2308 enum radeon_family family;
2309 unsigned long flags;
2310 int usec_timeout;
2311 enum radeon_pll_errata pll_errata;
2312 int num_gb_pipes;
2313 int num_z_pipes;
2314 int disp_priority;
2315 /* BIOS */
2316 uint8_t *bios;
2317 bool is_atom_bios;
2318 uint16_t bios_header_start;
2319 struct radeon_bo *stolen_vga_memory;
2320 /* Register mmio */
2321 resource_size_t rmmio_base;
2322 resource_size_t rmmio_size;
2323 /* protects concurrent MM_INDEX/DATA based register access */
2324 spinlock_t mmio_idx_lock;
2325 /* protects concurrent SMC based register access */
2326 spinlock_t smc_idx_lock;
2327 /* protects concurrent PLL register access */
2328 spinlock_t pll_idx_lock;
2329 /* protects concurrent MC register access */
2330 spinlock_t mc_idx_lock;
2331 /* protects concurrent PCIE register access */
2332 spinlock_t pcie_idx_lock;
2333 /* protects concurrent PCIE_PORT register access */
2334 spinlock_t pciep_idx_lock;
2335 /* protects concurrent PIF register access */
2336 spinlock_t pif_idx_lock;
2337 /* protects concurrent CG register access */
2338 spinlock_t cg_idx_lock;
2339 /* protects concurrent UVD register access */
2340 spinlock_t uvd_idx_lock;
2341 /* protects concurrent RCU register access */
2342 spinlock_t rcu_idx_lock;
2343 /* protects concurrent DIDT register access */
2344 spinlock_t didt_idx_lock;
2345 /* protects concurrent ENDPOINT (audio) register access */
2346 spinlock_t end_idx_lock;
2347 void __iomem *rmmio;
2348 radeon_rreg_t mc_rreg;
2349 radeon_wreg_t mc_wreg;
2350 radeon_rreg_t pll_rreg;
2351 radeon_wreg_t pll_wreg;
2352 uint32_t pcie_reg_mask;
2353 radeon_rreg_t pciep_rreg;
2354 radeon_wreg_t pciep_wreg;
2355 /* io port */
2356 void __iomem *rio_mem;
2357 resource_size_t rio_mem_size;
2358 struct radeon_clock clock;
2359 struct radeon_mc mc;
2360 struct radeon_gart gart;
2361 struct radeon_mode_info mode_info;
2362 struct radeon_scratch scratch;
2363 struct radeon_doorbell doorbell;
2364 struct radeon_mman mman;
2365 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2366 wait_queue_head_t fence_queue;
2367 u64 fence_context;
2368 struct mutex ring_lock;
2369 struct radeon_ring ring[RADEON_NUM_RINGS];
2370 bool ib_pool_ready;
2371 struct radeon_sa_manager ring_tmp_bo;
2372 struct radeon_irq irq;
2373 struct radeon_asic *asic;
2374 struct radeon_gem gem;
2375 struct radeon_pm pm;
2376 struct radeon_uvd uvd;
2377 struct radeon_vce vce;
2378 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2379 struct radeon_wb wb;
2380 struct radeon_dummy_page dummy_page;
2381 bool shutdown;
2382 bool need_swiotlb;
2383 bool accel_working;
2384 bool fastfb_working; /* IGP feature*/
2385 bool needs_reset, in_reset;
2386 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2387 const struct firmware *me_fw; /* all family ME firmware */
2388 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2389 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2390 const struct firmware *mc_fw; /* NI MC firmware */
2391 const struct firmware *ce_fw; /* SI CE firmware */
2392 const struct firmware *mec_fw; /* CIK MEC firmware */
2393 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2394 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2395 const struct firmware *smc_fw; /* SMC firmware */
2396 const struct firmware *uvd_fw; /* UVD firmware */
2397 const struct firmware *vce_fw; /* VCE firmware */
2398 bool new_fw;
2399 struct r600_vram_scratch vram_scratch;
2400 int msi_enabled; /* msi enabled */
2401 struct r600_ih ih; /* r6/700 interrupt ring */
2402 struct radeon_rlc rlc;
2403 struct radeon_mec mec;
2404 struct delayed_work hotplug_work;
2405 struct work_struct dp_work;
2406 struct work_struct audio_work;
2407 int num_crtc; /* number of crtcs */
2408 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2409 bool has_uvd;
2410 bool has_vce;
2411 struct r600_audio audio; /* audio stuff */
2412 struct notifier_block acpi_nb;
2413 /* only one userspace can use Hyperz features or CMASK at a time */
2414 struct drm_file *hyperz_filp;
2415 struct drm_file *cmask_filp;
2416 /* i2c buses */
2417 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2418 /* virtual memory */
2419 struct radeon_vm_manager vm_manager;
2420 struct mutex gpu_clock_mutex;
2421 /* memory stats */
2422 atomic64_t num_bytes_moved;
2423 atomic_t gpu_reset_counter;
2424 /* ACPI interface */
2425 struct radeon_atif atif;
2426 struct radeon_atcs atcs;
2427 /* srbm instance registers */
2428 struct mutex srbm_mutex;
2429 /* clock, powergating flags */
2430 u32 cg_flags;
2431 u32 pg_flags;
2432
2433 struct dev_pm_domain vga_pm_domain;
2434 bool have_disp_power_ref;
2435 u32 px_quirk_flags;
2436
2437 /* tracking pinned memory */
2438 u64 vram_pin_size;
2439 u64 gart_pin_size;
2440 };
2441
2442 bool radeon_is_px(struct drm_device *dev);
2443 int radeon_device_init(struct radeon_device *rdev,
2444 struct drm_device *ddev,
2445 struct pci_dev *pdev,
2446 uint32_t flags);
2447 void radeon_device_fini(struct radeon_device *rdev);
2448 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2449
2450 #define RADEON_MIN_MMIO_SIZE 0x10000
2451
2452 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2453 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2454 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2455 bool always_indirect)
2456 {
2457 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2458 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2459 return readl(((void __iomem *)rdev->rmmio) + reg);
2460 else
2461 return r100_mm_rreg_slow(rdev, reg);
2462 }
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2463 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2464 bool always_indirect)
2465 {
2466 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2467 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2468 else
2469 r100_mm_wreg_slow(rdev, reg, v);
2470 }
2471
2472 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2473 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2474
2475 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2476 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2477
rdev_to_drm(struct radeon_device * rdev)2478 static inline struct drm_device *rdev_to_drm(struct radeon_device *rdev)
2479 {
2480 return &rdev->ddev;
2481 }
2482
2483 /*
2484 * Cast helper
2485 */
2486 extern const struct dma_fence_ops radeon_fence_ops;
2487
to_radeon_fence(struct dma_fence * f)2488 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2489 {
2490 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2491
2492 if (__f->base.ops == &radeon_fence_ops)
2493 return __f;
2494
2495 return NULL;
2496 }
2497
2498 /*
2499 * Registers read & write functions.
2500 */
2501 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2502 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2503 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2504 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2505 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2506 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2507 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2508 r100_mm_rreg(rdev, (reg), false))
2509 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2510 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2511 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2512 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2513 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2514 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2515 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2516 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2517 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2518 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2519 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2520 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2521 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2522 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2523 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2524 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2525 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2526 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2527 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2528 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2529 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2530 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2531 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2532 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2533 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2534 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2535 #define WREG32_P(reg, val, mask) \
2536 do { \
2537 uint32_t tmp_ = RREG32(reg); \
2538 tmp_ &= (mask); \
2539 tmp_ |= ((val) & ~(mask)); \
2540 WREG32(reg, tmp_); \
2541 } while (0)
2542 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2543 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2544 #define WREG32_PLL_P(reg, val, mask) \
2545 do { \
2546 uint32_t tmp_ = RREG32_PLL(reg); \
2547 tmp_ &= (mask); \
2548 tmp_ |= ((val) & ~(mask)); \
2549 WREG32_PLL(reg, tmp_); \
2550 } while (0)
2551 #define WREG32_SMC_P(reg, val, mask) \
2552 do { \
2553 uint32_t tmp_ = RREG32_SMC(reg); \
2554 tmp_ &= (mask); \
2555 tmp_ |= ((val) & ~(mask)); \
2556 WREG32_SMC(reg, tmp_); \
2557 } while (0)
2558 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2559 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2560 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2561
2562 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2563 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2564
2565 /*
2566 * Indirect registers accessors.
2567 * They used to be inlined, but this increases code size by ~65 kbytes.
2568 * Since each performs a pair of MMIO ops
2569 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2570 * the cost of call+ret is almost negligible. MMIO and locking
2571 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2572 */
2573 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2574 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2575 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2576 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2577 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2578 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2579 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2580 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2581 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2582 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2583 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2584 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2585 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2586 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2587 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2588 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2589
2590 void r100_pll_errata_after_index(struct radeon_device *rdev);
2591
2592
2593 /*
2594 * ASICs helpers.
2595 */
2596 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2597 (rdev->pdev->device == 0x5969))
2598 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2599 (rdev->family == CHIP_RV200) || \
2600 (rdev->family == CHIP_RS100) || \
2601 (rdev->family == CHIP_RS200) || \
2602 (rdev->family == CHIP_RV250) || \
2603 (rdev->family == CHIP_RV280) || \
2604 (rdev->family == CHIP_RS300))
2605 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2606 (rdev->family == CHIP_RV350) || \
2607 (rdev->family == CHIP_R350) || \
2608 (rdev->family == CHIP_RV380) || \
2609 (rdev->family == CHIP_R420) || \
2610 (rdev->family == CHIP_R423) || \
2611 (rdev->family == CHIP_RV410) || \
2612 (rdev->family == CHIP_RS400) || \
2613 (rdev->family == CHIP_RS480))
2614 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2615 (rdev->pdev->device == 0x9443) || \
2616 (rdev->pdev->device == 0x944B) || \
2617 (rdev->pdev->device == 0x9506) || \
2618 (rdev->pdev->device == 0x9509) || \
2619 (rdev->pdev->device == 0x950F) || \
2620 (rdev->pdev->device == 0x689C) || \
2621 (rdev->pdev->device == 0x689D))
2622 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2623 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2624 (rdev->family == CHIP_RS690) || \
2625 (rdev->family == CHIP_RS740) || \
2626 (rdev->family >= CHIP_R600))
2627 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2628 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2629 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2630 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2631 (rdev->flags & RADEON_IS_IGP))
2632 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2633 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2634 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2635 (rdev->flags & RADEON_IS_IGP))
2636 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2637 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2638 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2639 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2640 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2641 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2642 (rdev->family == CHIP_MULLINS))
2643
2644 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2645 (rdev->pdev->device == 0x6850) || \
2646 (rdev->pdev->device == 0x6858) || \
2647 (rdev->pdev->device == 0x6859) || \
2648 (rdev->pdev->device == 0x6840) || \
2649 (rdev->pdev->device == 0x6841) || \
2650 (rdev->pdev->device == 0x6842) || \
2651 (rdev->pdev->device == 0x6843))
2652
2653 /*
2654 * BIOS helpers.
2655 */
2656 #define RBIOS8(i) (rdev->bios[i])
2657 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2658 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2659
2660 int radeon_combios_init(struct radeon_device *rdev);
2661 void radeon_combios_fini(struct radeon_device *rdev);
2662 int radeon_atombios_init(struct radeon_device *rdev);
2663 void radeon_atombios_fini(struct radeon_device *rdev);
2664
2665
2666 /*
2667 * RING helpers.
2668 */
2669
2670 /**
2671 * radeon_ring_write - write a value to the ring
2672 *
2673 * @ring: radeon_ring structure holding ring information
2674 * @v: dword (dw) value to write
2675 *
2676 * Write a value to the requested ring buffer (all asics).
2677 */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2678 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2679 {
2680 if (ring->count_dw <= 0)
2681 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2682
2683 ring->ring[ring->wptr++] = v;
2684 ring->wptr &= ring->ptr_mask;
2685 ring->count_dw--;
2686 ring->ring_free_dw--;
2687 }
2688
2689 /*
2690 * ASICs macro.
2691 */
2692 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2693 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2694 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2695 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2696 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2697 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2698 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2699 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2700 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2701 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2702 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2703 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2704 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2705 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2706 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2707 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2708 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2709 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2710 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2711 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2712 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2713 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2714 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2715 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2716 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2717 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2718 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2719 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2720 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2721 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2722 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2723 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2724 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2725 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2726 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2727 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2728 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2729 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2730 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2731 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2732 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2733 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2734 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2735 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2736 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2737 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2738 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2739 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2740 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2741 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2742 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2743 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2744 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2745 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2746 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2747 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2748 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2749 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2750 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2751 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2752 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2753 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2754 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2755 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2756 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2757 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2758 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2759 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2760 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2761 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2762 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2763 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2764 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2765 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2766 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2767 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2768 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2769 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2770 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2771 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2772 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2773 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2774 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2775 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2776 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2777 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2778 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2779 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2780 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2781 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2782 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2783
2784 /* Common functions */
2785 /* AGP */
2786 extern int radeon_gpu_reset(struct radeon_device *rdev);
2787 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2788 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2789 extern void radeon_agp_disable(struct radeon_device *rdev);
2790 extern int radeon_modeset_init(struct radeon_device *rdev);
2791 extern void radeon_modeset_fini(struct radeon_device *rdev);
2792 extern bool radeon_card_posted(struct radeon_device *rdev);
2793 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2794 extern void radeon_update_display_priority(struct radeon_device *rdev);
2795 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2796 extern void radeon_scratch_init(struct radeon_device *rdev);
2797 extern void radeon_wb_fini(struct radeon_device *rdev);
2798 extern int radeon_wb_init(struct radeon_device *rdev);
2799 extern void radeon_wb_disable(struct radeon_device *rdev);
2800 extern void radeon_surface_init(struct radeon_device *rdev);
2801 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2802 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2803 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2804 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2805 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2806 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2807 struct ttm_tt *ttm, uint64_t addr,
2808 uint32_t flags);
2809 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2810 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2811 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
2812 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2813 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2814 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2815 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2816 bool fbcon, bool freeze);
2817 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2818 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2819 const u32 *registers,
2820 const u32 array_size);
2821 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev);
2822
2823 /* KMS */
2824
2825 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
2826 int radeon_enable_vblank_kms(struct drm_crtc *crtc);
2827 void radeon_disable_vblank_kms(struct drm_crtc *crtc);
2828
2829 /*
2830 * vm
2831 */
2832 int radeon_vm_manager_init(struct radeon_device *rdev);
2833 void radeon_vm_manager_fini(struct radeon_device *rdev);
2834 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2835 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2836 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2837 struct radeon_vm *vm,
2838 struct list_head *head);
2839 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2840 struct radeon_vm *vm, int ring);
2841 void radeon_vm_flush(struct radeon_device *rdev,
2842 struct radeon_vm *vm,
2843 int ring, struct radeon_fence *fence);
2844 void radeon_vm_fence(struct radeon_device *rdev,
2845 struct radeon_vm *vm,
2846 struct radeon_fence *fence);
2847 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2848 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2849 struct radeon_vm *vm);
2850 int radeon_vm_clear_freed(struct radeon_device *rdev,
2851 struct radeon_vm *vm);
2852 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2853 struct radeon_vm *vm);
2854 int radeon_vm_bo_update(struct radeon_device *rdev,
2855 struct radeon_bo_va *bo_va,
2856 struct ttm_resource *mem);
2857 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2858 struct radeon_bo *bo);
2859 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2860 struct radeon_bo *bo);
2861 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2862 struct radeon_vm *vm,
2863 struct radeon_bo *bo);
2864 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2865 struct radeon_bo_va *bo_va,
2866 uint64_t offset,
2867 uint32_t flags);
2868 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2869 struct radeon_bo_va *bo_va);
2870
2871 /* audio */
2872 void r600_audio_update_hdmi(struct work_struct *work);
2873 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2874 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2875 void r600_audio_enable(struct radeon_device *rdev,
2876 struct r600_audio_pin *pin,
2877 u8 enable_mask);
2878 void dce6_audio_enable(struct radeon_device *rdev,
2879 struct r600_audio_pin *pin,
2880 u8 enable_mask);
2881
2882 /*
2883 * R600 vram scratch functions
2884 */
2885 int r600_vram_scratch_init(struct radeon_device *rdev);
2886 void r600_vram_scratch_fini(struct radeon_device *rdev);
2887
2888 /*
2889 * r600 cs checking helper
2890 */
2891 unsigned r600_mip_minify(unsigned size, unsigned level);
2892 bool r600_fmt_is_valid_color(u32 format);
2893 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2894 int r600_fmt_get_blocksize(u32 format);
2895 int r600_fmt_get_nblocksx(u32 format, u32 w);
2896 int r600_fmt_get_nblocksy(u32 format, u32 h);
2897
2898 /*
2899 * r600 functions used by radeon_encoder.c
2900 */
2901 struct radeon_hdmi_acr {
2902 u32 clock;
2903
2904 int n_32khz;
2905 int cts_32khz;
2906
2907 int n_44_1khz;
2908 int cts_44_1khz;
2909
2910 int n_48khz;
2911 int cts_48khz;
2912
2913 };
2914
2915 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2916 u32 tiling_pipe_num,
2917 u32 max_rb_num,
2918 u32 total_max_rb_num,
2919 u32 enabled_rb_mask);
2920
2921 /*
2922 * evergreen functions used by radeon_encoder.c
2923 */
2924
2925 extern int ni_init_microcode(struct radeon_device *rdev);
2926 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2927
2928 /* radeon_acpi.c */
2929 #if defined(CONFIG_ACPI)
2930 extern int radeon_acpi_init(struct radeon_device *rdev);
2931 extern void radeon_acpi_fini(struct radeon_device *rdev);
2932 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2933 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2934 u8 perf_req, bool advertise);
2935 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2936 #else
radeon_acpi_init(struct radeon_device * rdev)2937 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)2938 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2939 #endif
2940
2941 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2942 struct radeon_cs_packet *pkt,
2943 unsigned idx);
2944 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2945 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2946 struct radeon_cs_packet *pkt);
2947 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2948 struct radeon_bo_list **cs_reloc,
2949 int nomm);
2950 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2951 uint32_t *vline_start_end,
2952 uint32_t *vline_status);
2953
2954 /* interrupt control register helpers */
2955 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2956 u32 reg, u32 mask,
2957 bool enable, const char *name,
2958 unsigned n);
2959
2960 /* Audio component binding */
2961 void radeon_audio_component_init(struct radeon_device *rdev);
2962 void radeon_audio_component_fini(struct radeon_device *rdev);
2963
2964 #include "radeon_object.h"
2965
2966 #endif
2967