1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7 */
8
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14
15 #include "msm_gpu.h"
16
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22
23 enum {
24 ADRENO_FW_PM4 = 0,
25 ADRENO_FW_SQE = 0, /* a6xx */
26 ADRENO_FW_PFP = 1,
27 ADRENO_FW_GMU = 1, /* a6xx */
28 ADRENO_FW_GPMU = 2,
29 ADRENO_FW_MAX,
30 };
31
32 /**
33 * @enum adreno_family: identify generation and possibly sub-generation
34 *
35 * In some cases there are distinct sub-generations within a major revision
36 * so it helps to be able to group the GPU devices by generation and if
37 * necessary sub-generation.
38 */
39 enum adreno_family {
40 ADRENO_2XX_GEN1, /* a20x */
41 ADRENO_2XX_GEN2, /* a22x */
42 ADRENO_3XX,
43 ADRENO_4XX,
44 ADRENO_5XX,
45 ADRENO_6XX_GEN1, /* a630 family */
46 ADRENO_6XX_GEN2, /* a640 family */
47 ADRENO_6XX_GEN3, /* a650 family */
48 ADRENO_6XX_GEN4, /* a660 family */
49 ADRENO_7XX_GEN1, /* a730 family */
50 ADRENO_7XX_GEN2, /* a740 family */
51 };
52
53 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
54 #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
55 #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
56 #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
57 #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
58
59 /* Helper for formating the chip_id in the way that userspace tools like
60 * crashdec expect.
61 */
62 #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
63 #define ADRENO_CHIPID_ARGS(_c) \
64 (((_c) >> 24) & 0xff), \
65 (((_c) >> 16) & 0xff), \
66 (((_c) >> 8) & 0xff), \
67 ((_c) & 0xff)
68
69 struct adreno_gpu_funcs {
70 struct msm_gpu_funcs base;
71 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
72 };
73
74 struct adreno_reglist {
75 u32 offset;
76 u32 value;
77 };
78
79 extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
80 extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[];
81
82 struct adreno_speedbin {
83 uint16_t fuse;
84 uint16_t speedbin;
85 };
86
87 struct adreno_info {
88 const char *machine;
89 /**
90 * @chipids: Table of matching chip-ids
91 *
92 * Terminated with 0 sentinal
93 */
94 uint32_t *chip_ids;
95 enum adreno_family family;
96 uint32_t revn;
97 const char *fw[ADRENO_FW_MAX];
98 uint32_t gmem;
99 u64 quirks;
100 struct msm_gpu *(*init)(struct drm_device *dev);
101 const char *zapfw;
102 u32 inactive_period;
103 const struct adreno_reglist *hwcg;
104 u64 address_space_size;
105 /**
106 * @speedbins: Optional table of fuse to speedbin mappings
107 *
108 * Consists of pairs of fuse, index mappings, terminated with
109 * {SHRT_MAX, 0} sentinal.
110 */
111 struct adreno_speedbin *speedbins;
112 };
113
114 #define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
115
116 /*
117 * Helper to build a speedbin table, ie. the table:
118 * fuse | speedbin
119 * -----+---------
120 * 0 | 0
121 * 169 | 1
122 * 174 | 2
123 *
124 * would be declared as:
125 *
126 * .speedbins = ADRENO_SPEEDBINS(
127 * { 0, 0 },
128 * { 169, 1 },
129 * { 174, 2 },
130 * ),
131 */
132 #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} }
133
134 struct adreno_gpu {
135 struct msm_gpu base;
136 const struct adreno_info *info;
137 uint32_t chip_id;
138 uint16_t speedbin;
139 const struct adreno_gpu_funcs *funcs;
140
141 /* interesting register offsets to dump: */
142 const unsigned int *registers;
143
144 /*
145 * Are we loading fw from legacy path? Prior to addition
146 * of gpu firmware to linux-firmware, the fw files were
147 * placed in toplevel firmware directory, following qcom's
148 * android kernel. But linux-firmware preferred they be
149 * placed in a 'qcom' subdirectory.
150 *
151 * For backwards compatibility, we try first to load from
152 * the new path, using request_firmware_direct() to avoid
153 * any potential timeout waiting for usermode helper, then
154 * fall back to the old path (with direct load). And
155 * finally fall back to request_firmware() with the new
156 * path to allow the usermode helper.
157 */
158 enum {
159 FW_LOCATION_UNKNOWN = 0,
160 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
161 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
162 FW_LOCATION_HELPER,
163 } fwloc;
164
165 /* firmware: */
166 const struct firmware *fw[ADRENO_FW_MAX];
167
168 struct {
169 u32 rgb565_predicator;
170 u32 uavflagprd_inv;
171 u32 min_acc_len;
172 u32 ubwc_mode;
173 u32 highest_bank_bit;
174 u32 amsbc;
175 } ubwc_config;
176
177 /*
178 * Register offsets are different between some GPUs.
179 * GPU specific offsets will be exported by GPU specific
180 * code (a3xx_gpu.c) and stored in this common location.
181 */
182 const unsigned int *reg_offsets;
183 bool gmu_is_wrapper;
184 };
185 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
186
187 struct adreno_ocmem {
188 struct ocmem *ocmem;
189 unsigned long base;
190 void *hdl;
191 };
192
193 /* platform config data (ie. from DT, or pdata) */
194 struct adreno_platform_config {
195 uint32_t chip_id;
196 const struct adreno_info *info;
197 };
198
199 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
200
201 #define spin_until(X) ({ \
202 int __ret = -ETIMEDOUT; \
203 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
204 do { \
205 if (X) { \
206 __ret = 0; \
207 break; \
208 } \
209 } while (time_before(jiffies, __t)); \
210 __ret; \
211 })
212
adreno_patchid(const struct adreno_gpu * gpu)213 static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
214 {
215 /* It is probably ok to assume legacy "adreno_rev" format
216 * for all a6xx devices, but probably best to limit this
217 * to older things.
218 */
219 WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
220 return gpu->chip_id & 0xff;
221 }
222
adreno_is_revn(const struct adreno_gpu * gpu,uint32_t revn)223 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
224 {
225 if (WARN_ON_ONCE(!gpu->info))
226 return false;
227 return gpu->info->revn == revn;
228 }
229
adreno_has_gmu_wrapper(const struct adreno_gpu * gpu)230 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
231 {
232 return gpu->gmu_is_wrapper;
233 }
234
adreno_is_a2xx(const struct adreno_gpu * gpu)235 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
236 {
237 if (WARN_ON_ONCE(!gpu->info))
238 return false;
239 return gpu->info->family <= ADRENO_2XX_GEN2;
240 }
241
adreno_is_a20x(const struct adreno_gpu * gpu)242 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
243 {
244 if (WARN_ON_ONCE(!gpu->info))
245 return false;
246 return gpu->info->family == ADRENO_2XX_GEN1;
247 }
248
adreno_is_a225(const struct adreno_gpu * gpu)249 static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
250 {
251 return adreno_is_revn(gpu, 225);
252 }
253
adreno_is_a305(const struct adreno_gpu * gpu)254 static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
255 {
256 return adreno_is_revn(gpu, 305);
257 }
258
adreno_is_a306(const struct adreno_gpu * gpu)259 static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
260 {
261 /* yes, 307, because a305c is 306 */
262 return adreno_is_revn(gpu, 307);
263 }
264
adreno_is_a320(const struct adreno_gpu * gpu)265 static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
266 {
267 return adreno_is_revn(gpu, 320);
268 }
269
adreno_is_a330(const struct adreno_gpu * gpu)270 static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
271 {
272 return adreno_is_revn(gpu, 330);
273 }
274
adreno_is_a330v2(const struct adreno_gpu * gpu)275 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
276 {
277 return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
278 }
279
adreno_is_a405(const struct adreno_gpu * gpu)280 static inline int adreno_is_a405(const struct adreno_gpu *gpu)
281 {
282 return adreno_is_revn(gpu, 405);
283 }
284
adreno_is_a420(const struct adreno_gpu * gpu)285 static inline int adreno_is_a420(const struct adreno_gpu *gpu)
286 {
287 return adreno_is_revn(gpu, 420);
288 }
289
adreno_is_a430(const struct adreno_gpu * gpu)290 static inline int adreno_is_a430(const struct adreno_gpu *gpu)
291 {
292 return adreno_is_revn(gpu, 430);
293 }
294
adreno_is_a506(const struct adreno_gpu * gpu)295 static inline int adreno_is_a506(const struct adreno_gpu *gpu)
296 {
297 return adreno_is_revn(gpu, 506);
298 }
299
adreno_is_a508(const struct adreno_gpu * gpu)300 static inline int adreno_is_a508(const struct adreno_gpu *gpu)
301 {
302 return adreno_is_revn(gpu, 508);
303 }
304
adreno_is_a509(const struct adreno_gpu * gpu)305 static inline int adreno_is_a509(const struct adreno_gpu *gpu)
306 {
307 return adreno_is_revn(gpu, 509);
308 }
309
adreno_is_a510(const struct adreno_gpu * gpu)310 static inline int adreno_is_a510(const struct adreno_gpu *gpu)
311 {
312 return adreno_is_revn(gpu, 510);
313 }
314
adreno_is_a512(const struct adreno_gpu * gpu)315 static inline int adreno_is_a512(const struct adreno_gpu *gpu)
316 {
317 return adreno_is_revn(gpu, 512);
318 }
319
adreno_is_a530(const struct adreno_gpu * gpu)320 static inline int adreno_is_a530(const struct adreno_gpu *gpu)
321 {
322 return adreno_is_revn(gpu, 530);
323 }
324
adreno_is_a540(const struct adreno_gpu * gpu)325 static inline int adreno_is_a540(const struct adreno_gpu *gpu)
326 {
327 return adreno_is_revn(gpu, 540);
328 }
329
adreno_is_a610(const struct adreno_gpu * gpu)330 static inline int adreno_is_a610(const struct adreno_gpu *gpu)
331 {
332 return adreno_is_revn(gpu, 610);
333 }
334
adreno_is_a618(const struct adreno_gpu * gpu)335 static inline int adreno_is_a618(const struct adreno_gpu *gpu)
336 {
337 return adreno_is_revn(gpu, 618);
338 }
339
adreno_is_a619(const struct adreno_gpu * gpu)340 static inline int adreno_is_a619(const struct adreno_gpu *gpu)
341 {
342 return adreno_is_revn(gpu, 619);
343 }
344
adreno_is_a619_holi(const struct adreno_gpu * gpu)345 static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
346 {
347 return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
348 }
349
adreno_is_a630(const struct adreno_gpu * gpu)350 static inline int adreno_is_a630(const struct adreno_gpu *gpu)
351 {
352 return adreno_is_revn(gpu, 630);
353 }
354
adreno_is_a640(const struct adreno_gpu * gpu)355 static inline int adreno_is_a640(const struct adreno_gpu *gpu)
356 {
357 return adreno_is_revn(gpu, 640);
358 }
359
adreno_is_a650(const struct adreno_gpu * gpu)360 static inline int adreno_is_a650(const struct adreno_gpu *gpu)
361 {
362 return adreno_is_revn(gpu, 650);
363 }
364
adreno_is_7c3(const struct adreno_gpu * gpu)365 static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
366 {
367 return gpu->info->chip_ids[0] == 0x06030500;
368 }
369
adreno_is_a660(const struct adreno_gpu * gpu)370 static inline int adreno_is_a660(const struct adreno_gpu *gpu)
371 {
372 return adreno_is_revn(gpu, 660);
373 }
374
adreno_is_a680(const struct adreno_gpu * gpu)375 static inline int adreno_is_a680(const struct adreno_gpu *gpu)
376 {
377 return adreno_is_revn(gpu, 680);
378 }
379
adreno_is_a690(const struct adreno_gpu * gpu)380 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
381 {
382 return gpu->info->chip_ids[0] == 0x06090000;
383 }
384
385 /* check for a615, a616, a618, a619 or any a630 derivatives */
adreno_is_a630_family(const struct adreno_gpu * gpu)386 static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
387 {
388 if (WARN_ON_ONCE(!gpu->info))
389 return false;
390 return gpu->info->family == ADRENO_6XX_GEN1;
391 }
392
adreno_is_a660_family(const struct adreno_gpu * gpu)393 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
394 {
395 if (WARN_ON_ONCE(!gpu->info))
396 return false;
397 return gpu->info->family == ADRENO_6XX_GEN4;
398 }
399
400 /* check for a650, a660, or any derivatives */
adreno_is_a650_family(const struct adreno_gpu * gpu)401 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
402 {
403 if (WARN_ON_ONCE(!gpu->info))
404 return false;
405 return gpu->info->family == ADRENO_6XX_GEN3 ||
406 gpu->info->family == ADRENO_6XX_GEN4;
407 }
408
adreno_is_a640_family(const struct adreno_gpu * gpu)409 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
410 {
411 if (WARN_ON_ONCE(!gpu->info))
412 return false;
413 return gpu->info->family == ADRENO_6XX_GEN2;
414 }
415
adreno_is_a730(struct adreno_gpu * gpu)416 static inline int adreno_is_a730(struct adreno_gpu *gpu)
417 {
418 return gpu->info->chip_ids[0] == 0x07030001;
419 }
420
adreno_is_a740(struct adreno_gpu * gpu)421 static inline int adreno_is_a740(struct adreno_gpu *gpu)
422 {
423 return gpu->info->chip_ids[0] == 0x43050a01;
424 }
425
426 /* Placeholder to make future diffs smaller */
adreno_is_a740_family(struct adreno_gpu * gpu)427 static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
428 {
429 if (WARN_ON_ONCE(!gpu->info))
430 return false;
431 return gpu->info->family == ADRENO_7XX_GEN2;
432 }
433
adreno_is_a7xx(struct adreno_gpu * gpu)434 static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
435 {
436 /* Update with non-fake (i.e. non-A702) Gen 7 GPUs */
437 return gpu->info->family == ADRENO_7XX_GEN1 ||
438 adreno_is_a740_family(gpu);
439 }
440
441 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
442 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
443 uint32_t param, uint64_t *value, uint32_t *len);
444 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
445 uint32_t param, uint64_t value, uint32_t len);
446 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
447 const char *fwname);
448 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
449 const struct firmware *fw, u64 *iova);
450 int adreno_hw_init(struct msm_gpu *gpu);
451 void adreno_recover(struct msm_gpu *gpu);
452 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
453 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
454 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
455 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
456 struct drm_printer *p);
457 #endif
458 void adreno_dump_info(struct msm_gpu *gpu);
459 void adreno_dump(struct msm_gpu *gpu);
460 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
461 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
462
463 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
464 struct adreno_ocmem *ocmem);
465 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
466
467 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
468 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
469 int nr_rings);
470 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
471 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
472
473 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
474
475 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
476 int adreno_gpu_state_put(struct msm_gpu_state *state);
477 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
478 bool *encoded);
479
480 /*
481 * Common helper function to initialize the default address space for arm-smmu
482 * attached targets
483 */
484 struct msm_gem_address_space *
485 adreno_create_address_space(struct msm_gpu *gpu,
486 struct platform_device *pdev);
487
488 struct msm_gem_address_space *
489 adreno_iommu_create_address_space(struct msm_gpu *gpu,
490 struct platform_device *pdev,
491 unsigned long quirks);
492
493 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
494 struct adreno_smmu_fault_info *info, const char *block,
495 u32 scratch[4]);
496
497 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
498
499 /*
500 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
501 * out of secure mode
502 */
503 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
504
505 /* ringbuffer helpers (the parts that are adreno specific) */
506
507 static inline void
OUT_PKT0(struct msm_ringbuffer * ring,uint16_t regindx,uint16_t cnt)508 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
509 {
510 adreno_wait_ring(ring, cnt+1);
511 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
512 }
513
514 /* no-op packet: */
515 static inline void
OUT_PKT2(struct msm_ringbuffer * ring)516 OUT_PKT2(struct msm_ringbuffer *ring)
517 {
518 adreno_wait_ring(ring, 1);
519 OUT_RING(ring, CP_TYPE2_PKT);
520 }
521
522 static inline void
OUT_PKT3(struct msm_ringbuffer * ring,uint8_t opcode,uint16_t cnt)523 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
524 {
525 adreno_wait_ring(ring, cnt+1);
526 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
527 }
528
PM4_PARITY(u32 val)529 static inline u32 PM4_PARITY(u32 val)
530 {
531 return (0x9669 >> (0xF & (val ^
532 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
533 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
534 (val >> 28)))) & 1;
535 }
536
537 /* Maximum number of values that can be executed for one opcode */
538 #define TYPE4_MAX_PAYLOAD 127
539
540 #define PKT4(_reg, _cnt) \
541 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
542 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
543
544 static inline void
OUT_PKT4(struct msm_ringbuffer * ring,uint16_t regindx,uint16_t cnt)545 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
546 {
547 adreno_wait_ring(ring, cnt + 1);
548 OUT_RING(ring, PKT4(regindx, cnt));
549 }
550
551 static inline void
OUT_PKT7(struct msm_ringbuffer * ring,uint8_t opcode,uint16_t cnt)552 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
553 {
554 adreno_wait_ring(ring, cnt + 1);
555 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
556 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
557 }
558
559 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
560 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
561 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
562 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
563 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
564
get_wptr(struct msm_ringbuffer * ring)565 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
566 {
567 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
568 }
569
570 /*
571 * Given a register and a count, return a value to program into
572 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
573 * registers starting at _reg.
574 *
575 * The register base needs to be a multiple of the length. If it is not, the
576 * hardware will quietly mask off the bits for you and shift the size. For
577 * example, if you intend the protection to start at 0x07 for a length of 4
578 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
579 * expose registers you intended to protect!
580 */
581 #define ADRENO_PROTECT_RW(_reg, _len) \
582 ((1 << 30) | (1 << 29) | \
583 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
584
585 /*
586 * Same as above, but allow reads over the range. For areas of mixed use (such
587 * as performance counters) this allows us to protect a much larger range with a
588 * single register
589 */
590 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
591 ((1 << 29) \
592 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
593
594
595 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
596 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
597 interval, timeout)
598
599 #endif /* __ADRENO_GPU_H__ */
600