1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rockchip,rk3528-cru.h> 12#include <dt-bindings/reset/rockchip,rk3528-cru.h> 13 14/ { 15 compatible = "rockchip,rk3528"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 serial5 = &uart5; 33 serial6 = &uart6; 34 serial7 = &uart7; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&cpu0>; 45 }; 46 core1 { 47 cpu = <&cpu1>; 48 }; 49 core2 { 50 cpu = <&cpu2>; 51 }; 52 core3 { 53 cpu = <&cpu3>; 54 }; 55 }; 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53"; 60 reg = <0x0>; 61 device_type = "cpu"; 62 enable-method = "psci"; 63 clocks = <&scmi_clk SCMI_CLK_CPU>; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53"; 68 reg = <0x1>; 69 device_type = "cpu"; 70 enable-method = "psci"; 71 clocks = <&scmi_clk SCMI_CLK_CPU>; 72 }; 73 74 cpu2: cpu@2 { 75 compatible = "arm,cortex-a53"; 76 reg = <0x2>; 77 device_type = "cpu"; 78 enable-method = "psci"; 79 clocks = <&scmi_clk SCMI_CLK_CPU>; 80 }; 81 82 cpu3: cpu@3 { 83 compatible = "arm,cortex-a53"; 84 reg = <0x3>; 85 device_type = "cpu"; 86 enable-method = "psci"; 87 clocks = <&scmi_clk SCMI_CLK_CPU>; 88 }; 89 }; 90 91 firmware { 92 scmi: scmi { 93 compatible = "arm,scmi-smc"; 94 arm,smc-id = <0x82000010>; 95 shmem = <&scmi_shmem>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 scmi_clk: protocol@14 { 100 reg = <0x14>; 101 #clock-cells = <1>; 102 }; 103 }; 104 }; 105 106 psci { 107 compatible = "arm,psci-1.0", "arm,psci-0.2"; 108 method = "smc"; 109 }; 110 111 reserved-memory { 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges; 115 116 scmi_shmem: shmem@10f000 { 117 compatible = "arm,scmi-shmem"; 118 reg = <0x0 0x0010f000 0x0 0x100>; 119 no-map; 120 }; 121 }; 122 123 timer { 124 compatible = "arm,armv8-timer"; 125 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 xin24m: clock-xin24m { 132 compatible = "fixed-clock"; 133 clock-frequency = <24000000>; 134 clock-output-names = "xin24m"; 135 #clock-cells = <0>; 136 }; 137 138 gmac0_clk: clock-gmac50m { 139 compatible = "fixed-clock"; 140 clock-frequency = <50000000>; 141 clock-output-names = "gmac0"; 142 #clock-cells = <0>; 143 }; 144 145 soc { 146 compatible = "simple-bus"; 147 ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 151 gic: interrupt-controller@fed01000 { 152 compatible = "arm,gic-400"; 153 reg = <0x0 0xfed01000 0 0x1000>, 154 <0x0 0xfed02000 0 0x2000>, 155 <0x0 0xfed04000 0 0x2000>, 156 <0x0 0xfed06000 0 0x2000>; 157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 158 IRQ_TYPE_LEVEL_LOW)>; 159 interrupt-controller; 160 #address-cells = <0>; 161 #interrupt-cells = <3>; 162 }; 163 164 qos_crypto_a: qos@ff200000 { 165 compatible = "rockchip,rk3528-qos", "syscon"; 166 reg = <0x0 0xff200000 0x0 0x20>; 167 }; 168 169 qos_crypto_p: qos@ff200080 { 170 compatible = "rockchip,rk3528-qos", "syscon"; 171 reg = <0x0 0xff200080 0x0 0x20>; 172 }; 173 174 qos_dcf: qos@ff200100 { 175 compatible = "rockchip,rk3528-qos", "syscon"; 176 reg = <0x0 0xff200100 0x0 0x20>; 177 }; 178 179 qos_dft2apb: qos@ff200200 { 180 compatible = "rockchip,rk3528-qos", "syscon"; 181 reg = <0x0 0xff200200 0x0 0x20>; 182 }; 183 184 qos_dma2ddr: qos@ff200280 { 185 compatible = "rockchip,rk3528-qos", "syscon"; 186 reg = <0x0 0xff200280 0x0 0x20>; 187 }; 188 189 qos_dmac: qos@ff200300 { 190 compatible = "rockchip,rk3528-qos", "syscon"; 191 reg = <0x0 0xff200300 0x0 0x20>; 192 }; 193 194 qos_keyreader: qos@ff200380 { 195 compatible = "rockchip,rk3528-qos", "syscon"; 196 reg = <0x0 0xff200380 0x0 0x20>; 197 }; 198 199 qos_cpu: qos@ff210000 { 200 compatible = "rockchip,rk3528-qos", "syscon"; 201 reg = <0x0 0xff210000 0x0 0x20>; 202 }; 203 204 qos_debug: qos@ff210080 { 205 compatible = "rockchip,rk3528-qos", "syscon"; 206 reg = <0x0 0xff210080 0x0 0x20>; 207 }; 208 209 qos_gpu_m0: qos@ff220000 { 210 compatible = "rockchip,rk3528-qos", "syscon"; 211 reg = <0x0 0xff220000 0x0 0x20>; 212 }; 213 214 qos_gpu_m1: qos@ff220080 { 215 compatible = "rockchip,rk3528-qos", "syscon"; 216 reg = <0x0 0xff220080 0x0 0x20>; 217 }; 218 219 qos_pmu_mcu: qos@ff240000 { 220 compatible = "rockchip,rk3528-qos", "syscon"; 221 reg = <0x0 0xff240000 0x0 0x20>; 222 }; 223 224 qos_rkvdec: qos@ff250000 { 225 compatible = "rockchip,rk3528-qos", "syscon"; 226 reg = <0x0 0xff250000 0x0 0x20>; 227 }; 228 229 qos_rkvenc: qos@ff260000 { 230 compatible = "rockchip,rk3528-qos", "syscon"; 231 reg = <0x0 0xff260000 0x0 0x20>; 232 }; 233 234 qos_gmac0: qos@ff270000 { 235 compatible = "rockchip,rk3528-qos", "syscon"; 236 reg = <0x0 0xff270000 0x0 0x20>; 237 }; 238 239 qos_hdcp: qos@ff270080 { 240 compatible = "rockchip,rk3528-qos", "syscon"; 241 reg = <0x0 0xff270080 0x0 0x20>; 242 }; 243 244 qos_jpegdec: qos@ff270100 { 245 compatible = "rockchip,rk3528-qos", "syscon"; 246 reg = <0x0 0xff270100 0x0 0x20>; 247 }; 248 249 qos_rga2_m0ro: qos@ff270200 { 250 compatible = "rockchip,rk3528-qos", "syscon"; 251 reg = <0x0 0xff270200 0x0 0x20>; 252 }; 253 254 qos_rga2_m0wo: qos@ff270280 { 255 compatible = "rockchip,rk3528-qos", "syscon"; 256 reg = <0x0 0xff270280 0x0 0x20>; 257 }; 258 259 qos_sdmmc0: qos@ff270300 { 260 compatible = "rockchip,rk3528-qos", "syscon"; 261 reg = <0x0 0xff270300 0x0 0x20>; 262 }; 263 264 qos_usb2host: qos@ff270380 { 265 compatible = "rockchip,rk3528-qos", "syscon"; 266 reg = <0x0 0xff270380 0x0 0x20>; 267 }; 268 269 qos_vdpp: qos@ff270480 { 270 compatible = "rockchip,rk3528-qos", "syscon"; 271 reg = <0x0 0xff270480 0x0 0x20>; 272 }; 273 274 qos_vop: qos@ff270500 { 275 compatible = "rockchip,rk3528-qos", "syscon"; 276 reg = <0x0 0xff270500 0x0 0x20>; 277 }; 278 279 qos_emmc: qos@ff280000 { 280 compatible = "rockchip,rk3528-qos", "syscon"; 281 reg = <0x0 0xff280000 0x0 0x20>; 282 }; 283 284 qos_fspi: qos@ff280080 { 285 compatible = "rockchip,rk3528-qos", "syscon"; 286 reg = <0x0 0xff280080 0x0 0x20>; 287 }; 288 289 qos_gmac1: qos@ff280100 { 290 compatible = "rockchip,rk3528-qos", "syscon"; 291 reg = <0x0 0xff280100 0x0 0x20>; 292 }; 293 294 qos_pcie: qos@ff280180 { 295 compatible = "rockchip,rk3528-qos", "syscon"; 296 reg = <0x0 0xff280180 0x0 0x20>; 297 }; 298 299 qos_sdio0: qos@ff280200 { 300 compatible = "rockchip,rk3528-qos", "syscon"; 301 reg = <0x0 0xff280200 0x0 0x20>; 302 }; 303 304 qos_sdio1: qos@ff280280 { 305 compatible = "rockchip,rk3528-qos", "syscon"; 306 reg = <0x0 0xff280280 0x0 0x20>; 307 }; 308 309 qos_tsp: qos@ff280300 { 310 compatible = "rockchip,rk3528-qos", "syscon"; 311 reg = <0x0 0xff280300 0x0 0x20>; 312 }; 313 314 qos_usb3otg: qos@ff280380 { 315 compatible = "rockchip,rk3528-qos", "syscon"; 316 reg = <0x0 0xff280380 0x0 0x20>; 317 }; 318 319 qos_vpu: qos@ff280400 { 320 compatible = "rockchip,rk3528-qos", "syscon"; 321 reg = <0x0 0xff280400 0x0 0x20>; 322 }; 323 324 cru: clock-controller@ff4a0000 { 325 compatible = "rockchip,rk3528-cru"; 326 reg = <0x0 0xff4a0000 0x0 0x30000>; 327 assigned-clocks = 328 <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, 329 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 330 <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, 331 <&cru CLK_MATRIX_500M_SRC>, 332 <&cru CLK_MATRIX_50M_SRC>, 333 <&cru CLK_MATRIX_100M_SRC>, 334 <&cru CLK_MATRIX_150M_SRC>, 335 <&cru CLK_MATRIX_200M_SRC>, 336 <&cru CLK_MATRIX_300M_SRC>, 337 <&cru CLK_MATRIX_339M_SRC>, 338 <&cru CLK_MATRIX_400M_SRC>, 339 <&cru CLK_MATRIX_600M_SRC>, 340 <&cru CLK_PPLL_50M_MATRIX>, 341 <&cru CLK_PPLL_100M_MATRIX>, 342 <&cru CLK_PPLL_125M_MATRIX>, 343 <&cru ACLK_BUS_VOPGL_ROOT>; 344 assigned-clock-rates = 345 <32768>, <1188000000>, 346 <1000000000>, <996000000>, 347 <408000000>, <250000000>, 348 <500000000>, 349 <50000000>, 350 <100000000>, 351 <150000000>, 352 <200000000>, 353 <300000000>, 354 <340000000>, 355 <400000000>, 356 <600000000>, 357 <50000000>, 358 <100000000>, 359 <125000000>, 360 <500000000>; 361 clocks = <&xin24m>, <&gmac0_clk>; 362 clock-names = "xin24m", "gmac0"; 363 #clock-cells = <1>; 364 #reset-cells = <1>; 365 }; 366 367 ioc_grf: syscon@ff540000 { 368 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 369 reg = <0x0 0xff540000 0x0 0x40000>; 370 }; 371 372 uart0: serial@ff9f0000 { 373 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 374 reg = <0x0 0xff9f0000 0x0 0x100>; 375 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 376 clock-names = "baudclk", "apb_pclk"; 377 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 378 reg-io-width = <4>; 379 reg-shift = <2>; 380 status = "disabled"; 381 }; 382 383 uart1: serial@ff9f8000 { 384 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 385 reg = <0x0 0xff9f8000 0x0 0x100>; 386 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 387 clock-names = "baudclk", "apb_pclk"; 388 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 389 reg-io-width = <4>; 390 reg-shift = <2>; 391 status = "disabled"; 392 }; 393 394 uart2: serial@ffa00000 { 395 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 396 reg = <0x0 0xffa00000 0x0 0x100>; 397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 398 clock-names = "baudclk", "apb_pclk"; 399 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 400 reg-io-width = <4>; 401 reg-shift = <2>; 402 status = "disabled"; 403 }; 404 405 uart3: serial@ffa08000 { 406 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 407 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 408 clock-names = "baudclk", "apb_pclk"; 409 reg = <0x0 0xffa08000 0x0 0x100>; 410 reg-io-width = <4>; 411 reg-shift = <2>; 412 status = "disabled"; 413 }; 414 415 uart4: serial@ffa10000 { 416 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 417 reg = <0x0 0xffa10000 0x0 0x100>; 418 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 419 clock-names = "baudclk", "apb_pclk"; 420 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 421 reg-io-width = <4>; 422 reg-shift = <2>; 423 status = "disabled"; 424 }; 425 426 uart5: serial@ffa18000 { 427 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 428 reg = <0x0 0xffa18000 0x0 0x100>; 429 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 430 clock-names = "baudclk", "apb_pclk"; 431 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 432 reg-io-width = <4>; 433 reg-shift = <2>; 434 status = "disabled"; 435 }; 436 437 uart6: serial@ffa20000 { 438 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 439 reg = <0x0 0xffa20000 0x0 0x100>; 440 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 441 clock-names = "baudclk", "apb_pclk"; 442 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 443 reg-io-width = <4>; 444 reg-shift = <2>; 445 status = "disabled"; 446 }; 447 448 uart7: serial@ffa28000 { 449 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 450 reg = <0x0 0xffa28000 0x0 0x100>; 451 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 452 clock-names = "baudclk", "apb_pclk"; 453 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 454 reg-io-width = <4>; 455 reg-shift = <2>; 456 status = "disabled"; 457 }; 458 459 saradc: adc@ffae0000 { 460 compatible = "rockchip,rk3528-saradc"; 461 reg = <0x0 0xffae0000 0x0 0x10000>; 462 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 463 clock-names = "saradc", "apb_pclk"; 464 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 465 resets = <&cru SRST_P_SARADC>; 466 reset-names = "saradc-apb"; 467 #io-channel-cells = <1>; 468 status = "disabled"; 469 }; 470 471 sdhci: mmc@ffbf0000 { 472 compatible = "rockchip,rk3528-dwcmshc", 473 "rockchip,rk3588-dwcmshc"; 474 reg = <0x0 0xffbf0000 0x0 0x10000>; 475 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, 476 <&cru CCLK_SRC_EMMC>; 477 assigned-clock-rates = <200000000>, <24000000>, 478 <200000000>; 479 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 480 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 481 <&cru TCLK_EMMC>; 482 clock-names = "core", "bus", "axi", "block", "timer"; 483 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 484 max-frequency = <200000000>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, 487 <&emmc_strb>; 488 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 489 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 490 <&cru SRST_T_EMMC>; 491 reset-names = "core", "bus", "axi", "block", "timer"; 492 status = "disabled"; 493 }; 494 495 pinctrl: pinctrl { 496 compatible = "rockchip,rk3528-pinctrl"; 497 rockchip,grf = <&ioc_grf>; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 502 gpio0: gpio@ff610000 { 503 compatible = "rockchip,gpio-bank"; 504 reg = <0x0 0xff610000 0x0 0x200>; 505 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 506 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 507 gpio-controller; 508 #gpio-cells = <2>; 509 gpio-ranges = <&pinctrl 0 0 32>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 }; 513 514 gpio1: gpio@ffaf0000 { 515 compatible = "rockchip,gpio-bank"; 516 reg = <0x0 0xffaf0000 0x0 0x200>; 517 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 518 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 gpio-ranges = <&pinctrl 0 32 32>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 }; 525 526 gpio2: gpio@ffb00000 { 527 compatible = "rockchip,gpio-bank"; 528 reg = <0x0 0xffb00000 0x0 0x200>; 529 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 530 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 gpio-ranges = <&pinctrl 0 64 32>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 538 gpio3: gpio@ffb10000 { 539 compatible = "rockchip,gpio-bank"; 540 reg = <0x0 0xffb10000 0x0 0x200>; 541 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 542 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 543 gpio-controller; 544 #gpio-cells = <2>; 545 gpio-ranges = <&pinctrl 0 96 32>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 550 gpio4: gpio@ffb20000 { 551 compatible = "rockchip,gpio-bank"; 552 reg = <0x0 0xffb20000 0x0 0x200>; 553 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 554 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 555 gpio-controller; 556 #gpio-cells = <2>; 557 gpio-ranges = <&pinctrl 0 128 32>; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 }; 561 }; 562 }; 563}; 564 565#include "rk3528-pinctrl.dtsi" 566