1 /*
2 * qemu user cpu loop
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu.h"
22 #include "user-internals.h"
23 #include "elf.h"
24 #include "user/cpu_loop.h"
25 #include "signal-common.h"
26 #include "semihosting/common-semi.h"
27 #include "exec/page-protection.h"
28 #include "exec/mmap-lock.h"
29 #include "user/page-protection.h"
30 #include "target/arm/syndrome.h"
31
32 #define get_user_code_u32(x, gaddr, env) \
33 ({ abi_long __r = get_user_u32((x), (gaddr)); \
34 if (!__r && bswap_code(arm_sctlr_b(env))) { \
35 (x) = bswap32(x); \
36 } \
37 __r; \
38 })
39
40 /*
41 * Note that if we need to do data accesses here, they should do a
42 * bswap if arm_cpu_bswap_data() returns true.
43 */
44
45 /*
46 * Similar to code in accel/tcg/user-exec.c, but outside the execution loop.
47 * Must be called with mmap_lock.
48 * We get the PC of the entry address - which is as good as anything,
49 * on a real kernel what you get depends on which mode it uses.
50 */
atomic_mmu_lookup(CPUArchState * env,uint32_t addr,int size)51 static void *atomic_mmu_lookup(CPUArchState *env, uint32_t addr, int size)
52 {
53 int need_flags = PAGE_READ | PAGE_WRITE_ORG | PAGE_VALID;
54 int page_flags;
55
56 /* Enforce guest required alignment. */
57 if (unlikely(addr & (size - 1))) {
58 force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr);
59 return NULL;
60 }
61
62 page_flags = page_get_flags(addr);
63 if (unlikely((page_flags & need_flags) != need_flags)) {
64 force_sig_fault(TARGET_SIGSEGV,
65 page_flags & PAGE_VALID ?
66 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
67 return NULL;
68 }
69
70 return g2h(env_cpu(env), addr);
71 }
72
73 /*
74 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
75 * Input:
76 * r0 = oldval
77 * r1 = newval
78 * r2 = pointer to target value
79 *
80 * Output:
81 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
82 * C set if *ptr was changed, clear if no exchange happened
83 */
arm_kernel_cmpxchg32_helper(CPUARMState * env)84 static void arm_kernel_cmpxchg32_helper(CPUARMState *env)
85 {
86 uint32_t oldval, newval, val, addr, cpsr, *host_addr;
87
88 /* Swap if host != guest endianness, for the host cmpxchg below */
89 oldval = tswap32(env->regs[0]);
90 newval = tswap32(env->regs[1]);
91 addr = env->regs[2];
92
93 mmap_lock();
94 host_addr = atomic_mmu_lookup(env, addr, 4);
95 if (!host_addr) {
96 mmap_unlock();
97 return;
98 }
99
100 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
101 mmap_unlock();
102
103 cpsr = (val == oldval) * CPSR_C;
104 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
105 env->regs[0] = cpsr ? 0 : -1;
106 }
107
108 /*
109 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
110 * Input:
111 * r0 = pointer to oldval
112 * r1 = pointer to newval
113 * r2 = pointer to target value
114 *
115 * Output:
116 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
117 * C set if *ptr was changed, clear if no exchange happened
118 *
119 * Note segv's in kernel helpers are a bit tricky, we can set the
120 * data address sensibly but the PC address is just the entry point.
121 */
arm_kernel_cmpxchg64_helper(CPUARMState * env)122 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
123 {
124 uint64_t oldval, newval, val;
125 uint32_t addr, cpsr;
126 uint64_t *host_addr;
127
128 addr = env->regs[0];
129 if (get_user_u64(oldval, addr)) {
130 goto segv;
131 }
132
133 addr = env->regs[1];
134 if (get_user_u64(newval, addr)) {
135 goto segv;
136 }
137
138 mmap_lock();
139 addr = env->regs[2];
140 host_addr = atomic_mmu_lookup(env, addr, 8);
141 if (!host_addr) {
142 mmap_unlock();
143 return;
144 }
145
146 /* Swap if host != guest endianness, for the host cmpxchg below */
147 oldval = tswap64(oldval);
148 newval = tswap64(newval);
149
150 #ifdef CONFIG_ATOMIC64
151 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
152 cpsr = (val == oldval) * CPSR_C;
153 #else
154 /*
155 * This only works between threads, not between processes, but since
156 * the host has no 64-bit cmpxchg, it is the best that we can do.
157 */
158 start_exclusive();
159 val = *host_addr;
160 if (val == oldval) {
161 *host_addr = newval;
162 cpsr = CPSR_C;
163 } else {
164 cpsr = 0;
165 }
166 end_exclusive();
167 #endif
168 mmap_unlock();
169
170 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
171 env->regs[0] = cpsr ? 0 : -1;
172 return;
173
174 segv:
175 force_sig_fault(TARGET_SIGSEGV,
176 page_get_flags(addr) & PAGE_VALID ?
177 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
178 }
179
180 /* Handle a jump to the kernel code page. */
181 static int
do_kernel_trap(CPUARMState * env)182 do_kernel_trap(CPUARMState *env)
183 {
184 uint32_t addr;
185
186 switch (env->regs[15]) {
187 case 0xffff0fa0: /* __kernel_memory_barrier */
188 smp_mb();
189 break;
190 case 0xffff0fc0: /* __kernel_cmpxchg */
191 arm_kernel_cmpxchg32_helper(env);
192 break;
193 case 0xffff0fe0: /* __kernel_get_tls */
194 env->regs[0] = cpu_get_tls(env);
195 break;
196 case 0xffff0f60: /* __kernel_cmpxchg64 */
197 arm_kernel_cmpxchg64_helper(env);
198 break;
199
200 default:
201 return 1;
202 }
203 /* Jump back to the caller. */
204 addr = env->regs[14];
205 if (addr & 1) {
206 env->thumb = true;
207 addr &= ~1;
208 }
209 env->regs[15] = addr;
210
211 return 0;
212 }
213
insn_is_linux_bkpt(uint32_t opcode,bool is_thumb)214 static bool insn_is_linux_bkpt(uint32_t opcode, bool is_thumb)
215 {
216 /*
217 * Return true if this insn is one of the three magic UDF insns
218 * which the kernel treats as breakpoint insns.
219 */
220 if (!is_thumb) {
221 return (opcode & 0x0fffffff) == 0x07f001f0;
222 } else {
223 /*
224 * Note that we get the two halves of the 32-bit T32 insn
225 * in the opposite order to the value the kernel uses in
226 * its undef_hook struct.
227 */
228 return ((opcode & 0xffff) == 0xde01) || (opcode == 0xa000f7f0);
229 }
230 }
231
emulate_arm_fpa11(CPUARMState * env,uint32_t opcode)232 static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode)
233 {
234 TaskState *ts = get_task_state(env_cpu(env));
235 int rc = EmulateAll(opcode, &ts->fpa, env);
236 int raise, enabled;
237
238 if (rc == 0) {
239 /* Illegal instruction */
240 return false;
241 }
242 if (rc > 0) {
243 /* Everything ok. */
244 env->regs[15] += 4;
245 return true;
246 }
247
248 /* FP exception */
249 rc = -rc;
250 raise = 0;
251
252 /* Translate softfloat flags to FPSR flags */
253 if (rc & float_flag_invalid) {
254 raise |= BIT_IOC;
255 }
256 if (rc & float_flag_divbyzero) {
257 raise |= BIT_DZC;
258 }
259 if (rc & float_flag_overflow) {
260 raise |= BIT_OFC;
261 }
262 if (rc & float_flag_underflow) {
263 raise |= BIT_UFC;
264 }
265 if (rc & float_flag_inexact) {
266 raise |= BIT_IXC;
267 }
268
269 /* Accumulate unenabled exceptions */
270 enabled = ts->fpa.fpsr >> 16;
271 ts->fpa.fpsr |= raise & ~enabled;
272
273 if (raise & enabled) {
274 /*
275 * The kernel's nwfpe emulator does not pass a real si_code.
276 * It merely uses send_sig(SIGFPE, current, 1), which results in
277 * __send_signal() filling out SI_KERNEL with pid and uid 0 (under
278 * the "SEND_SIG_PRIV" case). That's what our force_sig() does.
279 */
280 force_sig(TARGET_SIGFPE);
281 } else {
282 env->regs[15] += 4;
283 }
284 return true;
285 }
286
cpu_loop(CPUARMState * env)287 void cpu_loop(CPUARMState *env)
288 {
289 CPUState *cs = env_cpu(env);
290 int trapnr, si_signo, si_code;
291 unsigned int n, insn;
292 abi_ulong ret;
293
294 for(;;) {
295 cpu_exec_start(cs);
296 trapnr = cpu_exec(cs);
297 cpu_exec_end(cs);
298 process_queued_cpu_work(cs);
299
300 switch(trapnr) {
301 case EXCP_UDEF:
302 case EXCP_NOCP:
303 case EXCP_INVSTATE:
304 {
305 uint32_t opcode;
306
307 /* we handle the FPU emulation here, as Linux */
308 /* we get the opcode */
309 /* FIXME - what to do if get_user() fails? */
310 get_user_code_u32(opcode, env->regs[15], env);
311
312 /*
313 * The Linux kernel treats some UDF patterns specially
314 * to use as breakpoints (instead of the architectural
315 * bkpt insn). These should trigger a SIGTRAP rather
316 * than SIGILL.
317 */
318 if (insn_is_linux_bkpt(opcode, env->thumb)) {
319 goto excp_debug;
320 }
321
322 if (!env->thumb && emulate_arm_fpa11(env, opcode)) {
323 break;
324 }
325
326 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN,
327 env->regs[15]);
328 }
329 break;
330 case EXCP_SWI:
331 {
332 env->eabi = true;
333 /* system call */
334 if (env->thumb) {
335 /* Thumb is always EABI style with syscall number in r7 */
336 n = env->regs[7];
337 } else {
338 /*
339 * Equivalent of kernel CONFIG_OABI_COMPAT: read the
340 * Arm SVC insn to extract the immediate, which is the
341 * syscall number in OABI.
342 */
343 /* FIXME - what to do if get_user() fails? */
344 get_user_code_u32(insn, env->regs[15] - 4, env);
345 n = insn & 0xffffff;
346 if (n == 0) {
347 /* zero immediate: EABI, syscall number in r7 */
348 n = env->regs[7];
349 } else {
350 /*
351 * This XOR matches the kernel code: an immediate
352 * in the valid range (0x900000 .. 0x9fffff) is
353 * converted into the correct EABI-style syscall
354 * number; invalid immediates end up as values
355 * > 0xfffff and are handled below as out-of-range.
356 */
357 n ^= ARM_SYSCALL_BASE;
358 env->eabi = false;
359 }
360 }
361
362 if (n > ARM_NR_BASE) {
363 switch (n) {
364 case ARM_NR_cacheflush:
365 /* nop */
366 break;
367 case ARM_NR_set_tls:
368 cpu_set_tls(env, env->regs[0]);
369 env->regs[0] = 0;
370 break;
371 case ARM_NR_breakpoint:
372 env->regs[15] -= env->thumb ? 2 : 4;
373 goto excp_debug;
374 case ARM_NR_get_tls:
375 env->regs[0] = cpu_get_tls(env);
376 break;
377 default:
378 if (n < 0xf0800) {
379 /*
380 * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
381 * 0x9f07ff in OABI numbering) are defined
382 * to return -ENOSYS rather than raising
383 * SIGILL. Note that we have already
384 * removed the 0x900000 prefix.
385 */
386 qemu_log_mask(LOG_UNIMP,
387 "qemu: Unsupported ARM syscall: 0x%x\n",
388 n);
389 env->regs[0] = -TARGET_ENOSYS;
390 } else {
391 /*
392 * Otherwise SIGILL. This includes any SWI with
393 * immediate not originally 0x9fxxxx, because
394 * of the earlier XOR.
395 * Like the real kernel, we report the addr of the
396 * SWI in the siginfo si_addr but leave the PC
397 * pointing at the insn after the SWI.
398 */
399 abi_ulong faultaddr = env->regs[15];
400 faultaddr -= env->thumb ? 2 : 4;
401 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP,
402 faultaddr);
403 }
404 break;
405 }
406 } else {
407 ret = do_syscall(env,
408 n,
409 env->regs[0],
410 env->regs[1],
411 env->regs[2],
412 env->regs[3],
413 env->regs[4],
414 env->regs[5],
415 0, 0);
416 if (ret == -QEMU_ERESTARTSYS) {
417 env->regs[15] -= env->thumb ? 2 : 4;
418 } else if (ret != -QEMU_ESIGRETURN) {
419 env->regs[0] = ret;
420 }
421 }
422 }
423 break;
424 case EXCP_SEMIHOST:
425 do_common_semihosting(cs);
426 env->regs[15] += env->thumb ? 2 : 4;
427 break;
428 case EXCP_INTERRUPT:
429 /* just indicate that signals should be handled asap */
430 break;
431 case EXCP_PREFETCH_ABORT:
432 case EXCP_DATA_ABORT:
433 /* For user-only we don't set TTBCR_EAE, so look at the FSR. */
434 switch (env->exception.fsr & 0x1f) {
435 case 0x1: /* Alignment */
436 si_signo = TARGET_SIGBUS;
437 si_code = TARGET_BUS_ADRALN;
438 break;
439 case 0x3: /* Access flag fault, level 1 */
440 case 0x6: /* Access flag fault, level 2 */
441 case 0x9: /* Domain fault, level 1 */
442 case 0xb: /* Domain fault, level 2 */
443 case 0xd: /* Permission fault, level 1 */
444 case 0xf: /* Permission fault, level 2 */
445 si_signo = TARGET_SIGSEGV;
446 si_code = TARGET_SEGV_ACCERR;
447 break;
448 case 0x5: /* Translation fault, level 1 */
449 case 0x7: /* Translation fault, level 2 */
450 si_signo = TARGET_SIGSEGV;
451 si_code = TARGET_SEGV_MAPERR;
452 break;
453 default:
454 g_assert_not_reached();
455 }
456 force_sig_fault(si_signo, si_code, env->exception.vaddress);
457 break;
458 case EXCP_DEBUG:
459 case EXCP_BKPT:
460 excp_debug:
461 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[15]);
462 break;
463 case EXCP_KERNEL_TRAP:
464 if (do_kernel_trap(env))
465 goto error;
466 break;
467 case EXCP_YIELD:
468 /* nothing to do here for user-mode, just resume guest code */
469 break;
470 case EXCP_ATOMIC:
471 cpu_exec_step_atomic(cs);
472 break;
473 default:
474 error:
475 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
476 abort();
477 }
478 process_pending_signals(env);
479 }
480 }
481
target_cpu_copy_regs(CPUArchState * env,target_pt_regs * regs)482 void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
483 {
484 CPUState *cpu = env_cpu(env);
485 TaskState *ts = get_task_state(cpu);
486 struct image_info *info = ts->info;
487 int i;
488
489 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
490 CPSRWriteByInstr);
491 for(i = 0; i < 16; i++) {
492 env->regs[i] = regs->uregs[i];
493 }
494 #if TARGET_BIG_ENDIAN
495 /* Enable BE8. */
496 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
497 && (info->elf_flags & EF_ARM_BE8)) {
498 env->uncached_cpsr |= CPSR_E;
499 env->cp15.sctlr_el[1] |= SCTLR_E0E;
500 } else {
501 env->cp15.sctlr_el[1] |= SCTLR_B;
502 }
503 arm_rebuild_hflags(env);
504 #endif
505
506 ts->stack_base = info->start_stack;
507 ts->heap_base = info->brk;
508 /* This will be filled in on the first SYS_HEAPINFO call. */
509 ts->heap_limit = 0;
510 }
511