1 /*
2 * QEMU 8259 interrupt controller emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/intc/i8259.h"
27 #include "hw/irq.h"
28 #include "hw/isa/isa.h"
29 #include "qemu/timer.h"
30 #include "qemu/log.h"
31 #include "hw/isa/i8259_internal.h"
32 #include "trace.h"
33 #include "qom/object.h"
34
35 /*#define DEBUG_IRQ_LATENCY*/
36
37 #define TYPE_I8259 "isa-i8259"
38 typedef struct PICClass PICClass;
39 DECLARE_CLASS_CHECKERS(PICClass, PIC,
40 TYPE_I8259)
41
42 /**
43 * PICClass:
44 * @parent_realize: The parent's realizefn.
45 */
46 struct PICClass {
47 PICCommonClass parent_class;
48
49 DeviceRealize parent_realize;
50 };
51
52 #ifdef DEBUG_IRQ_LATENCY
53 static int64_t irq_time[16];
54 #endif
55 PICCommonState *isa_pic;
56 static PICCommonState *slave_pic;
57
58 /* return the highest priority found in mask (highest = smallest
59 number). Return 8 if no irq */
get_priority(PICCommonState * s,int mask)60 static int get_priority(PICCommonState *s, int mask)
61 {
62 int priority;
63
64 if (mask == 0) {
65 return 8;
66 }
67 priority = 0;
68 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) {
69 priority++;
70 }
71 return priority;
72 }
73
74 /* return the pic wanted interrupt. return -1 if none */
pic_get_irq(PICCommonState * s)75 static int pic_get_irq(PICCommonState *s)
76 {
77 int mask, cur_priority, priority;
78
79 mask = s->irr & ~s->imr;
80 priority = get_priority(s, mask);
81 if (priority == 8) {
82 return -1;
83 }
84 /* compute current priority. If special fully nested mode on the
85 master, the IRQ coming from the slave is not taken into account
86 for the priority computation. */
87 mask = s->isr;
88 if (s->special_mask) {
89 mask &= ~s->imr;
90 }
91 if (s->special_fully_nested_mode && s->master) {
92 mask &= ~(1 << 2);
93 }
94 cur_priority = get_priority(s, mask);
95 if (priority < cur_priority) {
96 /* higher priority found: an irq should be generated */
97 return (priority + s->priority_add) & 7;
98 } else {
99 return -1;
100 }
101 }
102
103 /* Update INT output. Must be called every time the output may have changed. */
pic_update_irq(PICCommonState * s)104 static void pic_update_irq(PICCommonState *s)
105 {
106 int irq;
107
108 irq = pic_get_irq(s);
109 if (irq >= 0) {
110 trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add);
111 qemu_irq_raise(s->int_out[0]);
112 } else {
113 qemu_irq_lower(s->int_out[0]);
114 }
115 }
116
117 /* set irq level. If an edge is detected, then the IRR is set to 1 */
pic_set_irq(void * opaque,int irq,int level)118 static void pic_set_irq(void *opaque, int irq, int level)
119 {
120 PICCommonState *s = opaque;
121 int mask = 1 << irq;
122 int irq_index = s->master ? irq : irq + 8;
123
124 trace_pic_set_irq(s->master, irq, level);
125 pic_stat_update_irq(irq_index, level);
126
127 #ifdef DEBUG_IRQ_LATENCY
128 if (level) {
129 irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
130 }
131 #endif
132
133 if (s->ltim || (s->elcr & mask)) {
134 /* level triggered */
135 if (level) {
136 s->irr |= mask;
137 s->last_irr |= mask;
138 } else {
139 s->irr &= ~mask;
140 s->last_irr &= ~mask;
141 }
142 } else {
143 /* edge triggered */
144 if (level) {
145 if ((s->last_irr & mask) == 0) {
146 s->irr |= mask;
147 }
148 s->last_irr |= mask;
149 } else {
150 s->last_irr &= ~mask;
151 }
152 }
153 pic_update_irq(s);
154 }
155
156 /* acknowledge interrupt 'irq' */
pic_intack(PICCommonState * s,int irq)157 static void pic_intack(PICCommonState *s, int irq)
158 {
159 if (s->auto_eoi) {
160 if (s->rotate_on_auto_eoi) {
161 s->priority_add = (irq + 1) & 7;
162 }
163 } else {
164 s->isr |= (1 << irq);
165 }
166 /* We don't clear a level sensitive interrupt here */
167 if (!s->ltim && !(s->elcr & (1 << irq))) {
168 s->irr &= ~(1 << irq);
169 }
170 pic_update_irq(s);
171 }
172
pic_read_irq(PICCommonState * s)173 int pic_read_irq(PICCommonState *s)
174 {
175 int irq, intno;
176
177 irq = pic_get_irq(s);
178 if (irq >= 0) {
179 int irq2;
180
181 if (irq == 2) {
182 irq2 = pic_get_irq(slave_pic);
183 if (irq2 >= 0) {
184 pic_intack(slave_pic, irq2);
185 } else {
186 /* spurious IRQ on slave controller */
187 irq2 = 7;
188 }
189 intno = slave_pic->irq_base + irq2;
190 pic_intack(s, irq);
191 irq = irq2 + 8;
192 } else {
193 intno = s->irq_base + irq;
194 pic_intack(s, irq);
195 }
196 } else {
197 /* spurious IRQ on host controller */
198 irq = 7;
199 intno = s->irq_base + irq;
200 }
201
202 #ifdef DEBUG_IRQ_LATENCY
203 printf("IRQ%d latency=%0.3fus\n",
204 irq,
205 (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
206 irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND);
207 #endif
208
209 trace_pic_interrupt(irq, intno);
210 return intno;
211 }
212
pic_init_reset(PICCommonState * s)213 static void pic_init_reset(PICCommonState *s)
214 {
215 pic_reset_common(s);
216 pic_update_irq(s);
217 }
218
pic_reset(DeviceState * dev)219 static void pic_reset(DeviceState *dev)
220 {
221 PICCommonState *s = PIC_COMMON(dev);
222
223 s->elcr = 0;
224 s->ltim = 0;
225 pic_init_reset(s);
226 }
227
pic_ioport_write(void * opaque,hwaddr addr64,uint64_t val64,unsigned size)228 static void pic_ioport_write(void *opaque, hwaddr addr64,
229 uint64_t val64, unsigned size)
230 {
231 PICCommonState *s = opaque;
232 uint32_t addr = addr64;
233 uint32_t val = val64;
234 int priority, cmd, irq;
235
236 trace_pic_ioport_write(s->master, addr, val);
237
238 if (addr == 0) {
239 if (val & 0x10) {
240 pic_init_reset(s);
241 s->init_state = 1;
242 s->init4 = val & 1;
243 s->single_mode = val & 2;
244 s->ltim = val & 8;
245 } else if (val & 0x08) {
246 if (val & 0x04) {
247 s->poll = 1;
248 }
249 if (val & 0x02) {
250 s->read_reg_select = val & 1;
251 }
252 if (val & 0x40) {
253 s->special_mask = (val >> 5) & 1;
254 }
255 } else {
256 cmd = val >> 5;
257 switch (cmd) {
258 case 0:
259 case 4:
260 s->rotate_on_auto_eoi = cmd >> 2;
261 break;
262 case 1: /* end of interrupt */
263 case 5:
264 priority = get_priority(s, s->isr);
265 if (priority != 8) {
266 irq = (priority + s->priority_add) & 7;
267 s->isr &= ~(1 << irq);
268 if (cmd == 5) {
269 s->priority_add = (irq + 1) & 7;
270 }
271 pic_update_irq(s);
272 }
273 break;
274 case 3:
275 irq = val & 7;
276 s->isr &= ~(1 << irq);
277 pic_update_irq(s);
278 break;
279 case 6:
280 s->priority_add = (val + 1) & 7;
281 pic_update_irq(s);
282 break;
283 case 7:
284 irq = val & 7;
285 s->isr &= ~(1 << irq);
286 s->priority_add = (irq + 1) & 7;
287 pic_update_irq(s);
288 break;
289 default:
290 /* no operation */
291 break;
292 }
293 }
294 } else {
295 switch (s->init_state) {
296 case 0:
297 /* normal mode */
298 s->imr = val;
299 pic_update_irq(s);
300 break;
301 case 1:
302 s->irq_base = val & 0xf8;
303 s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
304 break;
305 case 2:
306 if (s->init4) {
307 s->init_state = 3;
308 } else {
309 s->init_state = 0;
310 }
311 break;
312 case 3:
313 s->special_fully_nested_mode = (val >> 4) & 1;
314 s->auto_eoi = (val >> 1) & 1;
315 s->init_state = 0;
316 break;
317 }
318 }
319 }
320
pic_ioport_read(void * opaque,hwaddr addr,unsigned size)321 static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
322 unsigned size)
323 {
324 PICCommonState *s = opaque;
325 int ret;
326
327 if (s->poll) {
328 ret = pic_get_irq(s);
329 if (ret >= 0) {
330 pic_intack(s, ret);
331 ret |= 0x80;
332 } else {
333 ret = 0;
334 }
335 s->poll = 0;
336 } else {
337 if (addr == 0) {
338 if (s->read_reg_select) {
339 ret = s->isr;
340 } else {
341 ret = s->irr;
342 }
343 } else {
344 ret = s->imr;
345 }
346 }
347 trace_pic_ioport_read(s->master, addr, ret);
348 return ret;
349 }
350
pic_get_output(PICCommonState * s)351 int pic_get_output(PICCommonState *s)
352 {
353 return (pic_get_irq(s) >= 0);
354 }
355
elcr_ioport_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)356 static void elcr_ioport_write(void *opaque, hwaddr addr,
357 uint64_t val, unsigned size)
358 {
359 PICCommonState *s = opaque;
360 s->elcr = val & s->elcr_mask;
361 }
362
elcr_ioport_read(void * opaque,hwaddr addr,unsigned size)363 static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
364 unsigned size)
365 {
366 PICCommonState *s = opaque;
367 return s->elcr;
368 }
369
370 static const MemoryRegionOps pic_base_ioport_ops = {
371 .read = pic_ioport_read,
372 .write = pic_ioport_write,
373 .impl = {
374 .min_access_size = 1,
375 .max_access_size = 1,
376 },
377 };
378
379 static const MemoryRegionOps pic_elcr_ioport_ops = {
380 .read = elcr_ioport_read,
381 .write = elcr_ioport_write,
382 .impl = {
383 .min_access_size = 1,
384 .max_access_size = 1,
385 },
386 };
387
pic_realize(DeviceState * dev,Error ** errp)388 static void pic_realize(DeviceState *dev, Error **errp)
389 {
390 PICCommonState *s = PIC_COMMON(dev);
391 PICClass *pc = PIC_GET_CLASS(dev);
392
393 memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s,
394 "pic", 2);
395 memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s,
396 "elcr", 1);
397
398 qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out));
399 qdev_init_gpio_in(dev, pic_set_irq, 8);
400
401 pc->parent_realize(dev, errp);
402 }
403
i8259_init(ISABus * bus,qemu_irq parent_irq_in)404 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in)
405 {
406 qemu_irq *irq_set;
407 DeviceState *dev;
408 ISADevice *isadev;
409 int i;
410
411 irq_set = g_new0(qemu_irq, ISA_NUM_IRQS);
412
413 isadev = i8259_init_chip(TYPE_I8259, bus, true);
414 dev = DEVICE(isadev);
415
416 qdev_connect_gpio_out(dev, 0, parent_irq_in);
417 for (i = 0 ; i < 8; i++) {
418 irq_set[i] = qdev_get_gpio_in(dev, i);
419 }
420
421 isa_pic = PIC_COMMON(dev);
422
423 isadev = i8259_init_chip(TYPE_I8259, bus, false);
424 dev = DEVICE(isadev);
425
426 qdev_connect_gpio_out(dev, 0, irq_set[2]);
427 for (i = 0 ; i < 8; i++) {
428 irq_set[i + 8] = qdev_get_gpio_in(dev, i);
429 }
430
431 slave_pic = PIC_COMMON(dev);
432
433 return irq_set;
434 }
435
i8259_class_init(ObjectClass * klass,const void * data)436 static void i8259_class_init(ObjectClass *klass, const void *data)
437 {
438 PICClass *k = PIC_CLASS(klass);
439 DeviceClass *dc = DEVICE_CLASS(klass);
440
441 device_class_set_parent_realize(dc, pic_realize, &k->parent_realize);
442 device_class_set_legacy_reset(dc, pic_reset);
443 }
444
445 static const TypeInfo i8259_info = {
446 .name = TYPE_I8259,
447 .instance_size = sizeof(PICCommonState),
448 .parent = TYPE_PIC_COMMON,
449 .class_init = i8259_class_init,
450 .class_size = sizeof(PICClass),
451 };
452
pic_register_types(void)453 static void pic_register_types(void)
454 {
455 type_register_static(&i8259_info);
456 }
457
458 type_init(pic_register_types)
459