1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
5 * www.emulex.com
6 *
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * Contact Information:
36 * linux-drivers@emulex.com
37 *
38 * Emulex
39 * 3333 Susan Street
40 * Costa Mesa, CA 92626
41 */
42
43 #ifndef __OCRDMA_H__
44 #define __OCRDMA_H__
45
46 #include <linux/mutex.h>
47 #include <linux/list.h>
48 #include <linux/spinlock.h>
49 #include <linux/pci.h>
50
51 #include <rdma/ib_verbs.h>
52 #include <rdma/ib_user_verbs.h>
53 #include <rdma/ib_addr.h>
54
55 #include <be_roce.h>
56 #include "ocrdma_sli.h"
57
58 #define OCRDMA_ROCE_DRV_VERSION "11.0.0.0"
59
60 #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver"
61 #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA"
62
63 #define OC_NAME_SH OCRDMA_NODE_DESC "(Skyhawk)"
64 #define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)"
65
66 #define OC_SKH_DEVICE_PF 0x720
67 #define OC_SKH_DEVICE_VF 0x728
68 #define OCRDMA_MAX_AH 512
69
70 #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo)
71 #define EQ_INTR_PER_SEC_THRSH_HI 150000
72 #define EQ_INTR_PER_SEC_THRSH_LOW 100000
73 #define EQ_AIC_MAX_EQD 20
74 #define EQ_AIC_MIN_EQD 0
75
76 void ocrdma_eqd_set_task(struct work_struct *work);
77
78 struct ocrdma_dev_attr {
79 u8 fw_ver[32];
80 u32 vendor_id;
81 u32 device_id;
82 u16 max_pd;
83 u16 max_dpp_pds;
84 u16 max_cq;
85 u16 max_cqe;
86 u16 max_qp;
87 u16 max_wqe;
88 u16 max_rqe;
89 u16 max_srq;
90 u32 max_inline_data;
91 int max_send_sge;
92 int max_recv_sge;
93 int max_srq_sge;
94 int max_rdma_sge;
95 int max_mr;
96 u64 max_mr_size;
97 u32 max_num_mr_pbl;
98 int max_mw;
99 int max_map_per_fmr;
100 int max_pages_per_frmr;
101 u16 max_ord_per_qp;
102 u16 max_ird_per_qp;
103
104 int device_cap_flags;
105 u8 cq_overflow_detect;
106 u8 srq_supported;
107
108 u32 wqe_size;
109 u32 rqe_size;
110 u32 ird_page_size;
111 u8 local_ca_ack_delay;
112 u8 ird;
113 u8 num_ird_pages;
114 u8 udp_encap;
115 };
116
117 struct ocrdma_dma_mem {
118 void *va;
119 dma_addr_t pa;
120 u32 size;
121 };
122
123 struct ocrdma_pbl {
124 void *va;
125 dma_addr_t pa;
126 };
127
128 struct ocrdma_queue_info {
129 void *va;
130 dma_addr_t dma;
131 u32 size;
132 u16 len;
133 u16 entry_size; /* Size of an element in the queue */
134 u16 id; /* qid, where to ring the doorbell. */
135 u16 head, tail;
136 bool created;
137 };
138
139 struct ocrdma_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
140 u32 prev_eqd;
141 u64 eq_intr_cnt;
142 u64 prev_eq_intr_cnt;
143 };
144
145 struct ocrdma_eq {
146 struct ocrdma_queue_info q;
147 u32 vector;
148 int cq_cnt;
149 struct ocrdma_dev *dev;
150 char irq_name[32];
151 struct ocrdma_aic_obj aic_obj;
152 };
153
154 struct ocrdma_mq {
155 struct ocrdma_queue_info sq;
156 struct ocrdma_queue_info cq;
157 bool rearm_cq;
158 };
159
160 struct mqe_ctx {
161 struct mutex lock; /* for serializing mailbox commands on MQ */
162 wait_queue_head_t cmd_wait;
163 u32 tag;
164 u16 cqe_status;
165 u16 ext_status;
166 bool cmd_done;
167 bool fw_error_state;
168 };
169
170 struct ocrdma_hw_mr {
171 u32 lkey;
172 u8 fr_mr;
173 u8 remote_atomic;
174 u8 remote_rd;
175 u8 remote_wr;
176 u8 local_rd;
177 u8 local_wr;
178 u8 mw_bind;
179 u8 rsvd;
180 u64 len;
181 struct ocrdma_pbl *pbl_table;
182 u32 num_pbls;
183 u32 num_pbes;
184 u32 pbl_size;
185 u32 pbe_size;
186 u64 va;
187 };
188
189 struct ocrdma_mr {
190 struct ib_mr ibmr;
191 struct ib_umem *umem;
192 struct ocrdma_hw_mr hwmr;
193 u64 *pages;
194 u32 npages;
195 };
196
197 struct ocrdma_stats {
198 u8 type;
199 struct ocrdma_dev *dev;
200 };
201
202 struct ocrdma_pd_resource_mgr {
203 u32 pd_norm_start;
204 u16 pd_norm_count;
205 u16 pd_norm_thrsh;
206 u16 max_normal_pd;
207 u32 pd_dpp_start;
208 u16 pd_dpp_count;
209 u16 pd_dpp_thrsh;
210 u16 max_dpp_pd;
211 u16 dpp_page_index;
212 unsigned long *pd_norm_bitmap;
213 unsigned long *pd_dpp_bitmap;
214 bool pd_prealloc_valid;
215 };
216
217 struct stats_mem {
218 struct ocrdma_mqe mqe;
219 void *va;
220 dma_addr_t pa;
221 u32 size;
222 char *debugfs_mem;
223 };
224
225 struct phy_info {
226 u16 auto_speeds_supported;
227 u16 fixed_speeds_supported;
228 u16 phy_type;
229 u16 interface_type;
230 };
231
232 enum ocrdma_flags {
233 OCRDMA_FLAGS_LINK_STATUS_INIT = 0x01
234 };
235
236 struct ocrdma_dev {
237 struct ib_device ibdev;
238 struct ocrdma_dev_attr attr;
239
240 struct mutex dev_lock; /* provides syncronise access to device data */
241 spinlock_t flush_q_lock ____cacheline_aligned;
242
243 struct ocrdma_cq **cq_tbl;
244 struct ocrdma_qp **qp_tbl;
245
246 struct ocrdma_eq *eq_tbl;
247 int eq_cnt;
248 struct delayed_work eqd_work;
249 u16 base_eqid;
250 u16 max_eq;
251
252 /* provided synchronization to sgid table for
253 * updating gid entries triggered by notifier.
254 */
255 spinlock_t sgid_lock;
256
257 int gsi_qp_created;
258 struct ocrdma_cq *gsi_sqcq;
259 struct ocrdma_cq *gsi_rqcq;
260
261 struct {
262 struct ocrdma_av *va;
263 dma_addr_t pa;
264 u32 size;
265 u32 num_ah;
266 /* provide synchronization for av
267 * entry allocations.
268 */
269 spinlock_t lock;
270 u32 ahid;
271 struct ocrdma_pbl pbl;
272 } av_tbl;
273
274 void *mbx_cmd;
275 struct ocrdma_mq mq;
276 struct mqe_ctx mqe_ctx;
277
278 struct be_dev_info nic_info;
279 struct phy_info phy;
280 char model_number[32];
281 u32 hba_port_num;
282
283 struct list_head entry;
284 int id;
285 u64 *stag_arr;
286 u8 sl; /* service level */
287 bool pfc_state;
288 atomic_t update_sl;
289 u16 pvid;
290 u32 asic_id;
291 u32 flags;
292
293 ulong last_stats_time;
294 struct mutex stats_lock; /* provide synch for debugfs operations */
295 struct stats_mem stats_mem;
296 struct ocrdma_stats rsrc_stats;
297 struct ocrdma_stats rx_stats;
298 struct ocrdma_stats wqe_stats;
299 struct ocrdma_stats tx_stats;
300 struct ocrdma_stats db_err_stats;
301 struct ocrdma_stats tx_qp_err_stats;
302 struct ocrdma_stats rx_qp_err_stats;
303 struct ocrdma_stats tx_dbg_stats;
304 struct ocrdma_stats rx_dbg_stats;
305 struct ocrdma_stats driver_stats;
306 struct ocrdma_stats reset_stats;
307 struct dentry *dir;
308 atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS];
309 atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR];
310 struct ocrdma_pd_resource_mgr *pd_mgr;
311 };
312
313 struct ocrdma_cq {
314 struct ib_cq ibcq;
315 struct ocrdma_cqe *va;
316 u32 phase;
317 u32 getp; /* pointer to pending wrs to
318 * return to stack, wrap arounds
319 * at max_hw_cqe
320 */
321 u32 max_hw_cqe;
322 bool phase_change;
323 spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization
324 * to cq polling
325 */
326 /* syncronizes cq completion handler invoked from multiple context */
327 spinlock_t comp_handler_lock ____cacheline_aligned;
328 u16 id;
329 u16 eqn;
330
331 struct ocrdma_ucontext *ucontext;
332 dma_addr_t pa;
333 u32 len;
334 u32 cqe_cnt;
335
336 /* head of all qp's sq and rq for which cqes need to be flushed
337 * by the software.
338 */
339 struct list_head sq_head, rq_head;
340 };
341
342 struct ocrdma_pd {
343 struct ib_pd ibpd;
344 struct ocrdma_ucontext *uctx;
345 u32 id;
346 int num_dpp_qp;
347 u32 dpp_page;
348 bool dpp_enabled;
349 };
350
351 struct ocrdma_ah {
352 struct ib_ah ibah;
353 struct ocrdma_av *av;
354 u16 sgid_index;
355 u32 id;
356 u8 hdr_type;
357 };
358
359 struct ocrdma_qp_hwq_info {
360 u8 *va; /* virtual address */
361 u32 max_sges;
362 u32 head, tail;
363 u32 entry_size;
364 u32 max_cnt;
365 u32 max_wqe_idx;
366 u16 dbid; /* qid, where to ring the doorbell. */
367 u32 len;
368 dma_addr_t pa;
369 };
370
371 struct ocrdma_srq {
372 struct ib_srq ibsrq;
373 u8 __iomem *db;
374 struct ocrdma_qp_hwq_info rq;
375 u64 *rqe_wr_id_tbl;
376 u32 *idx_bit_fields;
377 u32 bit_fields_len;
378
379 /* provide synchronization to multiple context(s) posting rqe */
380 spinlock_t q_lock ____cacheline_aligned;
381
382 struct ocrdma_pd *pd;
383 u32 id;
384 };
385
386 struct ocrdma_qp {
387 struct ib_qp ibqp;
388
389 u8 __iomem *sq_db;
390 struct ocrdma_qp_hwq_info sq;
391 struct {
392 uint64_t wrid;
393 uint16_t dpp_wqe_idx;
394 uint16_t dpp_wqe;
395 uint8_t signaled;
396 uint8_t rsvd[3];
397 } *wqe_wr_id_tbl;
398 u32 max_inline_data;
399
400 /* provide synchronization to multiple context(s) posting wqe, rqe */
401 spinlock_t q_lock ____cacheline_aligned;
402 struct ocrdma_cq *sq_cq;
403 /* list maintained per CQ to flush SQ errors */
404 struct list_head sq_entry;
405
406 u8 __iomem *rq_db;
407 struct ocrdma_qp_hwq_info rq;
408 u64 *rqe_wr_id_tbl;
409 struct ocrdma_cq *rq_cq;
410 struct ocrdma_srq *srq;
411 /* list maintained per CQ to flush RQ errors */
412 struct list_head rq_entry;
413
414 enum ocrdma_qp_state state; /* QP state */
415 int cap_flags;
416 u32 max_ord, max_ird;
417
418 u32 id;
419 struct ocrdma_pd *pd;
420
421 enum ib_qp_type qp_type;
422
423 int sgid_idx;
424 u32 qkey;
425 bool dpp_enabled;
426 u8 *ird_q_va;
427 bool signaled;
428 };
429
430 struct ocrdma_ucontext {
431 struct ib_ucontext ibucontext;
432
433 struct list_head mm_head;
434 struct mutex mm_list_lock; /* protects list entries of mm type */
435 struct ocrdma_pd *cntxt_pd;
436 int pd_in_use;
437
438 struct {
439 u32 *va;
440 dma_addr_t pa;
441 u32 len;
442 } ah_tbl;
443 };
444
445 struct ocrdma_mm {
446 struct {
447 u64 phy_addr;
448 unsigned long len;
449 } key;
450 struct list_head entry;
451 };
452
get_ocrdma_dev(struct ib_device * ibdev)453 static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev)
454 {
455 return container_of(ibdev, struct ocrdma_dev, ibdev);
456 }
457
get_ocrdma_ucontext(struct ib_ucontext * ibucontext)458 static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext
459 *ibucontext)
460 {
461 return container_of(ibucontext, struct ocrdma_ucontext, ibucontext);
462 }
463
get_ocrdma_pd(struct ib_pd * ibpd)464 static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd)
465 {
466 return container_of(ibpd, struct ocrdma_pd, ibpd);
467 }
468
get_ocrdma_cq(struct ib_cq * ibcq)469 static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq)
470 {
471 return container_of(ibcq, struct ocrdma_cq, ibcq);
472 }
473
get_ocrdma_qp(struct ib_qp * ibqp)474 static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp)
475 {
476 return container_of(ibqp, struct ocrdma_qp, ibqp);
477 }
478
get_ocrdma_mr(struct ib_mr * ibmr)479 static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr)
480 {
481 return container_of(ibmr, struct ocrdma_mr, ibmr);
482 }
483
get_ocrdma_ah(struct ib_ah * ibah)484 static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah)
485 {
486 return container_of(ibah, struct ocrdma_ah, ibah);
487 }
488
get_ocrdma_srq(struct ib_srq * ibsrq)489 static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq)
490 {
491 return container_of(ibsrq, struct ocrdma_srq, ibsrq);
492 }
493
is_cqe_valid(struct ocrdma_cq * cq,struct ocrdma_cqe * cqe)494 static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe)
495 {
496 int cqe_valid;
497 cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID;
498 return (cqe_valid == cq->phase);
499 }
500
is_cqe_for_sq(struct ocrdma_cqe * cqe)501 static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe)
502 {
503 return (le32_to_cpu(cqe->flags_status_srcqpn) &
504 OCRDMA_CQE_QTYPE) ? 0 : 1;
505 }
506
is_cqe_invalidated(struct ocrdma_cqe * cqe)507 static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe)
508 {
509 return (le32_to_cpu(cqe->flags_status_srcqpn) &
510 OCRDMA_CQE_INVALIDATE) ? 1 : 0;
511 }
512
is_cqe_imm(struct ocrdma_cqe * cqe)513 static inline int is_cqe_imm(struct ocrdma_cqe *cqe)
514 {
515 return (le32_to_cpu(cqe->flags_status_srcqpn) &
516 OCRDMA_CQE_IMM) ? 1 : 0;
517 }
518
is_cqe_wr_imm(struct ocrdma_cqe * cqe)519 static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe)
520 {
521 return (le32_to_cpu(cqe->flags_status_srcqpn) &
522 OCRDMA_CQE_WRITE_IMM) ? 1 : 0;
523 }
524
ocrdma_resolve_dmac(struct ocrdma_dev * dev,struct rdma_ah_attr * ah_attr,u8 * mac_addr)525 static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev,
526 struct rdma_ah_attr *ah_attr, u8 *mac_addr)
527 {
528 struct in6_addr in6;
529
530 memcpy(&in6, rdma_ah_read_grh(ah_attr)->dgid.raw, sizeof(in6));
531 if (rdma_is_multicast_addr(&in6))
532 rdma_get_mcast_mac(&in6, mac_addr);
533 else if (rdma_link_local_addr(&in6))
534 rdma_get_ll_mac(&in6, mac_addr);
535 else
536 memcpy(mac_addr, ah_attr->roce.dmac, ETH_ALEN);
537 return 0;
538 }
539
hca_name(struct ocrdma_dev * dev)540 static inline char *hca_name(struct ocrdma_dev *dev)
541 {
542 switch (dev->nic_info.pdev->device) {
543 case OC_SKH_DEVICE_PF:
544 case OC_SKH_DEVICE_VF:
545 return OC_NAME_SH;
546 default:
547 return OC_NAME_UNKNOWN;
548 }
549 }
550
ocrdma_get_eq_table_index(struct ocrdma_dev * dev,int eqid)551 static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev,
552 int eqid)
553 {
554 int indx;
555
556 for (indx = 0; indx < dev->eq_cnt; indx++) {
557 if (dev->eq_tbl[indx].q.id == eqid)
558 return indx;
559 }
560
561 return -EINVAL;
562 }
563
ocrdma_get_asic_type(struct ocrdma_dev * dev)564 static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev)
565 {
566 if (dev->nic_info.dev_family == 0xF && !dev->asic_id) {
567 pci_read_config_dword(
568 dev->nic_info.pdev,
569 OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id);
570 }
571
572 return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >>
573 OCRDMA_SLI_ASIC_GEN_NUM_SHIFT;
574 }
575
ocrdma_get_pfc_prio(u8 * pfc,u8 prio)576 static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio)
577 {
578 return *(pfc + prio);
579 }
580
ocrdma_get_app_prio(u8 * app_prio,u8 prio)581 static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio)
582 {
583 return *(app_prio + prio);
584 }
585
ocrdma_is_enabled_and_synced(u32 state)586 static inline u8 ocrdma_is_enabled_and_synced(u32 state)
587 { /* May also be used to interpret TC-state, QCN-state
588 * Appl-state and Logical-link-state in future.
589 */
590 return (state & OCRDMA_STATE_FLAG_ENABLED) &&
591 (state & OCRDMA_STATE_FLAG_SYNC);
592 }
593
ocrdma_get_ae_link_state(u32 ae_state)594 static inline u8 ocrdma_get_ae_link_state(u32 ae_state)
595 {
596 return ((ae_state & OCRDMA_AE_LSC_LS_MASK) >> OCRDMA_AE_LSC_LS_SHIFT);
597 }
598
ocrdma_is_udp_encap_supported(struct ocrdma_dev * dev)599 static inline bool ocrdma_is_udp_encap_supported(struct ocrdma_dev *dev)
600 {
601 return (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV4) ||
602 (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV6);
603 }
604
605 #endif
606