1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "exec/target_page.h"
25 #include "tcg/tcg-op.h"
26 #include "tcg/tcg-op-gvec.h"
27 #include "qemu/host-utils.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "exec/translator.h"
33 #include "exec/translation-block.h"
34 #include "exec/log.h"
35 #include "qemu/atomic128.h"
36 #include "spr_common.h"
37 #include "power8-pmu.h"
38
39 #include "qemu/qemu-print.h"
40 #include "qapi/error.h"
41
42 #define HELPER_H "helper.h"
43 #include "exec/helper-info.c.inc"
44 #undef HELPER_H
45
46 #define CPU_SINGLE_STEP 0x1
47 #define CPU_BRANCH_STEP 0x2
48
49 /* Include definitions for instructions classes and implementations flags */
50 /* #define PPC_DEBUG_DISAS */
51
52 #ifdef PPC_DEBUG_DISAS
53 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
54 #else
55 # define LOG_DISAS(...) do { } while (0)
56 #endif
57 /*****************************************************************************/
58 /* Code translation helpers */
59
60 /* global register indexes */
61 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
62 + 10 * 4 + 22 * 5 /* SPE GPRh */
63 + 8 * 5 /* CRF */];
64 static TCGv cpu_gpr[32];
65 static TCGv cpu_gprh[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_length;
77 static TCGv cpu_reserve_val;
78 #if defined(TARGET_PPC64)
79 static TCGv cpu_reserve_val2;
80 #endif
81 static TCGv cpu_fpscr;
82 static TCGv_i32 cpu_access_type;
83
ppc_translate_init(void)84 void ppc_translate_init(void)
85 {
86 int i;
87 char *p;
88 size_t cpu_reg_names_size;
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(tcg_env,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(tcg_env,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 snprintf(p, cpu_reg_names_size, "r%dH", i);
108 cpu_gprh[i] = tcg_global_mem_new(tcg_env,
109 offsetof(CPUPPCState, gprh[i]), p);
110 p += (i < 10) ? 4 : 5;
111 cpu_reg_names_size -= (i < 10) ? 4 : 5;
112 }
113
114 cpu_nip = tcg_global_mem_new(tcg_env,
115 offsetof(CPUPPCState, nip), "nip");
116
117 cpu_msr = tcg_global_mem_new(tcg_env,
118 offsetof(CPUPPCState, msr), "msr");
119
120 cpu_ctr = tcg_global_mem_new(tcg_env,
121 offsetof(CPUPPCState, ctr), "ctr");
122
123 cpu_lr = tcg_global_mem_new(tcg_env,
124 offsetof(CPUPPCState, lr), "lr");
125
126 #if defined(TARGET_PPC64)
127 cpu_cfar = tcg_global_mem_new(tcg_env,
128 offsetof(CPUPPCState, cfar), "cfar");
129 #endif
130
131 cpu_xer = tcg_global_mem_new(tcg_env,
132 offsetof(CPUPPCState, xer), "xer");
133 cpu_so = tcg_global_mem_new(tcg_env,
134 offsetof(CPUPPCState, so), "SO");
135 cpu_ov = tcg_global_mem_new(tcg_env,
136 offsetof(CPUPPCState, ov), "OV");
137 cpu_ca = tcg_global_mem_new(tcg_env,
138 offsetof(CPUPPCState, ca), "CA");
139 cpu_ov32 = tcg_global_mem_new(tcg_env,
140 offsetof(CPUPPCState, ov32), "OV32");
141 cpu_ca32 = tcg_global_mem_new(tcg_env,
142 offsetof(CPUPPCState, ca32), "CA32");
143
144 cpu_reserve = tcg_global_mem_new(tcg_env,
145 offsetof(CPUPPCState, reserve_addr),
146 "reserve_addr");
147 cpu_reserve_length = tcg_global_mem_new(tcg_env,
148 offsetof(CPUPPCState,
149 reserve_length),
150 "reserve_length");
151 cpu_reserve_val = tcg_global_mem_new(tcg_env,
152 offsetof(CPUPPCState, reserve_val),
153 "reserve_val");
154 #if defined(TARGET_PPC64)
155 cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
156 offsetof(CPUPPCState, reserve_val2),
157 "reserve_val2");
158 #endif
159
160 cpu_fpscr = tcg_global_mem_new(tcg_env,
161 offsetof(CPUPPCState, fpscr), "fpscr");
162
163 cpu_access_type = tcg_global_mem_new_i32(tcg_env,
164 offsetof(CPUPPCState, access_type),
165 "access_type");
166 }
167
168 /* internal defines */
169 struct DisasContext {
170 DisasContextBase base;
171 target_ulong cia; /* current instruction address */
172 uint32_t opcode;
173 /* Routine used to access memory */
174 bool pr, hv, dr, le_mode;
175 bool lazy_tlb_flush;
176 bool need_access_type;
177 int mem_idx;
178 int access_type;
179 /* Translation flags */
180 MemOp default_tcg_memop_mask;
181 #if defined(TARGET_PPC64)
182 powerpc_excp_t excp_model;
183 bool sf_mode;
184 bool has_cfar;
185 bool has_bhrb;
186 #endif
187 bool fpu_enabled;
188 bool altivec_enabled;
189 bool vsx_enabled;
190 bool spe_enabled;
191 bool tm_enabled;
192 bool gtse;
193 bool hr;
194 bool mmcr0_pmcc0;
195 bool mmcr0_pmcc1;
196 bool mmcr0_pmcjce;
197 bool pmc_other;
198 bool pmu_insn_cnt;
199 bool bhrb_enable;
200 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
201 int singlestep_enabled;
202 uint32_t flags;
203 uint64_t insns_flags;
204 uint64_t insns_flags2;
205 };
206
207 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */
208 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */
209 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */
210 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
211
212 /* Return true iff byteswap is needed in a scalar memop */
need_byteswap(const DisasContext * ctx)213 static inline bool need_byteswap(const DisasContext *ctx)
214 {
215 #if TARGET_BIG_ENDIAN
216 return ctx->le_mode;
217 #else
218 return !ctx->le_mode;
219 #endif
220 }
221
222 /* True when active word size < size of target_long. */
223 #ifdef TARGET_PPC64
224 # define NARROW_MODE(C) (!(C)->sf_mode)
225 #else
226 # define NARROW_MODE(C) 0
227 #endif
228
229 struct opc_handler_t {
230 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
231 uint32_t inval1;
232 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
233 uint32_t inval2;
234 /* instruction type */
235 uint64_t type;
236 /* extended instruction type */
237 uint64_t type2;
238 /* handler */
239 void (*handler)(DisasContext *ctx);
240 };
241
gen_serialize(DisasContext * ctx)242 static inline bool gen_serialize(DisasContext *ctx)
243 {
244 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
245 /* Restart with exclusive lock. */
246 gen_helper_exit_atomic(tcg_env);
247 ctx->base.is_jmp = DISAS_NORETURN;
248 return false;
249 }
250 return true;
251 }
252
253 #if !defined(CONFIG_USER_ONLY)
254 #if defined(TARGET_PPC64)
gen_serialize_core(DisasContext * ctx)255 static inline bool gen_serialize_core(DisasContext *ctx)
256 {
257 if (ctx->flags & POWERPC_FLAG_SMT) {
258 return gen_serialize(ctx);
259 }
260 return true;
261 }
262 #endif
263
gen_serialize_core_lpar(DisasContext * ctx)264 static inline bool gen_serialize_core_lpar(DisasContext *ctx)
265 {
266 #if defined(TARGET_PPC64)
267 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
268 return gen_serialize(ctx);
269 }
270 #endif
271 return true;
272 }
273 #endif
274
275 /* SPR load/store helpers */
gen_load_spr(TCGv t,int reg)276 static inline void gen_load_spr(TCGv t, int reg)
277 {
278 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg]));
279 }
280
gen_store_spr(int reg,TCGv t)281 static inline void gen_store_spr(int reg, TCGv t)
282 {
283 tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg]));
284 }
285
gen_set_access_type(DisasContext * ctx,int access_type)286 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
287 {
288 if (ctx->need_access_type && ctx->access_type != access_type) {
289 tcg_gen_movi_i32(cpu_access_type, access_type);
290 ctx->access_type = access_type;
291 }
292 }
293
gen_update_nip(DisasContext * ctx,target_ulong nip)294 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
295 {
296 if (NARROW_MODE(ctx)) {
297 nip = (uint32_t)nip;
298 }
299 tcg_gen_movi_tl(cpu_nip, nip);
300 }
301
gen_exception_err_nip(DisasContext * ctx,uint32_t excp,uint32_t error,target_ulong nip)302 static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp,
303 uint32_t error, target_ulong nip)
304 {
305 TCGv_i32 t0, t1;
306
307 gen_update_nip(ctx, nip);
308 t0 = tcg_constant_i32(excp);
309 t1 = tcg_constant_i32(error);
310 gen_helper_raise_exception_err(tcg_env, t0, t1);
311 ctx->base.is_jmp = DISAS_NORETURN;
312 }
313
gen_exception_err(DisasContext * ctx,uint32_t excp,uint32_t error)314 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp,
315 uint32_t error)
316 {
317 /*
318 * These are all synchronous exceptions, we set the PC back to the
319 * faulting instruction
320 */
321 gen_exception_err_nip(ctx, excp, error, ctx->cia);
322 }
323
gen_exception_nip(DisasContext * ctx,uint32_t excp,target_ulong nip)324 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
325 target_ulong nip)
326 {
327 TCGv_i32 t0;
328
329 gen_update_nip(ctx, nip);
330 t0 = tcg_constant_i32(excp);
331 gen_helper_raise_exception(tcg_env, t0);
332 ctx->base.is_jmp = DISAS_NORETURN;
333 }
334
gen_exception(DisasContext * ctx,uint32_t excp)335 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
336 {
337 /*
338 * These are all synchronous exceptions, we set the PC back to the
339 * faulting instruction
340 */
341 gen_exception_nip(ctx, excp, ctx->cia);
342 }
343
344 #if !defined(CONFIG_USER_ONLY)
gen_ppc_maybe_interrupt(DisasContext * ctx)345 static void gen_ppc_maybe_interrupt(DisasContext *ctx)
346 {
347 translator_io_start(&ctx->base);
348 gen_helper_ppc_maybe_interrupt(tcg_env);
349 }
350 #endif
351
352 /*
353 * Tells the caller what is the appropriate exception to generate and prepares
354 * SPR registers for this exception.
355 *
356 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
357 * POWERPC_EXCP_DEBUG (on BookE).
358 */
gen_debug_exception(DisasContext * ctx,bool rfi_type)359 static void gen_debug_exception(DisasContext *ctx, bool rfi_type)
360 {
361 #if !defined(CONFIG_USER_ONLY)
362 if (ctx->flags & POWERPC_FLAG_DE) {
363 target_ulong dbsr = 0;
364 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
365 dbsr = DBCR0_ICMP;
366 } else {
367 /* Must have been branch */
368 dbsr = DBCR0_BRT;
369 }
370 TCGv t0 = tcg_temp_new();
371 gen_load_spr(t0, SPR_BOOKE_DBSR);
372 tcg_gen_ori_tl(t0, t0, dbsr);
373 gen_store_spr(SPR_BOOKE_DBSR, t0);
374 gen_helper_raise_exception(tcg_env,
375 tcg_constant_i32(POWERPC_EXCP_DEBUG));
376 ctx->base.is_jmp = DISAS_NORETURN;
377 } else {
378 if (!rfi_type) { /* BookS does not single step rfi type instructions */
379 TCGv t0 = tcg_temp_new();
380 tcg_gen_movi_tl(t0, ctx->cia);
381 gen_helper_book3s_trace(tcg_env, t0);
382 ctx->base.is_jmp = DISAS_NORETURN;
383 }
384 }
385 #endif
386 }
387
gen_inval_exception(DisasContext * ctx,uint32_t error)388 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
389 {
390 /* Will be converted to program check if needed */
391 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
392 }
393
gen_priv_exception(DisasContext * ctx,uint32_t error)394 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
395 {
396 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
397 }
398
gen_hvpriv_exception(DisasContext * ctx,uint32_t error)399 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
400 {
401 /* Will be converted to program check if needed */
402 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
403 }
404
405 /*****************************************************************************/
406 /* SPR READ/WRITE CALLBACKS */
407
spr_noaccess(DisasContext * ctx,int gprn,int sprn)408 void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
409 {
410 #if 0
411 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
412 printf("ERROR: try to access SPR %d !\n", sprn);
413 #endif
414 }
415
416 /* #define PPC_DUMP_SPR_ACCESSES */
417
418 /*
419 * Generic callbacks:
420 * do nothing but store/retrieve spr value
421 */
spr_load_dump_spr(int sprn)422 static void spr_load_dump_spr(int sprn)
423 {
424 #ifdef PPC_DUMP_SPR_ACCESSES
425 TCGv_i32 t0 = tcg_constant_i32(sprn);
426 gen_helper_load_dump_spr(tcg_env, t0);
427 #endif
428 }
429
spr_read_generic(DisasContext * ctx,int gprn,int sprn)430 void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
431 {
432 gen_load_spr(cpu_gpr[gprn], sprn);
433 spr_load_dump_spr(sprn);
434 }
435
spr_store_dump_spr(int sprn)436 static void spr_store_dump_spr(int sprn)
437 {
438 #ifdef PPC_DUMP_SPR_ACCESSES
439 TCGv_i32 t0 = tcg_constant_i32(sprn);
440 gen_helper_store_dump_spr(tcg_env, t0);
441 #endif
442 }
443
spr_write_generic(DisasContext * ctx,int sprn,int gprn)444 void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
445 {
446 gen_store_spr(sprn, cpu_gpr[gprn]);
447 spr_store_dump_spr(sprn);
448 }
449
spr_write_generic32(DisasContext * ctx,int sprn,int gprn)450 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
451 {
452 #ifdef TARGET_PPC64
453 TCGv t0 = tcg_temp_new();
454 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
455 gen_store_spr(sprn, t0);
456 spr_store_dump_spr(sprn);
457 #else
458 spr_write_generic(ctx, sprn, gprn);
459 #endif
460 }
461
spr_core_write_generic(DisasContext * ctx,int sprn,int gprn)462 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn)
463 {
464 if (!(ctx->flags & POWERPC_FLAG_SMT)) {
465 spr_write_generic(ctx, sprn, gprn);
466 return;
467 }
468
469 if (!gen_serialize(ctx)) {
470 return;
471 }
472
473 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn),
474 cpu_gpr[gprn]);
475 spr_store_dump_spr(sprn);
476 }
477
spr_core_write_generic32(DisasContext * ctx,int sprn,int gprn)478 void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn)
479 {
480 TCGv t0;
481
482 if (!(ctx->flags & POWERPC_FLAG_SMT)) {
483 spr_write_generic32(ctx, sprn, gprn);
484 return;
485 }
486
487 if (!gen_serialize(ctx)) {
488 return;
489 }
490
491 t0 = tcg_temp_new();
492 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
493 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0);
494 spr_store_dump_spr(sprn);
495 }
496
spr_core_lpar_write_generic(DisasContext * ctx,int sprn,int gprn)497 void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn)
498 {
499 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
500 spr_core_write_generic(ctx, sprn, gprn);
501 } else {
502 spr_write_generic(ctx, sprn, gprn);
503 }
504 }
505
spr_write_CTRL_ST(DisasContext * ctx,int sprn,int gprn)506 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
507 {
508 /* This does not implement >1 thread */
509 TCGv t0 = tcg_temp_new();
510 TCGv t1 = tcg_temp_new();
511 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */
512 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */
513 tcg_gen_or_tl(t1, t1, t0);
514 gen_store_spr(sprn, t1);
515 }
516
spr_write_CTRL(DisasContext * ctx,int sprn,int gprn)517 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
518 {
519 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) {
520 /* CTRL behaves as 1-thread in LPAR-per-thread mode */
521 spr_write_CTRL_ST(ctx, sprn, gprn);
522 goto out;
523 }
524
525 if (!gen_serialize(ctx)) {
526 return;
527 }
528
529 gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn),
530 cpu_gpr[gprn]);
531 out:
532 spr_store_dump_spr(sprn);
533
534 /*
535 * SPR_CTRL writes must force a new translation block,
536 * allowing the PMU to calculate the run latch events with
537 * more accuracy.
538 */
539 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
540 }
541
542 #if !defined(CONFIG_USER_ONLY)
spr_write_clear(DisasContext * ctx,int sprn,int gprn)543 void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
544 {
545 TCGv t0 = tcg_temp_new();
546 TCGv t1 = tcg_temp_new();
547 gen_load_spr(t0, sprn);
548 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
549 tcg_gen_and_tl(t0, t0, t1);
550 gen_store_spr(sprn, t0);
551 }
552
spr_access_nop(DisasContext * ctx,int sprn,int gprn)553 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
554 {
555 }
556
557 #endif
558
559 /* SPR common to all PowerPC */
560 /* XER */
spr_read_xer(DisasContext * ctx,int gprn,int sprn)561 void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
562 {
563 TCGv dst = cpu_gpr[gprn];
564 TCGv t0 = tcg_temp_new();
565 TCGv t1 = tcg_temp_new();
566 TCGv t2 = tcg_temp_new();
567 tcg_gen_mov_tl(dst, cpu_xer);
568 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
569 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
570 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
571 tcg_gen_or_tl(t0, t0, t1);
572 tcg_gen_or_tl(dst, dst, t2);
573 tcg_gen_or_tl(dst, dst, t0);
574 if (is_isa300(ctx)) {
575 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
576 tcg_gen_or_tl(dst, dst, t0);
577 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
578 tcg_gen_or_tl(dst, dst, t0);
579 }
580 }
581
spr_write_xer(DisasContext * ctx,int sprn,int gprn)582 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
583 {
584 TCGv src = cpu_gpr[gprn];
585 /* Write all flags, while reading back check for isa300 */
586 tcg_gen_andi_tl(cpu_xer, src,
587 ~((1u << XER_SO) |
588 (1u << XER_OV) | (1u << XER_OV32) |
589 (1u << XER_CA) | (1u << XER_CA32)));
590 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
591 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
592 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
593 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
594 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
595 }
596
597 /* LR */
spr_read_lr(DisasContext * ctx,int gprn,int sprn)598 void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
599 {
600 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
601 }
602
spr_write_lr(DisasContext * ctx,int sprn,int gprn)603 void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
604 {
605 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
606 }
607
608 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
609 /* Debug facilities */
610 /* CFAR */
spr_read_cfar(DisasContext * ctx,int gprn,int sprn)611 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
612 {
613 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
614 }
615
spr_write_cfar(DisasContext * ctx,int sprn,int gprn)616 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
617 {
618 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
619 }
620
621 /* Breakpoint */
spr_write_ciabr(DisasContext * ctx,int sprn,int gprn)622 void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn)
623 {
624 translator_io_start(&ctx->base);
625 gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]);
626 }
627
628 /* Watchpoint */
spr_write_dawr0(DisasContext * ctx,int sprn,int gprn)629 void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn)
630 {
631 translator_io_start(&ctx->base);
632 gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]);
633 }
634
spr_write_dawrx0(DisasContext * ctx,int sprn,int gprn)635 void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn)
636 {
637 translator_io_start(&ctx->base);
638 gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]);
639 }
640
spr_write_dawr1(DisasContext * ctx,int sprn,int gprn)641 void spr_write_dawr1(DisasContext *ctx, int sprn, int gprn)
642 {
643 translator_io_start(&ctx->base);
644 gen_helper_store_dawr1(tcg_env, cpu_gpr[gprn]);
645 }
646
spr_write_dawrx1(DisasContext * ctx,int sprn,int gprn)647 void spr_write_dawrx1(DisasContext *ctx, int sprn, int gprn)
648 {
649 translator_io_start(&ctx->base);
650 gen_helper_store_dawrx1(tcg_env, cpu_gpr[gprn]);
651 }
652 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
653
654 /* CTR */
spr_read_ctr(DisasContext * ctx,int gprn,int sprn)655 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
656 {
657 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
658 }
659
spr_write_ctr(DisasContext * ctx,int sprn,int gprn)660 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
661 {
662 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
663 }
664
665 /* User read access to SPR */
666 /* USPRx */
667 /* UMMCRx */
668 /* UPMCx */
669 /* USIA */
670 /* UDECR */
spr_read_ureg(DisasContext * ctx,int gprn,int sprn)671 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
672 {
673 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
674 }
675
676 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
spr_write_ureg(DisasContext * ctx,int sprn,int gprn)677 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
678 {
679 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
680 }
681 #endif
682
683 /* SPR common to all non-embedded PowerPC */
684 /* DECR */
685 #if !defined(CONFIG_USER_ONLY)
spr_read_decr(DisasContext * ctx,int gprn,int sprn)686 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
687 {
688 translator_io_start(&ctx->base);
689 gen_helper_load_decr(cpu_gpr[gprn], tcg_env);
690 }
691
spr_write_decr(DisasContext * ctx,int sprn,int gprn)692 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
693 {
694 translator_io_start(&ctx->base);
695 gen_helper_store_decr(tcg_env, cpu_gpr[gprn]);
696 }
697 #endif
698
699 /* SPR common to all non-embedded PowerPC, except 601 */
700 /* Time base */
spr_read_tbl(DisasContext * ctx,int gprn,int sprn)701 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
702 {
703 translator_io_start(&ctx->base);
704 gen_helper_load_tbl(cpu_gpr[gprn], tcg_env);
705 }
706
spr_read_tbu(DisasContext * ctx,int gprn,int sprn)707 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
708 {
709 translator_io_start(&ctx->base);
710 gen_helper_load_tbu(cpu_gpr[gprn], tcg_env);
711 }
712
spr_read_atbl(DisasContext * ctx,int gprn,int sprn)713 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
714 {
715 gen_helper_load_atbl(cpu_gpr[gprn], tcg_env);
716 }
717
spr_read_atbu(DisasContext * ctx,int gprn,int sprn)718 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
719 {
720 gen_helper_load_atbu(cpu_gpr[gprn], tcg_env);
721 }
722
723 #if !defined(CONFIG_USER_ONLY)
spr_write_tbl(DisasContext * ctx,int sprn,int gprn)724 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
725 {
726 if (!gen_serialize_core_lpar(ctx)) {
727 return;
728 }
729
730 translator_io_start(&ctx->base);
731 gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]);
732 }
733
spr_write_tbu(DisasContext * ctx,int sprn,int gprn)734 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
735 {
736 if (!gen_serialize_core_lpar(ctx)) {
737 return;
738 }
739
740 translator_io_start(&ctx->base);
741 gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]);
742 }
743
spr_write_atbl(DisasContext * ctx,int sprn,int gprn)744 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
745 {
746 gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]);
747 }
748
spr_write_atbu(DisasContext * ctx,int sprn,int gprn)749 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
750 {
751 gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]);
752 }
753
754 #if defined(TARGET_PPC64)
spr_read_purr(DisasContext * ctx,int gprn,int sprn)755 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
756 {
757 translator_io_start(&ctx->base);
758 gen_helper_load_purr(cpu_gpr[gprn], tcg_env);
759 }
760
spr_write_purr(DisasContext * ctx,int sprn,int gprn)761 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
762 {
763 if (!gen_serialize_core_lpar(ctx)) {
764 return;
765 }
766 translator_io_start(&ctx->base);
767 gen_helper_store_purr(tcg_env, cpu_gpr[gprn]);
768 }
769
770 /* HDECR */
spr_read_hdecr(DisasContext * ctx,int gprn,int sprn)771 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
772 {
773 translator_io_start(&ctx->base);
774 gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env);
775 }
776
spr_write_hdecr(DisasContext * ctx,int sprn,int gprn)777 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
778 {
779 if (!gen_serialize_core_lpar(ctx)) {
780 return;
781 }
782 translator_io_start(&ctx->base);
783 gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]);
784 }
785
spr_read_vtb(DisasContext * ctx,int gprn,int sprn)786 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
787 {
788 translator_io_start(&ctx->base);
789 gen_helper_load_vtb(cpu_gpr[gprn], tcg_env);
790 }
791
spr_write_vtb(DisasContext * ctx,int sprn,int gprn)792 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
793 {
794 if (!gen_serialize_core_lpar(ctx)) {
795 return;
796 }
797 translator_io_start(&ctx->base);
798 gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]);
799 }
800
spr_write_tbu40(DisasContext * ctx,int sprn,int gprn)801 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
802 {
803 if (!gen_serialize_core_lpar(ctx)) {
804 return;
805 }
806 translator_io_start(&ctx->base);
807 gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]);
808 }
809
810 #endif
811 #endif
812
813 #if !defined(CONFIG_USER_ONLY)
814 /* IBAT0U...IBAT0U */
815 /* IBAT0L...IBAT7L */
spr_read_ibat(DisasContext * ctx,int gprn,int sprn)816 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
817 {
818 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
819 offsetof(CPUPPCState,
820 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
821 }
822
spr_read_ibat_h(DisasContext * ctx,int gprn,int sprn)823 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
824 {
825 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
826 offsetof(CPUPPCState,
827 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
828 }
829
spr_write_ibatu(DisasContext * ctx,int sprn,int gprn)830 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
831 {
832 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
833 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]);
834 }
835
spr_write_ibatu_h(DisasContext * ctx,int sprn,int gprn)836 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
837 {
838 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
839 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]);
840 }
841
spr_write_ibatl(DisasContext * ctx,int sprn,int gprn)842 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
843 {
844 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
845 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]);
846 }
847
spr_write_ibatl_h(DisasContext * ctx,int sprn,int gprn)848 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
849 {
850 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
851 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]);
852 }
853
854 /* DBAT0U...DBAT7U */
855 /* DBAT0L...DBAT7L */
spr_read_dbat(DisasContext * ctx,int gprn,int sprn)856 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
857 {
858 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
859 offsetof(CPUPPCState,
860 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
861 }
862
spr_read_dbat_h(DisasContext * ctx,int gprn,int sprn)863 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
864 {
865 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
866 offsetof(CPUPPCState,
867 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
868 }
869
spr_write_dbatu(DisasContext * ctx,int sprn,int gprn)870 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
871 {
872 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
873 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]);
874 }
875
spr_write_dbatu_h(DisasContext * ctx,int sprn,int gprn)876 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
877 {
878 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
879 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]);
880 }
881
spr_write_dbatl(DisasContext * ctx,int sprn,int gprn)882 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
883 {
884 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
885 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]);
886 }
887
spr_write_dbatl_h(DisasContext * ctx,int sprn,int gprn)888 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
889 {
890 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
891 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]);
892 }
893
894 /* SDR1 */
spr_write_sdr1(DisasContext * ctx,int sprn,int gprn)895 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
896 {
897 gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]);
898 }
899
900 #if defined(TARGET_PPC64)
901 /* 64 bits PowerPC specific SPRs */
902 /* PIDR */
spr_write_pidr(DisasContext * ctx,int sprn,int gprn)903 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
904 {
905 gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]);
906 }
907
spr_write_lpidr(DisasContext * ctx,int sprn,int gprn)908 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
909 {
910 gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]);
911 }
912
spr_read_hior(DisasContext * ctx,int gprn,int sprn)913 void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
914 {
915 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefix));
916 }
917
spr_write_hior(DisasContext * ctx,int sprn,int gprn)918 void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
919 {
920 TCGv t0 = tcg_temp_new();
921 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
922 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix));
923 }
spr_write_ptcr(DisasContext * ctx,int sprn,int gprn)924 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
925 {
926 if (!gen_serialize_core(ctx)) {
927 return;
928 }
929
930 gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]);
931 }
932
spr_write_pcr(DisasContext * ctx,int sprn,int gprn)933 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
934 {
935 gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]);
936 }
937
938 /* DPDES */
spr_read_dpdes(DisasContext * ctx,int gprn,int sprn)939 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
940 {
941 if (!gen_serialize_core_lpar(ctx)) {
942 return;
943 }
944
945 gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env);
946 }
947
spr_write_dpdes(DisasContext * ctx,int sprn,int gprn)948 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
949 {
950 if (!gen_serialize_core_lpar(ctx)) {
951 return;
952 }
953
954 gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]);
955 }
956 #endif
957 #endif
958
959 /* PowerPC 40x specific registers */
960 #if !defined(CONFIG_USER_ONLY)
spr_read_40x_pit(DisasContext * ctx,int gprn,int sprn)961 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
962 {
963 translator_io_start(&ctx->base);
964 gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env);
965 }
966
spr_write_40x_pit(DisasContext * ctx,int sprn,int gprn)967 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
968 {
969 translator_io_start(&ctx->base);
970 gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]);
971 }
972
spr_write_40x_dbcr0(DisasContext * ctx,int sprn,int gprn)973 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
974 {
975 translator_io_start(&ctx->base);
976 gen_store_spr(sprn, cpu_gpr[gprn]);
977 gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]);
978 /* We must stop translation as we may have rebooted */
979 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
980 }
981
spr_write_40x_sler(DisasContext * ctx,int sprn,int gprn)982 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
983 {
984 translator_io_start(&ctx->base);
985 gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]);
986 }
987
spr_write_40x_tcr(DisasContext * ctx,int sprn,int gprn)988 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
989 {
990 translator_io_start(&ctx->base);
991 gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]);
992 }
993
spr_write_40x_tsr(DisasContext * ctx,int sprn,int gprn)994 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
995 {
996 translator_io_start(&ctx->base);
997 gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]);
998 }
999
spr_write_40x_pid(DisasContext * ctx,int sprn,int gprn)1000 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
1001 {
1002 TCGv t0 = tcg_temp_new();
1003 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
1004 gen_helper_store_40x_pid(tcg_env, t0);
1005 }
1006
spr_write_booke_tcr(DisasContext * ctx,int sprn,int gprn)1007 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
1008 {
1009 translator_io_start(&ctx->base);
1010 gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]);
1011 }
1012
spr_write_booke_tsr(DisasContext * ctx,int sprn,int gprn)1013 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
1014 {
1015 translator_io_start(&ctx->base);
1016 gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]);
1017 }
1018 #endif
1019
1020 /* PIR */
1021 #if !defined(CONFIG_USER_ONLY)
spr_write_pir(DisasContext * ctx,int sprn,int gprn)1022 void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
1023 {
1024 TCGv t0 = tcg_temp_new();
1025 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
1026 gen_store_spr(SPR_PIR, t0);
1027 }
1028 #endif
1029
1030 /* SPE specific registers */
spr_read_spefscr(DisasContext * ctx,int gprn,int sprn)1031 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
1032 {
1033 TCGv_i32 t0 = tcg_temp_new_i32();
1034 tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr));
1035 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
1036 }
1037
spr_write_spefscr(DisasContext * ctx,int sprn,int gprn)1038 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
1039 {
1040 TCGv_i32 t0 = tcg_temp_new_i32();
1041 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1042 tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr));
1043 }
1044
1045 #if !defined(CONFIG_USER_ONLY)
1046 /* Callback used to write the exception vector base */
spr_write_excp_prefix(DisasContext * ctx,int sprn,int gprn)1047 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
1048 {
1049 TCGv t0 = tcg_temp_new();
1050 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask));
1051 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1052 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix));
1053 gen_store_spr(sprn, t0);
1054 }
1055
spr_write_excp_vector(DisasContext * ctx,int sprn,int gprn)1056 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
1057 {
1058 int sprn_offs;
1059
1060 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
1061 sprn_offs = sprn - SPR_BOOKE_IVOR0;
1062 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
1063 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
1064 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
1065 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
1066 } else {
1067 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception"
1068 " vector 0x%03x\n", sprn);
1069 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1070 return;
1071 }
1072
1073 TCGv t0 = tcg_temp_new();
1074 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask));
1075 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1076 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
1077 gen_store_spr(sprn, t0);
1078 }
1079 #endif
1080
1081 #ifdef TARGET_PPC64
1082 #ifndef CONFIG_USER_ONLY
spr_write_amr(DisasContext * ctx,int sprn,int gprn)1083 void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1084 {
1085 TCGv t0 = tcg_temp_new();
1086 TCGv t1 = tcg_temp_new();
1087 TCGv t2 = tcg_temp_new();
1088
1089 /*
1090 * Note, the HV=1 PR=0 case is handled earlier by simply using
1091 * spr_write_generic for HV mode in the SPR table
1092 */
1093
1094 /* Build insertion mask into t1 based on context */
1095 if (ctx->pr) {
1096 gen_load_spr(t1, SPR_UAMOR);
1097 } else {
1098 gen_load_spr(t1, SPR_AMOR);
1099 }
1100
1101 /* Mask new bits into t2 */
1102 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1103
1104 /* Load AMR and clear new bits in t0 */
1105 gen_load_spr(t0, SPR_AMR);
1106 tcg_gen_andc_tl(t0, t0, t1);
1107
1108 /* Or'in new bits and write it out */
1109 tcg_gen_or_tl(t0, t0, t2);
1110 gen_store_spr(SPR_AMR, t0);
1111 spr_store_dump_spr(SPR_AMR);
1112 }
1113
spr_write_uamor(DisasContext * ctx,int sprn,int gprn)1114 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1115 {
1116 TCGv t0 = tcg_temp_new();
1117 TCGv t1 = tcg_temp_new();
1118 TCGv t2 = tcg_temp_new();
1119
1120 /*
1121 * Note, the HV=1 case is handled earlier by simply using
1122 * spr_write_generic for HV mode in the SPR table
1123 */
1124
1125 /* Build insertion mask into t1 based on context */
1126 gen_load_spr(t1, SPR_AMOR);
1127
1128 /* Mask new bits into t2 */
1129 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1130
1131 /* Load AMR and clear new bits in t0 */
1132 gen_load_spr(t0, SPR_UAMOR);
1133 tcg_gen_andc_tl(t0, t0, t1);
1134
1135 /* Or'in new bits and write it out */
1136 tcg_gen_or_tl(t0, t0, t2);
1137 gen_store_spr(SPR_UAMOR, t0);
1138 spr_store_dump_spr(SPR_UAMOR);
1139 }
1140
spr_write_iamr(DisasContext * ctx,int sprn,int gprn)1141 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1142 {
1143 TCGv t0 = tcg_temp_new();
1144 TCGv t1 = tcg_temp_new();
1145 TCGv t2 = tcg_temp_new();
1146
1147 /*
1148 * Note, the HV=1 case is handled earlier by simply using
1149 * spr_write_generic for HV mode in the SPR table
1150 */
1151
1152 /* Build insertion mask into t1 based on context */
1153 gen_load_spr(t1, SPR_AMOR);
1154
1155 /* Mask new bits into t2 */
1156 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1157
1158 /* Load AMR and clear new bits in t0 */
1159 gen_load_spr(t0, SPR_IAMR);
1160 tcg_gen_andc_tl(t0, t0, t1);
1161
1162 /* Or'in new bits and write it out */
1163 tcg_gen_or_tl(t0, t0, t2);
1164 gen_store_spr(SPR_IAMR, t0);
1165 spr_store_dump_spr(SPR_IAMR);
1166 }
1167 #endif
1168 #endif
1169
1170 #ifndef CONFIG_USER_ONLY
spr_read_thrm(DisasContext * ctx,int gprn,int sprn)1171 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1172 {
1173 gen_helper_fixup_thrm(tcg_env);
1174 gen_load_spr(cpu_gpr[gprn], sprn);
1175 spr_load_dump_spr(sprn);
1176 }
1177 #endif /* !CONFIG_USER_ONLY */
1178
1179 #if !defined(CONFIG_USER_ONLY)
spr_write_e500_l1csr0(DisasContext * ctx,int sprn,int gprn)1180 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1181 {
1182 TCGv t0 = tcg_temp_new();
1183
1184 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1185 gen_store_spr(sprn, t0);
1186 }
1187
spr_write_e500_l1csr1(DisasContext * ctx,int sprn,int gprn)1188 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1189 {
1190 TCGv t0 = tcg_temp_new();
1191
1192 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1193 gen_store_spr(sprn, t0);
1194 }
1195
spr_write_e500_l2csr0(DisasContext * ctx,int sprn,int gprn)1196 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
1197 {
1198 TCGv t0 = tcg_temp_new();
1199
1200 tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1201 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1202 gen_store_spr(sprn, t0);
1203 }
1204
spr_write_booke206_mmucsr0(DisasContext * ctx,int sprn,int gprn)1205 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1206 {
1207 gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]);
1208 }
1209
spr_write_booke_pid(DisasContext * ctx,int sprn,int gprn)1210 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1211 {
1212 TCGv_i32 t0 = tcg_constant_i32(sprn);
1213 gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]);
1214 }
1215
spr_write_eplc(DisasContext * ctx,int sprn,int gprn)1216 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1217 {
1218 gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]);
1219 }
1220
spr_write_epsc(DisasContext * ctx,int sprn,int gprn)1221 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1222 {
1223 gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]);
1224 }
1225
1226 #endif
1227
1228 #if !defined(CONFIG_USER_ONLY)
spr_write_mas73(DisasContext * ctx,int sprn,int gprn)1229 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
1230 {
1231 TCGv val = tcg_temp_new();
1232 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1233 gen_store_spr(SPR_BOOKE_MAS3, val);
1234 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1235 gen_store_spr(SPR_BOOKE_MAS7, val);
1236 }
1237
spr_read_mas73(DisasContext * ctx,int gprn,int sprn)1238 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
1239 {
1240 TCGv mas7 = tcg_temp_new();
1241 TCGv mas3 = tcg_temp_new();
1242 gen_load_spr(mas7, SPR_BOOKE_MAS7);
1243 tcg_gen_shli_tl(mas7, mas7, 32);
1244 gen_load_spr(mas3, SPR_BOOKE_MAS3);
1245 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1246 }
1247
1248 #endif
1249
1250 #ifdef TARGET_PPC64
gen_fscr_facility_check(DisasContext * ctx,int facility_sprn,int bit,int sprn,int cause)1251 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1252 int bit, int sprn, int cause)
1253 {
1254 TCGv_i32 t1 = tcg_constant_i32(bit);
1255 TCGv_i32 t2 = tcg_constant_i32(sprn);
1256 TCGv_i32 t3 = tcg_constant_i32(cause);
1257
1258 gen_helper_fscr_facility_check(tcg_env, t1, t2, t3);
1259 }
1260
gen_msr_facility_check(DisasContext * ctx,int facility_sprn,int bit,int sprn,int cause)1261 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1262 int bit, int sprn, int cause)
1263 {
1264 TCGv_i32 t1 = tcg_constant_i32(bit);
1265 TCGv_i32 t2 = tcg_constant_i32(sprn);
1266 TCGv_i32 t3 = tcg_constant_i32(cause);
1267
1268 gen_helper_msr_facility_check(tcg_env, t1, t2, t3);
1269 }
1270
spr_read_prev_upper32(DisasContext * ctx,int gprn,int sprn)1271 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
1272 {
1273 TCGv spr_up = tcg_temp_new();
1274 TCGv spr = tcg_temp_new();
1275
1276 gen_load_spr(spr, sprn - 1);
1277 tcg_gen_shri_tl(spr_up, spr, 32);
1278 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1279 }
1280
spr_write_prev_upper32(DisasContext * ctx,int sprn,int gprn)1281 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
1282 {
1283 TCGv spr = tcg_temp_new();
1284
1285 gen_load_spr(spr, sprn - 1);
1286 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1287 gen_store_spr(sprn - 1, spr);
1288 }
1289
1290 #if !defined(CONFIG_USER_ONLY)
spr_write_hmer(DisasContext * ctx,int sprn,int gprn)1291 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
1292 {
1293 TCGv hmer = tcg_temp_new();
1294
1295 gen_load_spr(hmer, sprn);
1296 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1297 gen_store_spr(sprn, hmer);
1298 spr_store_dump_spr(sprn);
1299 }
1300
spr_read_tfmr(DisasContext * ctx,int gprn,int sprn)1301 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn)
1302 {
1303 /* Reading TFMR can cause it to be updated, so serialize threads here too */
1304 if (!gen_serialize_core(ctx)) {
1305 return;
1306 }
1307 gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env);
1308 }
1309
spr_write_tfmr(DisasContext * ctx,int sprn,int gprn)1310 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn)
1311 {
1312 if (!gen_serialize_core(ctx)) {
1313 return;
1314 }
1315 gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]);
1316 }
1317
spr_write_sprc(DisasContext * ctx,int sprn,int gprn)1318 void spr_write_sprc(DisasContext *ctx, int sprn, int gprn)
1319 {
1320 gen_helper_store_sprc(tcg_env, cpu_gpr[gprn]);
1321 }
1322
spr_read_sprd(DisasContext * ctx,int gprn,int sprn)1323 void spr_read_sprd(DisasContext *ctx, int gprn, int sprn)
1324 {
1325 gen_helper_load_sprd(cpu_gpr[gprn], tcg_env);
1326 }
1327
spr_write_sprd(DisasContext * ctx,int sprn,int gprn)1328 void spr_write_sprd(DisasContext *ctx, int sprn, int gprn)
1329 {
1330 if (!gen_serialize_core(ctx)) {
1331 return;
1332 }
1333 gen_helper_store_sprd(tcg_env, cpu_gpr[gprn]);
1334 }
1335
spr_write_lpcr(DisasContext * ctx,int sprn,int gprn)1336 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
1337 {
1338 translator_io_start(&ctx->base);
1339 gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]);
1340 }
1341
spr_read_pmsr(DisasContext * ctx,int gprn,int sprn)1342 void spr_read_pmsr(DisasContext *ctx, int gprn, int sprn)
1343 {
1344 translator_io_start(&ctx->base);
1345 gen_helper_load_pmsr(cpu_gpr[gprn], tcg_env);
1346 }
1347
spr_write_pmcr(DisasContext * ctx,int sprn,int gprn)1348 void spr_write_pmcr(DisasContext *ctx, int sprn, int gprn)
1349 {
1350 if (!gen_serialize_core_lpar(ctx)) {
1351 return;
1352 }
1353 translator_io_start(&ctx->base);
1354 gen_helper_store_pmcr(tcg_env, cpu_gpr[gprn]);
1355 }
1356
1357 #endif /* !defined(CONFIG_USER_ONLY) */
1358
spr_read_tar(DisasContext * ctx,int gprn,int sprn)1359 void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
1360 {
1361 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1362 spr_read_generic(ctx, gprn, sprn);
1363 }
1364
spr_write_tar(DisasContext * ctx,int sprn,int gprn)1365 void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
1366 {
1367 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1368 spr_write_generic(ctx, sprn, gprn);
1369 }
1370
spr_read_tm(DisasContext * ctx,int gprn,int sprn)1371 void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
1372 {
1373 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1374 spr_read_generic(ctx, gprn, sprn);
1375 }
1376
spr_write_tm(DisasContext * ctx,int sprn,int gprn)1377 void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
1378 {
1379 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1380 spr_write_generic(ctx, sprn, gprn);
1381 }
1382
spr_read_tm_upper32(DisasContext * ctx,int gprn,int sprn)1383 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
1384 {
1385 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1386 spr_read_prev_upper32(ctx, gprn, sprn);
1387 }
1388
spr_write_tm_upper32(DisasContext * ctx,int sprn,int gprn)1389 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
1390 {
1391 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1392 spr_write_prev_upper32(ctx, sprn, gprn);
1393 }
1394
spr_read_ebb(DisasContext * ctx,int gprn,int sprn)1395 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
1396 {
1397 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1398 spr_read_generic(ctx, gprn, sprn);
1399 }
1400
spr_write_ebb(DisasContext * ctx,int sprn,int gprn)1401 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
1402 {
1403 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1404 spr_write_generic(ctx, sprn, gprn);
1405 }
1406
spr_read_ebb_upper32(DisasContext * ctx,int gprn,int sprn)1407 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
1408 {
1409 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1410 spr_read_prev_upper32(ctx, gprn, sprn);
1411 }
1412
spr_write_ebb_upper32(DisasContext * ctx,int sprn,int gprn)1413 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
1414 {
1415 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1416 spr_write_prev_upper32(ctx, sprn, gprn);
1417 }
1418
spr_read_dexcr_ureg(DisasContext * ctx,int gprn,int sprn)1419 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn)
1420 {
1421 TCGv t0 = tcg_temp_new();
1422
1423 /*
1424 * Access to the (H)DEXCR in problem state is done using separated
1425 * SPR indexes which are 16 below the SPR indexes which have full
1426 * access to the (H)DEXCR in privileged state. Problem state can
1427 * only read bits 32:63, bits 0:31 return 0.
1428 *
1429 * See section 9.3.1-9.3.2 of PowerISA v3.1B
1430 */
1431
1432 gen_load_spr(t0, sprn + 16);
1433 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0);
1434 }
1435
1436 /* The PPR32 SPR accesses the upper 32-bits of PPR */
spr_read_ppr32(DisasContext * ctx,int gprn,int sprn)1437 void spr_read_ppr32(DisasContext *ctx, int gprn, int sprn)
1438 {
1439 gen_load_spr(cpu_gpr[gprn], SPR_PPR);
1440 tcg_gen_shri_tl(cpu_gpr[gprn], cpu_gpr[gprn], 32);
1441 spr_load_dump_spr(SPR_PPR);
1442 }
1443
spr_write_ppr32(DisasContext * ctx,int sprn,int gprn)1444 void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn)
1445 {
1446 TCGv t0 = tcg_temp_new();
1447
1448 /*
1449 * Don't clobber the low 32-bits of the PPR. These are all reserved bits
1450 * but TCG does implement them, so it would be surprising to zero them
1451 * here. "Priority nops" are similarly careful not to clobber reserved
1452 * bits.
1453 */
1454 gen_load_spr(t0, SPR_PPR);
1455 tcg_gen_deposit_tl(t0, t0, cpu_gpr[gprn], 32, 32);
1456 gen_store_spr(SPR_PPR, t0);
1457 spr_store_dump_spr(SPR_PPR);
1458 }
1459 #endif
1460
1461 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
1462 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1463
1464 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
1465 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1466
1467 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
1468 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1469
1470 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
1471 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1472
1473 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
1474 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1475
1476 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1477 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1478
1479 typedef struct opcode_t {
1480 unsigned char opc1, opc2, opc3, opc4;
1481 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1482 unsigned char pad[4];
1483 #endif
1484 opc_handler_t handler;
1485 const char *oname;
1486 } opcode_t;
1487
gen_priv_opc(DisasContext * ctx)1488 static void gen_priv_opc(DisasContext *ctx)
1489 {
1490 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
1491 }
1492
1493 /* Helpers for priv. check */
1494 #define GEN_PRIV(CTX) \
1495 do { \
1496 gen_priv_opc(CTX); return; \
1497 } while (0)
1498
1499 #if defined(CONFIG_USER_ONLY)
1500 #define CHK_HV(CTX) GEN_PRIV(CTX)
1501 #define CHK_SV(CTX) GEN_PRIV(CTX)
1502 #define CHK_HVRM(CTX) GEN_PRIV(CTX)
1503 #else
1504 #define CHK_HV(CTX) \
1505 do { \
1506 if (unlikely(ctx->pr || !ctx->hv)) {\
1507 GEN_PRIV(CTX); \
1508 } \
1509 } while (0)
1510 #define CHK_SV(CTX) \
1511 do { \
1512 if (unlikely(ctx->pr)) { \
1513 GEN_PRIV(CTX); \
1514 } \
1515 } while (0)
1516 #define CHK_HVRM(CTX) \
1517 do { \
1518 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1519 GEN_PRIV(CTX); \
1520 } \
1521 } while (0)
1522 #endif
1523
1524 #define CHK_NONE(CTX)
1525
1526 /*****************************************************************************/
1527 /* PowerPC instructions table */
1528
1529 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1530 { \
1531 .opc1 = op1, \
1532 .opc2 = op2, \
1533 .opc3 = op3, \
1534 .opc4 = 0xff, \
1535 .handler = { \
1536 .inval1 = invl, \
1537 .type = _typ, \
1538 .type2 = _typ2, \
1539 .handler = &gen_##name, \
1540 }, \
1541 .oname = stringify(name), \
1542 }
1543 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1544 { \
1545 .opc1 = op1, \
1546 .opc2 = op2, \
1547 .opc3 = op3, \
1548 .opc4 = 0xff, \
1549 .handler = { \
1550 .inval1 = invl1, \
1551 .inval2 = invl2, \
1552 .type = _typ, \
1553 .type2 = _typ2, \
1554 .handler = &gen_##name, \
1555 }, \
1556 .oname = stringify(name), \
1557 }
1558 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1559 { \
1560 .opc1 = op1, \
1561 .opc2 = op2, \
1562 .opc3 = op3, \
1563 .opc4 = 0xff, \
1564 .handler = { \
1565 .inval1 = invl, \
1566 .type = _typ, \
1567 .type2 = _typ2, \
1568 .handler = &gen_##name, \
1569 }, \
1570 .oname = onam, \
1571 }
1572 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1573 { \
1574 .opc1 = op1, \
1575 .opc2 = op2, \
1576 .opc3 = op3, \
1577 .opc4 = op4, \
1578 .handler = { \
1579 .inval1 = invl, \
1580 .type = _typ, \
1581 .type2 = _typ2, \
1582 .handler = &gen_##name, \
1583 }, \
1584 .oname = stringify(name), \
1585 }
1586 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1587 { \
1588 .opc1 = op1, \
1589 .opc2 = op2, \
1590 .opc3 = op3, \
1591 .opc4 = op4, \
1592 .handler = { \
1593 .inval1 = invl, \
1594 .type = _typ, \
1595 .type2 = _typ2, \
1596 .handler = &gen_##name, \
1597 }, \
1598 .oname = onam, \
1599 }
1600
1601 /* Invalid instruction */
gen_invalid(DisasContext * ctx)1602 static void gen_invalid(DisasContext *ctx)
1603 {
1604 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1605 }
1606
1607 static opc_handler_t invalid_handler = {
1608 .inval1 = 0xFFFFFFFF,
1609 .inval2 = 0xFFFFFFFF,
1610 .type = PPC_NONE,
1611 .type2 = PPC_NONE,
1612 .handler = gen_invalid,
1613 };
1614
1615 /*** Integer comparison ***/
1616
gen_op_cmp(TCGv arg0,TCGv arg1,int s,int crf)1617 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
1618 {
1619 TCGv t0 = tcg_temp_new();
1620 TCGv_i32 t = tcg_temp_new_i32();
1621
1622 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1623 t0, arg0, arg1,
1624 tcg_constant_tl(CRF_LT), tcg_constant_tl(CRF_EQ));
1625 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1626 t0, arg0, arg1, tcg_constant_tl(CRF_GT), t0);
1627
1628 tcg_gen_trunc_tl_i32(t, t0);
1629 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1630 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
1631 }
1632
gen_op_cmpi(TCGv arg0,target_ulong arg1,int s,int crf)1633 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
1634 {
1635 TCGv t0 = tcg_constant_tl(arg1);
1636 gen_op_cmp(arg0, t0, s, crf);
1637 }
1638
gen_op_cmp32(TCGv arg0,TCGv arg1,int s,int crf)1639 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
1640 {
1641 TCGv t0, t1;
1642 t0 = tcg_temp_new();
1643 t1 = tcg_temp_new();
1644 if (s) {
1645 tcg_gen_ext32s_tl(t0, arg0);
1646 tcg_gen_ext32s_tl(t1, arg1);
1647 } else {
1648 tcg_gen_ext32u_tl(t0, arg0);
1649 tcg_gen_ext32u_tl(t1, arg1);
1650 }
1651 gen_op_cmp(t0, t1, s, crf);
1652 }
1653
gen_op_cmpi32(TCGv arg0,target_ulong arg1,int s,int crf)1654 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
1655 {
1656 TCGv t0 = tcg_constant_tl(arg1);
1657 gen_op_cmp32(arg0, t0, s, crf);
1658 }
1659
gen_set_Rc0(DisasContext * ctx,TCGv reg)1660 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
1661 {
1662 if (NARROW_MODE(ctx)) {
1663 gen_op_cmpi32(reg, 0, 1, 0);
1664 } else {
1665 gen_op_cmpi(reg, 0, 1, 0);
1666 }
1667 }
1668
1669 /*** Integer arithmetic ***/
1670
gen_op_arith_compute_ov(DisasContext * ctx,TCGv arg0,TCGv arg1,TCGv arg2,int sub)1671 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1672 TCGv arg1, TCGv arg2, int sub)
1673 {
1674 TCGv t0 = tcg_temp_new();
1675
1676 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
1677 tcg_gen_xor_tl(t0, arg1, arg2);
1678 if (sub) {
1679 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1680 } else {
1681 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1682 }
1683 if (NARROW_MODE(ctx)) {
1684 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1685 if (is_isa300(ctx)) {
1686 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1687 }
1688 } else {
1689 if (is_isa300(ctx)) {
1690 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1691 }
1692 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
1693 }
1694 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1695 }
1696
gen_op_arith_compute_ca32(DisasContext * ctx,TCGv res,TCGv arg0,TCGv arg1,TCGv ca32,int sub)1697 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1698 TCGv res, TCGv arg0, TCGv arg1,
1699 TCGv ca32, int sub)
1700 {
1701 TCGv t0;
1702
1703 if (!is_isa300(ctx)) {
1704 return;
1705 }
1706
1707 t0 = tcg_temp_new();
1708 if (sub) {
1709 tcg_gen_eqv_tl(t0, arg0, arg1);
1710 } else {
1711 tcg_gen_xor_tl(t0, arg0, arg1);
1712 }
1713 tcg_gen_xor_tl(t0, t0, res);
1714 tcg_gen_extract_tl(ca32, t0, 32, 1);
1715 }
1716
1717 /* Common add function */
gen_op_arith_add(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,TCGv ca,TCGv ca32,bool add_ca,bool compute_ca,bool compute_ov,bool compute_rc0)1718 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
1719 TCGv arg2, TCGv ca, TCGv ca32,
1720 bool add_ca, bool compute_ca,
1721 bool compute_ov, bool compute_rc0)
1722 {
1723 TCGv t0 = ret;
1724
1725 if (compute_ca || compute_ov) {
1726 t0 = tcg_temp_new();
1727 }
1728
1729 if (compute_ca) {
1730 if (NARROW_MODE(ctx)) {
1731 /*
1732 * Caution: a non-obvious corner case of the spec is that
1733 * we must produce the *entire* 64-bit addition, but
1734 * produce the carry into bit 32.
1735 */
1736 TCGv t1 = tcg_temp_new();
1737 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
1738 tcg_gen_add_tl(t0, arg1, arg2);
1739 if (add_ca) {
1740 tcg_gen_add_tl(t0, t0, ca);
1741 }
1742 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */
1743 tcg_gen_extract_tl(ca, ca, 32, 1);
1744 if (is_isa300(ctx)) {
1745 tcg_gen_mov_tl(ca32, ca);
1746 }
1747 } else {
1748 if (add_ca) {
1749 tcg_gen_addcio_tl(t0, ca, arg1, arg2, ca);
1750 } else {
1751 TCGv zero = tcg_constant_tl(0);
1752 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
1753 }
1754 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
1755 }
1756 } else {
1757 tcg_gen_add_tl(t0, arg1, arg2);
1758 if (add_ca) {
1759 tcg_gen_add_tl(t0, t0, ca);
1760 }
1761 }
1762
1763 if (compute_ov) {
1764 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1765 }
1766 if (unlikely(compute_rc0)) {
1767 gen_set_Rc0(ctx, t0);
1768 }
1769
1770 if (t0 != ret) {
1771 tcg_gen_mov_tl(ret, t0);
1772 }
1773 }
1774
gen_op_arith_divw(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,bool sign,bool compute_ov,bool compute_rc0)1775 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret,
1776 TCGv arg1, TCGv arg2, bool sign,
1777 bool compute_ov, bool compute_rc0)
1778 {
1779 TCGv_i32 t0 = tcg_temp_new_i32();
1780 TCGv_i32 t1 = tcg_temp_new_i32();
1781 TCGv_i32 t2 = tcg_temp_new_i32();
1782 TCGv_i32 t3 = tcg_temp_new_i32();
1783
1784 tcg_gen_trunc_tl_i32(t0, arg1);
1785 tcg_gen_trunc_tl_i32(t1, arg2);
1786 if (sign) {
1787 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1788 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1789 tcg_gen_and_i32(t2, t2, t3);
1790 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1791 tcg_gen_or_i32(t2, t2, t3);
1792 tcg_gen_movi_i32(t3, 0);
1793 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1794 tcg_gen_div_i32(t3, t0, t1);
1795 tcg_gen_extu_i32_tl(ret, t3);
1796 } else {
1797 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1798 tcg_gen_movi_i32(t3, 0);
1799 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1800 tcg_gen_divu_i32(t3, t0, t1);
1801 tcg_gen_extu_i32_tl(ret, t3);
1802 }
1803 if (compute_ov) {
1804 tcg_gen_extu_i32_tl(cpu_ov, t2);
1805 if (is_isa300(ctx)) {
1806 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1807 }
1808 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1809 }
1810
1811 if (unlikely(compute_rc0)) {
1812 gen_set_Rc0(ctx, ret);
1813 }
1814 }
1815
1816 #if defined(TARGET_PPC64)
gen_op_arith_divd(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,bool sign,bool compute_ov,bool compute_rc0)1817 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret,
1818 TCGv arg1, TCGv arg2, bool sign,
1819 bool compute_ov, bool compute_rc0)
1820 {
1821 TCGv_i64 t0 = tcg_temp_new_i64();
1822 TCGv_i64 t1 = tcg_temp_new_i64();
1823 TCGv_i64 t2 = tcg_temp_new_i64();
1824 TCGv_i64 t3 = tcg_temp_new_i64();
1825
1826 tcg_gen_mov_i64(t0, arg1);
1827 tcg_gen_mov_i64(t1, arg2);
1828 if (sign) {
1829 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1830 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1831 tcg_gen_and_i64(t2, t2, t3);
1832 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1833 tcg_gen_or_i64(t2, t2, t3);
1834 tcg_gen_movi_i64(t3, 0);
1835 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1836 tcg_gen_div_i64(ret, t0, t1);
1837 } else {
1838 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1839 tcg_gen_movi_i64(t3, 0);
1840 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1841 tcg_gen_divu_i64(ret, t0, t1);
1842 }
1843 if (compute_ov) {
1844 tcg_gen_mov_tl(cpu_ov, t2);
1845 if (is_isa300(ctx)) {
1846 tcg_gen_mov_tl(cpu_ov32, t2);
1847 }
1848 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1849 }
1850
1851 if (unlikely(compute_rc0)) {
1852 gen_set_Rc0(ctx, ret);
1853 }
1854 }
1855 #endif
1856
gen_op_arith_modw(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,int sign)1857 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1858 TCGv arg2, int sign)
1859 {
1860 TCGv_i32 t0 = tcg_temp_new_i32();
1861 TCGv_i32 t1 = tcg_temp_new_i32();
1862
1863 tcg_gen_trunc_tl_i32(t0, arg1);
1864 tcg_gen_trunc_tl_i32(t1, arg2);
1865 if (sign) {
1866 TCGv_i32 t2 = tcg_temp_new_i32();
1867 TCGv_i32 t3 = tcg_temp_new_i32();
1868 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1869 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1870 tcg_gen_and_i32(t2, t2, t3);
1871 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1872 tcg_gen_or_i32(t2, t2, t3);
1873 tcg_gen_movi_i32(t3, 0);
1874 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1875 tcg_gen_rem_i32(t3, t0, t1);
1876 tcg_gen_ext_i32_tl(ret, t3);
1877 } else {
1878 TCGv_i32 t2 = tcg_constant_i32(1);
1879 TCGv_i32 t3 = tcg_constant_i32(0);
1880 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1881 tcg_gen_remu_i32(t0, t0, t1);
1882 tcg_gen_extu_i32_tl(ret, t0);
1883 }
1884 }
1885
1886 #if defined(TARGET_PPC64)
gen_op_arith_modd(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,int sign)1887 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1888 TCGv arg2, int sign)
1889 {
1890 TCGv_i64 t0 = tcg_temp_new_i64();
1891 TCGv_i64 t1 = tcg_temp_new_i64();
1892
1893 tcg_gen_mov_i64(t0, arg1);
1894 tcg_gen_mov_i64(t1, arg2);
1895 if (sign) {
1896 TCGv_i64 t2 = tcg_temp_new_i64();
1897 TCGv_i64 t3 = tcg_temp_new_i64();
1898 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1899 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1900 tcg_gen_and_i64(t2, t2, t3);
1901 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1902 tcg_gen_or_i64(t2, t2, t3);
1903 tcg_gen_movi_i64(t3, 0);
1904 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1905 tcg_gen_rem_i64(ret, t0, t1);
1906 } else {
1907 TCGv_i64 t2 = tcg_constant_i64(1);
1908 TCGv_i64 t3 = tcg_constant_i64(0);
1909 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1910 tcg_gen_remu_i64(ret, t0, t1);
1911 }
1912 }
1913 #endif
1914
1915 /* Common subf function */
gen_op_arith_subf(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,bool add_ca,bool compute_ca,bool compute_ov,bool compute_rc0)1916 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1917 TCGv arg2, bool add_ca, bool compute_ca,
1918 bool compute_ov, bool compute_rc0)
1919 {
1920 TCGv t0 = ret;
1921
1922 if (compute_ca || compute_ov) {
1923 t0 = tcg_temp_new();
1924 }
1925
1926 if (compute_ca) {
1927 /* dest = ~arg1 + arg2 [+ ca]. */
1928 if (NARROW_MODE(ctx)) {
1929 /*
1930 * Caution: a non-obvious corner case of the spec is that
1931 * we must produce the *entire* 64-bit addition, but
1932 * produce the carry into bit 32.
1933 */
1934 TCGv inv1 = tcg_temp_new();
1935 TCGv t1 = tcg_temp_new();
1936 tcg_gen_not_tl(inv1, arg1);
1937 if (add_ca) {
1938 tcg_gen_add_tl(t0, arg2, cpu_ca);
1939 } else {
1940 tcg_gen_addi_tl(t0, arg2, 1);
1941 }
1942 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1943 tcg_gen_add_tl(t0, t0, inv1);
1944 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1945 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1946 if (is_isa300(ctx)) {
1947 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1948 }
1949 } else if (add_ca) {
1950 TCGv inv1 = tcg_temp_new();
1951 tcg_gen_not_tl(inv1, arg1);
1952 tcg_gen_addcio_tl(t0, cpu_ca, arg2, inv1, cpu_ca);
1953 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
1954 } else {
1955 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1956 tcg_gen_sub_tl(t0, arg2, arg1);
1957 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
1958 }
1959 } else if (add_ca) {
1960 /*
1961 * Since we're ignoring carry-out, we can simplify the
1962 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
1963 */
1964 tcg_gen_sub_tl(t0, arg2, arg1);
1965 tcg_gen_add_tl(t0, t0, cpu_ca);
1966 tcg_gen_subi_tl(t0, t0, 1);
1967 } else {
1968 tcg_gen_sub_tl(t0, arg2, arg1);
1969 }
1970
1971 if (compute_ov) {
1972 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1973 }
1974 if (unlikely(compute_rc0)) {
1975 gen_set_Rc0(ctx, t0);
1976 }
1977
1978 if (t0 != ret) {
1979 tcg_gen_mov_tl(ret, t0);
1980 }
1981 }
1982
1983 /*** Integer logical ***/
1984
1985 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
gen_pause(DisasContext * ctx)1986 static void gen_pause(DisasContext *ctx)
1987 {
1988 TCGv_i32 t0 = tcg_constant_i32(0);
1989 tcg_gen_st_i32(t0, tcg_env,
1990 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1991
1992 /* Stop translation, this gives other CPUs a chance to run */
1993 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
1994 }
1995 #endif /* defined(TARGET_PPC64) */
1996
1997 /*** Integer rotate ***/
1998
1999 /* rlwimi & rlwimi. */
gen_rlwimi(DisasContext * ctx)2000 static void gen_rlwimi(DisasContext *ctx)
2001 {
2002 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2003 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2004 uint32_t sh = SH(ctx->opcode);
2005 uint32_t mb = MB(ctx->opcode);
2006 uint32_t me = ME(ctx->opcode);
2007
2008 if (sh == (31 - me) && mb <= me) {
2009 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2010 } else {
2011 target_ulong mask;
2012 bool mask_in_32b = true;
2013 TCGv t1;
2014
2015 #if defined(TARGET_PPC64)
2016 mb += 32;
2017 me += 32;
2018 #endif
2019 mask = MASK(mb, me);
2020
2021 #if defined(TARGET_PPC64)
2022 if (mask > 0xffffffffu) {
2023 mask_in_32b = false;
2024 }
2025 #endif
2026 t1 = tcg_temp_new();
2027 if (mask_in_32b) {
2028 TCGv_i32 t0 = tcg_temp_new_i32();
2029 tcg_gen_trunc_tl_i32(t0, t_rs);
2030 tcg_gen_rotli_i32(t0, t0, sh);
2031 tcg_gen_extu_i32_tl(t1, t0);
2032 } else {
2033 #if defined(TARGET_PPC64)
2034 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2035 tcg_gen_rotli_i64(t1, t1, sh);
2036 #else
2037 g_assert_not_reached();
2038 #endif
2039 }
2040
2041 tcg_gen_andi_tl(t1, t1, mask);
2042 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2043 tcg_gen_or_tl(t_ra, t_ra, t1);
2044 }
2045 if (unlikely(Rc(ctx->opcode) != 0)) {
2046 gen_set_Rc0(ctx, t_ra);
2047 }
2048 }
2049
2050 /* rlwinm & rlwinm. */
gen_rlwinm(DisasContext * ctx)2051 static void gen_rlwinm(DisasContext *ctx)
2052 {
2053 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2054 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2055 int sh = SH(ctx->opcode);
2056 int mb = MB(ctx->opcode);
2057 int me = ME(ctx->opcode);
2058 int len = me - mb + 1;
2059 int rsh = (32 - sh) & 31;
2060
2061 if (sh != 0 && len > 0 && me == (31 - sh)) {
2062 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2063 } else if (me == 31 && rsh + len <= 32) {
2064 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2065 } else {
2066 target_ulong mask;
2067 bool mask_in_32b = true;
2068 #if defined(TARGET_PPC64)
2069 mb += 32;
2070 me += 32;
2071 #endif
2072 mask = MASK(mb, me);
2073 #if defined(TARGET_PPC64)
2074 if (mask > 0xffffffffu) {
2075 mask_in_32b = false;
2076 }
2077 #endif
2078 if (mask_in_32b) {
2079 if (sh == 0) {
2080 tcg_gen_andi_tl(t_ra, t_rs, mask);
2081 } else {
2082 TCGv_i32 t0 = tcg_temp_new_i32();
2083 tcg_gen_trunc_tl_i32(t0, t_rs);
2084 tcg_gen_rotli_i32(t0, t0, sh);
2085 tcg_gen_andi_i32(t0, t0, mask);
2086 tcg_gen_extu_i32_tl(t_ra, t0);
2087 }
2088 } else {
2089 #if defined(TARGET_PPC64)
2090 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2091 tcg_gen_rotli_i64(t_ra, t_ra, sh);
2092 tcg_gen_andi_i64(t_ra, t_ra, mask);
2093 #else
2094 g_assert_not_reached();
2095 #endif
2096 }
2097 }
2098 if (unlikely(Rc(ctx->opcode) != 0)) {
2099 gen_set_Rc0(ctx, t_ra);
2100 }
2101 }
2102
2103 /* rlwnm & rlwnm. */
gen_rlwnm(DisasContext * ctx)2104 static void gen_rlwnm(DisasContext *ctx)
2105 {
2106 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2107 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2108 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2109 uint32_t mb = MB(ctx->opcode);
2110 uint32_t me = ME(ctx->opcode);
2111 target_ulong mask;
2112 bool mask_in_32b = true;
2113
2114 #if defined(TARGET_PPC64)
2115 mb += 32;
2116 me += 32;
2117 #endif
2118 mask = MASK(mb, me);
2119
2120 #if defined(TARGET_PPC64)
2121 if (mask > 0xffffffffu) {
2122 mask_in_32b = false;
2123 }
2124 #endif
2125 if (mask_in_32b) {
2126 TCGv_i32 t0 = tcg_temp_new_i32();
2127 TCGv_i32 t1 = tcg_temp_new_i32();
2128 tcg_gen_trunc_tl_i32(t0, t_rb);
2129 tcg_gen_trunc_tl_i32(t1, t_rs);
2130 tcg_gen_andi_i32(t0, t0, 0x1f);
2131 tcg_gen_rotl_i32(t1, t1, t0);
2132 tcg_gen_extu_i32_tl(t_ra, t1);
2133 } else {
2134 #if defined(TARGET_PPC64)
2135 TCGv_i64 t0 = tcg_temp_new_i64();
2136 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2137 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2138 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2139 #else
2140 g_assert_not_reached();
2141 #endif
2142 }
2143
2144 tcg_gen_andi_tl(t_ra, t_ra, mask);
2145
2146 if (unlikely(Rc(ctx->opcode) != 0)) {
2147 gen_set_Rc0(ctx, t_ra);
2148 }
2149 }
2150
2151 #if defined(TARGET_PPC64)
2152 #define GEN_PPC64_R2(name, opc1, opc2) \
2153 static void glue(gen_, name##0)(DisasContext *ctx) \
2154 { \
2155 gen_##name(ctx, 0); \
2156 } \
2157 \
2158 static void glue(gen_, name##1)(DisasContext *ctx) \
2159 { \
2160 gen_##name(ctx, 1); \
2161 }
2162 #define GEN_PPC64_R4(name, opc1, opc2) \
2163 static void glue(gen_, name##0)(DisasContext *ctx) \
2164 { \
2165 gen_##name(ctx, 0, 0); \
2166 } \
2167 \
2168 static void glue(gen_, name##1)(DisasContext *ctx) \
2169 { \
2170 gen_##name(ctx, 0, 1); \
2171 } \
2172 \
2173 static void glue(gen_, name##2)(DisasContext *ctx) \
2174 { \
2175 gen_##name(ctx, 1, 0); \
2176 } \
2177 \
2178 static void glue(gen_, name##3)(DisasContext *ctx) \
2179 { \
2180 gen_##name(ctx, 1, 1); \
2181 }
2182
gen_rldinm(DisasContext * ctx,int mb,int me,int sh)2183 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2184 {
2185 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2186 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2187 int len = me - mb + 1;
2188 int rsh = (64 - sh) & 63;
2189
2190 if (sh != 0 && len > 0 && me == (63 - sh)) {
2191 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2192 } else if (me == 63 && rsh + len <= 64) {
2193 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2194 } else {
2195 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2196 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2197 }
2198 if (unlikely(Rc(ctx->opcode) != 0)) {
2199 gen_set_Rc0(ctx, t_ra);
2200 }
2201 }
2202
2203 /* rldicl - rldicl. */
gen_rldicl(DisasContext * ctx,int mbn,int shn)2204 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2205 {
2206 uint32_t sh, mb;
2207
2208 sh = SH(ctx->opcode) | (shn << 5);
2209 mb = MB(ctx->opcode) | (mbn << 5);
2210 gen_rldinm(ctx, mb, 63, sh);
2211 }
2212 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2213
2214 /* rldicr - rldicr. */
gen_rldicr(DisasContext * ctx,int men,int shn)2215 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2216 {
2217 uint32_t sh, me;
2218
2219 sh = SH(ctx->opcode) | (shn << 5);
2220 me = MB(ctx->opcode) | (men << 5);
2221 gen_rldinm(ctx, 0, me, sh);
2222 }
2223 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2224
2225 /* rldic - rldic. */
gen_rldic(DisasContext * ctx,int mbn,int shn)2226 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2227 {
2228 uint32_t sh, mb;
2229
2230 sh = SH(ctx->opcode) | (shn << 5);
2231 mb = MB(ctx->opcode) | (mbn << 5);
2232 gen_rldinm(ctx, mb, 63 - sh, sh);
2233 }
2234 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2235
gen_rldnm(DisasContext * ctx,int mb,int me)2236 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2237 {
2238 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2239 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2240 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2241 TCGv t0;
2242
2243 t0 = tcg_temp_new();
2244 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2245 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2246
2247 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2248 if (unlikely(Rc(ctx->opcode) != 0)) {
2249 gen_set_Rc0(ctx, t_ra);
2250 }
2251 }
2252
2253 /* rldcl - rldcl. */
gen_rldcl(DisasContext * ctx,int mbn)2254 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2255 {
2256 uint32_t mb;
2257
2258 mb = MB(ctx->opcode) | (mbn << 5);
2259 gen_rldnm(ctx, mb, 63);
2260 }
2261 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2262
2263 /* rldcr - rldcr. */
gen_rldcr(DisasContext * ctx,int men)2264 static inline void gen_rldcr(DisasContext *ctx, int men)
2265 {
2266 uint32_t me;
2267
2268 me = MB(ctx->opcode) | (men << 5);
2269 gen_rldnm(ctx, 0, me);
2270 }
2271 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2272
2273 /* rldimi - rldimi. */
gen_rldimi(DisasContext * ctx,int mbn,int shn)2274 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2275 {
2276 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2277 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2278 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2279 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2280 uint32_t me = 63 - sh;
2281
2282 if (mb <= me) {
2283 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2284 } else {
2285 target_ulong mask = MASK(mb, me);
2286 TCGv t1 = tcg_temp_new();
2287
2288 tcg_gen_rotli_tl(t1, t_rs, sh);
2289 tcg_gen_andi_tl(t1, t1, mask);
2290 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2291 tcg_gen_or_tl(t_ra, t_ra, t1);
2292 }
2293 if (unlikely(Rc(ctx->opcode) != 0)) {
2294 gen_set_Rc0(ctx, t_ra);
2295 }
2296 }
2297 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2298 #endif
2299
2300 /*** Integer shift ***/
2301
2302 /* slw & slw. */
gen_slw(DisasContext * ctx)2303 static void gen_slw(DisasContext *ctx)
2304 {
2305 TCGv t0, t1;
2306
2307 t0 = tcg_temp_new();
2308 /* AND rS with a mask that is 0 when rB >= 0x20 */
2309 #if defined(TARGET_PPC64)
2310 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2311 tcg_gen_sari_tl(t0, t0, 0x3f);
2312 #else
2313 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2314 tcg_gen_sari_tl(t0, t0, 0x1f);
2315 #endif
2316 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2317 t1 = tcg_temp_new();
2318 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2319 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2320 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2321 if (unlikely(Rc(ctx->opcode) != 0)) {
2322 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2323 }
2324 }
2325
2326 /* sraw & sraw. */
gen_sraw(DisasContext * ctx)2327 static void gen_sraw(DisasContext *ctx)
2328 {
2329 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env,
2330 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2331 if (unlikely(Rc(ctx->opcode) != 0)) {
2332 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2333 }
2334 }
2335
2336 /* srawi & srawi. */
gen_srawi(DisasContext * ctx)2337 static void gen_srawi(DisasContext *ctx)
2338 {
2339 int sh = SH(ctx->opcode);
2340 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2341 TCGv src = cpu_gpr[rS(ctx->opcode)];
2342 if (sh == 0) {
2343 tcg_gen_ext32s_tl(dst, src);
2344 tcg_gen_movi_tl(cpu_ca, 0);
2345 if (is_isa300(ctx)) {
2346 tcg_gen_movi_tl(cpu_ca32, 0);
2347 }
2348 } else {
2349 TCGv t0;
2350 tcg_gen_ext32s_tl(dst, src);
2351 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2352 t0 = tcg_temp_new();
2353 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2354 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2355 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2356 if (is_isa300(ctx)) {
2357 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2358 }
2359 tcg_gen_sari_tl(dst, dst, sh);
2360 }
2361 if (unlikely(Rc(ctx->opcode) != 0)) {
2362 gen_set_Rc0(ctx, dst);
2363 }
2364 }
2365
2366 /* srw & srw. */
gen_srw(DisasContext * ctx)2367 static void gen_srw(DisasContext *ctx)
2368 {
2369 TCGv t0, t1;
2370
2371 t0 = tcg_temp_new();
2372 /* AND rS with a mask that is 0 when rB >= 0x20 */
2373 #if defined(TARGET_PPC64)
2374 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2375 tcg_gen_sari_tl(t0, t0, 0x3f);
2376 #else
2377 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2378 tcg_gen_sari_tl(t0, t0, 0x1f);
2379 #endif
2380 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2381 tcg_gen_ext32u_tl(t0, t0);
2382 t1 = tcg_temp_new();
2383 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2384 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2385 if (unlikely(Rc(ctx->opcode) != 0)) {
2386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2387 }
2388 }
2389
2390 #if defined(TARGET_PPC64)
2391 /* sld & sld. */
gen_sld(DisasContext * ctx)2392 static void gen_sld(DisasContext *ctx)
2393 {
2394 TCGv t0, t1;
2395
2396 t0 = tcg_temp_new();
2397 /* AND rS with a mask that is 0 when rB >= 0x40 */
2398 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2399 tcg_gen_sari_tl(t0, t0, 0x3f);
2400 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2401 t1 = tcg_temp_new();
2402 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2403 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2404 if (unlikely(Rc(ctx->opcode) != 0)) {
2405 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2406 }
2407 }
2408
2409 /* srad & srad. */
gen_srad(DisasContext * ctx)2410 static void gen_srad(DisasContext *ctx)
2411 {
2412 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env,
2413 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2414 if (unlikely(Rc(ctx->opcode) != 0)) {
2415 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2416 }
2417 }
2418 /* sradi & sradi. */
gen_sradi(DisasContext * ctx,int n)2419 static inline void gen_sradi(DisasContext *ctx, int n)
2420 {
2421 int sh = SH(ctx->opcode) + (n << 5);
2422 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2423 TCGv src = cpu_gpr[rS(ctx->opcode)];
2424 if (sh == 0) {
2425 tcg_gen_mov_tl(dst, src);
2426 tcg_gen_movi_tl(cpu_ca, 0);
2427 if (is_isa300(ctx)) {
2428 tcg_gen_movi_tl(cpu_ca32, 0);
2429 }
2430 } else {
2431 TCGv t0;
2432 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2433 t0 = tcg_temp_new();
2434 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2435 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2436 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2437 if (is_isa300(ctx)) {
2438 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2439 }
2440 tcg_gen_sari_tl(dst, src, sh);
2441 }
2442 if (unlikely(Rc(ctx->opcode) != 0)) {
2443 gen_set_Rc0(ctx, dst);
2444 }
2445 }
2446
gen_sradi0(DisasContext * ctx)2447 static void gen_sradi0(DisasContext *ctx)
2448 {
2449 gen_sradi(ctx, 0);
2450 }
2451
gen_sradi1(DisasContext * ctx)2452 static void gen_sradi1(DisasContext *ctx)
2453 {
2454 gen_sradi(ctx, 1);
2455 }
2456
2457 /* extswsli & extswsli. */
gen_extswsli(DisasContext * ctx,int n)2458 static inline void gen_extswsli(DisasContext *ctx, int n)
2459 {
2460 int sh = SH(ctx->opcode) + (n << 5);
2461 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2462 TCGv src = cpu_gpr[rS(ctx->opcode)];
2463
2464 tcg_gen_ext32s_tl(dst, src);
2465 tcg_gen_shli_tl(dst, dst, sh);
2466 if (unlikely(Rc(ctx->opcode) != 0)) {
2467 gen_set_Rc0(ctx, dst);
2468 }
2469 }
2470
gen_extswsli0(DisasContext * ctx)2471 static void gen_extswsli0(DisasContext *ctx)
2472 {
2473 gen_extswsli(ctx, 0);
2474 }
2475
gen_extswsli1(DisasContext * ctx)2476 static void gen_extswsli1(DisasContext *ctx)
2477 {
2478 gen_extswsli(ctx, 1);
2479 }
2480
2481 /* srd & srd. */
gen_srd(DisasContext * ctx)2482 static void gen_srd(DisasContext *ctx)
2483 {
2484 TCGv t0, t1;
2485
2486 t0 = tcg_temp_new();
2487 /* AND rS with a mask that is 0 when rB >= 0x40 */
2488 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2489 tcg_gen_sari_tl(t0, t0, 0x3f);
2490 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2491 t1 = tcg_temp_new();
2492 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2493 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2494 if (unlikely(Rc(ctx->opcode) != 0)) {
2495 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2496 }
2497 }
2498 #endif
2499
2500 /*** Addressing modes ***/
2501 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
gen_addr_imm_index(DisasContext * ctx,TCGv EA,target_long maskl)2502 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2503 target_long maskl)
2504 {
2505 target_long simm = SIMM(ctx->opcode);
2506
2507 simm &= ~maskl;
2508 if (rA(ctx->opcode) == 0) {
2509 if (NARROW_MODE(ctx)) {
2510 simm = (uint32_t)simm;
2511 }
2512 tcg_gen_movi_tl(EA, simm);
2513 } else if (likely(simm != 0)) {
2514 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2515 if (NARROW_MODE(ctx)) {
2516 tcg_gen_ext32u_tl(EA, EA);
2517 }
2518 } else {
2519 if (NARROW_MODE(ctx)) {
2520 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2521 } else {
2522 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2523 }
2524 }
2525 }
2526
gen_addr_reg_index(DisasContext * ctx,TCGv EA)2527 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2528 {
2529 if (rA(ctx->opcode) == 0) {
2530 if (NARROW_MODE(ctx)) {
2531 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2532 } else {
2533 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2534 }
2535 } else {
2536 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2537 if (NARROW_MODE(ctx)) {
2538 tcg_gen_ext32u_tl(EA, EA);
2539 }
2540 }
2541 }
2542
gen_addr_register(DisasContext * ctx,TCGv EA)2543 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2544 {
2545 if (rA(ctx->opcode) == 0) {
2546 tcg_gen_movi_tl(EA, 0);
2547 } else if (NARROW_MODE(ctx)) {
2548 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2549 } else {
2550 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2551 }
2552 }
2553
gen_addr_add(DisasContext * ctx,TCGv ret,TCGv arg1,target_long val)2554 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2555 target_long val)
2556 {
2557 tcg_gen_addi_tl(ret, arg1, val);
2558 if (NARROW_MODE(ctx)) {
2559 tcg_gen_ext32u_tl(ret, ret);
2560 }
2561 }
2562
gen_align_no_le(DisasContext * ctx)2563 static inline void gen_align_no_le(DisasContext *ctx)
2564 {
2565 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2566 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2567 }
2568
2569 /* EA <- {(ra == 0) ? 0 : GPR[ra]} + displ */
do_ea_calc(DisasContext * ctx,int ra,TCGv displ)2570 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ)
2571 {
2572 TCGv ea = tcg_temp_new();
2573 if (ra) {
2574 tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
2575 } else {
2576 tcg_gen_mov_tl(ea, displ);
2577 }
2578 if (NARROW_MODE(ctx)) {
2579 tcg_gen_ext32u_tl(ea, ea);
2580 }
2581 return ea;
2582 }
2583
2584 #if defined(TARGET_PPC64)
2585 /* EA <- (ra == 0) ? 0 : GPR[ra] */
do_ea_calc_ra(DisasContext * ctx,int ra)2586 static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
2587 {
2588 TCGv EA = tcg_temp_new();
2589 if (!ra) {
2590 tcg_gen_movi_tl(EA, 0);
2591 } else if (NARROW_MODE(ctx)) {
2592 tcg_gen_ext32u_tl(EA, cpu_gpr[ra]);
2593 } else {
2594 tcg_gen_mov_tl(EA, cpu_gpr[ra]);
2595 }
2596 return EA;
2597 }
2598 #endif
2599
2600 /*** Integer load ***/
2601 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2602 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2603
2604 #define GEN_QEMU_LOAD_TL(ldop, op) \
2605 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2606 TCGv val, \
2607 TCGv addr) \
2608 { \
2609 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2610 }
2611
2612 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2613 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2614 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2615 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2616 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2617
2618 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2619 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2620
2621 #define GEN_QEMU_LOAD_64(ldop, op) \
2622 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2623 TCGv_i64 val, \
2624 TCGv addr) \
2625 { \
2626 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2627 }
2628
2629 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2630 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2631 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2632 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2633 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ))
2634
2635 #if defined(TARGET_PPC64)
2636 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
2637 #endif
2638
2639 #define GEN_QEMU_STORE_TL(stop, op) \
2640 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2641 TCGv val, \
2642 TCGv addr) \
2643 { \
2644 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2645 }
2646
2647 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
2648 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2649 #endif
2650 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2651 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2652
2653 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2654 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2655
2656 #define GEN_QEMU_STORE_64(stop, op) \
2657 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2658 TCGv_i64 val, \
2659 TCGv addr) \
2660 { \
2661 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2662 }
2663
2664 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2665 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2666 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2667 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ))
2668
2669 #if defined(TARGET_PPC64)
2670 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
2671 #endif
2672
2673 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2674 static void glue(gen_, name##x)(DisasContext *ctx) \
2675 { \
2676 TCGv EA; \
2677 chk(ctx); \
2678 gen_set_access_type(ctx, ACCESS_INT); \
2679 EA = tcg_temp_new(); \
2680 gen_addr_reg_index(ctx, EA); \
2681 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2682 }
2683
2684 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2685 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2686
2687 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2688 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2689
2690 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2691 static void glue(gen_, name##epx)(DisasContext *ctx) \
2692 { \
2693 TCGv EA; \
2694 CHK_SV(ctx); \
2695 gen_set_access_type(ctx, ACCESS_INT); \
2696 EA = tcg_temp_new(); \
2697 gen_addr_reg_index(ctx, EA); \
2698 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2699 }
2700
2701 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
2702 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
2703 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
2704 #if defined(TARGET_PPC64)
2705 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
2706 #endif
2707
2708 #if defined(TARGET_PPC64)
2709 /* CI load/store variants */
2710 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2711 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2712 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2713 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2714 #endif
2715
2716 /*** Integer store ***/
2717 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2718 static void glue(gen_, name##x)(DisasContext *ctx) \
2719 { \
2720 TCGv EA; \
2721 chk(ctx); \
2722 gen_set_access_type(ctx, ACCESS_INT); \
2723 EA = tcg_temp_new(); \
2724 gen_addr_reg_index(ctx, EA); \
2725 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2726 }
2727 #define GEN_STX(name, stop, opc2, opc3, type) \
2728 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2729
2730 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2731 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2732
2733 #define GEN_STEPX(name, stop, opc2, opc3) \
2734 static void glue(gen_, name##epx)(DisasContext *ctx) \
2735 { \
2736 TCGv EA; \
2737 CHK_SV(ctx); \
2738 gen_set_access_type(ctx, ACCESS_INT); \
2739 EA = tcg_temp_new(); \
2740 gen_addr_reg_index(ctx, EA); \
2741 tcg_gen_qemu_st_tl( \
2742 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2743 }
2744
2745 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
2746 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
2747 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
2748 #if defined(TARGET_PPC64)
2749 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04)
2750 #endif
2751
2752 #if defined(TARGET_PPC64)
2753 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2754 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2755 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2756 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2757 #endif
2758 /*** Integer load and store with byte reverse ***/
2759
2760 /* lhbrx */
2761 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2762
2763 /* lwbrx */
2764 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2765
2766 #if defined(TARGET_PPC64)
2767 /* ldbrx */
2768 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2769 /* stdbrx */
2770 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2771 #endif /* TARGET_PPC64 */
2772
2773 /* sthbrx */
2774 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2775 /* stwbrx */
2776 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2777
2778 /*** Integer load and store multiple ***/
2779
2780 /* lmw */
gen_lmw(DisasContext * ctx)2781 static void gen_lmw(DisasContext *ctx)
2782 {
2783 TCGv t0;
2784 TCGv_i32 t1;
2785
2786 if (ctx->le_mode) {
2787 gen_align_no_le(ctx);
2788 return;
2789 }
2790 gen_set_access_type(ctx, ACCESS_INT);
2791 t0 = tcg_temp_new();
2792 t1 = tcg_constant_i32(rD(ctx->opcode));
2793 gen_addr_imm_index(ctx, t0, 0);
2794 gen_helper_lmw(tcg_env, t0, t1);
2795 }
2796
2797 /* stmw */
gen_stmw(DisasContext * ctx)2798 static void gen_stmw(DisasContext *ctx)
2799 {
2800 TCGv t0;
2801 TCGv_i32 t1;
2802
2803 if (ctx->le_mode) {
2804 gen_align_no_le(ctx);
2805 return;
2806 }
2807 gen_set_access_type(ctx, ACCESS_INT);
2808 t0 = tcg_temp_new();
2809 t1 = tcg_constant_i32(rS(ctx->opcode));
2810 gen_addr_imm_index(ctx, t0, 0);
2811 gen_helper_stmw(tcg_env, t0, t1);
2812 }
2813
2814 /*** Integer load and store strings ***/
2815
2816 /* lswi */
2817 /*
2818 * PowerPC32 specification says we must generate an exception if rA is
2819 * in the range of registers to be loaded. In an other hand, IBM says
2820 * this is valid, but rA won't be loaded. For now, I'll follow the
2821 * spec...
2822 */
gen_lswi(DisasContext * ctx)2823 static void gen_lswi(DisasContext *ctx)
2824 {
2825 TCGv t0;
2826 TCGv_i32 t1, t2;
2827 int nb = NB(ctx->opcode);
2828 int start = rD(ctx->opcode);
2829 int ra = rA(ctx->opcode);
2830 int nr;
2831
2832 if (ctx->le_mode) {
2833 gen_align_no_le(ctx);
2834 return;
2835 }
2836 if (nb == 0) {
2837 nb = 32;
2838 }
2839 nr = DIV_ROUND_UP(nb, 4);
2840 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2841 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2842 return;
2843 }
2844 gen_set_access_type(ctx, ACCESS_INT);
2845 t0 = tcg_temp_new();
2846 gen_addr_register(ctx, t0);
2847 t1 = tcg_constant_i32(nb);
2848 t2 = tcg_constant_i32(start);
2849 gen_helper_lsw(tcg_env, t0, t1, t2);
2850 }
2851
2852 /* lswx */
gen_lswx(DisasContext * ctx)2853 static void gen_lswx(DisasContext *ctx)
2854 {
2855 TCGv t0;
2856 TCGv_i32 t1, t2, t3;
2857
2858 if (ctx->le_mode) {
2859 gen_align_no_le(ctx);
2860 return;
2861 }
2862 gen_set_access_type(ctx, ACCESS_INT);
2863 t0 = tcg_temp_new();
2864 gen_addr_reg_index(ctx, t0);
2865 t1 = tcg_constant_i32(rD(ctx->opcode));
2866 t2 = tcg_constant_i32(rA(ctx->opcode));
2867 t3 = tcg_constant_i32(rB(ctx->opcode));
2868 gen_helper_lswx(tcg_env, t0, t1, t2, t3);
2869 }
2870
2871 /* stswi */
gen_stswi(DisasContext * ctx)2872 static void gen_stswi(DisasContext *ctx)
2873 {
2874 TCGv t0;
2875 TCGv_i32 t1, t2;
2876 int nb = NB(ctx->opcode);
2877
2878 if (ctx->le_mode) {
2879 gen_align_no_le(ctx);
2880 return;
2881 }
2882 gen_set_access_type(ctx, ACCESS_INT);
2883 t0 = tcg_temp_new();
2884 gen_addr_register(ctx, t0);
2885 if (nb == 0) {
2886 nb = 32;
2887 }
2888 t1 = tcg_constant_i32(nb);
2889 t2 = tcg_constant_i32(rS(ctx->opcode));
2890 gen_helper_stsw(tcg_env, t0, t1, t2);
2891 }
2892
2893 /* stswx */
gen_stswx(DisasContext * ctx)2894 static void gen_stswx(DisasContext *ctx)
2895 {
2896 TCGv t0;
2897 TCGv_i32 t1, t2;
2898
2899 if (ctx->le_mode) {
2900 gen_align_no_le(ctx);
2901 return;
2902 }
2903 gen_set_access_type(ctx, ACCESS_INT);
2904 t0 = tcg_temp_new();
2905 gen_addr_reg_index(ctx, t0);
2906 t1 = tcg_temp_new_i32();
2907 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2908 tcg_gen_andi_i32(t1, t1, 0x7F);
2909 t2 = tcg_constant_i32(rS(ctx->opcode));
2910 gen_helper_stsw(tcg_env, t0, t1, t2);
2911 }
2912
2913 #if !defined(CONFIG_USER_ONLY)
gen_check_tlb_flush(DisasContext * ctx,bool global)2914 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2915 {
2916 TCGv_i32 t;
2917 TCGLabel *l;
2918
2919 if (!ctx->lazy_tlb_flush) {
2920 return;
2921 }
2922 l = gen_new_label();
2923 t = tcg_temp_new_i32();
2924 tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
2925 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
2926 if (global) {
2927 gen_helper_check_tlb_flush_global(tcg_env);
2928 } else {
2929 gen_helper_check_tlb_flush_local(tcg_env);
2930 }
2931 gen_set_label(l);
2932 if (global) {
2933 /*
2934 * Global TLB flush uses async-work which must run before the
2935 * next instruction, so this must be the last in the TB.
2936 */
2937 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
2938 }
2939 }
2940 #else
gen_check_tlb_flush(DisasContext * ctx,bool global)2941 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
2942 #endif
2943
2944 /* isync */
gen_isync(DisasContext * ctx)2945 static void gen_isync(DisasContext *ctx)
2946 {
2947 /*
2948 * We need to check for a pending TLB flush. This can only happen in
2949 * kernel mode however so check MSR_PR
2950 */
2951 if (!ctx->pr) {
2952 gen_check_tlb_flush(ctx, false);
2953 }
2954 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
2955 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
2956 }
2957
gen_load_locked(DisasContext * ctx,MemOp memop)2958 static void gen_load_locked(DisasContext *ctx, MemOp memop)
2959 {
2960 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
2961 TCGv t0 = tcg_temp_new();
2962
2963 gen_set_access_type(ctx, ACCESS_RES);
2964 gen_addr_reg_index(ctx, t0);
2965 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN);
2966 tcg_gen_mov_tl(cpu_reserve, t0);
2967 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
2968 tcg_gen_mov_tl(cpu_reserve_val, gpr);
2969 }
2970
2971 #define LARX(name, memop) \
2972 static void gen_##name(DisasContext *ctx) \
2973 { \
2974 gen_load_locked(ctx, memop); \
2975 }
2976
2977 /* lwarx */
LARX(lbarx,MO_UB)2978 LARX(lbarx, MO_UB)
2979 LARX(lharx, MO_UW)
2980 LARX(lwarx, MO_UL)
2981
2982 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
2983 TCGv EA, TCGCond cond, int addend)
2984 {
2985 TCGv t = tcg_temp_new();
2986 TCGv t2 = tcg_temp_new();
2987 TCGv u = tcg_temp_new();
2988
2989 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
2990 tcg_gen_addi_tl(t2, EA, memop_size(memop));
2991 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
2992 tcg_gen_addi_tl(u, t, addend);
2993
2994 /* E.g. for fetch and increment bounded... */
2995 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
2996 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
2997 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
2998
2999 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3000 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t,
3001 tcg_constant_tl(1 << (memop_size(memop) * 8 - 1)));
3002 }
3003
gen_ld_atomic(DisasContext * ctx,MemOp memop)3004 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
3005 {
3006 uint32_t gpr_FC = FC(ctx->opcode);
3007 TCGv EA = tcg_temp_new();
3008 int rt = rD(ctx->opcode);
3009 bool need_serial;
3010 TCGv src, dst;
3011
3012 gen_addr_register(ctx, EA);
3013 dst = cpu_gpr[rt];
3014 src = cpu_gpr[(rt + 1) & 31];
3015
3016 need_serial = false;
3017 memop |= MO_ALIGN;
3018 switch (gpr_FC) {
3019 case 0: /* Fetch and add */
3020 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3021 break;
3022 case 1: /* Fetch and xor */
3023 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3024 break;
3025 case 2: /* Fetch and or */
3026 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3027 break;
3028 case 3: /* Fetch and 'and' */
3029 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3030 break;
3031 case 4: /* Fetch and max unsigned */
3032 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3033 break;
3034 case 5: /* Fetch and max signed */
3035 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3036 break;
3037 case 6: /* Fetch and min unsigned */
3038 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3039 break;
3040 case 7: /* Fetch and min signed */
3041 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3042 break;
3043 case 8: /* Swap */
3044 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3045 break;
3046
3047 case 16: /* Compare and swap not equal */
3048 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3049 need_serial = true;
3050 } else {
3051 TCGv t0 = tcg_temp_new();
3052 TCGv t1 = tcg_temp_new();
3053
3054 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3055 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3056 tcg_gen_mov_tl(t1, src);
3057 } else {
3058 tcg_gen_ext32u_tl(t1, src);
3059 }
3060 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3061 cpu_gpr[(rt + 2) & 31], t0);
3062 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3063 tcg_gen_mov_tl(dst, t0);
3064 }
3065 break;
3066
3067 case 24: /* Fetch and increment bounded */
3068 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3069 need_serial = true;
3070 } else {
3071 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3072 }
3073 break;
3074 case 25: /* Fetch and increment equal */
3075 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3076 need_serial = true;
3077 } else {
3078 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3079 }
3080 break;
3081 case 28: /* Fetch and decrement bounded */
3082 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3083 need_serial = true;
3084 } else {
3085 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3086 }
3087 break;
3088
3089 default:
3090 /* invoke data storage error handler */
3091 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3092 }
3093
3094 if (need_serial) {
3095 /* Restart with exclusive lock. */
3096 gen_helper_exit_atomic(tcg_env);
3097 ctx->base.is_jmp = DISAS_NORETURN;
3098 }
3099 }
3100
gen_lwat(DisasContext * ctx)3101 static void gen_lwat(DisasContext *ctx)
3102 {
3103 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3104 }
3105
3106 #ifdef TARGET_PPC64
gen_ldat(DisasContext * ctx)3107 static void gen_ldat(DisasContext *ctx)
3108 {
3109 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));
3110 }
3111 #endif
3112
gen_st_atomic(DisasContext * ctx,MemOp memop)3113 static void gen_st_atomic(DisasContext *ctx, MemOp memop)
3114 {
3115 uint32_t gpr_FC = FC(ctx->opcode);
3116 TCGv EA = tcg_temp_new();
3117 TCGv src, discard;
3118
3119 gen_addr_register(ctx, EA);
3120 src = cpu_gpr[rD(ctx->opcode)];
3121 discard = tcg_temp_new();
3122
3123 memop |= MO_ALIGN;
3124 switch (gpr_FC) {
3125 case 0: /* add and Store */
3126 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3127 break;
3128 case 1: /* xor and Store */
3129 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3130 break;
3131 case 2: /* Or and Store */
3132 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3133 break;
3134 case 3: /* 'and' and Store */
3135 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3136 break;
3137 case 4: /* Store max unsigned */
3138 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3139 break;
3140 case 5: /* Store max signed */
3141 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3142 break;
3143 case 6: /* Store min unsigned */
3144 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3145 break;
3146 case 7: /* Store min signed */
3147 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3148 break;
3149 case 24: /* Store twin */
3150 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3151 /* Restart with exclusive lock. */
3152 gen_helper_exit_atomic(tcg_env);
3153 ctx->base.is_jmp = DISAS_NORETURN;
3154 } else {
3155 TCGv t = tcg_temp_new();
3156 TCGv t2 = tcg_temp_new();
3157 TCGv s = tcg_temp_new();
3158 TCGv s2 = tcg_temp_new();
3159 TCGv ea_plus_s = tcg_temp_new();
3160
3161 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3162 tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop));
3163 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3164 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3165 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3166 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3167 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3168 }
3169 break;
3170 default:
3171 /* invoke data storage error handler */
3172 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3173 }
3174 }
3175
gen_stwat(DisasContext * ctx)3176 static void gen_stwat(DisasContext *ctx)
3177 {
3178 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3179 }
3180
3181 #ifdef TARGET_PPC64
gen_stdat(DisasContext * ctx)3182 static void gen_stdat(DisasContext *ctx)
3183 {
3184 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));
3185 }
3186 #endif
3187
gen_conditional_store(DisasContext * ctx,MemOp memop)3188 static void gen_conditional_store(DisasContext *ctx, MemOp memop)
3189 {
3190 TCGLabel *lfail;
3191 TCGv EA;
3192 TCGv cr0;
3193 TCGv t0;
3194 int rs = rS(ctx->opcode);
3195
3196 lfail = gen_new_label();
3197 EA = tcg_temp_new();
3198 cr0 = tcg_temp_new();
3199 t0 = tcg_temp_new();
3200
3201 tcg_gen_mov_tl(cr0, cpu_so);
3202 gen_set_access_type(ctx, ACCESS_RES);
3203 gen_addr_reg_index(ctx, EA);
3204 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
3205 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail);
3206
3207 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3208 cpu_gpr[rs], ctx->mem_idx,
3209 DEF_MEMOP(memop) | MO_ALIGN);
3210 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3211 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3212 tcg_gen_or_tl(cr0, cr0, t0);
3213
3214 gen_set_label(lfail);
3215 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
3216 tcg_gen_movi_tl(cpu_reserve, -1);
3217 }
3218
3219 #define STCX(name, memop) \
3220 static void gen_##name(DisasContext *ctx) \
3221 { \
3222 gen_conditional_store(ctx, memop); \
3223 }
3224
STCX(stbcx_,MO_UB)3225 STCX(stbcx_, MO_UB)
3226 STCX(sthcx_, MO_UW)
3227 STCX(stwcx_, MO_UL)
3228
3229 #if defined(TARGET_PPC64)
3230 /* ldarx */
3231 LARX(ldarx, MO_UQ)
3232 /* stdcx. */
3233 STCX(stdcx_, MO_UQ)
3234
3235 /* lqarx */
3236 static void gen_lqarx(DisasContext *ctx)
3237 {
3238 int rd = rD(ctx->opcode);
3239 TCGv EA, hi, lo;
3240 TCGv_i128 t16;
3241
3242 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3243 (rd == rB(ctx->opcode)))) {
3244 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3245 return;
3246 }
3247
3248 gen_set_access_type(ctx, ACCESS_RES);
3249 EA = tcg_temp_new();
3250 gen_addr_reg_index(ctx, EA);
3251
3252 /* Note that the low part is always in RD+1, even in LE mode. */
3253 lo = cpu_gpr[rd + 1];
3254 hi = cpu_gpr[rd];
3255
3256 t16 = tcg_temp_new_i128();
3257 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN));
3258 tcg_gen_extr_i128_i64(lo, hi, t16);
3259
3260 tcg_gen_mov_tl(cpu_reserve, EA);
3261 tcg_gen_movi_tl(cpu_reserve_length, 16);
3262 tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val));
3263 tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2));
3264 }
3265
3266 /* stqcx. */
gen_stqcx_(DisasContext * ctx)3267 static void gen_stqcx_(DisasContext *ctx)
3268 {
3269 TCGLabel *lfail;
3270 TCGv EA, t0, t1;
3271 TCGv cr0;
3272 TCGv_i128 cmp, val;
3273 int rs = rS(ctx->opcode);
3274
3275 if (unlikely(rs & 1)) {
3276 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3277 return;
3278 }
3279
3280 lfail = gen_new_label();
3281 EA = tcg_temp_new();
3282 cr0 = tcg_temp_new();
3283
3284 tcg_gen_mov_tl(cr0, cpu_so);
3285 gen_set_access_type(ctx, ACCESS_RES);
3286 gen_addr_reg_index(ctx, EA);
3287 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
3288 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail);
3289
3290 cmp = tcg_temp_new_i128();
3291 val = tcg_temp_new_i128();
3292
3293 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val);
3294
3295 /* Note that the low part is always in RS+1, even in LE mode. */
3296 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]);
3297
3298 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx,
3299 DEF_MEMOP(MO_128 | MO_ALIGN));
3300
3301 t0 = tcg_temp_new();
3302 t1 = tcg_temp_new();
3303 tcg_gen_extr_i128_i64(t1, t0, val);
3304
3305 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);
3306 tcg_gen_xor_tl(t0, t0, cpu_reserve_val);
3307 tcg_gen_or_tl(t0, t0, t1);
3308
3309 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0);
3310 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3311 tcg_gen_or_tl(cr0, cr0, t0);
3312
3313 gen_set_label(lfail);
3314 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
3315 tcg_gen_movi_tl(cpu_reserve, -1);
3316 }
3317 #endif /* defined(TARGET_PPC64) */
3318
3319 /* wait */
gen_wait(DisasContext * ctx)3320 static void gen_wait(DisasContext *ctx)
3321 {
3322 uint32_t wc;
3323
3324 if (ctx->insns_flags & PPC_WAIT) {
3325 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */
3326
3327 if (ctx->insns_flags2 & PPC2_PM_ISA206) {
3328 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */
3329 wc = WC(ctx->opcode);
3330 } else {
3331 wc = 0;
3332 }
3333
3334 } else if (ctx->insns_flags2 & PPC2_ISA300) {
3335 /* v3.0 defines a new 'wait' encoding. */
3336 wc = WC(ctx->opcode);
3337 if (ctx->insns_flags2 & PPC2_ISA310) {
3338 uint32_t pl = PL(ctx->opcode);
3339
3340 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */
3341 if (wc == 3) {
3342 gen_invalid(ctx);
3343 return;
3344 }
3345
3346 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */
3347 if (pl > 0 && wc != 2) {
3348 gen_invalid(ctx);
3349 return;
3350 }
3351
3352 } else { /* ISA300 */
3353 /* WC 1-3 are reserved */
3354 if (wc > 0) {
3355 gen_invalid(ctx);
3356 return;
3357 }
3358 }
3359
3360 } else {
3361 warn_report("wait instruction decoded with wrong ISA flags.");
3362 gen_invalid(ctx);
3363 return;
3364 }
3365
3366 /*
3367 * wait without WC field or with WC=0 waits for an exception / interrupt
3368 * to occur.
3369 */
3370 if (wc == 0) {
3371 TCGv_i32 t0 = tcg_constant_i32(1);
3372 tcg_gen_st_i32(t0, tcg_env,
3373 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3374 /* Stop translation, as the CPU is supposed to sleep from now */
3375 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3376 }
3377
3378 /*
3379 * Other wait types must not just wait until an exception occurs because
3380 * ignoring their other wake-up conditions could cause a hang.
3381 *
3382 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as
3383 * no-ops.
3384 *
3385 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op.
3386 *
3387 * wc=2 waits for an implementation-specific condition, such could be
3388 * always true, so it can be implemented as a no-op.
3389 *
3390 * For v3.1, wc=1,2 are architected but may be implemented as no-ops.
3391 *
3392 * wc=1 (waitrsv) waits for an exception or a reservation to be lost.
3393 * Reservation-loss may have implementation-specific conditions, so it
3394 * can be implemented as a no-op.
3395 *
3396 * wc=2 waits for an exception or an amount of time to pass. This
3397 * amount is implementation-specific so it can be implemented as a
3398 * no-op.
3399 *
3400 * ISA v3.1 allows for execution to resume "in the rare case of
3401 * an implementation-dependent event", so in any case software must
3402 * not depend on the architected resumption condition to become
3403 * true, so no-op implementations should be architecturally correct
3404 * (if suboptimal).
3405 */
3406 }
3407
3408 #if defined(TARGET_PPC64)
gen_doze(DisasContext * ctx)3409 static void gen_doze(DisasContext *ctx)
3410 {
3411 #if defined(CONFIG_USER_ONLY)
3412 GEN_PRIV(ctx);
3413 #else
3414 TCGv_i32 t;
3415
3416 CHK_HV(ctx);
3417 translator_io_start(&ctx->base);
3418 t = tcg_constant_i32(PPC_PM_DOZE);
3419 gen_helper_pminsn(tcg_env, t);
3420 /* Stop translation, as the CPU is supposed to sleep from now */
3421 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3422 #endif /* defined(CONFIG_USER_ONLY) */
3423 }
3424
gen_nap(DisasContext * ctx)3425 static void gen_nap(DisasContext *ctx)
3426 {
3427 #if defined(CONFIG_USER_ONLY)
3428 GEN_PRIV(ctx);
3429 #else
3430 TCGv_i32 t;
3431
3432 CHK_HV(ctx);
3433 translator_io_start(&ctx->base);
3434 t = tcg_constant_i32(PPC_PM_NAP);
3435 gen_helper_pminsn(tcg_env, t);
3436 /* Stop translation, as the CPU is supposed to sleep from now */
3437 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3438 #endif /* defined(CONFIG_USER_ONLY) */
3439 }
3440
gen_stop(DisasContext * ctx)3441 static void gen_stop(DisasContext *ctx)
3442 {
3443 #if defined(CONFIG_USER_ONLY)
3444 GEN_PRIV(ctx);
3445 #else
3446 TCGv_i32 t;
3447
3448 CHK_HV(ctx);
3449 translator_io_start(&ctx->base);
3450 t = tcg_constant_i32(PPC_PM_STOP);
3451 gen_helper_pminsn(tcg_env, t);
3452 /* Stop translation, as the CPU is supposed to sleep from now */
3453 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3454 #endif /* defined(CONFIG_USER_ONLY) */
3455 }
3456
gen_sleep(DisasContext * ctx)3457 static void gen_sleep(DisasContext *ctx)
3458 {
3459 #if defined(CONFIG_USER_ONLY)
3460 GEN_PRIV(ctx);
3461 #else
3462 TCGv_i32 t;
3463
3464 CHK_HV(ctx);
3465 translator_io_start(&ctx->base);
3466 t = tcg_constant_i32(PPC_PM_SLEEP);
3467 gen_helper_pminsn(tcg_env, t);
3468 /* Stop translation, as the CPU is supposed to sleep from now */
3469 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3470 #endif /* defined(CONFIG_USER_ONLY) */
3471 }
3472
gen_rvwinkle(DisasContext * ctx)3473 static void gen_rvwinkle(DisasContext *ctx)
3474 {
3475 #if defined(CONFIG_USER_ONLY)
3476 GEN_PRIV(ctx);
3477 #else
3478 TCGv_i32 t;
3479
3480 CHK_HV(ctx);
3481 translator_io_start(&ctx->base);
3482 t = tcg_constant_i32(PPC_PM_RVWINKLE);
3483 gen_helper_pminsn(tcg_env, t);
3484 /* Stop translation, as the CPU is supposed to sleep from now */
3485 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3486 #endif /* defined(CONFIG_USER_ONLY) */
3487 }
3488
gen_write_bhrb(TCGv_ptr base,TCGv offset,TCGv mask,TCGv value)3489 static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value)
3490 {
3491 TCGv_ptr tmp = tcg_temp_new_ptr();
3492
3493 /* add base and offset to get address of bhrb entry */
3494 tcg_gen_add_ptr(tmp, base, (TCGv_ptr)offset);
3495
3496 /* store value into bhrb at bhrb_offset */
3497 tcg_gen_st_i64(value, tmp, 0);
3498
3499 /* add 8 to current bhrb_offset */
3500 tcg_gen_addi_tl(offset, offset, 8);
3501
3502 /* apply offset mask */
3503 tcg_gen_and_tl(offset, offset, mask);
3504
3505 return offset;
3506 }
3507 #endif /* #if defined(TARGET_PPC64) */
3508
gen_update_branch_history(DisasContext * ctx,target_ulong nip,TCGv target,target_long inst_type)3509 static inline void gen_update_branch_history(DisasContext *ctx,
3510 target_ulong nip,
3511 TCGv target,
3512 target_long inst_type)
3513 {
3514 #if defined(TARGET_PPC64)
3515 TCGv_ptr base;
3516 TCGv tmp;
3517 TCGv offset;
3518 TCGv mask;
3519 TCGLabel *no_update;
3520
3521 if (ctx->has_cfar) {
3522 tcg_gen_movi_tl(cpu_cfar, nip);
3523 }
3524
3525 if (!ctx->has_bhrb ||
3526 !ctx->bhrb_enable ||
3527 inst_type == BHRB_TYPE_NORECORD) {
3528 return;
3529 }
3530
3531 tmp = tcg_temp_new();
3532 no_update = gen_new_label();
3533
3534 /* check for bhrb filtering */
3535 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
3536 tcg_gen_andi_tl(tmp, tmp, inst_type);
3537 tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update);
3538
3539 base = tcg_temp_new_ptr();
3540 offset = tcg_temp_new();
3541 mask = tcg_temp_new();
3542
3543 /* load bhrb base address */
3544 tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base));
3545
3546 /* load current bhrb_offset */
3547 tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
3548
3549 /* load a BHRB offset mask */
3550 tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
3551
3552 offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip));
3553
3554 /* Also record the target address for XL-Form branches */
3555 if (inst_type & BHRB_TYPE_XL_FORM) {
3556
3557 /* Set the 'T' bit for target entries */
3558 tcg_gen_ori_tl(tmp, target, 0x2);
3559
3560 offset = gen_write_bhrb(base, offset, mask, tmp);
3561 }
3562
3563 /* save updated bhrb_offset for next time */
3564 tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
3565
3566 gen_set_label(no_update);
3567 #endif
3568 }
3569
3570 #if defined(TARGET_PPC64)
pmu_count_insns(DisasContext * ctx)3571 static void pmu_count_insns(DisasContext *ctx)
3572 {
3573 /*
3574 * Do not bother calling the helper if the PMU isn't counting
3575 * instructions.
3576 */
3577 if (!ctx->pmu_insn_cnt) {
3578 return;
3579 }
3580
3581 #if !defined(CONFIG_USER_ONLY)
3582 TCGLabel *l;
3583 TCGv t0;
3584
3585 /*
3586 * The PMU insns_inc() helper stops the internal PMU timer if a
3587 * counter overflows happens. In that case, if the guest is
3588 * running with icount and we do not handle it beforehand,
3589 * the helper can trigger a 'bad icount read'.
3590 */
3591 translator_io_start(&ctx->base);
3592
3593 /* Avoid helper calls when only PMC5-6 are enabled. */
3594 if (!ctx->pmc_other) {
3595 l = gen_new_label();
3596 t0 = tcg_temp_new();
3597
3598 gen_load_spr(t0, SPR_POWER_PMC5);
3599 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
3600 gen_store_spr(SPR_POWER_PMC5, t0);
3601 /* Check for overflow, if it's enabled */
3602 if (ctx->mmcr0_pmcjce) {
3603 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l);
3604 gen_helper_handle_pmc5_overflow(tcg_env);
3605 }
3606
3607 gen_set_label(l);
3608 } else {
3609 gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns));
3610 }
3611 #else
3612 /*
3613 * User mode can read (but not write) PMC5 and start/stop
3614 * the PMU via MMCR0_FC. In this case just increment
3615 * PMC5 with base.num_insns.
3616 */
3617 TCGv t0 = tcg_temp_new();
3618
3619 gen_load_spr(t0, SPR_POWER_PMC5);
3620 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
3621 gen_store_spr(SPR_POWER_PMC5, t0);
3622 #endif /* #if !defined(CONFIG_USER_ONLY) */
3623 }
3624 #else
pmu_count_insns(DisasContext * ctx)3625 static void pmu_count_insns(DisasContext *ctx)
3626 {
3627 }
3628 #endif /* #if defined(TARGET_PPC64) */
3629
use_goto_tb(DisasContext * ctx,target_ulong dest)3630 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3631 {
3632 if (unlikely(ctx->singlestep_enabled)) {
3633 return false;
3634 }
3635 return translator_use_goto_tb(&ctx->base, dest);
3636 }
3637
gen_lookup_and_goto_ptr(DisasContext * ctx)3638 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
3639 {
3640 if (unlikely(ctx->singlestep_enabled)) {
3641 gen_debug_exception(ctx, false);
3642 } else {
3643 /*
3644 * tcg_gen_lookup_and_goto_ptr will exit the TB if
3645 * CF_NO_GOTO_PTR is set. Count insns now.
3646 */
3647 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
3648 pmu_count_insns(ctx);
3649 }
3650
3651 tcg_gen_lookup_and_goto_ptr();
3652 }
3653 }
3654
3655 /*** Branch ***/
gen_goto_tb(DisasContext * ctx,int n,target_ulong dest)3656 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3657 {
3658 if (NARROW_MODE(ctx)) {
3659 dest = (uint32_t) dest;
3660 }
3661 if (use_goto_tb(ctx, dest)) {
3662 pmu_count_insns(ctx);
3663 tcg_gen_goto_tb(n);
3664 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3665 tcg_gen_exit_tb(ctx->base.tb, n);
3666 } else {
3667 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3668 gen_lookup_and_goto_ptr(ctx);
3669 }
3670 }
3671
gen_setlr(DisasContext * ctx,target_ulong nip)3672 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3673 {
3674 if (NARROW_MODE(ctx)) {
3675 nip = (uint32_t)nip;
3676 }
3677 tcg_gen_movi_tl(cpu_lr, nip);
3678 }
3679
3680 /* b ba bl bla */
gen_b(DisasContext * ctx)3681 static void gen_b(DisasContext *ctx)
3682 {
3683 target_ulong li, target;
3684
3685 /* sign extend LI */
3686 li = LI(ctx->opcode);
3687 li = (li ^ 0x02000000) - 0x02000000;
3688 if (likely(AA(ctx->opcode) == 0)) {
3689 target = ctx->cia + li;
3690 } else {
3691 target = li;
3692 }
3693 if (LK(ctx->opcode)) {
3694 gen_setlr(ctx, ctx->base.pc_next);
3695 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL);
3696 } else {
3697 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER);
3698 }
3699 gen_goto_tb(ctx, 0, target);
3700 ctx->base.is_jmp = DISAS_NORETURN;
3701 }
3702
3703 #define BCOND_IM 0
3704 #define BCOND_LR 1
3705 #define BCOND_CTR 2
3706 #define BCOND_TAR 3
3707
gen_bcond(DisasContext * ctx,int type)3708 static void gen_bcond(DisasContext *ctx, int type)
3709 {
3710 uint32_t bo = BO(ctx->opcode);
3711 TCGLabel *l1;
3712 TCGv target;
3713 target_long bhrb_type = BHRB_TYPE_OTHER;
3714
3715 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3716 target = tcg_temp_new();
3717 if (type == BCOND_CTR) {
3718 tcg_gen_mov_tl(target, cpu_ctr);
3719 } else if (type == BCOND_TAR) {
3720 gen_load_spr(target, SPR_TAR);
3721 } else {
3722 tcg_gen_mov_tl(target, cpu_lr);
3723 }
3724 if (!LK(ctx->opcode)) {
3725 bhrb_type |= BHRB_TYPE_INDIRECT;
3726 }
3727 bhrb_type |= BHRB_TYPE_XL_FORM;
3728 } else {
3729 target = NULL;
3730 }
3731 if (LK(ctx->opcode)) {
3732 gen_setlr(ctx, ctx->base.pc_next);
3733 bhrb_type |= BHRB_TYPE_CALL;
3734 }
3735 l1 = gen_new_label();
3736 if ((bo & 0x4) == 0) {
3737 /* Decrement and test CTR */
3738 TCGv temp = tcg_temp_new();
3739
3740 if (type == BCOND_CTR) {
3741 /*
3742 * All ISAs up to v3 describe this form of bcctr as invalid but
3743 * some processors, ie. 64-bit server processors compliant with
3744 * arch 2.x, do implement a "test and decrement" logic instead,
3745 * as described in their respective UMs. This logic involves CTR
3746 * to act as both the branch target and a counter, which makes
3747 * it basically useless and thus never used in real code.
3748 *
3749 * This form was hence chosen to trigger extra micro-architectural
3750 * side-effect on real HW needed for the Spectre v2 workaround.
3751 * It is up to guests that implement such workaround, ie. linux, to
3752 * use this form in a way it just triggers the side-effect without
3753 * doing anything else harmful.
3754 */
3755 if (unlikely(!is_book3s_arch2x(ctx))) {
3756 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3757 return;
3758 }
3759
3760 if (NARROW_MODE(ctx)) {
3761 tcg_gen_ext32u_tl(temp, cpu_ctr);
3762 } else {
3763 tcg_gen_mov_tl(temp, cpu_ctr);
3764 }
3765 if (bo & 0x2) {
3766 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3767 } else {
3768 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3769 }
3770 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3771 } else {
3772 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3773 if (NARROW_MODE(ctx)) {
3774 tcg_gen_ext32u_tl(temp, cpu_ctr);
3775 } else {
3776 tcg_gen_mov_tl(temp, cpu_ctr);
3777 }
3778 if (bo & 0x2) {
3779 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3780 } else {
3781 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3782 }
3783 }
3784 bhrb_type |= BHRB_TYPE_COND;
3785 }
3786 if ((bo & 0x10) == 0) {
3787 /* Test CR */
3788 uint32_t bi = BI(ctx->opcode);
3789 uint32_t mask = 0x08 >> (bi & 0x03);
3790 TCGv_i32 temp = tcg_temp_new_i32();
3791
3792 if (bo & 0x8) {
3793 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3794 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3795 } else {
3796 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3797 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3798 }
3799 bhrb_type |= BHRB_TYPE_COND;
3800 }
3801
3802 gen_update_branch_history(ctx, ctx->cia, target, bhrb_type);
3803
3804 if (type == BCOND_IM) {
3805 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3806 if (likely(AA(ctx->opcode) == 0)) {
3807 gen_goto_tb(ctx, 0, ctx->cia + li);
3808 } else {
3809 gen_goto_tb(ctx, 0, li);
3810 }
3811 } else {
3812 if (NARROW_MODE(ctx)) {
3813 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3814 } else {
3815 tcg_gen_andi_tl(cpu_nip, target, ~3);
3816 }
3817 gen_lookup_and_goto_ptr(ctx);
3818 }
3819 if ((bo & 0x14) != 0x14) {
3820 /* fallthrough case */
3821 gen_set_label(l1);
3822 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3823 }
3824 ctx->base.is_jmp = DISAS_NORETURN;
3825 }
3826
gen_bc(DisasContext * ctx)3827 static void gen_bc(DisasContext *ctx)
3828 {
3829 gen_bcond(ctx, BCOND_IM);
3830 }
3831
gen_bcctr(DisasContext * ctx)3832 static void gen_bcctr(DisasContext *ctx)
3833 {
3834 gen_bcond(ctx, BCOND_CTR);
3835 }
3836
gen_bclr(DisasContext * ctx)3837 static void gen_bclr(DisasContext *ctx)
3838 {
3839 gen_bcond(ctx, BCOND_LR);
3840 }
3841
gen_bctar(DisasContext * ctx)3842 static void gen_bctar(DisasContext *ctx)
3843 {
3844 gen_bcond(ctx, BCOND_TAR);
3845 }
3846
3847 /*** Condition register logical ***/
3848 #define GEN_CRLOGIC(name, tcg_op, opc) \
3849 static void glue(gen_, name)(DisasContext *ctx) \
3850 { \
3851 uint8_t bitmask; \
3852 int sh; \
3853 TCGv_i32 t0, t1; \
3854 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3855 t0 = tcg_temp_new_i32(); \
3856 if (sh > 0) \
3857 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3858 else if (sh < 0) \
3859 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3860 else \
3861 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3862 t1 = tcg_temp_new_i32(); \
3863 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3864 if (sh > 0) \
3865 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3866 else if (sh < 0) \
3867 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3868 else \
3869 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3870 tcg_op(t0, t0, t1); \
3871 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3872 tcg_gen_andi_i32(t0, t0, bitmask); \
3873 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3874 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3875 }
3876
3877 /* crand */
3878 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3879 /* crandc */
3880 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3881 /* creqv */
3882 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3883 /* crnand */
3884 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3885 /* crnor */
3886 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3887 /* cror */
3888 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3889 /* crorc */
3890 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3891 /* crxor */
3892 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3893
3894 /* mcrf */
gen_mcrf(DisasContext * ctx)3895 static void gen_mcrf(DisasContext *ctx)
3896 {
3897 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3898 }
3899
3900 /*** System linkage ***/
3901
3902 /* rfi (supervisor only) */
gen_rfi(DisasContext * ctx)3903 static void gen_rfi(DisasContext *ctx)
3904 {
3905 #if defined(CONFIG_USER_ONLY)
3906 GEN_PRIV(ctx);
3907 #else
3908 /*
3909 * This instruction doesn't exist anymore on 64-bit server
3910 * processors compliant with arch 2.x
3911 */
3912 if (is_book3s_arch2x(ctx)) {
3913 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3914 return;
3915 }
3916 /* Restore CPU state */
3917 CHK_SV(ctx);
3918 translator_io_start(&ctx->base);
3919 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
3920 gen_helper_rfi(tcg_env);
3921 ctx->base.is_jmp = DISAS_EXIT;
3922 #endif
3923 }
3924
3925 #if defined(TARGET_PPC64)
gen_rfid(DisasContext * ctx)3926 static void gen_rfid(DisasContext *ctx)
3927 {
3928 #if defined(CONFIG_USER_ONLY)
3929 GEN_PRIV(ctx);
3930 #else
3931 /* Restore CPU state */
3932 CHK_SV(ctx);
3933 translator_io_start(&ctx->base);
3934 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
3935 gen_helper_rfid(tcg_env);
3936 ctx->base.is_jmp = DISAS_EXIT;
3937 #endif
3938 }
3939
3940 #if !defined(CONFIG_USER_ONLY)
gen_rfscv(DisasContext * ctx)3941 static void gen_rfscv(DisasContext *ctx)
3942 {
3943 #if defined(CONFIG_USER_ONLY)
3944 GEN_PRIV(ctx);
3945 #else
3946 /* Restore CPU state */
3947 CHK_SV(ctx);
3948 translator_io_start(&ctx->base);
3949 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
3950 gen_helper_rfscv(tcg_env);
3951 ctx->base.is_jmp = DISAS_EXIT;
3952 #endif
3953 }
3954 #endif
3955
gen_hrfid(DisasContext * ctx)3956 static void gen_hrfid(DisasContext *ctx)
3957 {
3958 #if defined(CONFIG_USER_ONLY)
3959 GEN_PRIV(ctx);
3960 #else
3961 /* Restore CPU state */
3962 CHK_HV(ctx);
3963 translator_io_start(&ctx->base);
3964 gen_helper_hrfid(tcg_env);
3965 ctx->base.is_jmp = DISAS_EXIT;
3966 #endif
3967 }
3968 #endif
3969
3970 /* sc */
3971 #if defined(CONFIG_USER_ONLY)
3972 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3973 #else
3974 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3975 #endif
gen_sc(DisasContext * ctx)3976 static void gen_sc(DisasContext *ctx)
3977 {
3978 uint32_t lev;
3979
3980 /*
3981 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved
3982 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
3983 * for Ultravisor which TCG does not support, so just ignore the top 6.
3984 */
3985 lev = (ctx->opcode >> 5) & 0x1;
3986 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3987 }
3988
3989 #if defined(TARGET_PPC64)
3990 #if !defined(CONFIG_USER_ONLY)
gen_scv(DisasContext * ctx)3991 static void gen_scv(DisasContext *ctx)
3992 {
3993 uint32_t lev = (ctx->opcode >> 5) & 0x7F;
3994
3995 /* Set the PC back to the faulting instruction. */
3996 gen_update_nip(ctx, ctx->cia);
3997 gen_helper_scv(tcg_env, tcg_constant_i32(lev));
3998
3999 ctx->base.is_jmp = DISAS_NORETURN;
4000 }
4001 #endif
4002 #endif
4003
4004 /*** Trap ***/
4005
4006 /* Check for unconditional traps (always or never) */
check_unconditional_trap(DisasContext * ctx,int to)4007 static bool check_unconditional_trap(DisasContext *ctx, int to)
4008 {
4009 /* Trap never */
4010 if (to == 0) {
4011 return true;
4012 }
4013 /* Trap always */
4014 if (to == 31) {
4015 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
4016 return true;
4017 }
4018 return false;
4019 }
4020
4021 /*** Processor control ***/
4022
4023 /* mcrxr */
gen_mcrxr(DisasContext * ctx)4024 static void gen_mcrxr(DisasContext *ctx)
4025 {
4026 TCGv_i32 t0 = tcg_temp_new_i32();
4027 TCGv_i32 t1 = tcg_temp_new_i32();
4028 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4029
4030 tcg_gen_trunc_tl_i32(t0, cpu_so);
4031 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4032 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4033 tcg_gen_shli_i32(t0, t0, 3);
4034 tcg_gen_shli_i32(t1, t1, 2);
4035 tcg_gen_shli_i32(dst, dst, 1);
4036 tcg_gen_or_i32(dst, dst, t0);
4037 tcg_gen_or_i32(dst, dst, t1);
4038
4039 tcg_gen_movi_tl(cpu_so, 0);
4040 tcg_gen_movi_tl(cpu_ov, 0);
4041 tcg_gen_movi_tl(cpu_ca, 0);
4042 }
4043
4044 #ifdef TARGET_PPC64
4045 /* mcrxrx */
gen_mcrxrx(DisasContext * ctx)4046 static void gen_mcrxrx(DisasContext *ctx)
4047 {
4048 TCGv t0 = tcg_temp_new();
4049 TCGv t1 = tcg_temp_new();
4050 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4051
4052 /* copy OV and OV32 */
4053 tcg_gen_shli_tl(t0, cpu_ov, 1);
4054 tcg_gen_or_tl(t0, t0, cpu_ov32);
4055 tcg_gen_shli_tl(t0, t0, 2);
4056 /* copy CA and CA32 */
4057 tcg_gen_shli_tl(t1, cpu_ca, 1);
4058 tcg_gen_or_tl(t1, t1, cpu_ca32);
4059 tcg_gen_or_tl(t0, t0, t1);
4060 tcg_gen_trunc_tl_i32(dst, t0);
4061 }
4062 #endif
4063
4064 /* mfcr mfocrf */
gen_mfcr(DisasContext * ctx)4065 static void gen_mfcr(DisasContext *ctx)
4066 {
4067 uint32_t crm, crn;
4068
4069 if (likely(ctx->opcode & 0x00100000)) {
4070 crm = CRM(ctx->opcode);
4071 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4072 crn = ctz32(crm);
4073 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4074 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4075 cpu_gpr[rD(ctx->opcode)], crn * 4);
4076 }
4077 } else {
4078 TCGv_i32 t0 = tcg_temp_new_i32();
4079 tcg_gen_mov_i32(t0, cpu_crf[0]);
4080 tcg_gen_shli_i32(t0, t0, 4);
4081 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4082 tcg_gen_shli_i32(t0, t0, 4);
4083 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4084 tcg_gen_shli_i32(t0, t0, 4);
4085 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4086 tcg_gen_shli_i32(t0, t0, 4);
4087 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4088 tcg_gen_shli_i32(t0, t0, 4);
4089 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4090 tcg_gen_shli_i32(t0, t0, 4);
4091 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4092 tcg_gen_shli_i32(t0, t0, 4);
4093 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4094 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4095 }
4096 }
4097
4098 /* mfmsr */
gen_mfmsr(DisasContext * ctx)4099 static void gen_mfmsr(DisasContext *ctx)
4100 {
4101 CHK_SV(ctx);
4102 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4103 }
4104
4105 /* mfspr */
gen_op_mfspr(DisasContext * ctx)4106 static inline void gen_op_mfspr(DisasContext *ctx)
4107 {
4108 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4109 uint32_t sprn = SPR(ctx->opcode);
4110
4111 #if defined(CONFIG_USER_ONLY)
4112 read_cb = ctx->spr_cb[sprn].uea_read;
4113 #else
4114 if (ctx->pr) {
4115 read_cb = ctx->spr_cb[sprn].uea_read;
4116 } else if (ctx->hv) {
4117 read_cb = ctx->spr_cb[sprn].hea_read;
4118 } else {
4119 read_cb = ctx->spr_cb[sprn].oea_read;
4120 }
4121 #endif
4122 if (likely(read_cb != NULL)) {
4123 if (likely(read_cb != SPR_NOACCESS)) {
4124 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4125 } else {
4126 /* Privilege exception */
4127 /*
4128 * This is a hack to avoid warnings when running Linux:
4129 * this OS breaks the PowerPC virtualisation model,
4130 * allowing userland application to read the PVR
4131 */
4132 if (sprn != SPR_PVR) {
4133 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4134 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4135 ctx->cia);
4136 }
4137 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4138 }
4139 } else {
4140 /* ISA 2.07 defines these as no-ops */
4141 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4142 (sprn >= 808 && sprn <= 811)) {
4143 /* This is a nop */
4144 return;
4145 }
4146 /* Not defined */
4147 qemu_log_mask(LOG_GUEST_ERROR,
4148 "Trying to read invalid spr %d (0x%03x) at "
4149 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4150
4151 /*
4152 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4153 * generate a priv, a hv emu or a no-op
4154 */
4155 if (sprn & 0x10) {
4156 if (ctx->pr) {
4157 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4158 }
4159 } else {
4160 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4161 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4162 }
4163 }
4164 }
4165 }
4166
gen_mfspr(DisasContext * ctx)4167 static void gen_mfspr(DisasContext *ctx)
4168 {
4169 gen_op_mfspr(ctx);
4170 }
4171
4172 /* mftb */
gen_mftb(DisasContext * ctx)4173 static void gen_mftb(DisasContext *ctx)
4174 {
4175 gen_op_mfspr(ctx);
4176 }
4177
4178 /* mtcrf mtocrf*/
gen_mtcrf(DisasContext * ctx)4179 static void gen_mtcrf(DisasContext *ctx)
4180 {
4181 uint32_t crm, crn;
4182
4183 crm = CRM(ctx->opcode);
4184 if (likely((ctx->opcode & 0x00100000))) {
4185 if (crm && ((crm & (crm - 1)) == 0)) {
4186 TCGv_i32 temp = tcg_temp_new_i32();
4187 crn = ctz32(crm);
4188 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4189 tcg_gen_shri_i32(temp, temp, crn * 4);
4190 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4191 }
4192 } else {
4193 TCGv_i32 temp = tcg_temp_new_i32();
4194 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4195 for (crn = 0 ; crn < 8 ; crn++) {
4196 if (crm & (1 << crn)) {
4197 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4198 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4199 }
4200 }
4201 }
4202 }
4203
4204 /* mtmsr */
4205 #if defined(TARGET_PPC64)
gen_mtmsrd(DisasContext * ctx)4206 static void gen_mtmsrd(DisasContext *ctx)
4207 {
4208 if (unlikely(!is_book3s_arch2x(ctx))) {
4209 gen_invalid(ctx);
4210 return;
4211 }
4212
4213 CHK_SV(ctx);
4214
4215 #if !defined(CONFIG_USER_ONLY)
4216 TCGv t0, t1;
4217 target_ulong mask;
4218
4219 t0 = tcg_temp_new();
4220 t1 = tcg_temp_new();
4221
4222 translator_io_start(&ctx->base);
4223
4224 if (ctx->opcode & 0x00010000) {
4225 /* L=1 form only updates EE and RI */
4226 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE);
4227 } else {
4228 /* mtmsrd does not alter HV, S, ME, or LE */
4229 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) |
4230 (1ULL << MSR_HV));
4231 /*
4232 * XXX: we need to update nip before the store if we enter
4233 * power saving mode, we will exit the loop directly from
4234 * ppc_store_msr
4235 */
4236 gen_update_nip(ctx, ctx->base.pc_next);
4237 }
4238
4239 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4240 tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4241 tcg_gen_or_tl(t0, t0, t1);
4242
4243 gen_helper_store_msr(tcg_env, t0);
4244
4245 /* Must stop the translation as machine state (may have) changed */
4246 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4247 #endif /* !defined(CONFIG_USER_ONLY) */
4248 }
4249 #endif /* defined(TARGET_PPC64) */
4250
gen_mtmsr(DisasContext * ctx)4251 static void gen_mtmsr(DisasContext *ctx)
4252 {
4253 CHK_SV(ctx);
4254
4255 #if !defined(CONFIG_USER_ONLY)
4256 TCGv t0, t1;
4257 target_ulong mask = 0xFFFFFFFF;
4258
4259 t0 = tcg_temp_new();
4260 t1 = tcg_temp_new();
4261
4262 translator_io_start(&ctx->base);
4263 if (ctx->opcode & 0x00010000) {
4264 /* L=1 form only updates EE and RI */
4265 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
4266 } else {
4267 /* mtmsr does not alter S, ME, or LE */
4268 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S));
4269
4270 /*
4271 * XXX: we need to update nip before the store if we enter
4272 * power saving mode, we will exit the loop directly from
4273 * ppc_store_msr
4274 */
4275 gen_update_nip(ctx, ctx->base.pc_next);
4276 }
4277
4278 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4279 tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4280 tcg_gen_or_tl(t0, t0, t1);
4281
4282 gen_helper_store_msr(tcg_env, t0);
4283
4284 /* Must stop the translation as machine state (may have) changed */
4285 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4286 #endif
4287 }
4288
4289 /* mtspr */
gen_mtspr(DisasContext * ctx)4290 static void gen_mtspr(DisasContext *ctx)
4291 {
4292 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4293 uint32_t sprn = SPR(ctx->opcode);
4294
4295 #if defined(CONFIG_USER_ONLY)
4296 write_cb = ctx->spr_cb[sprn].uea_write;
4297 #else
4298 if (ctx->pr) {
4299 write_cb = ctx->spr_cb[sprn].uea_write;
4300 } else if (ctx->hv) {
4301 write_cb = ctx->spr_cb[sprn].hea_write;
4302 } else {
4303 write_cb = ctx->spr_cb[sprn].oea_write;
4304 }
4305 #endif
4306 if (likely(write_cb != NULL)) {
4307 if (likely(write_cb != SPR_NOACCESS)) {
4308 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4309 } else {
4310 /* Privilege exception */
4311 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4312 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4313 ctx->cia);
4314 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4315 }
4316 } else {
4317 /* ISA 2.07 defines these as no-ops */
4318 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4319 (sprn >= 808 && sprn <= 811)) {
4320 /* This is a nop */
4321 return;
4322 }
4323
4324 /* Not defined */
4325 qemu_log_mask(LOG_GUEST_ERROR,
4326 "Trying to write invalid spr %d (0x%03x) at "
4327 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4328
4329
4330 /*
4331 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4332 * generate a priv, a hv emu or a no-op
4333 */
4334 if (sprn & 0x10) {
4335 if (ctx->pr) {
4336 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4337 }
4338 } else {
4339 if (ctx->pr || sprn == 0) {
4340 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4341 }
4342 }
4343 }
4344 }
4345
4346 #if defined(TARGET_PPC64)
4347 /* setb */
gen_setb(DisasContext * ctx)4348 static void gen_setb(DisasContext *ctx)
4349 {
4350 TCGv_i32 t0 = tcg_temp_new_i32();
4351 TCGv_i32 t8 = tcg_constant_i32(8);
4352 TCGv_i32 tm1 = tcg_constant_i32(-1);
4353 int crf = crfS(ctx->opcode);
4354
4355 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4356 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4357 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4358 }
4359 #endif
4360
4361 /*** Cache management ***/
4362
4363 /* dcbf */
gen_dcbf(DisasContext * ctx)4364 static void gen_dcbf(DisasContext *ctx)
4365 {
4366 /* XXX: specification says this is treated as a load by the MMU */
4367 TCGv t0;
4368 gen_set_access_type(ctx, ACCESS_CACHE);
4369 t0 = tcg_temp_new();
4370 gen_addr_reg_index(ctx, t0);
4371 gen_qemu_ld8u(ctx, t0, t0);
4372 }
4373
4374 /* dcbfep (external PID dcbf) */
gen_dcbfep(DisasContext * ctx)4375 static void gen_dcbfep(DisasContext *ctx)
4376 {
4377 /* XXX: specification says this is treated as a load by the MMU */
4378 TCGv t0;
4379 CHK_SV(ctx);
4380 gen_set_access_type(ctx, ACCESS_CACHE);
4381 t0 = tcg_temp_new();
4382 gen_addr_reg_index(ctx, t0);
4383 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4384 }
4385
4386 /* dcbi (Supervisor only) */
gen_dcbi(DisasContext * ctx)4387 static void gen_dcbi(DisasContext *ctx)
4388 {
4389 #if defined(CONFIG_USER_ONLY)
4390 GEN_PRIV(ctx);
4391 #else
4392 TCGv EA, val;
4393
4394 CHK_SV(ctx);
4395 EA = tcg_temp_new();
4396 gen_set_access_type(ctx, ACCESS_CACHE);
4397 gen_addr_reg_index(ctx, EA);
4398 val = tcg_temp_new();
4399 /* XXX: specification says this should be treated as a store by the MMU */
4400 gen_qemu_ld8u(ctx, val, EA);
4401 gen_qemu_st8(ctx, val, EA);
4402 #endif /* defined(CONFIG_USER_ONLY) */
4403 }
4404
4405 /* dcdst */
gen_dcbst(DisasContext * ctx)4406 static void gen_dcbst(DisasContext *ctx)
4407 {
4408 /* XXX: specification say this is treated as a load by the MMU */
4409 TCGv t0;
4410 gen_set_access_type(ctx, ACCESS_CACHE);
4411 t0 = tcg_temp_new();
4412 gen_addr_reg_index(ctx, t0);
4413 gen_qemu_ld8u(ctx, t0, t0);
4414 }
4415
4416 /* dcbstep (dcbstep External PID version) */
gen_dcbstep(DisasContext * ctx)4417 static void gen_dcbstep(DisasContext *ctx)
4418 {
4419 /* XXX: specification say this is treated as a load by the MMU */
4420 TCGv t0;
4421 gen_set_access_type(ctx, ACCESS_CACHE);
4422 t0 = tcg_temp_new();
4423 gen_addr_reg_index(ctx, t0);
4424 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4425 }
4426
4427 /* dcbt */
gen_dcbt(DisasContext * ctx)4428 static void gen_dcbt(DisasContext *ctx)
4429 {
4430 /*
4431 * interpreted as no-op
4432 * XXX: specification say this is treated as a load by the MMU but
4433 * does not generate any exception
4434 */
4435 }
4436
4437 /* dcbtep */
gen_dcbtep(DisasContext * ctx)4438 static void gen_dcbtep(DisasContext *ctx)
4439 {
4440 /*
4441 * interpreted as no-op
4442 * XXX: specification say this is treated as a load by the MMU but
4443 * does not generate any exception
4444 */
4445 }
4446
4447 /* dcbtst */
gen_dcbtst(DisasContext * ctx)4448 static void gen_dcbtst(DisasContext *ctx)
4449 {
4450 /*
4451 * interpreted as no-op
4452 * XXX: specification say this is treated as a load by the MMU but
4453 * does not generate any exception
4454 */
4455 }
4456
4457 /* dcbtstep */
gen_dcbtstep(DisasContext * ctx)4458 static void gen_dcbtstep(DisasContext *ctx)
4459 {
4460 /*
4461 * interpreted as no-op
4462 * XXX: specification say this is treated as a load by the MMU but
4463 * does not generate any exception
4464 */
4465 }
4466
4467 /* dcbtls */
gen_dcbtls(DisasContext * ctx)4468 static void gen_dcbtls(DisasContext *ctx)
4469 {
4470 /* Always fails locking the cache */
4471 TCGv t0 = tcg_temp_new();
4472 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4473 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4474 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4475 }
4476
4477 /* dcblc */
gen_dcblc(DisasContext * ctx)4478 static void gen_dcblc(DisasContext *ctx)
4479 {
4480 /*
4481 * interpreted as no-op
4482 */
4483 }
4484
4485 /* dcbz */
gen_dcbz(DisasContext * ctx)4486 static void gen_dcbz(DisasContext *ctx)
4487 {
4488 TCGv tcgv_addr = tcg_temp_new();
4489
4490 gen_set_access_type(ctx, ACCESS_CACHE);
4491 gen_addr_reg_index(ctx, tcgv_addr);
4492
4493 #ifdef TARGET_PPC64
4494 if (ctx->excp_model == POWERPC_EXCP_970 && !(ctx->opcode & 0x00200000)) {
4495 gen_helper_dcbzl(tcg_env, tcgv_addr);
4496 return;
4497 }
4498 #endif
4499
4500 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(ctx->mem_idx));
4501 }
4502
4503 /* dcbzep */
gen_dcbzep(DisasContext * ctx)4504 static void gen_dcbzep(DisasContext *ctx)
4505 {
4506 TCGv tcgv_addr = tcg_temp_new();
4507
4508 gen_set_access_type(ctx, ACCESS_CACHE);
4509 gen_addr_reg_index(ctx, tcgv_addr);
4510 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(PPC_TLB_EPID_STORE));
4511 }
4512
4513 /* dst / dstt */
gen_dst(DisasContext * ctx)4514 static void gen_dst(DisasContext *ctx)
4515 {
4516 if (rA(ctx->opcode) == 0) {
4517 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4518 } else {
4519 /* interpreted as no-op */
4520 }
4521 }
4522
4523 /* dstst /dststt */
gen_dstst(DisasContext * ctx)4524 static void gen_dstst(DisasContext *ctx)
4525 {
4526 if (rA(ctx->opcode) == 0) {
4527 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4528 } else {
4529 /* interpreted as no-op */
4530 }
4531
4532 }
4533
4534 /* dss / dssall */
gen_dss(DisasContext * ctx)4535 static void gen_dss(DisasContext *ctx)
4536 {
4537 /* interpreted as no-op */
4538 }
4539
4540 /* icbi */
gen_icbi(DisasContext * ctx)4541 static void gen_icbi(DisasContext *ctx)
4542 {
4543 TCGv t0;
4544 gen_set_access_type(ctx, ACCESS_CACHE);
4545 t0 = tcg_temp_new();
4546 gen_addr_reg_index(ctx, t0);
4547 gen_helper_icbi(tcg_env, t0);
4548 }
4549
4550 /* icbiep */
gen_icbiep(DisasContext * ctx)4551 static void gen_icbiep(DisasContext *ctx)
4552 {
4553 TCGv t0;
4554 gen_set_access_type(ctx, ACCESS_CACHE);
4555 t0 = tcg_temp_new();
4556 gen_addr_reg_index(ctx, t0);
4557 gen_helper_icbiep(tcg_env, t0);
4558 }
4559
4560 /* Optional: */
4561 /* dcba */
gen_dcba(DisasContext * ctx)4562 static void gen_dcba(DisasContext *ctx)
4563 {
4564 /*
4565 * interpreted as no-op
4566 * XXX: specification say this is treated as a store by the MMU
4567 * but does not generate any exception
4568 */
4569 }
4570
4571 /*** Segment register manipulation ***/
4572 /* Supervisor only: */
4573
4574 /* mfsr */
gen_mfsr(DisasContext * ctx)4575 static void gen_mfsr(DisasContext *ctx)
4576 {
4577 #if defined(CONFIG_USER_ONLY)
4578 GEN_PRIV(ctx);
4579 #else
4580 TCGv t0;
4581
4582 CHK_SV(ctx);
4583 t0 = tcg_constant_tl(SR(ctx->opcode));
4584 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
4585 #endif /* defined(CONFIG_USER_ONLY) */
4586 }
4587
4588 /* mfsrin */
gen_mfsrin(DisasContext * ctx)4589 static void gen_mfsrin(DisasContext *ctx)
4590 {
4591 #if defined(CONFIG_USER_ONLY)
4592 GEN_PRIV(ctx);
4593 #else
4594 TCGv t0;
4595
4596 CHK_SV(ctx);
4597 t0 = tcg_temp_new();
4598 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4599 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
4600 #endif /* defined(CONFIG_USER_ONLY) */
4601 }
4602
4603 /* mtsr */
gen_mtsr(DisasContext * ctx)4604 static void gen_mtsr(DisasContext *ctx)
4605 {
4606 #if defined(CONFIG_USER_ONLY)
4607 GEN_PRIV(ctx);
4608 #else
4609 TCGv t0;
4610
4611 CHK_SV(ctx);
4612 t0 = tcg_constant_tl(SR(ctx->opcode));
4613 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]);
4614 #endif /* defined(CONFIG_USER_ONLY) */
4615 }
4616
4617 /* mtsrin */
gen_mtsrin(DisasContext * ctx)4618 static void gen_mtsrin(DisasContext *ctx)
4619 {
4620 #if defined(CONFIG_USER_ONLY)
4621 GEN_PRIV(ctx);
4622 #else
4623 TCGv t0;
4624 CHK_SV(ctx);
4625
4626 t0 = tcg_temp_new();
4627 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4628 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]);
4629 #endif /* defined(CONFIG_USER_ONLY) */
4630 }
4631
4632 #if defined(TARGET_PPC64)
4633 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4634
4635 /* mfsr */
gen_mfsr_64b(DisasContext * ctx)4636 static void gen_mfsr_64b(DisasContext *ctx)
4637 {
4638 #if defined(CONFIG_USER_ONLY)
4639 GEN_PRIV(ctx);
4640 #else
4641 TCGv t0;
4642
4643 CHK_SV(ctx);
4644 t0 = tcg_constant_tl(SR(ctx->opcode));
4645 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
4646 #endif /* defined(CONFIG_USER_ONLY) */
4647 }
4648
4649 /* mfsrin */
gen_mfsrin_64b(DisasContext * ctx)4650 static void gen_mfsrin_64b(DisasContext *ctx)
4651 {
4652 #if defined(CONFIG_USER_ONLY)
4653 GEN_PRIV(ctx);
4654 #else
4655 TCGv t0;
4656
4657 CHK_SV(ctx);
4658 t0 = tcg_temp_new();
4659 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4660 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
4661 #endif /* defined(CONFIG_USER_ONLY) */
4662 }
4663
4664 /* mtsr */
gen_mtsr_64b(DisasContext * ctx)4665 static void gen_mtsr_64b(DisasContext *ctx)
4666 {
4667 #if defined(CONFIG_USER_ONLY)
4668 GEN_PRIV(ctx);
4669 #else
4670 TCGv t0;
4671
4672 CHK_SV(ctx);
4673 t0 = tcg_constant_tl(SR(ctx->opcode));
4674 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]);
4675 #endif /* defined(CONFIG_USER_ONLY) */
4676 }
4677
4678 /* mtsrin */
gen_mtsrin_64b(DisasContext * ctx)4679 static void gen_mtsrin_64b(DisasContext *ctx)
4680 {
4681 #if defined(CONFIG_USER_ONLY)
4682 GEN_PRIV(ctx);
4683 #else
4684 TCGv t0;
4685
4686 CHK_SV(ctx);
4687 t0 = tcg_temp_new();
4688 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4689 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]);
4690 #endif /* defined(CONFIG_USER_ONLY) */
4691 }
4692
4693 #endif /* defined(TARGET_PPC64) */
4694
4695 /*** Lookaside buffer management ***/
4696 /* Optional & supervisor only: */
4697
4698 /* tlbia */
gen_tlbia(DisasContext * ctx)4699 static void gen_tlbia(DisasContext *ctx)
4700 {
4701 #if defined(CONFIG_USER_ONLY)
4702 GEN_PRIV(ctx);
4703 #else
4704 CHK_HV(ctx);
4705
4706 gen_helper_tlbia(tcg_env);
4707 #endif /* defined(CONFIG_USER_ONLY) */
4708 }
4709
4710 /* tlbsync */
gen_tlbsync(DisasContext * ctx)4711 static void gen_tlbsync(DisasContext *ctx)
4712 {
4713 #if defined(CONFIG_USER_ONLY)
4714 GEN_PRIV(ctx);
4715 #else
4716
4717 if (ctx->gtse) {
4718 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */
4719 } else {
4720 CHK_HV(ctx); /* Else hypervisor privileged */
4721 }
4722
4723 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4724 if (ctx->insns_flags & PPC_BOOKE) {
4725 gen_check_tlb_flush(ctx, true);
4726 }
4727 #endif /* defined(CONFIG_USER_ONLY) */
4728 }
4729
4730 /*** External control ***/
4731 /* Optional: */
4732
4733 /* eciwx */
gen_eciwx(DisasContext * ctx)4734 static void gen_eciwx(DisasContext *ctx)
4735 {
4736 TCGv t0;
4737 /* Should check EAR[E] ! */
4738 gen_set_access_type(ctx, ACCESS_EXT);
4739 t0 = tcg_temp_new();
4740 gen_addr_reg_index(ctx, t0);
4741 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4742 DEF_MEMOP(MO_UL | MO_ALIGN));
4743 }
4744
4745 /* ecowx */
gen_ecowx(DisasContext * ctx)4746 static void gen_ecowx(DisasContext *ctx)
4747 {
4748 TCGv t0;
4749 /* Should check EAR[E] ! */
4750 gen_set_access_type(ctx, ACCESS_EXT);
4751 t0 = tcg_temp_new();
4752 gen_addr_reg_index(ctx, t0);
4753 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4754 DEF_MEMOP(MO_UL | MO_ALIGN));
4755 }
4756
4757 /* 602 - 603 - G2 TLB management */
4758
4759 /* tlbld */
gen_tlbld_6xx(DisasContext * ctx)4760 static void gen_tlbld_6xx(DisasContext *ctx)
4761 {
4762 #if defined(CONFIG_USER_ONLY)
4763 GEN_PRIV(ctx);
4764 #else
4765 CHK_SV(ctx);
4766 gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]);
4767 #endif /* defined(CONFIG_USER_ONLY) */
4768 }
4769
4770 /* tlbli */
gen_tlbli_6xx(DisasContext * ctx)4771 static void gen_tlbli_6xx(DisasContext *ctx)
4772 {
4773 #if defined(CONFIG_USER_ONLY)
4774 GEN_PRIV(ctx);
4775 #else
4776 CHK_SV(ctx);
4777 gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]);
4778 #endif /* defined(CONFIG_USER_ONLY) */
4779 }
4780
4781 /* BookE specific instructions */
4782
4783 /* XXX: not implemented on 440 ? */
gen_mfapidi(DisasContext * ctx)4784 static void gen_mfapidi(DisasContext *ctx)
4785 {
4786 /* XXX: TODO */
4787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4788 }
4789
4790 /* XXX: not implemented on 440 ? */
gen_tlbiva(DisasContext * ctx)4791 static void gen_tlbiva(DisasContext *ctx)
4792 {
4793 #if defined(CONFIG_USER_ONLY)
4794 GEN_PRIV(ctx);
4795 #else
4796 TCGv t0;
4797
4798 CHK_SV(ctx);
4799 t0 = tcg_temp_new();
4800 gen_addr_reg_index(ctx, t0);
4801 gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]);
4802 #endif /* defined(CONFIG_USER_ONLY) */
4803 }
4804
4805 /* All 405 MAC instructions are translated here */
gen_405_mulladd_insn(DisasContext * ctx,int opc2,int opc3,int ra,int rb,int rt,int Rc)4806 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
4807 int ra, int rb, int rt, int Rc)
4808 {
4809 TCGv t0, t1;
4810
4811 t0 = tcg_temp_new();
4812 t1 = tcg_temp_new();
4813
4814 switch (opc3 & 0x0D) {
4815 case 0x05:
4816 /* macchw - macchw. - macchwo - macchwo. */
4817 /* macchws - macchws. - macchwso - macchwso. */
4818 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4819 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4820 /* mulchw - mulchw. */
4821 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
4822 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
4823 tcg_gen_ext16s_tl(t1, t1);
4824 break;
4825 case 0x04:
4826 /* macchwu - macchwu. - macchwuo - macchwuo. */
4827 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4828 /* mulchwu - mulchwu. */
4829 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
4830 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
4831 tcg_gen_ext16u_tl(t1, t1);
4832 break;
4833 case 0x01:
4834 /* machhw - machhw. - machhwo - machhwo. */
4835 /* machhws - machhws. - machhwso - machhwso. */
4836 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4837 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4838 /* mulhhw - mulhhw. */
4839 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
4840 tcg_gen_ext16s_tl(t0, t0);
4841 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
4842 tcg_gen_ext16s_tl(t1, t1);
4843 break;
4844 case 0x00:
4845 /* machhwu - machhwu. - machhwuo - machhwuo. */
4846 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4847 /* mulhhwu - mulhhwu. */
4848 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
4849 tcg_gen_ext16u_tl(t0, t0);
4850 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
4851 tcg_gen_ext16u_tl(t1, t1);
4852 break;
4853 case 0x0D:
4854 /* maclhw - maclhw. - maclhwo - maclhwo. */
4855 /* maclhws - maclhws. - maclhwso - maclhwso. */
4856 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4857 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4858 /* mullhw - mullhw. */
4859 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
4860 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
4861 break;
4862 case 0x0C:
4863 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4864 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4865 /* mullhwu - mullhwu. */
4866 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
4867 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
4868 break;
4869 }
4870 if (opc2 & 0x04) {
4871 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
4872 tcg_gen_mul_tl(t1, t0, t1);
4873 if (opc2 & 0x02) {
4874 /* nmultiply-and-accumulate (0x0E) */
4875 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
4876 } else {
4877 /* multiply-and-accumulate (0x0C) */
4878 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
4879 }
4880
4881 if (opc3 & 0x12) {
4882 /* Check overflow and/or saturate */
4883 TCGLabel *l1 = gen_new_label();
4884
4885 if (opc3 & 0x10) {
4886 /* Start with XER OV disabled, the most likely case */
4887 tcg_gen_movi_tl(cpu_ov, 0);
4888 }
4889 if (opc3 & 0x01) {
4890 /* Signed */
4891 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
4892 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
4893 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
4894 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
4895 if (opc3 & 0x02) {
4896 /* Saturate */
4897 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
4898 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
4899 }
4900 } else {
4901 /* Unsigned */
4902 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
4903 if (opc3 & 0x02) {
4904 /* Saturate */
4905 tcg_gen_movi_tl(t0, UINT32_MAX);
4906 }
4907 }
4908 if (opc3 & 0x10) {
4909 /* Check overflow */
4910 tcg_gen_movi_tl(cpu_ov, 1);
4911 tcg_gen_movi_tl(cpu_so, 1);
4912 }
4913 gen_set_label(l1);
4914 tcg_gen_mov_tl(cpu_gpr[rt], t0);
4915 }
4916 } else {
4917 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
4918 }
4919 if (unlikely(Rc) != 0) {
4920 /* Update Rc0 */
4921 gen_set_Rc0(ctx, cpu_gpr[rt]);
4922 }
4923 }
4924
4925 #define GEN_MAC_HANDLER(name, opc2, opc3) \
4926 static void glue(gen_, name)(DisasContext *ctx) \
4927 { \
4928 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4929 rD(ctx->opcode), Rc(ctx->opcode)); \
4930 }
4931
4932 /* macchw - macchw. */
4933 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
4934 /* macchwo - macchwo. */
4935 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
4936 /* macchws - macchws. */
4937 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
4938 /* macchwso - macchwso. */
4939 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
4940 /* macchwsu - macchwsu. */
4941 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
4942 /* macchwsuo - macchwsuo. */
4943 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
4944 /* macchwu - macchwu. */
4945 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
4946 /* macchwuo - macchwuo. */
4947 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
4948 /* machhw - machhw. */
4949 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
4950 /* machhwo - machhwo. */
4951 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
4952 /* machhws - machhws. */
4953 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
4954 /* machhwso - machhwso. */
4955 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
4956 /* machhwsu - machhwsu. */
4957 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
4958 /* machhwsuo - machhwsuo. */
4959 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
4960 /* machhwu - machhwu. */
4961 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
4962 /* machhwuo - machhwuo. */
4963 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
4964 /* maclhw - maclhw. */
4965 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
4966 /* maclhwo - maclhwo. */
4967 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
4968 /* maclhws - maclhws. */
4969 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
4970 /* maclhwso - maclhwso. */
4971 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
4972 /* maclhwu - maclhwu. */
4973 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
4974 /* maclhwuo - maclhwuo. */
4975 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
4976 /* maclhwsu - maclhwsu. */
4977 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
4978 /* maclhwsuo - maclhwsuo. */
4979 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
4980 /* nmacchw - nmacchw. */
4981 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
4982 /* nmacchwo - nmacchwo. */
4983 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
4984 /* nmacchws - nmacchws. */
4985 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
4986 /* nmacchwso - nmacchwso. */
4987 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
4988 /* nmachhw - nmachhw. */
4989 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
4990 /* nmachhwo - nmachhwo. */
4991 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
4992 /* nmachhws - nmachhws. */
4993 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
4994 /* nmachhwso - nmachhwso. */
4995 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
4996 /* nmaclhw - nmaclhw. */
4997 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
4998 /* nmaclhwo - nmaclhwo. */
4999 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5000 /* nmaclhws - nmaclhws. */
5001 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5002 /* nmaclhwso - nmaclhwso. */
5003 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5004
5005 /* mulchw - mulchw. */
5006 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5007 /* mulchwu - mulchwu. */
5008 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5009 /* mulhhw - mulhhw. */
5010 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5011 /* mulhhwu - mulhhwu. */
5012 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5013 /* mullhw - mullhw. */
5014 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5015 /* mullhwu - mullhwu. */
5016 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5017
5018 /* mfdcr */
gen_mfdcr(DisasContext * ctx)5019 static void gen_mfdcr(DisasContext *ctx)
5020 {
5021 #if defined(CONFIG_USER_ONLY)
5022 GEN_PRIV(ctx);
5023 #else
5024 TCGv dcrn;
5025
5026 CHK_SV(ctx);
5027 dcrn = tcg_constant_tl(SPR(ctx->opcode));
5028 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn);
5029 #endif /* defined(CONFIG_USER_ONLY) */
5030 }
5031
5032 /* mtdcr */
gen_mtdcr(DisasContext * ctx)5033 static void gen_mtdcr(DisasContext *ctx)
5034 {
5035 #if defined(CONFIG_USER_ONLY)
5036 GEN_PRIV(ctx);
5037 #else
5038 TCGv dcrn;
5039
5040 CHK_SV(ctx);
5041 dcrn = tcg_constant_tl(SPR(ctx->opcode));
5042 gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5043 #endif /* defined(CONFIG_USER_ONLY) */
5044 }
5045
5046 /* mfdcrx */
5047 /* XXX: not implemented on 440 ? */
gen_mfdcrx(DisasContext * ctx)5048 static void gen_mfdcrx(DisasContext *ctx)
5049 {
5050 #if defined(CONFIG_USER_ONLY)
5051 GEN_PRIV(ctx);
5052 #else
5053 CHK_SV(ctx);
5054 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env,
5055 cpu_gpr[rA(ctx->opcode)]);
5056 /* Note: Rc update flag set leads to undefined state of Rc0 */
5057 #endif /* defined(CONFIG_USER_ONLY) */
5058 }
5059
5060 /* mtdcrx */
5061 /* XXX: not implemented on 440 ? */
gen_mtdcrx(DisasContext * ctx)5062 static void gen_mtdcrx(DisasContext *ctx)
5063 {
5064 #if defined(CONFIG_USER_ONLY)
5065 GEN_PRIV(ctx);
5066 #else
5067 CHK_SV(ctx);
5068 gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)],
5069 cpu_gpr[rS(ctx->opcode)]);
5070 /* Note: Rc update flag set leads to undefined state of Rc0 */
5071 #endif /* defined(CONFIG_USER_ONLY) */
5072 }
5073
5074 /* dccci */
gen_dccci(DisasContext * ctx)5075 static void gen_dccci(DisasContext *ctx)
5076 {
5077 CHK_SV(ctx);
5078 /* interpreted as no-op */
5079 }
5080
5081 /* dcread */
gen_dcread(DisasContext * ctx)5082 static void gen_dcread(DisasContext *ctx)
5083 {
5084 #if defined(CONFIG_USER_ONLY)
5085 GEN_PRIV(ctx);
5086 #else
5087 TCGv EA, val;
5088
5089 CHK_SV(ctx);
5090 gen_set_access_type(ctx, ACCESS_CACHE);
5091 EA = tcg_temp_new();
5092 gen_addr_reg_index(ctx, EA);
5093 val = tcg_temp_new();
5094 gen_qemu_ld32u(ctx, val, EA);
5095 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5096 #endif /* defined(CONFIG_USER_ONLY) */
5097 }
5098
5099 /* icbt */
gen_icbt_40x(DisasContext * ctx)5100 static void gen_icbt_40x(DisasContext *ctx)
5101 {
5102 /*
5103 * interpreted as no-op
5104 * XXX: specification say this is treated as a load by the MMU but
5105 * does not generate any exception
5106 */
5107 }
5108
5109 /* iccci */
gen_iccci(DisasContext * ctx)5110 static void gen_iccci(DisasContext *ctx)
5111 {
5112 CHK_SV(ctx);
5113 /* interpreted as no-op */
5114 }
5115
5116 /* icread */
gen_icread(DisasContext * ctx)5117 static void gen_icread(DisasContext *ctx)
5118 {
5119 CHK_SV(ctx);
5120 /* interpreted as no-op */
5121 }
5122
5123 /* rfci (supervisor only) */
gen_rfci_40x(DisasContext * ctx)5124 static void gen_rfci_40x(DisasContext *ctx)
5125 {
5126 #if defined(CONFIG_USER_ONLY)
5127 GEN_PRIV(ctx);
5128 #else
5129 CHK_SV(ctx);
5130 /* Restore CPU state */
5131 gen_helper_40x_rfci(tcg_env);
5132 ctx->base.is_jmp = DISAS_EXIT;
5133 #endif /* defined(CONFIG_USER_ONLY) */
5134 }
5135
gen_rfci(DisasContext * ctx)5136 static void gen_rfci(DisasContext *ctx)
5137 {
5138 #if defined(CONFIG_USER_ONLY)
5139 GEN_PRIV(ctx);
5140 #else
5141 CHK_SV(ctx);
5142 /* Restore CPU state */
5143 gen_helper_rfci(tcg_env);
5144 ctx->base.is_jmp = DISAS_EXIT;
5145 #endif /* defined(CONFIG_USER_ONLY) */
5146 }
5147
5148 /* BookE specific */
5149
5150 /* XXX: not implemented on 440 ? */
gen_rfdi(DisasContext * ctx)5151 static void gen_rfdi(DisasContext *ctx)
5152 {
5153 #if defined(CONFIG_USER_ONLY)
5154 GEN_PRIV(ctx);
5155 #else
5156 CHK_SV(ctx);
5157 /* Restore CPU state */
5158 gen_helper_rfdi(tcg_env);
5159 ctx->base.is_jmp = DISAS_EXIT;
5160 #endif /* defined(CONFIG_USER_ONLY) */
5161 }
5162
5163 /* XXX: not implemented on 440 ? */
gen_rfmci(DisasContext * ctx)5164 static void gen_rfmci(DisasContext *ctx)
5165 {
5166 #if defined(CONFIG_USER_ONLY)
5167 GEN_PRIV(ctx);
5168 #else
5169 CHK_SV(ctx);
5170 /* Restore CPU state */
5171 gen_helper_rfmci(tcg_env);
5172 ctx->base.is_jmp = DISAS_EXIT;
5173 #endif /* defined(CONFIG_USER_ONLY) */
5174 }
5175
5176 /* TLB management - PowerPC 405 implementation */
5177
5178 /* tlbre */
gen_tlbre_40x(DisasContext * ctx)5179 static void gen_tlbre_40x(DisasContext *ctx)
5180 {
5181 #if defined(CONFIG_USER_ONLY)
5182 GEN_PRIV(ctx);
5183 #else
5184 CHK_SV(ctx);
5185 switch (rB(ctx->opcode)) {
5186 case 0:
5187 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env,
5188 cpu_gpr[rA(ctx->opcode)]);
5189 break;
5190 case 1:
5191 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env,
5192 cpu_gpr[rA(ctx->opcode)]);
5193 break;
5194 default:
5195 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5196 break;
5197 }
5198 #endif /* defined(CONFIG_USER_ONLY) */
5199 }
5200
5201 /* tlbsx - tlbsx. */
gen_tlbsx_40x(DisasContext * ctx)5202 static void gen_tlbsx_40x(DisasContext *ctx)
5203 {
5204 #if defined(CONFIG_USER_ONLY)
5205 GEN_PRIV(ctx);
5206 #else
5207 TCGv t0;
5208
5209 CHK_SV(ctx);
5210 t0 = tcg_temp_new();
5211 gen_addr_reg_index(ctx, t0);
5212 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
5213 if (Rc(ctx->opcode)) {
5214 TCGLabel *l1 = gen_new_label();
5215 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5216 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5217 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5218 gen_set_label(l1);
5219 }
5220 #endif /* defined(CONFIG_USER_ONLY) */
5221 }
5222
5223 /* tlbwe */
gen_tlbwe_40x(DisasContext * ctx)5224 static void gen_tlbwe_40x(DisasContext *ctx)
5225 {
5226 #if defined(CONFIG_USER_ONLY)
5227 GEN_PRIV(ctx);
5228 #else
5229 CHK_SV(ctx);
5230
5231 switch (rB(ctx->opcode)) {
5232 case 0:
5233 gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)],
5234 cpu_gpr[rS(ctx->opcode)]);
5235 break;
5236 case 1:
5237 gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)],
5238 cpu_gpr[rS(ctx->opcode)]);
5239 break;
5240 default:
5241 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5242 break;
5243 }
5244 #endif /* defined(CONFIG_USER_ONLY) */
5245 }
5246
5247 /* TLB management - PowerPC 440 implementation */
5248
5249 /* tlbre */
gen_tlbre_440(DisasContext * ctx)5250 static void gen_tlbre_440(DisasContext *ctx)
5251 {
5252 #if defined(CONFIG_USER_ONLY)
5253 GEN_PRIV(ctx);
5254 #else
5255 CHK_SV(ctx);
5256
5257 switch (rB(ctx->opcode)) {
5258 case 0:
5259 case 1:
5260 case 2:
5261 {
5262 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
5263 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env,
5264 t0, cpu_gpr[rA(ctx->opcode)]);
5265 }
5266 break;
5267 default:
5268 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5269 break;
5270 }
5271 #endif /* defined(CONFIG_USER_ONLY) */
5272 }
5273
5274 /* tlbsx - tlbsx. */
gen_tlbsx_440(DisasContext * ctx)5275 static void gen_tlbsx_440(DisasContext *ctx)
5276 {
5277 #if defined(CONFIG_USER_ONLY)
5278 GEN_PRIV(ctx);
5279 #else
5280 TCGv t0;
5281
5282 CHK_SV(ctx);
5283 t0 = tcg_temp_new();
5284 gen_addr_reg_index(ctx, t0);
5285 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
5286 if (Rc(ctx->opcode)) {
5287 TCGLabel *l1 = gen_new_label();
5288 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5289 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5290 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5291 gen_set_label(l1);
5292 }
5293 #endif /* defined(CONFIG_USER_ONLY) */
5294 }
5295
5296 /* tlbwe */
gen_tlbwe_440(DisasContext * ctx)5297 static void gen_tlbwe_440(DisasContext *ctx)
5298 {
5299 #if defined(CONFIG_USER_ONLY)
5300 GEN_PRIV(ctx);
5301 #else
5302 CHK_SV(ctx);
5303 switch (rB(ctx->opcode)) {
5304 case 0:
5305 case 1:
5306 case 2:
5307 {
5308 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
5309 gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)],
5310 cpu_gpr[rS(ctx->opcode)]);
5311 }
5312 break;
5313 default:
5314 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5315 break;
5316 }
5317 #endif /* defined(CONFIG_USER_ONLY) */
5318 }
5319
5320 /* TLB management - PowerPC BookE 2.06 implementation */
5321
5322 /* tlbre */
gen_tlbre_booke206(DisasContext * ctx)5323 static void gen_tlbre_booke206(DisasContext *ctx)
5324 {
5325 #if defined(CONFIG_USER_ONLY)
5326 GEN_PRIV(ctx);
5327 #else
5328 CHK_SV(ctx);
5329 gen_helper_booke206_tlbre(tcg_env);
5330 #endif /* defined(CONFIG_USER_ONLY) */
5331 }
5332
5333 /* tlbsx - tlbsx. */
gen_tlbsx_booke206(DisasContext * ctx)5334 static void gen_tlbsx_booke206(DisasContext *ctx)
5335 {
5336 #if defined(CONFIG_USER_ONLY)
5337 GEN_PRIV(ctx);
5338 #else
5339 TCGv t0;
5340
5341 CHK_SV(ctx);
5342 if (rA(ctx->opcode)) {
5343 t0 = tcg_temp_new();
5344 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5345 } else {
5346 t0 = cpu_gpr[rB(ctx->opcode)];
5347 }
5348 gen_helper_booke206_tlbsx(tcg_env, t0);
5349 #endif /* defined(CONFIG_USER_ONLY) */
5350 }
5351
5352 /* tlbwe */
gen_tlbwe_booke206(DisasContext * ctx)5353 static void gen_tlbwe_booke206(DisasContext *ctx)
5354 {
5355 #if defined(CONFIG_USER_ONLY)
5356 GEN_PRIV(ctx);
5357 #else
5358 CHK_SV(ctx);
5359 gen_helper_booke206_tlbwe(tcg_env);
5360 #endif /* defined(CONFIG_USER_ONLY) */
5361 }
5362
gen_tlbivax_booke206(DisasContext * ctx)5363 static void gen_tlbivax_booke206(DisasContext *ctx)
5364 {
5365 #if defined(CONFIG_USER_ONLY)
5366 GEN_PRIV(ctx);
5367 #else
5368 TCGv t0;
5369
5370 CHK_SV(ctx);
5371 t0 = tcg_temp_new();
5372 gen_addr_reg_index(ctx, t0);
5373 gen_helper_booke206_tlbivax(tcg_env, t0);
5374 #endif /* defined(CONFIG_USER_ONLY) */
5375 }
5376
gen_tlbilx_booke206(DisasContext * ctx)5377 static void gen_tlbilx_booke206(DisasContext *ctx)
5378 {
5379 #if defined(CONFIG_USER_ONLY)
5380 GEN_PRIV(ctx);
5381 #else
5382 TCGv t0;
5383
5384 CHK_SV(ctx);
5385 t0 = tcg_temp_new();
5386 gen_addr_reg_index(ctx, t0);
5387
5388 switch ((ctx->opcode >> 21) & 0x3) {
5389 case 0:
5390 gen_helper_booke206_tlbilx0(tcg_env, t0);
5391 break;
5392 case 1:
5393 gen_helper_booke206_tlbilx1(tcg_env, t0);
5394 break;
5395 case 3:
5396 gen_helper_booke206_tlbilx3(tcg_env, t0);
5397 break;
5398 default:
5399 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5400 break;
5401 }
5402 #endif /* defined(CONFIG_USER_ONLY) */
5403 }
5404
5405 /* wrtee */
gen_wrtee(DisasContext * ctx)5406 static void gen_wrtee(DisasContext *ctx)
5407 {
5408 #if defined(CONFIG_USER_ONLY)
5409 GEN_PRIV(ctx);
5410 #else
5411 TCGv t0;
5412
5413 CHK_SV(ctx);
5414 t0 = tcg_temp_new();
5415 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5416 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5417 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5418 gen_ppc_maybe_interrupt(ctx);
5419 /*
5420 * Stop translation to have a chance to raise an exception if we
5421 * just set msr_ee to 1
5422 */
5423 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
5424 #endif /* defined(CONFIG_USER_ONLY) */
5425 }
5426
5427 /* wrteei */
gen_wrteei(DisasContext * ctx)5428 static void gen_wrteei(DisasContext *ctx)
5429 {
5430 #if defined(CONFIG_USER_ONLY)
5431 GEN_PRIV(ctx);
5432 #else
5433 CHK_SV(ctx);
5434 if (ctx->opcode & 0x00008000) {
5435 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5436 gen_ppc_maybe_interrupt(ctx);
5437 /* Stop translation to have a chance to raise an exception */
5438 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
5439 } else {
5440 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5441 }
5442 #endif /* defined(CONFIG_USER_ONLY) */
5443 }
5444
5445 /* PowerPC 440 specific instructions */
5446
5447 /* dlmzb */
gen_dlmzb(DisasContext * ctx)5448 static void gen_dlmzb(DisasContext *ctx)
5449 {
5450 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
5451 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env,
5452 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5453 }
5454
5455 /* icbt */
gen_icbt_440(DisasContext * ctx)5456 static void gen_icbt_440(DisasContext *ctx)
5457 {
5458 /*
5459 * interpreted as no-op
5460 * XXX: specification say this is treated as a load by the MMU but
5461 * does not generate any exception
5462 */
5463 }
5464
gen_tbegin(DisasContext * ctx)5465 static void gen_tbegin(DisasContext *ctx)
5466 {
5467 if (unlikely(!ctx->tm_enabled)) {
5468 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
5469 return;
5470 }
5471 gen_helper_tbegin(tcg_env);
5472 }
5473
5474 #define GEN_TM_NOOP(name) \
5475 static inline void gen_##name(DisasContext *ctx) \
5476 { \
5477 if (unlikely(!ctx->tm_enabled)) { \
5478 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
5479 return; \
5480 } \
5481 /* \
5482 * Because tbegin always fails in QEMU, these user \
5483 * space instructions all have a simple implementation: \
5484 * \
5485 * CR[0] = 0b0 || MSR[TS] || 0b0 \
5486 * = 0b0 || 0b00 || 0b0 \
5487 */ \
5488 tcg_gen_movi_i32(cpu_crf[0], 0); \
5489 }
5490
5491 GEN_TM_NOOP(tend);
5492 GEN_TM_NOOP(tabort);
5493 GEN_TM_NOOP(tabortwc);
5494 GEN_TM_NOOP(tabortwci);
5495 GEN_TM_NOOP(tabortdc);
5496 GEN_TM_NOOP(tabortdci);
5497 GEN_TM_NOOP(tsr);
5498
gen_cp_abort(DisasContext * ctx)5499 static inline void gen_cp_abort(DisasContext *ctx)
5500 {
5501 /* Do Nothing */
5502 }
5503
5504 #define GEN_CP_PASTE_NOOP(name) \
5505 static inline void gen_##name(DisasContext *ctx) \
5506 { \
5507 /* \
5508 * Generate invalid exception until we have an \
5509 * implementation of the copy paste facility \
5510 */ \
5511 gen_invalid(ctx); \
5512 }
5513
5514 GEN_CP_PASTE_NOOP(copy)
GEN_CP_PASTE_NOOP(paste)5515 GEN_CP_PASTE_NOOP(paste)
5516
5517 static void gen_tcheck(DisasContext *ctx)
5518 {
5519 if (unlikely(!ctx->tm_enabled)) {
5520 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
5521 return;
5522 }
5523 /*
5524 * Because tbegin always fails, the tcheck implementation is
5525 * simple:
5526 *
5527 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
5528 * = 0b1 || 0b00 || 0b0
5529 */
5530 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
5531 }
5532
5533 #if defined(CONFIG_USER_ONLY)
5534 #define GEN_TM_PRIV_NOOP(name) \
5535 static inline void gen_##name(DisasContext *ctx) \
5536 { \
5537 gen_priv_opc(ctx); \
5538 }
5539
5540 #else
5541
5542 #define GEN_TM_PRIV_NOOP(name) \
5543 static inline void gen_##name(DisasContext *ctx) \
5544 { \
5545 CHK_SV(ctx); \
5546 if (unlikely(!ctx->tm_enabled)) { \
5547 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
5548 return; \
5549 } \
5550 /* \
5551 * Because tbegin always fails, the implementation is \
5552 * simple: \
5553 * \
5554 * CR[0] = 0b0 || MSR[TS] || 0b0 \
5555 * = 0b0 || 0b00 | 0b0 \
5556 */ \
5557 tcg_gen_movi_i32(cpu_crf[0], 0); \
5558 }
5559
5560 #endif
5561
5562 GEN_TM_PRIV_NOOP(treclaim);
5563 GEN_TM_PRIV_NOOP(trechkpt);
5564
get_fpr(TCGv_i64 dst,int regno)5565 static inline void get_fpr(TCGv_i64 dst, int regno)
5566 {
5567 tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno));
5568 }
5569
set_fpr(int regno,TCGv_i64 src)5570 static inline void set_fpr(int regno, TCGv_i64 src)
5571 {
5572 tcg_gen_st_i64(src, tcg_env, fpr_offset(regno));
5573 /*
5574 * Before PowerISA v3.1 the result of doubleword 1 of the VSR
5575 * corresponding to the target FPR was undefined. However,
5576 * most (if not all) real hardware were setting the result to 0.
5577 * Starting at ISA v3.1, the result for doubleword 1 is now defined
5578 * to be 0.
5579 */
5580 tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false));
5581 }
5582
5583 /*
5584 * Helpers for decodetree used by !function for decoding arguments.
5585 */
times_2(DisasContext * ctx,int x)5586 static int times_2(DisasContext *ctx, int x)
5587 {
5588 return x * 2;
5589 }
5590
times_4(DisasContext * ctx,int x)5591 static int times_4(DisasContext *ctx, int x)
5592 {
5593 return x * 4;
5594 }
5595
times_16(DisasContext * ctx,int x)5596 static int times_16(DisasContext *ctx, int x)
5597 {
5598 return x * 16;
5599 }
5600
dw_compose_ea(DisasContext * ctx,int x)5601 static int64_t dw_compose_ea(DisasContext *ctx, int x)
5602 {
5603 return deposit64(0xfffffffffffffe00, 3, 6, x);
5604 }
5605
5606 /*
5607 * Helpers for trans_* functions to check for specific insns flags.
5608 * Use token pasting to ensure that we use the proper flag with the
5609 * proper variable.
5610 */
5611 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \
5612 do { \
5613 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
5614 return false; \
5615 } \
5616 } while (0)
5617
5618 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
5619 do { \
5620 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
5621 return false; \
5622 } \
5623 } while (0)
5624
5625 /* Then special-case the check for 64-bit so that we elide code for ppc32. */
5626 #if TARGET_LONG_BITS == 32
5627 # define REQUIRE_64BIT(CTX) return false
5628 #else
5629 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
5630 #endif
5631
5632 #define REQUIRE_VECTOR(CTX) \
5633 do { \
5634 if (unlikely(!(CTX)->altivec_enabled)) { \
5635 gen_exception((CTX), POWERPC_EXCP_VPU); \
5636 return true; \
5637 } \
5638 } while (0)
5639
5640 #define REQUIRE_VSX(CTX) \
5641 do { \
5642 if (unlikely(!(CTX)->vsx_enabled)) { \
5643 gen_exception((CTX), POWERPC_EXCP_VSXU); \
5644 return true; \
5645 } \
5646 } while (0)
5647
5648 #define REQUIRE_FPU(ctx) \
5649 do { \
5650 if (unlikely(!(ctx)->fpu_enabled)) { \
5651 gen_exception((ctx), POWERPC_EXCP_FPU); \
5652 return true; \
5653 } \
5654 } while (0)
5655
5656 #if !defined(CONFIG_USER_ONLY)
5657 #define REQUIRE_SV(CTX) \
5658 do { \
5659 if (unlikely((CTX)->pr)) { \
5660 gen_priv_opc(CTX); \
5661 return true; \
5662 } \
5663 } while (0)
5664
5665 #define REQUIRE_HV(CTX) \
5666 do { \
5667 if (unlikely((CTX)->pr || !(CTX)->hv)) { \
5668 gen_priv_opc(CTX); \
5669 return true; \
5670 } \
5671 } while (0)
5672 #else
5673 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
5674 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
5675 #endif
5676
5677 /*
5678 * Helpers for implementing sets of trans_* functions.
5679 * Defer the implementation of NAME to FUNC, with optional extra arguments.
5680 */
5681 #define TRANS(NAME, FUNC, ...) \
5682 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
5683 { return FUNC(ctx, a, __VA_ARGS__); }
5684 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \
5685 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
5686 { \
5687 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \
5688 return FUNC(ctx, a, __VA_ARGS__); \
5689 }
5690 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \
5691 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
5692 { \
5693 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \
5694 return FUNC(ctx, a, __VA_ARGS__); \
5695 }
5696
5697 #define TRANS64(NAME, FUNC, ...) \
5698 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
5699 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
5700 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \
5701 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
5702 { \
5703 REQUIRE_64BIT(ctx); \
5704 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \
5705 return FUNC(ctx, a, __VA_ARGS__); \
5706 }
5707
5708 /* TODO: More TRANS* helpers for extra insn_flags checks. */
5709
5710
5711 #include "decode-insn32.c.inc"
5712 #include "decode-insn64.c.inc"
5713 #include "power8-pmu-regs.c.inc"
5714
5715 /*
5716 * Incorporate CIA into the constant when R=1.
5717 * Validate that when R=1, RA=0.
5718 */
resolve_PLS_D(DisasContext * ctx,arg_D * d,arg_PLS_D * a)5719 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
5720 {
5721 d->rt = a->rt;
5722 d->ra = a->ra;
5723 d->si = a->si;
5724 if (a->r) {
5725 if (unlikely(a->ra != 0)) {
5726 gen_invalid(ctx);
5727 return false;
5728 }
5729 d->si += ctx->cia;
5730 }
5731 return true;
5732 }
5733
5734 #include "translate/fixedpoint-impl.c.inc"
5735
5736 #include "translate/fp-impl.c.inc"
5737
5738 #include "translate/vmx-impl.c.inc"
5739
5740 #include "translate/vsx-impl.c.inc"
5741
5742 #include "translate/dfp-impl.c.inc"
5743
5744 #include "translate/spe-impl.c.inc"
5745
5746 #include "translate/branch-impl.c.inc"
5747
5748 #include "translate/processor-ctrl-impl.c.inc"
5749
5750 #include "translate/storage-ctrl-impl.c.inc"
5751
5752 #include "translate/misc-impl.c.inc"
5753
5754 #include "translate/bhrb-impl.c.inc"
5755
5756 /* Handles lfdp */
gen_dform39(DisasContext * ctx)5757 static void gen_dform39(DisasContext *ctx)
5758 {
5759 if ((ctx->opcode & 0x3) == 0) {
5760 if (ctx->insns_flags2 & PPC2_ISA205) {
5761 return gen_lfdp(ctx);
5762 }
5763 }
5764 return gen_invalid(ctx);
5765 }
5766
5767 /* Handles stfdp */
gen_dform3D(DisasContext * ctx)5768 static void gen_dform3D(DisasContext *ctx)
5769 {
5770 if ((ctx->opcode & 3) == 0) { /* DS-FORM */
5771 /* stfdp */
5772 if (ctx->insns_flags2 & PPC2_ISA205) {
5773 return gen_stfdp(ctx);
5774 }
5775 }
5776 return gen_invalid(ctx);
5777 }
5778
5779 #if defined(TARGET_PPC64)
5780 /* brd */
gen_brd(DisasContext * ctx)5781 static void gen_brd(DisasContext *ctx)
5782 {
5783 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5784 }
5785
5786 /* brw */
gen_brw(DisasContext * ctx)5787 static void gen_brw(DisasContext *ctx)
5788 {
5789 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5790 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
5791
5792 }
5793
5794 /* brh */
gen_brh(DisasContext * ctx)5795 static void gen_brh(DisasContext *ctx)
5796 {
5797 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull);
5798 TCGv_i64 t1 = tcg_temp_new_i64();
5799 TCGv_i64 t2 = tcg_temp_new_i64();
5800
5801 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
5802 tcg_gen_and_i64(t2, t1, mask);
5803 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask);
5804 tcg_gen_shli_i64(t1, t1, 8);
5805 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
5806 }
5807 #endif
5808
5809 static opcode_t opcodes[] = {
5810 #if defined(TARGET_PPC64)
5811 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
5812 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
5813 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
5814 #endif
5815 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
5816 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
5817 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
5818 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
5819 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
5820 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
5821 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
5822 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
5823 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
5824 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
5825 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
5826 #if defined(TARGET_PPC64)
5827 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
5828 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
5829 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
5830 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
5831 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
5832 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
5833 PPC_NONE, PPC2_ISA300),
5834 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
5835 PPC_NONE, PPC2_ISA300),
5836 #endif
5837 /* handles lfdp, lxsd, lxssp */
5838 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
5839 /* handles stfdp, stxsd, stxssp */
5840 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
5841 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
5842 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
5843 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
5844 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
5845 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
5846 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
5847 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5848 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5849 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5850 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
5851 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
5852 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
5853 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5854 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5855 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
5856 #if defined(TARGET_PPC64)
5857 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
5858 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
5859 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
5860 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5861 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
5862 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5863 #endif
5864 /* ISA v3.0 changed the extended opcode from 62 to 30 */
5865 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
5866 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300),
5867 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
5868 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
5869 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
5870 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
5871 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
5872 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
5873 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
5874 #if defined(TARGET_PPC64)
5875 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
5876 #if !defined(CONFIG_USER_ONLY)
5877 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
5878 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
5879 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
5880 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
5881 #endif
5882 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
5883 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
5884 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
5885 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
5886 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
5887 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
5888 #endif
5889 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
5890 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
5891 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
5892 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
5893 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
5894 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
5895 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
5896 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
5897 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
5898 #if defined(TARGET_PPC64)
5899 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
5900 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
5901 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
5902 #endif
5903 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
5904 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
5905 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
5906 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
5907 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
5908 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
5909 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
5910 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
5911 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
5912 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
5913 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
5914 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
5915 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
5916 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
5917 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
5918 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
5919 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
5920 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
5921 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
5922 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
5923 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
5924 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
5925 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
5926 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
5927 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
5928 #if defined(TARGET_PPC64)
5929 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
5930 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
5931 PPC_SEGMENT_64B),
5932 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
5933 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
5934 PPC_SEGMENT_64B),
5935 #endif
5936 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
5937 /*
5938 * XXX Those instructions will need to be handled differently for
5939 * different ISA versions
5940 */
5941 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
5942 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
5943 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
5944 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
5945 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
5946 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
5947 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
5948 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
5949 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
5950 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
5951 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
5952 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
5953 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
5954 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
5955 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
5956 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
5957 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
5958 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
5959 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
5960 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
5961 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
5962 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
5963 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
5964 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
5965 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
5966 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
5967 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
5968 PPC_NONE, PPC2_BOOKE206),
5969 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
5970 PPC_NONE, PPC2_BOOKE206),
5971 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
5972 PPC_NONE, PPC2_BOOKE206),
5973 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
5974 PPC_NONE, PPC2_BOOKE206),
5975 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
5976 PPC_NONE, PPC2_BOOKE206),
5977 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
5978 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
5979 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
5980 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
5981 PPC_BOOKE, PPC2_BOOKE206),
5982 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
5983 PPC_440_SPEC),
5984 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
5985 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
5986
5987 #if defined(TARGET_PPC64)
5988 #undef GEN_PPC64_R2
5989 #undef GEN_PPC64_R4
5990 #define GEN_PPC64_R2(name, opc1, opc2) \
5991 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
5992 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
5993 PPC_64B)
5994 #define GEN_PPC64_R4(name, opc1, opc2) \
5995 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
5996 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
5997 PPC_64B), \
5998 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
5999 PPC_64B), \
6000 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6001 PPC_64B)
6002 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6003 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6004 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6005 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6006 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6007 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6008 #endif
6009
6010 #undef GEN_LDX_E
6011 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6012 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6013
6014 #if defined(TARGET_PPC64)
6015 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6016
6017 /* HV/P7 and later only */
6018 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6019 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6020 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6021 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6022 #endif
6023 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6024 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6025
6026 /* External PID based load */
6027 #undef GEN_LDEPX
6028 #define GEN_LDEPX(name, ldop, opc2, opc3) \
6029 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
6030 0x00000001, PPC_NONE, PPC2_BOOKE206),
6031
6032 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
6033 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
6034 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
6035 #if defined(TARGET_PPC64)
6036 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
6037 #endif
6038
6039 #undef GEN_STX_E
6040 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6041 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
6042
6043 #if defined(TARGET_PPC64)
6044 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6045 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6046 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6047 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6048 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6049 #endif
6050 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6051 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6052
6053 #undef GEN_STEPX
6054 #define GEN_STEPX(name, ldop, opc2, opc3) \
6055 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
6056 0x00000001, PPC_NONE, PPC2_BOOKE206),
6057
6058 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
6059 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
6060 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
6061 #if defined(TARGET_PPC64)
6062 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04)
6063 #endif
6064
6065 #undef GEN_CRLOGIC
6066 #define GEN_CRLOGIC(name, tcg_op, opc) \
6067 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6068 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6069 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6070 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6071 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6072 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6073 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6074 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6075 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6076
6077 #undef GEN_MAC_HANDLER
6078 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6079 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6080 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6081 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6082 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6083 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6084 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6085 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6086 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6087 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6088 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6089 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6090 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6091 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6092 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6093 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6094 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6095 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6096 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6097 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6098 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6099 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6100 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6101 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6102 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6103 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6104 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6105 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6106 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6107 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6108 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6109 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6110 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6111 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6112 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6113 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6114 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6115 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6116 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6117 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6118 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6119 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6120 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6121 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6122
6123 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6124 PPC_NONE, PPC2_TM),
6125 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6126 PPC_NONE, PPC2_TM),
6127 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6128 PPC_NONE, PPC2_TM),
6129 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6130 PPC_NONE, PPC2_TM),
6131 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6132 PPC_NONE, PPC2_TM),
6133 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6134 PPC_NONE, PPC2_TM),
6135 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6136 PPC_NONE, PPC2_TM),
6137 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6138 PPC_NONE, PPC2_TM),
6139 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6140 PPC_NONE, PPC2_TM),
6141 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6142 PPC_NONE, PPC2_TM),
6143 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6144 PPC_NONE, PPC2_TM),
6145
6146 #include "translate/fp-ops.c.inc"
6147
6148 #include "translate/vmx-ops.c.inc"
6149
6150 #include "translate/vsx-ops.c.inc"
6151
6152 #include "translate/spe-ops.c.inc"
6153 };
6154
6155 /*****************************************************************************/
6156 /* Opcode types */
6157 enum {
6158 PPC_DIRECT = 0, /* Opcode routine */
6159 PPC_INDIRECT = 1, /* Indirect opcode table */
6160 };
6161
6162 #define PPC_OPCODE_MASK 0x3
6163
is_indirect_opcode(void * handler)6164 static inline int is_indirect_opcode(void *handler)
6165 {
6166 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
6167 }
6168
ind_table(void * handler)6169 static inline opc_handler_t **ind_table(void *handler)
6170 {
6171 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
6172 }
6173
6174 /* Instruction table creation */
6175 /* Opcodes tables creation */
fill_new_table(opc_handler_t ** table,int len)6176 static void fill_new_table(opc_handler_t **table, int len)
6177 {
6178 int i;
6179
6180 for (i = 0; i < len; i++) {
6181 table[i] = &invalid_handler;
6182 }
6183 }
6184
create_new_table(opc_handler_t ** table,unsigned char idx)6185 static int create_new_table(opc_handler_t **table, unsigned char idx)
6186 {
6187 opc_handler_t **tmp;
6188
6189 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
6190 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
6191 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
6192
6193 return 0;
6194 }
6195
insert_in_table(opc_handler_t ** table,unsigned char idx,opc_handler_t * handler)6196 static int insert_in_table(opc_handler_t **table, unsigned char idx,
6197 opc_handler_t *handler)
6198 {
6199 if (table[idx] != &invalid_handler) {
6200 return -1;
6201 }
6202 table[idx] = handler;
6203
6204 return 0;
6205 }
6206
register_direct_insn(opc_handler_t ** ppc_opcodes,unsigned char idx,opc_handler_t * handler)6207 static int register_direct_insn(opc_handler_t **ppc_opcodes,
6208 unsigned char idx, opc_handler_t *handler)
6209 {
6210 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
6211 printf("*** ERROR: opcode %02x already assigned in main "
6212 "opcode table\n", idx);
6213 return -1;
6214 }
6215
6216 return 0;
6217 }
6218
register_ind_in_table(opc_handler_t ** table,unsigned char idx1,unsigned char idx2,opc_handler_t * handler)6219 static int register_ind_in_table(opc_handler_t **table,
6220 unsigned char idx1, unsigned char idx2,
6221 opc_handler_t *handler)
6222 {
6223 if (table[idx1] == &invalid_handler) {
6224 if (create_new_table(table, idx1) < 0) {
6225 printf("*** ERROR: unable to create indirect table "
6226 "idx=%02x\n", idx1);
6227 return -1;
6228 }
6229 } else {
6230 if (!is_indirect_opcode(table[idx1])) {
6231 printf("*** ERROR: idx %02x already assigned to a direct "
6232 "opcode\n", idx1);
6233 return -1;
6234 }
6235 }
6236 if (handler != NULL &&
6237 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
6238 printf("*** ERROR: opcode %02x already assigned in "
6239 "opcode table %02x\n", idx2, idx1);
6240 return -1;
6241 }
6242
6243 return 0;
6244 }
6245
register_ind_insn(opc_handler_t ** ppc_opcodes,unsigned char idx1,unsigned char idx2,opc_handler_t * handler)6246 static int register_ind_insn(opc_handler_t **ppc_opcodes,
6247 unsigned char idx1, unsigned char idx2,
6248 opc_handler_t *handler)
6249 {
6250 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
6251 }
6252
register_dblind_insn(opc_handler_t ** ppc_opcodes,unsigned char idx1,unsigned char idx2,unsigned char idx3,opc_handler_t * handler)6253 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
6254 unsigned char idx1, unsigned char idx2,
6255 unsigned char idx3, opc_handler_t *handler)
6256 {
6257 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6258 printf("*** ERROR: unable to join indirect table idx "
6259 "[%02x-%02x]\n", idx1, idx2);
6260 return -1;
6261 }
6262 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
6263 handler) < 0) {
6264 printf("*** ERROR: unable to insert opcode "
6265 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
6266 return -1;
6267 }
6268
6269 return 0;
6270 }
6271
register_trplind_insn(opc_handler_t ** ppc_opcodes,unsigned char idx1,unsigned char idx2,unsigned char idx3,unsigned char idx4,opc_handler_t * handler)6272 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
6273 unsigned char idx1, unsigned char idx2,
6274 unsigned char idx3, unsigned char idx4,
6275 opc_handler_t *handler)
6276 {
6277 opc_handler_t **table;
6278
6279 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6280 printf("*** ERROR: unable to join indirect table idx "
6281 "[%02x-%02x]\n", idx1, idx2);
6282 return -1;
6283 }
6284 table = ind_table(ppc_opcodes[idx1]);
6285 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
6286 printf("*** ERROR: unable to join 2nd-level indirect table idx "
6287 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
6288 return -1;
6289 }
6290 table = ind_table(table[idx2]);
6291 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
6292 printf("*** ERROR: unable to insert opcode "
6293 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
6294 return -1;
6295 }
6296 return 0;
6297 }
register_insn(opc_handler_t ** ppc_opcodes,opcode_t * insn)6298 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
6299 {
6300 if (insn->opc2 != 0xFF) {
6301 if (insn->opc3 != 0xFF) {
6302 if (insn->opc4 != 0xFF) {
6303 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
6304 insn->opc3, insn->opc4,
6305 &insn->handler) < 0) {
6306 return -1;
6307 }
6308 } else {
6309 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
6310 insn->opc3, &insn->handler) < 0) {
6311 return -1;
6312 }
6313 }
6314 } else {
6315 if (register_ind_insn(ppc_opcodes, insn->opc1,
6316 insn->opc2, &insn->handler) < 0) {
6317 return -1;
6318 }
6319 }
6320 } else {
6321 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
6322 return -1;
6323 }
6324 }
6325
6326 return 0;
6327 }
6328
test_opcode_table(opc_handler_t ** table,int len)6329 static int test_opcode_table(opc_handler_t **table, int len)
6330 {
6331 int i, count, tmp;
6332
6333 for (i = 0, count = 0; i < len; i++) {
6334 /* Consistency fixup */
6335 if (table[i] == NULL) {
6336 table[i] = &invalid_handler;
6337 }
6338 if (table[i] != &invalid_handler) {
6339 if (is_indirect_opcode(table[i])) {
6340 tmp = test_opcode_table(ind_table(table[i]),
6341 PPC_CPU_INDIRECT_OPCODES_LEN);
6342 if (tmp == 0) {
6343 g_free(table[i]);
6344 table[i] = &invalid_handler;
6345 } else {
6346 count++;
6347 }
6348 } else {
6349 count++;
6350 }
6351 }
6352 }
6353
6354 return count;
6355 }
6356
fix_opcode_tables(opc_handler_t ** ppc_opcodes)6357 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
6358 {
6359 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
6360 printf("*** WARNING: no opcode defined !\n");
6361 }
6362 }
6363
6364 /*****************************************************************************/
create_ppc_opcodes(PowerPCCPU * cpu,Error ** errp)6365 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
6366 {
6367 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6368 opcode_t *opc;
6369
6370 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
6371 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
6372 if (((opc->handler.type & pcc->insns_flags) != 0) ||
6373 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
6374 if (register_insn(cpu->opcodes, opc) < 0) {
6375 error_setg(errp, "ERROR initializing PowerPC instruction "
6376 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
6377 opc->opc3);
6378 return;
6379 }
6380 }
6381 }
6382 fix_opcode_tables(cpu->opcodes);
6383 fflush(stdout);
6384 fflush(stderr);
6385 }
6386
destroy_ppc_opcodes(PowerPCCPU * cpu)6387 void destroy_ppc_opcodes(PowerPCCPU *cpu)
6388 {
6389 opc_handler_t **table, **table_2;
6390 int i, j, k;
6391
6392 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
6393 if (cpu->opcodes[i] == &invalid_handler) {
6394 continue;
6395 }
6396 if (is_indirect_opcode(cpu->opcodes[i])) {
6397 table = ind_table(cpu->opcodes[i]);
6398 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
6399 if (table[j] == &invalid_handler) {
6400 continue;
6401 }
6402 if (is_indirect_opcode(table[j])) {
6403 table_2 = ind_table(table[j]);
6404 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
6405 if (table_2[k] != &invalid_handler &&
6406 is_indirect_opcode(table_2[k])) {
6407 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
6408 ~PPC_INDIRECT));
6409 }
6410 }
6411 g_free((opc_handler_t *)((uintptr_t)table[j] &
6412 ~PPC_INDIRECT));
6413 }
6414 }
6415 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
6416 ~PPC_INDIRECT));
6417 }
6418 }
6419 }
6420
ppc_fixup_cpu(PowerPCCPU * cpu)6421 int ppc_fixup_cpu(PowerPCCPU *cpu)
6422 {
6423 CPUPPCState *env = &cpu->env;
6424
6425 /*
6426 * TCG doesn't (yet) emulate some groups of instructions that are
6427 * implemented on some otherwise supported CPUs (e.g. VSX and
6428 * decimal floating point instructions on POWER7). We remove
6429 * unsupported instruction groups from the cpu state's instruction
6430 * masks and hope the guest can cope. For at least the pseries
6431 * machine, the unavailability of these instructions can be
6432 * advertised to the guest via the device tree.
6433 */
6434 if ((env->insns_flags & ~PPC_TCG_INSNS)
6435 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
6436 warn_report("Disabling some instructions which are not "
6437 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
6438 env->insns_flags & ~PPC_TCG_INSNS,
6439 env->insns_flags2 & ~PPC_TCG_INSNS2);
6440 }
6441 env->insns_flags &= PPC_TCG_INSNS;
6442 env->insns_flags2 &= PPC_TCG_INSNS2;
6443 return 0;
6444 }
6445
decode_legacy(PowerPCCPU * cpu,DisasContext * ctx,uint32_t insn)6446 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
6447 {
6448 opc_handler_t **table, *handler;
6449 uint32_t inval;
6450
6451 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
6452 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
6453 ctx->le_mode ? "little" : "big");
6454
6455 table = cpu->opcodes;
6456 handler = table[opc1(insn)];
6457 if (is_indirect_opcode(handler)) {
6458 table = ind_table(handler);
6459 handler = table[opc2(insn)];
6460 if (is_indirect_opcode(handler)) {
6461 table = ind_table(handler);
6462 handler = table[opc3(insn)];
6463 if (is_indirect_opcode(handler)) {
6464 table = ind_table(handler);
6465 handler = table[opc4(insn)];
6466 }
6467 }
6468 }
6469
6470 /* Is opcode *REALLY* valid ? */
6471 if (unlikely(handler->handler == &gen_invalid)) {
6472 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
6473 "%02x - %02x - %02x - %02x (%08x) "
6474 TARGET_FMT_lx "\n",
6475 opc1(insn), opc2(insn), opc3(insn), opc4(insn),
6476 insn, ctx->cia);
6477 return false;
6478 }
6479
6480 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
6481 && Rc(insn))) {
6482 inval = handler->inval2;
6483 } else {
6484 inval = handler->inval1;
6485 }
6486
6487 if (unlikely((insn & inval) != 0)) {
6488 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
6489 "%02x - %02x - %02x - %02x (%08x) "
6490 TARGET_FMT_lx "\n", insn & inval,
6491 opc1(insn), opc2(insn), opc3(insn), opc4(insn),
6492 insn, ctx->cia);
6493 return false;
6494 }
6495
6496 handler->handler(ctx);
6497 return true;
6498 }
6499
ppc_tr_init_disas_context(DisasContextBase * dcbase,CPUState * cs)6500 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
6501 {
6502 DisasContext *ctx = container_of(dcbase, DisasContext, base);
6503 CPUPPCState *env = cpu_env(cs);
6504 uint32_t hflags = ctx->base.tb->flags;
6505
6506 ctx->spr_cb = env->spr_cb;
6507 ctx->pr = (hflags >> HFLAGS_PR) & 1;
6508 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
6509 ctx->dr = (hflags >> HFLAGS_DR) & 1;
6510 ctx->hv = (hflags >> HFLAGS_HV) & 1;
6511 ctx->insns_flags = env->insns_flags;
6512 ctx->insns_flags2 = env->insns_flags2;
6513 ctx->access_type = -1;
6514 ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
6515 ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
6516 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
6517 ctx->flags = env->flags;
6518 #if defined(TARGET_PPC64)
6519 ctx->excp_model = env->excp_model;
6520 ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
6521 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6522 ctx->has_bhrb = !!(env->flags & POWERPC_FLAG_BHRB);
6523 #endif
6524 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
6525 || env->mmu_model & POWERPC_MMU_64;
6526
6527 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
6528 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
6529 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
6530 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
6531 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
6532 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
6533 ctx->hr = (hflags >> HFLAGS_HR) & 1;
6534 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
6535 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
6536 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1;
6537 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1;
6538 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
6539 ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1;
6540
6541 ctx->singlestep_enabled = 0;
6542 if ((hflags >> HFLAGS_SE) & 1) {
6543 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
6544 ctx->base.max_insns = 1;
6545 }
6546 if ((hflags >> HFLAGS_BE) & 1) {
6547 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
6548 }
6549 }
6550
ppc_tr_tb_start(DisasContextBase * db,CPUState * cs)6551 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
6552 {
6553 }
6554
ppc_tr_insn_start(DisasContextBase * dcbase,CPUState * cs)6555 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
6556 {
6557 tcg_gen_insn_start(dcbase->pc_next);
6558 }
6559
is_prefix_insn(DisasContext * ctx,uint32_t insn)6560 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
6561 {
6562 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
6563 return opc1(insn) == 1;
6564 }
6565
ppc_tr_translate_insn(DisasContextBase * dcbase,CPUState * cs)6566 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
6567 {
6568 DisasContext *ctx = container_of(dcbase, DisasContext, base);
6569 PowerPCCPU *cpu = POWERPC_CPU(cs);
6570 CPUPPCState *env = cpu_env(cs);
6571 target_ulong pc;
6572 uint32_t insn;
6573 bool ok;
6574
6575 LOG_DISAS("----------------\n");
6576 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
6577 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
6578
6579 ctx->cia = pc = ctx->base.pc_next;
6580 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
6581 ctx->base.pc_next = pc += 4;
6582
6583 if (!is_prefix_insn(ctx, insn)) {
6584 ctx->opcode = insn;
6585 ok = (decode_insn32(ctx, insn) ||
6586 decode_legacy(cpu, ctx, insn));
6587 } else if ((pc & 63) == 0) {
6588 /*
6589 * Power v3.1, section 1.9 Exceptions:
6590 * attempt to execute a prefixed instruction that crosses a
6591 * 64-byte address boundary (system alignment error).
6592 */
6593 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
6594 ok = true;
6595 } else {
6596 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
6597 need_byteswap(ctx));
6598 ctx->base.pc_next = pc += 4;
6599 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
6600 }
6601 if (!ok) {
6602 gen_invalid(ctx);
6603 }
6604
6605 /* End the TB when crossing a page boundary. */
6606 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
6607 ctx->base.is_jmp = DISAS_TOO_MANY;
6608 }
6609 }
6610
ppc_tr_tb_stop(DisasContextBase * dcbase,CPUState * cs)6611 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
6612 {
6613 DisasContext *ctx = container_of(dcbase, DisasContext, base);
6614 DisasJumpType is_jmp = ctx->base.is_jmp;
6615 target_ulong nip = ctx->base.pc_next;
6616
6617 if (is_jmp == DISAS_NORETURN) {
6618 /* We have already exited the TB. */
6619 return;
6620 }
6621
6622 /* Honor single stepping. */
6623 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) {
6624 bool rfi_type = false;
6625
6626 switch (is_jmp) {
6627 case DISAS_TOO_MANY:
6628 case DISAS_EXIT_UPDATE:
6629 case DISAS_CHAIN_UPDATE:
6630 gen_update_nip(ctx, nip);
6631 break;
6632 case DISAS_EXIT:
6633 case DISAS_CHAIN:
6634 /*
6635 * This is a heuristic, to put it kindly. The rfi class of
6636 * instructions are among the few outside branches that change
6637 * NIP without taking an interrupt. Single step trace interrupts
6638 * do not fire on completion of these instructions.
6639 */
6640 rfi_type = true;
6641 break;
6642 default:
6643 g_assert_not_reached();
6644 }
6645
6646 gen_debug_exception(ctx, rfi_type);
6647 return;
6648 }
6649
6650 switch (is_jmp) {
6651 case DISAS_TOO_MANY:
6652 if (use_goto_tb(ctx, nip)) {
6653 pmu_count_insns(ctx);
6654 tcg_gen_goto_tb(0);
6655 gen_update_nip(ctx, nip);
6656 tcg_gen_exit_tb(ctx->base.tb, 0);
6657 break;
6658 }
6659 /* fall through */
6660 case DISAS_CHAIN_UPDATE:
6661 gen_update_nip(ctx, nip);
6662 /* fall through */
6663 case DISAS_CHAIN:
6664 /*
6665 * tcg_gen_lookup_and_goto_ptr will exit the TB if
6666 * CF_NO_GOTO_PTR is set. Count insns now.
6667 */
6668 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
6669 pmu_count_insns(ctx);
6670 }
6671
6672 tcg_gen_lookup_and_goto_ptr();
6673 break;
6674
6675 case DISAS_EXIT_UPDATE:
6676 gen_update_nip(ctx, nip);
6677 /* fall through */
6678 case DISAS_EXIT:
6679 pmu_count_insns(ctx);
6680 tcg_gen_exit_tb(NULL, 0);
6681 break;
6682
6683 default:
6684 g_assert_not_reached();
6685 }
6686 }
6687
6688 static const TranslatorOps ppc_tr_ops = {
6689 .init_disas_context = ppc_tr_init_disas_context,
6690 .tb_start = ppc_tr_tb_start,
6691 .insn_start = ppc_tr_insn_start,
6692 .translate_insn = ppc_tr_translate_insn,
6693 .tb_stop = ppc_tr_tb_stop,
6694 };
6695
ppc_translate_code(CPUState * cs,TranslationBlock * tb,int * max_insns,vaddr pc,void * host_pc)6696 void ppc_translate_code(CPUState *cs, TranslationBlock *tb,
6697 int *max_insns, vaddr pc, void *host_pc)
6698 {
6699 DisasContext ctx;
6700
6701 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base);
6702 }
6703