1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include <linux/log2.h>
7
8 #include "gen8_ppgtt.h"
9 #include "i915_scatterlist.h"
10 #include "i915_trace.h"
11 #include "i915_pvinfo.h"
12 #include "i915_vgpu.h"
13 #include "intel_gt.h"
14 #include "intel_gtt.h"
15
gen8_pde_encode(const dma_addr_t addr,const enum i915_cache_level level)16 static u64 gen8_pde_encode(const dma_addr_t addr,
17 const enum i915_cache_level level)
18 {
19 u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
20
21 if (level != I915_CACHE_NONE)
22 pde |= PPAT_CACHED_PDE;
23 else
24 pde |= PPAT_UNCACHED;
25
26 return pde;
27 }
28
gen8_pte_encode(dma_addr_t addr,enum i915_cache_level level,u32 flags)29 static u64 gen8_pte_encode(dma_addr_t addr,
30 enum i915_cache_level level,
31 u32 flags)
32 {
33 gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
34
35 if (unlikely(flags & PTE_READ_ONLY))
36 pte &= ~_PAGE_RW;
37
38 switch (level) {
39 case I915_CACHE_NONE:
40 pte |= PPAT_UNCACHED;
41 break;
42 case I915_CACHE_WT:
43 pte |= PPAT_DISPLAY_ELLC;
44 break;
45 default:
46 pte |= PPAT_CACHED;
47 break;
48 }
49
50 return pte;
51 }
52
gen8_ppgtt_notify_vgt(struct i915_ppgtt * ppgtt,bool create)53 static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
54 {
55 struct drm_i915_private *i915 = ppgtt->vm.i915;
56 struct intel_uncore *uncore = ppgtt->vm.gt->uncore;
57 enum vgt_g2v_type msg;
58 int i;
59
60 if (create)
61 atomic_inc(px_used(ppgtt->pd)); /* never remove */
62 else
63 atomic_dec(px_used(ppgtt->pd));
64
65 mutex_lock(&i915->vgpu.lock);
66
67 if (i915_vm_is_4lvl(&ppgtt->vm)) {
68 const u64 daddr = px_dma(ppgtt->pd);
69
70 intel_uncore_write(uncore,
71 vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
72 intel_uncore_write(uncore,
73 vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
74
75 msg = create ?
76 VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
77 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY;
78 } else {
79 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
80 const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
81
82 intel_uncore_write(uncore,
83 vgtif_reg(pdp[i].lo),
84 lower_32_bits(daddr));
85 intel_uncore_write(uncore,
86 vgtif_reg(pdp[i].hi),
87 upper_32_bits(daddr));
88 }
89
90 msg = create ?
91 VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
92 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY;
93 }
94
95 /* g2v_notify atomically (via hv trap) consumes the message packet. */
96 intel_uncore_write(uncore, vgtif_reg(g2v_notify), msg);
97
98 mutex_unlock(&i915->vgpu.lock);
99 }
100
101 /* Index shifts into the pagetable are offset by GEN8_PTE_SHIFT [12] */
102 #define GEN8_PAGE_SIZE (SZ_4K) /* page and page-directory sizes are the same */
103 #define GEN8_PTE_SHIFT (ilog2(GEN8_PAGE_SIZE))
104 #define GEN8_PDES (GEN8_PAGE_SIZE / sizeof(u64))
105 #define gen8_pd_shift(lvl) ((lvl) * ilog2(GEN8_PDES))
106 #define gen8_pd_index(i, lvl) i915_pde_index((i), gen8_pd_shift(lvl))
107 #define __gen8_pte_shift(lvl) (GEN8_PTE_SHIFT + gen8_pd_shift(lvl))
108 #define __gen8_pte_index(a, lvl) i915_pde_index((a), __gen8_pte_shift(lvl))
109
110 #define as_pd(x) container_of((x), typeof(struct i915_page_directory), pt)
111
112 static inline unsigned int
gen8_pd_range(u64 start,u64 end,int lvl,unsigned int * idx)113 gen8_pd_range(u64 start, u64 end, int lvl, unsigned int *idx)
114 {
115 const int shift = gen8_pd_shift(lvl);
116 const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
117
118 GEM_BUG_ON(start >= end);
119 end += ~mask >> gen8_pd_shift(1);
120
121 *idx = i915_pde_index(start, shift);
122 if ((start ^ end) & mask)
123 return GEN8_PDES - *idx;
124 else
125 return i915_pde_index(end, shift) - *idx;
126 }
127
gen8_pd_contains(u64 start,u64 end,int lvl)128 static inline bool gen8_pd_contains(u64 start, u64 end, int lvl)
129 {
130 const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
131
132 GEM_BUG_ON(start >= end);
133 return (start ^ end) & mask && (start & ~mask) == 0;
134 }
135
gen8_pt_count(u64 start,u64 end)136 static inline unsigned int gen8_pt_count(u64 start, u64 end)
137 {
138 GEM_BUG_ON(start >= end);
139 if ((start ^ end) >> gen8_pd_shift(1))
140 return GEN8_PDES - (start & (GEN8_PDES - 1));
141 else
142 return end - start;
143 }
144
145 static inline unsigned int
gen8_pd_top_count(const struct i915_address_space * vm)146 gen8_pd_top_count(const struct i915_address_space *vm)
147 {
148 unsigned int shift = __gen8_pte_shift(vm->top);
149 return (vm->total + (1ull << shift) - 1) >> shift;
150 }
151
152 static inline struct i915_page_directory *
gen8_pdp_for_page_index(struct i915_address_space * const vm,const u64 idx)153 gen8_pdp_for_page_index(struct i915_address_space * const vm, const u64 idx)
154 {
155 struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
156
157 if (vm->top == 2)
158 return ppgtt->pd;
159 else
160 return i915_pd_entry(ppgtt->pd, gen8_pd_index(idx, vm->top));
161 }
162
163 static inline struct i915_page_directory *
gen8_pdp_for_page_address(struct i915_address_space * const vm,const u64 addr)164 gen8_pdp_for_page_address(struct i915_address_space * const vm, const u64 addr)
165 {
166 return gen8_pdp_for_page_index(vm, addr >> GEN8_PTE_SHIFT);
167 }
168
__gen8_ppgtt_cleanup(struct i915_address_space * vm,struct i915_page_directory * pd,int count,int lvl)169 static void __gen8_ppgtt_cleanup(struct i915_address_space *vm,
170 struct i915_page_directory *pd,
171 int count, int lvl)
172 {
173 if (lvl) {
174 void **pde = pd->entry;
175
176 do {
177 if (!*pde)
178 continue;
179
180 __gen8_ppgtt_cleanup(vm, *pde, GEN8_PDES, lvl - 1);
181 } while (pde++, --count);
182 }
183
184 free_px(vm, &pd->pt, lvl);
185 }
186
gen8_ppgtt_cleanup(struct i915_address_space * vm)187 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
188 {
189 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
190
191 if (intel_vgpu_active(vm->i915))
192 gen8_ppgtt_notify_vgt(ppgtt, false);
193
194 __gen8_ppgtt_cleanup(vm, ppgtt->pd, gen8_pd_top_count(vm), vm->top);
195 free_scratch(vm);
196 }
197
__gen8_ppgtt_clear(struct i915_address_space * const vm,struct i915_page_directory * const pd,u64 start,const u64 end,int lvl)198 static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,
199 struct i915_page_directory * const pd,
200 u64 start, const u64 end, int lvl)
201 {
202 const struct drm_i915_gem_object * const scratch = vm->scratch[lvl];
203 unsigned int idx, len;
204
205 GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT);
206
207 len = gen8_pd_range(start, end, lvl--, &idx);
208 DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
209 __func__, vm, lvl + 1, start, end,
210 idx, len, atomic_read(px_used(pd)));
211 GEM_BUG_ON(!len || len >= atomic_read(px_used(pd)));
212
213 do {
214 struct i915_page_table *pt = pd->entry[idx];
215
216 if (atomic_fetch_inc(&pt->used) >> gen8_pd_shift(1) &&
217 gen8_pd_contains(start, end, lvl)) {
218 DBG("%s(%p):{ lvl:%d, idx:%d, start:%llx, end:%llx } removing pd\n",
219 __func__, vm, lvl + 1, idx, start, end);
220 clear_pd_entry(pd, idx, scratch);
221 __gen8_ppgtt_cleanup(vm, as_pd(pt), I915_PDES, lvl);
222 start += (u64)I915_PDES << gen8_pd_shift(lvl);
223 continue;
224 }
225
226 if (lvl) {
227 start = __gen8_ppgtt_clear(vm, as_pd(pt),
228 start, end, lvl);
229 } else {
230 unsigned int count;
231 u64 *vaddr;
232
233 count = gen8_pt_count(start, end);
234 DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } removing pte\n",
235 __func__, vm, lvl, start, end,
236 gen8_pd_index(start, 0), count,
237 atomic_read(&pt->used));
238 GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
239
240 vaddr = kmap_atomic_px(pt);
241 memset64(vaddr + gen8_pd_index(start, 0),
242 vm->scratch[0]->encode,
243 count);
244 kunmap_atomic(vaddr);
245
246 atomic_sub(count, &pt->used);
247 start += count;
248 }
249
250 if (release_pd_entry(pd, idx, pt, scratch))
251 free_px(vm, pt, lvl);
252 } while (idx++, --len);
253
254 return start;
255 }
256
gen8_ppgtt_clear(struct i915_address_space * vm,u64 start,u64 length)257 static void gen8_ppgtt_clear(struct i915_address_space *vm,
258 u64 start, u64 length)
259 {
260 GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
261 GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
262 GEM_BUG_ON(range_overflows(start, length, vm->total));
263
264 start >>= GEN8_PTE_SHIFT;
265 length >>= GEN8_PTE_SHIFT;
266 GEM_BUG_ON(length == 0);
267
268 __gen8_ppgtt_clear(vm, i915_vm_to_ppgtt(vm)->pd,
269 start, start + length, vm->top);
270 }
271
__gen8_ppgtt_alloc(struct i915_address_space * const vm,struct i915_vm_pt_stash * stash,struct i915_page_directory * const pd,u64 * const start,const u64 end,int lvl)272 static void __gen8_ppgtt_alloc(struct i915_address_space * const vm,
273 struct i915_vm_pt_stash *stash,
274 struct i915_page_directory * const pd,
275 u64 * const start, const u64 end, int lvl)
276 {
277 unsigned int idx, len;
278
279 GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT);
280
281 len = gen8_pd_range(*start, end, lvl--, &idx);
282 DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
283 __func__, vm, lvl + 1, *start, end,
284 idx, len, atomic_read(px_used(pd)));
285 GEM_BUG_ON(!len || (idx + len - 1) >> gen8_pd_shift(1));
286
287 spin_lock(&pd->lock);
288 GEM_BUG_ON(!atomic_read(px_used(pd))); /* Must be pinned! */
289 do {
290 struct i915_page_table *pt = pd->entry[idx];
291
292 if (!pt) {
293 spin_unlock(&pd->lock);
294
295 DBG("%s(%p):{ lvl:%d, idx:%d } allocating new tree\n",
296 __func__, vm, lvl + 1, idx);
297
298 pt = stash->pt[!!lvl];
299 __i915_gem_object_pin_pages(pt->base);
300 i915_gem_object_make_unshrinkable(pt->base);
301
302 if (lvl ||
303 gen8_pt_count(*start, end) < I915_PDES ||
304 intel_vgpu_active(vm->i915))
305 fill_px(pt, vm->scratch[lvl]->encode);
306
307 spin_lock(&pd->lock);
308 if (likely(!pd->entry[idx])) {
309 stash->pt[!!lvl] = pt->stash;
310 atomic_set(&pt->used, 0);
311 set_pd_entry(pd, idx, pt);
312 } else {
313 pt = pd->entry[idx];
314 }
315 }
316
317 if (lvl) {
318 atomic_inc(&pt->used);
319 spin_unlock(&pd->lock);
320
321 __gen8_ppgtt_alloc(vm, stash,
322 as_pd(pt), start, end, lvl);
323
324 spin_lock(&pd->lock);
325 atomic_dec(&pt->used);
326 GEM_BUG_ON(!atomic_read(&pt->used));
327 } else {
328 unsigned int count = gen8_pt_count(*start, end);
329
330 DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } inserting pte\n",
331 __func__, vm, lvl, *start, end,
332 gen8_pd_index(*start, 0), count,
333 atomic_read(&pt->used));
334
335 atomic_add(count, &pt->used);
336 /* All other pdes may be simultaneously removed */
337 GEM_BUG_ON(atomic_read(&pt->used) > NALLOC * I915_PDES);
338 *start += count;
339 }
340 } while (idx++, --len);
341 spin_unlock(&pd->lock);
342 }
343
gen8_ppgtt_alloc(struct i915_address_space * vm,struct i915_vm_pt_stash * stash,u64 start,u64 length)344 static void gen8_ppgtt_alloc(struct i915_address_space *vm,
345 struct i915_vm_pt_stash *stash,
346 u64 start, u64 length)
347 {
348 GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
349 GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
350 GEM_BUG_ON(range_overflows(start, length, vm->total));
351
352 start >>= GEN8_PTE_SHIFT;
353 length >>= GEN8_PTE_SHIFT;
354 GEM_BUG_ON(length == 0);
355
356 __gen8_ppgtt_alloc(vm, stash, i915_vm_to_ppgtt(vm)->pd,
357 &start, start + length, vm->top);
358 }
359
360 static __always_inline u64
gen8_ppgtt_insert_pte(struct i915_ppgtt * ppgtt,struct i915_page_directory * pdp,struct sgt_dma * iter,u64 idx,enum i915_cache_level cache_level,u32 flags)361 gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
362 struct i915_page_directory *pdp,
363 struct sgt_dma *iter,
364 u64 idx,
365 enum i915_cache_level cache_level,
366 u32 flags)
367 {
368 struct i915_page_directory *pd;
369 const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
370 gen8_pte_t *vaddr;
371
372 pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
373 vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
374 do {
375 GEM_BUG_ON(iter->sg->length < I915_GTT_PAGE_SIZE);
376 vaddr[gen8_pd_index(idx, 0)] = pte_encode | iter->dma;
377
378 iter->dma += I915_GTT_PAGE_SIZE;
379 if (iter->dma >= iter->max) {
380 iter->sg = __sg_next(iter->sg);
381 if (!iter->sg) {
382 idx = 0;
383 break;
384 }
385
386 iter->dma = sg_dma_address(iter->sg);
387 iter->max = iter->dma + iter->sg->length;
388 }
389
390 if (gen8_pd_index(++idx, 0) == 0) {
391 if (gen8_pd_index(idx, 1) == 0) {
392 /* Limited by sg length for 3lvl */
393 if (gen8_pd_index(idx, 2) == 0)
394 break;
395
396 pd = pdp->entry[gen8_pd_index(idx, 2)];
397 }
398
399 clflush_cache_range(vaddr, PAGE_SIZE);
400 kunmap_atomic(vaddr);
401 vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
402 }
403 } while (1);
404 clflush_cache_range(vaddr, PAGE_SIZE);
405 kunmap_atomic(vaddr);
406
407 return idx;
408 }
409
gen8_ppgtt_insert_huge(struct i915_vma * vma,struct sgt_dma * iter,enum i915_cache_level cache_level,u32 flags)410 static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
411 struct sgt_dma *iter,
412 enum i915_cache_level cache_level,
413 u32 flags)
414 {
415 const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
416 u64 start = vma->node.start;
417 dma_addr_t rem = iter->sg->length;
418
419 GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
420
421 do {
422 struct i915_page_directory * const pdp =
423 gen8_pdp_for_page_address(vma->vm, start);
424 struct i915_page_directory * const pd =
425 i915_pd_entry(pdp, __gen8_pte_index(start, 2));
426 gen8_pte_t encode = pte_encode;
427 unsigned int maybe_64K = -1;
428 unsigned int page_size;
429 gen8_pte_t *vaddr;
430 u16 index;
431
432 if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
433 IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
434 rem >= I915_GTT_PAGE_SIZE_2M &&
435 !__gen8_pte_index(start, 0)) {
436 index = __gen8_pte_index(start, 1);
437 encode |= GEN8_PDE_PS_2M;
438 page_size = I915_GTT_PAGE_SIZE_2M;
439
440 vaddr = kmap_atomic_px(pd);
441 } else {
442 struct i915_page_table *pt =
443 i915_pt_entry(pd, __gen8_pte_index(start, 1));
444
445 index = __gen8_pte_index(start, 0);
446 page_size = I915_GTT_PAGE_SIZE;
447
448 if (!index &&
449 vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
450 IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
451 (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
452 rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
453 maybe_64K = __gen8_pte_index(start, 1);
454
455 vaddr = kmap_atomic_px(pt);
456 }
457
458 do {
459 GEM_BUG_ON(iter->sg->length < page_size);
460 vaddr[index++] = encode | iter->dma;
461
462 start += page_size;
463 iter->dma += page_size;
464 rem -= page_size;
465 if (iter->dma >= iter->max) {
466 iter->sg = __sg_next(iter->sg);
467 if (!iter->sg)
468 break;
469
470 rem = iter->sg->length;
471 iter->dma = sg_dma_address(iter->sg);
472 iter->max = iter->dma + rem;
473
474 if (maybe_64K != -1 && index < I915_PDES &&
475 !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
476 (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
477 rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE)))
478 maybe_64K = -1;
479
480 if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
481 break;
482 }
483 } while (rem >= page_size && index < I915_PDES);
484
485 clflush_cache_range(vaddr, PAGE_SIZE);
486 kunmap_atomic(vaddr);
487
488 /*
489 * Is it safe to mark the 2M block as 64K? -- Either we have
490 * filled whole page-table with 64K entries, or filled part of
491 * it and have reached the end of the sg table and we have
492 * enough padding.
493 */
494 if (maybe_64K != -1 &&
495 (index == I915_PDES ||
496 (i915_vm_has_scratch_64K(vma->vm) &&
497 !iter->sg && IS_ALIGNED(vma->node.start +
498 vma->node.size,
499 I915_GTT_PAGE_SIZE_2M)))) {
500 vaddr = kmap_atomic_px(pd);
501 vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
502 kunmap_atomic(vaddr);
503 page_size = I915_GTT_PAGE_SIZE_64K;
504
505 /*
506 * We write all 4K page entries, even when using 64K
507 * pages. In order to verify that the HW isn't cheating
508 * by using the 4K PTE instead of the 64K PTE, we want
509 * to remove all the surplus entries. If the HW skipped
510 * the 64K PTE, it will read/write into the scratch page
511 * instead - which we detect as missing results during
512 * selftests.
513 */
514 if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) {
515 u16 i;
516
517 encode = vma->vm->scratch[0]->encode;
518 vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
519
520 for (i = 1; i < index; i += 16)
521 memset64(vaddr + i, encode, 15);
522
523 kunmap_atomic(vaddr);
524 }
525 }
526
527 vma->page_sizes.gtt |= page_size;
528 } while (iter->sg);
529 }
530
gen8_ppgtt_insert(struct i915_address_space * vm,struct i915_vma * vma,enum i915_cache_level cache_level,u32 flags)531 static void gen8_ppgtt_insert(struct i915_address_space *vm,
532 struct i915_vma *vma,
533 enum i915_cache_level cache_level,
534 u32 flags)
535 {
536 struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
537 struct sgt_dma iter = sgt_dma(vma);
538
539 if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
540 gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
541 } else {
542 u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
543
544 do {
545 struct i915_page_directory * const pdp =
546 gen8_pdp_for_page_index(vm, idx);
547
548 idx = gen8_ppgtt_insert_pte(ppgtt, pdp, &iter, idx,
549 cache_level, flags);
550 } while (idx);
551
552 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
553 }
554 }
555
gen8_init_scratch(struct i915_address_space * vm)556 static int gen8_init_scratch(struct i915_address_space *vm)
557 {
558 int ret;
559 int i;
560
561 /*
562 * If everybody agrees to not to write into the scratch page,
563 * we can reuse it for all vm, keeping contexts and processes separate.
564 */
565 if (vm->has_read_only && vm->gt->vm && !i915_is_ggtt(vm->gt->vm)) {
566 struct i915_address_space *clone = vm->gt->vm;
567
568 GEM_BUG_ON(!clone->has_read_only);
569
570 vm->scratch_order = clone->scratch_order;
571 for (i = 0; i <= vm->top; i++)
572 vm->scratch[i] = i915_gem_object_get(clone->scratch[i]);
573
574 return 0;
575 }
576
577 ret = setup_scratch_page(vm);
578 if (ret)
579 return ret;
580
581 vm->scratch[0]->encode =
582 gen8_pte_encode(px_dma(vm->scratch[0]),
583 I915_CACHE_LLC, vm->has_read_only);
584
585 for (i = 1; i <= vm->top; i++) {
586 struct drm_i915_gem_object *obj;
587
588 obj = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
589 if (IS_ERR(obj))
590 goto free_scratch;
591
592 ret = pin_pt_dma(vm, obj);
593 if (ret) {
594 i915_gem_object_put(obj);
595 goto free_scratch;
596 }
597
598 fill_px(obj, vm->scratch[i - 1]->encode);
599 obj->encode = gen8_pde_encode(px_dma(obj), I915_CACHE_LLC);
600
601 vm->scratch[i] = obj;
602 }
603
604 return 0;
605
606 free_scratch:
607 while (i--)
608 i915_gem_object_put(vm->scratch[i]);
609 return -ENOMEM;
610 }
611
gen8_preallocate_top_level_pdp(struct i915_ppgtt * ppgtt)612 static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
613 {
614 struct i915_address_space *vm = &ppgtt->vm;
615 struct i915_page_directory *pd = ppgtt->pd;
616 unsigned int idx;
617
618 GEM_BUG_ON(vm->top != 2);
619 GEM_BUG_ON(gen8_pd_top_count(vm) != GEN8_3LVL_PDPES);
620
621 for (idx = 0; idx < GEN8_3LVL_PDPES; idx++) {
622 struct i915_page_directory *pde;
623 int err;
624
625 pde = alloc_pd(vm);
626 if (IS_ERR(pde))
627 return PTR_ERR(pde);
628
629 err = pin_pt_dma(vm, pde->pt.base);
630 if (err) {
631 i915_gem_object_put(pde->pt.base);
632 free_pd(vm, pde);
633 return err;
634 }
635
636 fill_px(pde, vm->scratch[1]->encode);
637 set_pd_entry(pd, idx, pde);
638 atomic_inc(px_used(pde)); /* keep pinned */
639 }
640 wmb();
641
642 return 0;
643 }
644
645 static struct i915_page_directory *
gen8_alloc_top_pd(struct i915_address_space * vm)646 gen8_alloc_top_pd(struct i915_address_space *vm)
647 {
648 const unsigned int count = gen8_pd_top_count(vm);
649 struct i915_page_directory *pd;
650 int err;
651
652 GEM_BUG_ON(count > I915_PDES);
653
654 pd = __alloc_pd(count);
655 if (unlikely(!pd))
656 return ERR_PTR(-ENOMEM);
657
658 pd->pt.base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
659 if (IS_ERR(pd->pt.base)) {
660 err = PTR_ERR(pd->pt.base);
661 pd->pt.base = NULL;
662 goto err_pd;
663 }
664
665 err = pin_pt_dma(vm, pd->pt.base);
666 if (err)
667 goto err_pd;
668
669 fill_page_dma(px_base(pd), vm->scratch[vm->top]->encode, count);
670 atomic_inc(px_used(pd)); /* mark as pinned */
671 return pd;
672
673 err_pd:
674 free_pd(vm, pd);
675 return ERR_PTR(err);
676 }
677
678 /*
679 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
680 * with a net effect resembling a 2-level page table in normal x86 terms. Each
681 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
682 * space.
683 *
684 */
gen8_ppgtt_create(struct intel_gt * gt)685 struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
686 {
687 struct i915_ppgtt *ppgtt;
688 int err;
689
690 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
691 if (!ppgtt)
692 return ERR_PTR(-ENOMEM);
693
694 ppgtt_init(ppgtt, gt);
695 ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
696 ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
697
698 /*
699 * From bdw, there is hw support for read-only pages in the PPGTT.
700 *
701 * Gen11 has HSDES#:1807136187 unresolved. Disable ro support
702 * for now.
703 *
704 * Gen12 has inherited the same read-only fault issue from gen11.
705 */
706 ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
707
708 ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
709
710 err = gen8_init_scratch(&ppgtt->vm);
711 if (err)
712 goto err_free;
713
714 ppgtt->pd = gen8_alloc_top_pd(&ppgtt->vm);
715 if (IS_ERR(ppgtt->pd)) {
716 err = PTR_ERR(ppgtt->pd);
717 goto err_free_scratch;
718 }
719
720 if (!i915_vm_is_4lvl(&ppgtt->vm)) {
721 err = gen8_preallocate_top_level_pdp(ppgtt);
722 if (err)
723 goto err_free_pd;
724 }
725
726 ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
727 ppgtt->vm.insert_entries = gen8_ppgtt_insert;
728 ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
729 ppgtt->vm.clear_range = gen8_ppgtt_clear;
730
731 ppgtt->vm.pte_encode = gen8_pte_encode;
732
733 if (intel_vgpu_active(gt->i915))
734 gen8_ppgtt_notify_vgt(ppgtt, true);
735
736 ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
737
738 return ppgtt;
739
740 err_free_pd:
741 __gen8_ppgtt_cleanup(&ppgtt->vm, ppgtt->pd,
742 gen8_pd_top_count(&ppgtt->vm), ppgtt->vm.top);
743 err_free_scratch:
744 free_scratch(&ppgtt->vm);
745 err_free:
746 kfree(ppgtt);
747 return ERR_PTR(err);
748 }
749