1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #ifndef ATH12K_CORE_H
8 #define ATH12K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/firmware.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/panic_notifier.h>
19 #include <linux/average.h>
20 #include <linux/of.h>
21 #if defined(__FreeBSD__)
22 #include <linux/wait.h>
23 #endif
24 #include "qmi.h"
25 #include "htc.h"
26 #include "wmi.h"
27 #include "hal.h"
28 #include "dp.h"
29 #include "ce.h"
30 #include "mac.h"
31 #include "hw.h"
32 #include "hal_rx.h"
33 #include "reg.h"
34 #include "dbring.h"
35 #include "fw.h"
36 #include "acpi.h"
37 #include "wow.h"
38 #include "debugfs_htt_stats.h"
39 #include "coredump.h"
40
41 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
42
43 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
44
45 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
46
47 /* Pending management packets threshold for dropping probe responses */
48 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
49
50 /* SMBIOS type containing Board Data File Name Extension */
51 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8
52
53 /* SMBIOS type structure length (excluding strings-set) */
54 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9
55
56 /* The magic used by QCA spec */
57 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_"
58
59 #define ATH12K_INVALID_HW_MAC_ID 0xFF
60 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ)
61
62 #define ATH12K_MON_TIMER_INTERVAL 10
63 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
64 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
65 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
66 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
67 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
68 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
69
70 #if defined(__FreeBSD__)
71 #ifdef WME_AC_BE
72 #undef WME_AC_BE
73 #endif
74 #ifdef WME_AC_BK
75 #undef WME_AC_BK
76 #endif
77 #ifdef WME_AC_VI
78 #undef WME_AC_VI
79 #endif
80 #ifdef WME_AC_VO
81 #undef WME_AC_VO
82 #endif
83 #ifdef WME_NUM_AC
84 #undef WME_NUM_AC
85 #endif
86 #endif
87
88 #define ATH12K_MAX_DEVICES 3
89 #define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_DEVICES * MAX_RADIOS)
90 #define ATH12K_INVALID_GROUP_ID 0xFF
91 #define ATH12K_INVALID_DEVICE_ID 0xFF
92
93 #define ATH12K_MAX_MLO_PEERS 256
94 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF
95
96 #define ATH12K_INVALID_RSSI_FULL -1
97 #define ATH12K_INVALID_RSSI_EMPTY -128
98
99 enum ath12k_bdf_search {
100 ATH12K_BDF_SEARCH_DEFAULT,
101 ATH12K_BDF_SEARCH_BUS_AND_BOARD,
102 };
103
104 enum wme_ac {
105 WME_AC_BE,
106 WME_AC_BK,
107 WME_AC_VI,
108 WME_AC_VO,
109 WME_NUM_AC
110 };
111
112 #define ATH12K_HT_MCS_MAX 7
113 #define ATH12K_VHT_MCS_MAX 9
114 #define ATH12K_HE_MCS_MAX 11
115 #define ATH12K_EHT_MCS_MAX 15
116
117 enum ath12k_crypt_mode {
118 /* Only use hardware crypto engine */
119 ATH12K_CRYPT_MODE_HW,
120 /* Only use software crypto */
121 ATH12K_CRYPT_MODE_SW,
122 };
123
ath12k_tid_to_ac(u32 tid)124 static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
125 {
126 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
127 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
128 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
129 WME_AC_VO);
130 }
131
ath12k_le32hilo_to_u64(__le32 hi,__le32 lo)132 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo)
133 {
134 u64 hi64 = le32_to_cpu(hi);
135 u64 lo64 = le32_to_cpu(lo);
136
137 return (hi64 << 32) | lo64;
138 }
139
140 enum ath12k_skb_flags {
141 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
142 ATH12K_SKB_CIPHER_SET = BIT(1),
143 ATH12K_SKB_MLO_STA = BIT(2),
144 };
145
146 struct ath12k_skb_cb {
147 dma_addr_t paddr;
148 struct ath12k *ar;
149 struct ieee80211_vif *vif;
150 dma_addr_t paddr_ext_desc;
151 u32 cipher;
152 u8 flags;
153 u8 link_id;
154 };
155
156 struct ath12k_skb_rxcb {
157 dma_addr_t paddr;
158 bool is_first_msdu;
159 bool is_last_msdu;
160 bool is_continuation;
161 bool is_mcbc;
162 bool is_eapol;
163 struct hal_rx_desc *rx_desc;
164 u8 err_rel_src;
165 u8 err_code;
166 u8 hw_link_id;
167 u8 unmapped;
168 u8 is_frag;
169 u8 tid;
170 u16 peer_id;
171 bool is_end_of_ppdu;
172 };
173
174 enum ath12k_hw_rev {
175 ATH12K_HW_QCN9274_HW10,
176 ATH12K_HW_QCN9274_HW20,
177 ATH12K_HW_WCN7850_HW20,
178 ATH12K_HW_IPQ5332_HW10,
179 };
180
181 enum ath12k_firmware_mode {
182 /* the default mode, standard 802.11 functionality */
183 ATH12K_FIRMWARE_MODE_NORMAL,
184
185 /* factory tests etc */
186 ATH12K_FIRMWARE_MODE_FTM,
187 };
188
189 #define ATH12K_IRQ_NUM_MAX 57
190 #define ATH12K_EXT_IRQ_NUM_MAX 16
191 #define ATH12K_MAX_TCL_RING_NUM 3
192
193 struct ath12k_ext_irq_grp {
194 struct ath12k_base *ab;
195 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
196 u32 num_irq;
197 u32 grp_id;
198 u64 timestamp;
199 bool napi_enabled;
200 struct napi_struct napi;
201 struct net_device *napi_ndev;
202 };
203
204 enum ath12k_smbios_cc_type {
205 /* disable country code setting from SMBIOS */
206 ATH12K_SMBIOS_CC_DISABLE = 0,
207
208 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
209 ATH12K_SMBIOS_CC_ISO = 1,
210
211 /* worldwide regdomain */
212 ATH12K_SMBIOS_CC_WW = 2,
213 };
214
215 struct ath12k_smbios_bdf {
216 struct dmi_header hdr;
217 u8 features_disabled;
218
219 /* enum ath12k_smbios_cc_type */
220 u8 country_code_flag;
221
222 /* To set specific country, you need to set country code
223 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United
224 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
225 * 0x53). To set country to INDONESIA, then country code value =
226 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
227 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory
228 * setting.
229 */
230 u16 cc_code;
231
232 u8 bdf_enabled;
233 u8 bdf_ext[];
234 } __packed;
235
236 #define HEHANDLE_CAP_PHYINFO_SIZE 3
237 #define HECAP_PHYINFO_SIZE 9
238 #define HECAP_MACINFO_SIZE 5
239 #define HECAP_TXRX_MCS_NSS_SIZE 2
240 #define HECAP_PPET16_PPET8_MAX_SIZE 25
241
242 #define HE_PPET16_PPET8_SIZE 8
243
244 /* 802.11ax PPE (PPDU packet Extension) threshold */
245 struct he_ppe_threshold {
246 u32 numss_m1;
247 u32 ru_mask;
248 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
249 };
250
251 struct ath12k_he {
252 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
253 u32 hecap_rxmcsnssmap;
254 u32 hecap_txmcsnssmap;
255 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
256 struct he_ppe_threshold hecap_ppet;
257 u32 heop_param;
258 };
259
260 enum {
261 WMI_HOST_TP_SCALE_MAX = 0,
262 WMI_HOST_TP_SCALE_50 = 1,
263 WMI_HOST_TP_SCALE_25 = 2,
264 WMI_HOST_TP_SCALE_12 = 3,
265 WMI_HOST_TP_SCALE_MIN = 4,
266 WMI_HOST_TP_SCALE_SIZE = 5,
267 };
268
269 enum ath12k_scan_state {
270 ATH12K_SCAN_IDLE,
271 ATH12K_SCAN_STARTING,
272 ATH12K_SCAN_RUNNING,
273 ATH12K_SCAN_ABORTING,
274 };
275
276 enum ath12k_11d_state {
277 ATH12K_11D_IDLE,
278 ATH12K_11D_PREPARING,
279 ATH12K_11D_RUNNING,
280 };
281
282 enum ath12k_hw_group_flags {
283 ATH12K_GROUP_FLAG_REGISTERED,
284 ATH12K_GROUP_FLAG_UNREGISTER,
285 };
286
287 enum ath12k_dev_flags {
288 ATH12K_FLAG_CAC_RUNNING,
289 ATH12K_FLAG_CRASH_FLUSH,
290 ATH12K_FLAG_RAW_MODE,
291 ATH12K_FLAG_HW_CRYPTO_DISABLED,
292 ATH12K_FLAG_RECOVERY,
293 ATH12K_FLAG_UNREGISTERING,
294 ATH12K_FLAG_REGISTERED,
295 ATH12K_FLAG_QMI_FAIL,
296 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
297 ATH12K_FLAG_CE_IRQ_ENABLED,
298 ATH12K_FLAG_EXT_IRQ_ENABLED,
299 ATH12K_FLAG_QMI_FW_READY_COMPLETE,
300 ATH12K_FLAG_FTM_SEGMENTED,
301 ATH12K_FLAG_FIXED_MEM_REGION,
302 };
303
304 struct ath12k_tx_conf {
305 bool changed;
306 u16 ac;
307 struct ieee80211_tx_queue_params tx_queue_params;
308 };
309
310 struct ath12k_key_conf {
311 enum set_key_cmd cmd;
312 struct list_head list;
313 struct ieee80211_sta *sta;
314 struct ieee80211_key_conf *key;
315 };
316
317 struct ath12k_vif_cache {
318 struct ath12k_tx_conf tx_conf;
319 struct ath12k_key_conf key_conf;
320 u32 bss_conf_changed;
321 };
322
323 struct ath12k_rekey_data {
324 u8 kck[NL80211_KCK_LEN];
325 u8 kek[NL80211_KCK_LEN];
326 u64 replay_ctr;
327 bool enable_offload;
328 };
329
330 struct ath12k_link_vif {
331 u32 vdev_id;
332 u32 beacon_interval;
333 u32 dtim_period;
334 u16 ast_hash;
335 u16 ast_idx;
336 u16 tcl_metadata;
337 u8 hal_addr_search_flags;
338 u8 search_type;
339
340 struct ath12k *ar;
341
342 int bank_id;
343 u8 vdev_id_check_en;
344 bool beacon_prot;
345
346 struct wmi_wmm_params_all_arg wmm_params;
347 struct list_head list;
348
349 bool is_created;
350 bool is_started;
351 bool is_up;
352 u8 bssid[ETH_ALEN];
353 struct cfg80211_bitrate_mask bitrate_mask;
354 struct delayed_work connection_loss_work;
355 int num_legacy_stations;
356 int rtscts_prot_mode;
357 int txpower;
358 bool rsnie_present;
359 bool wpaie_present;
360 u8 vdev_stats_id;
361 u32 punct_bitmap;
362 u8 link_id;
363 struct ath12k_vif *ahvif;
364 struct ath12k_rekey_data rekey_data;
365 struct ath12k_link_stats link_stats;
366 spinlock_t link_stats_lock; /* Protects updates to link_stats */
367
368 u8 current_cntdown_counter;
369
370 /* only used in station mode */
371 bool is_sta_assoc_link;
372
373 struct ath12k_reg_tpc_power_info reg_tpc_info;
374
375 bool group_key_valid;
376 struct wmi_vdev_install_key_arg group_key;
377 bool pairwise_key_done;
378 u16 num_stations;
379 bool is_csa_in_progress;
380 struct wiphy_work bcn_tx_work;
381 };
382
383 struct ath12k_vif {
384 enum wmi_vdev_type vdev_type;
385 enum wmi_vdev_subtype vdev_subtype;
386 struct ieee80211_vif *vif;
387 struct ath12k_hw *ah;
388
389 union {
390 struct {
391 u32 uapsd;
392 } sta;
393 struct {
394 /* 127 stations; wmi limit */
395 u8 tim_bitmap[16];
396 u8 tim_len;
397 u32 ssid_len;
398 u8 ssid[IEEE80211_MAX_SSID_LEN];
399 bool hidden_ssid;
400 /* P2P_IE with NoA attribute for P2P_GO case */
401 u32 noa_len;
402 u8 *noa_data;
403 } ap;
404 } u;
405
406 u32 aid;
407 u32 key_cipher;
408 u8 tx_encap_type;
409 bool ps;
410 atomic_t mcbc_gsn;
411
412 struct ath12k_link_vif deflink;
413 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS];
414 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS];
415 /* indicates bitmap of link vif created in FW */
416 u32 links_map;
417 /* Must be last - ends in a flexible-array member.
418 *
419 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
420 * especially because it has a flexible array. Find a better way.
421 */
422 struct ieee80211_chanctx_conf chanctx;
423 };
424
425 struct ath12k_vif_iter {
426 u32 vdev_id;
427 struct ath12k *ar;
428 struct ath12k_link_vif *arvif;
429 };
430
431 #define HAL_AST_IDX_INVALID 0xFFFF
432 #define HAL_RX_MAX_MCS 12
433 #define HAL_RX_MAX_MCS_HT 31
434 #define HAL_RX_MAX_MCS_VHT 9
435 #define HAL_RX_MAX_MCS_HE 11
436 #define HAL_RX_MAX_MCS_BE 15
437 #define HAL_RX_MAX_NSS 8
438 #define HAL_RX_MAX_NUM_LEGACY_RATES 12
439
440 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ)
441
442 struct ath12k_rx_peer_rate_stats {
443 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
444 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
445 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
446 u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1];
447 u64 nss_count[HAL_RX_MAX_NSS];
448 u64 bw_count[HAL_RX_BW_MAX];
449 u64 gi_count[HAL_RX_GI_MAX];
450 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
451 u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1];
452 };
453
454 struct ath12k_rx_peer_stats {
455 u64 num_msdu;
456 u64 num_mpdu_fcs_ok;
457 u64 num_mpdu_fcs_err;
458 u64 tcp_msdu_count;
459 u64 udp_msdu_count;
460 u64 other_msdu_count;
461 u64 ampdu_msdu_count;
462 u64 non_ampdu_msdu_count;
463 u64 stbc_count;
464 u64 beamformed_count;
465 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
466 u64 tid_count[IEEE80211_NUM_TIDS + 1];
467 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
468 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
469 u64 rx_duration;
470 u64 dcm_count;
471 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
472 struct ath12k_rx_peer_rate_stats pkt_stats;
473 struct ath12k_rx_peer_rate_stats byte_stats;
474 };
475
476 #define ATH12K_HE_MCS_NUM 12
477 #define ATH12K_VHT_MCS_NUM 10
478 #define ATH12K_BW_NUM 5
479 #define ATH12K_NSS_NUM 4
480 #define ATH12K_LEGACY_NUM 12
481 #define ATH12K_GI_NUM 4
482 #define ATH12K_HT_MCS_NUM 32
483
484 enum ath12k_pkt_rx_err {
485 ATH12K_PKT_RX_ERR_FCS,
486 ATH12K_PKT_RX_ERR_TKIP,
487 ATH12K_PKT_RX_ERR_CRYPT,
488 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
489 ATH12K_PKT_RX_ERR_MAX,
490 };
491
492 enum ath12k_ampdu_subfrm_num {
493 ATH12K_AMPDU_SUBFRM_NUM_10,
494 ATH12K_AMPDU_SUBFRM_NUM_20,
495 ATH12K_AMPDU_SUBFRM_NUM_30,
496 ATH12K_AMPDU_SUBFRM_NUM_40,
497 ATH12K_AMPDU_SUBFRM_NUM_50,
498 ATH12K_AMPDU_SUBFRM_NUM_60,
499 ATH12K_AMPDU_SUBFRM_NUM_MORE,
500 ATH12K_AMPDU_SUBFRM_NUM_MAX,
501 };
502
503 enum ath12k_amsdu_subfrm_num {
504 ATH12K_AMSDU_SUBFRM_NUM_1,
505 ATH12K_AMSDU_SUBFRM_NUM_2,
506 ATH12K_AMSDU_SUBFRM_NUM_3,
507 ATH12K_AMSDU_SUBFRM_NUM_4,
508 ATH12K_AMSDU_SUBFRM_NUM_MORE,
509 ATH12K_AMSDU_SUBFRM_NUM_MAX,
510 };
511
512 enum ath12k_counter_type {
513 ATH12K_COUNTER_TYPE_BYTES,
514 ATH12K_COUNTER_TYPE_PKTS,
515 ATH12K_COUNTER_TYPE_MAX,
516 };
517
518 enum ath12k_stats_type {
519 ATH12K_STATS_TYPE_SUCC,
520 ATH12K_STATS_TYPE_FAIL,
521 ATH12K_STATS_TYPE_RETRY,
522 ATH12K_STATS_TYPE_AMPDU,
523 ATH12K_STATS_TYPE_MAX,
524 };
525
526 struct ath12k_htt_data_stats {
527 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
528 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
529 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
530 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
531 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
532 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
533 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
534 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
535 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
536 };
537
538 struct ath12k_htt_tx_stats {
539 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
540 u64 tx_duration;
541 u64 ba_fails;
542 u64 ack_fails;
543 u16 ru_start;
544 u16 ru_tones;
545 u32 mu_group[MAX_MU_GROUP_ID];
546 };
547
548 struct ath12k_per_ppdu_tx_stats {
549 u16 succ_pkts;
550 u16 failed_pkts;
551 u16 retry_pkts;
552 u32 succ_bytes;
553 u32 failed_bytes;
554 u32 retry_bytes;
555 };
556
557 struct ath12k_wbm_tx_stats {
558 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
559 };
560
561 DECLARE_EWMA(avg_rssi, 10, 8)
562
563 struct ath12k_link_sta {
564 struct ath12k_link_vif *arvif;
565 struct ath12k_sta *ahsta;
566
567 /* link address similar to ieee80211_link_sta */
568 u8 addr[ETH_ALEN];
569
570 /* the following are protected by ar->data_lock */
571 u32 changed; /* IEEE80211_RC_* */
572 u32 bw;
573 u32 nss;
574 u32 smps;
575
576 struct wiphy_work update_wk;
577 struct rate_info txrate;
578 struct rate_info last_txrate;
579 u64 rx_duration;
580 u64 tx_duration;
581 u8 rssi_comb;
582 struct ewma_avg_rssi avg_rssi;
583 u8 link_id;
584 struct ath12k_rx_peer_stats *rx_stats;
585 struct ath12k_wbm_tx_stats *wbm_tx_stats;
586 u32 bw_prev;
587 u32 peer_nss;
588 s8 rssi_beacon;
589 s8 chain_signal[IEEE80211_MAX_CHAINS];
590
591 /* For now the assoc link will be considered primary */
592 bool is_assoc_link;
593
594 /* for firmware use only */
595 u8 link_idx;
596 u32 tx_retry_failed;
597 u32 tx_retry_count;
598 };
599
600 struct ath12k_reoq_buf {
601 void *vaddr;
602 dma_addr_t paddr_aligned;
603 u32 size;
604 };
605
606 struct ath12k_sta {
607 struct ath12k_vif *ahvif;
608 enum hal_pn_type pn_type;
609 struct ath12k_link_sta deflink;
610 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
611 /* indicates bitmap of link sta created in FW */
612 u16 links_map;
613 u8 assoc_link_id;
614 u16 ml_peer_id;
615 u8 num_peer;
616
617 enum ieee80211_sta_state state;
618
619 struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1];
620 };
621
622 #define ATH12K_HALF_20MHZ_BW 10
623 #define ATH12K_2GHZ_MIN_CENTER 2412
624 #define ATH12K_2GHZ_MAX_CENTER 2484
625 #define ATH12K_5GHZ_MIN_CENTER 4900
626 #define ATH12K_5GHZ_MAX_CENTER 5920
627 #define ATH12K_6GHZ_MIN_CENTER 5935
628 #define ATH12K_6GHZ_MAX_CENTER 7115
629 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1)
630 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1)
631 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
632 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
633 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
634 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
635 #define ATH12K_NUM_CHANS 101
636 #define ATH12K_MAX_5GHZ_CHAN 173
637
ath12k_is_2ghz_channel_freq(u32 freq)638 static inline bool ath12k_is_2ghz_channel_freq(u32 freq)
639 {
640 return freq >= ATH12K_MIN_2GHZ_FREQ &&
641 freq <= ATH12K_MAX_2GHZ_FREQ;
642 }
643
644 enum ath12k_hw_state {
645 ATH12K_HW_STATE_OFF,
646 ATH12K_HW_STATE_ON,
647 ATH12K_HW_STATE_RESTARTING,
648 ATH12K_HW_STATE_RESTARTED,
649 ATH12K_HW_STATE_WEDGED,
650 ATH12K_HW_STATE_TM,
651 /* Add other states as required */
652 };
653
654 /* Antenna noise floor */
655 #define ATH12K_DEFAULT_NOISE_FLOOR -95
656
657 struct ath12k_ftm_event_obj {
658 u32 data_pos;
659 u32 expected_seq;
660 u8 *eventdata;
661 };
662
663 struct ath12k_fw_stats {
664 u32 pdev_id;
665 u32 stats_id;
666 struct list_head pdevs;
667 struct list_head vdevs;
668 struct list_head bcn;
669 u32 num_vdev_recvd;
670 };
671
672 struct ath12k_dbg_htt_stats {
673 enum ath12k_dbg_htt_ext_stats_type type;
674 u32 cfg_param[4];
675 u8 reset;
676 struct debug_htt_stats_req *stats_req;
677 };
678
679 struct ath12k_debug {
680 struct dentry *debugfs_pdev;
681 struct dentry *debugfs_pdev_symlink;
682 struct ath12k_dbg_htt_stats htt_stats;
683 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type;
684 bool tpc_request;
685 struct completion tpc_complete;
686 struct wmi_tpc_stats_arg *tpc_stats;
687 u32 rx_filter;
688 bool extd_rx_stats;
689 };
690
691 struct ath12k_per_peer_tx_stats {
692 u32 succ_bytes;
693 u32 retry_bytes;
694 u32 failed_bytes;
695 u32 duration;
696 u16 succ_pkts;
697 u16 retry_pkts;
698 u16 failed_pkts;
699 u16 ru_start;
700 u16 ru_tones;
701 u8 ba_fails;
702 u8 ppdu_type;
703 u32 mu_grpid;
704 u32 mu_pos;
705 bool is_ampdu;
706 };
707
708 struct ath12k_pdev_rssi_offsets {
709 s32 temp_offset;
710 s8 min_nf_dbm;
711 /* Cache the sum here to avoid calculating it every time in hot path
712 * noise_floor = min_nf_dbm + temp_offset
713 */
714 s32 noise_floor;
715 };
716
717 #define ATH12K_FLUSH_TIMEOUT (5 * HZ)
718 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
719
720 struct ath12k {
721 struct ath12k_base *ab;
722 struct ath12k_pdev *pdev;
723 struct ath12k_hw *ah;
724 struct ath12k_wmi_pdev *wmi;
725 struct ath12k_pdev_dp dp;
726 u8 mac_addr[ETH_ALEN];
727 u32 ht_cap_info;
728 u32 vht_cap_info;
729 struct ath12k_he ar_he;
730 bool supports_6ghz;
731 struct {
732 struct completion started;
733 struct completion completed;
734 struct completion on_channel;
735 struct delayed_work timeout;
736 enum ath12k_scan_state state;
737 bool is_roc;
738 int roc_freq;
739 bool roc_notify;
740 struct wiphy_work vdev_clean_wk;
741 struct ath12k_link_vif *arvif;
742 } scan;
743
744 struct {
745 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
746 struct ieee80211_sband_iftype_data
747 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
748 } mac;
749
750 unsigned long dev_flags;
751 unsigned int filter_flags;
752 u32 min_tx_power;
753 u32 max_tx_power;
754 u32 txpower_limit_2g;
755 u32 txpower_limit_5g;
756 u32 txpower_scale;
757 u32 power_scale;
758 u32 chan_tx_pwr;
759 u32 rts_threshold;
760 u32 num_stations;
761 u32 max_num_stations;
762
763 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
764 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info,
765 * channel context data, survey info, test mode data, regd_channel_update_queue.
766 */
767 spinlock_t data_lock;
768
769 struct list_head arvifs;
770 /* should never be NULL; needed for regular htt rx */
771 struct ieee80211_channel *rx_channel;
772
773 /* valid during scan; needed for mgmt rx during scan */
774 struct ieee80211_channel *scan_channel;
775
776 u8 cfg_tx_chainmask;
777 u8 cfg_rx_chainmask;
778 u8 num_rx_chains;
779 u8 num_tx_chains;
780 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
781 u8 pdev_idx;
782 u8 lmac_id;
783 u8 hw_link_id;
784
785 struct completion peer_assoc_done;
786 struct completion peer_delete_done;
787
788 int install_key_status;
789 struct completion install_key_done;
790
791 int last_wmi_vdev_start_status;
792 struct completion vdev_setup_done;
793 struct completion vdev_delete_done;
794
795 int num_peers;
796 int max_num_peers;
797 u32 num_started_vdevs;
798 u32 num_created_vdevs;
799 unsigned long long allocated_vdev_map;
800
801 struct idr txmgmt_idr;
802 /* protects txmgmt_idr data */
803 spinlock_t txmgmt_idr_lock;
804 atomic_t num_pending_mgmt_tx;
805 wait_queue_head_t txmgmt_empty_waitq;
806
807 /* cycle count is reported twice for each visited channel during scan.
808 * access protected by data_lock
809 */
810 u32 survey_last_rx_clear_count;
811 u32 survey_last_cycle_count;
812
813 /* Channel info events are expected to come in pairs without and with
814 * COMPLETE flag set respectively for each channel visit during scan.
815 *
816 * However there are deviations from this rule. This flag is used to
817 * avoid reporting garbage data.
818 */
819 bool ch_info_can_report_survey;
820 struct survey_info survey[ATH12K_NUM_CHANS];
821 struct completion bss_survey_done;
822
823 struct work_struct regd_update_work;
824 struct work_struct regd_channel_update_work;
825 struct list_head regd_channel_update_queue;
826
827 struct wiphy_work wmi_mgmt_tx_work;
828 struct sk_buff_head wmi_mgmt_tx_queue;
829
830 struct ath12k_wow wow;
831 struct completion target_suspend;
832 bool target_suspend_ack;
833 struct ath12k_per_peer_tx_stats peer_tx_stats;
834 struct list_head ppdu_stats_info;
835 u32 ppdu_stat_list_depth;
836
837 struct ath12k_per_peer_tx_stats cached_stats;
838 u32 last_ppdu_id;
839 u32 cached_ppdu_id;
840 #ifdef CONFIG_ATH12K_DEBUGFS
841 struct ath12k_debug debug;
842 #endif
843
844 bool dfs_block_radar_events;
845 bool monitor_vdev_created;
846 bool monitor_started;
847 int monitor_vdev_id;
848
849 struct wiphy_radio_freq_range freq_range;
850
851 bool nlo_enabled;
852
853 /* Protected by wiphy::mtx lock. */
854 u32 vdev_id_11d_scan;
855 struct completion completed_11d_scan;
856 enum ath12k_11d_state state_11d;
857 u8 alpha2[REG_ALPHA2_LEN];
858 bool regdom_set_by_user;
859 struct completion regd_update_completed;
860
861 struct completion fw_stats_complete;
862 struct completion fw_stats_done;
863
864 struct completion mlo_setup_done;
865 u32 mlo_setup_status;
866 u8 ftm_msgref;
867 struct ath12k_fw_stats fw_stats;
868 unsigned long last_tx_power_update;
869
870 s8 max_allowed_tx_power;
871 struct ath12k_pdev_rssi_offsets rssi_info;
872 };
873
874 struct ath12k_hw {
875 struct ieee80211_hw *hw;
876 struct device *dev;
877
878 /* Protect the write operation of the hardware state ath12k_hw::state
879 * between hardware start<=>reconfigure<=>stop transitions.
880 */
881 struct mutex hw_mutex;
882 enum ath12k_hw_state state;
883 bool regd_updated;
884 bool use_6ghz_regd;
885
886 u8 num_radio;
887
888 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS);
889
890 /* protected by wiphy_lock() */
891 struct list_head ml_peers;
892
893 /* Keep last */
894 struct ath12k radio[] __aligned(sizeof(void *));
895 };
896
897 struct ath12k_band_cap {
898 u32 phy_id;
899 u32 max_bw_supported;
900 u32 ht_cap_info;
901 u32 he_cap_info[2];
902 u32 he_mcs;
903 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
904 struct ath12k_wmi_ppe_threshold_arg he_ppet;
905 u16 he_6ghz_capa;
906 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
907 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
908 u32 eht_mcs_20_only;
909 u32 eht_mcs_80;
910 u32 eht_mcs_160;
911 u32 eht_mcs_320;
912 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
913 u32 eht_cap_info_internal;
914 };
915
916 struct ath12k_pdev_cap {
917 u32 supported_bands;
918 u32 ampdu_density;
919 u32 vht_cap;
920 u32 vht_mcs;
921 u32 he_mcs;
922 u32 tx_chain_mask;
923 u32 rx_chain_mask;
924 u32 tx_chain_mask_shift;
925 u32 rx_chain_mask_shift;
926 struct ath12k_band_cap band[NUM_NL80211_BANDS];
927 u32 eml_cap;
928 u32 mld_cap;
929 bool nss_ratio_enabled;
930 u8 nss_ratio_info;
931 };
932
933 struct mlo_timestamp {
934 u32 info;
935 u32 sync_timestamp_lo_us;
936 u32 sync_timestamp_hi_us;
937 u32 mlo_offset_lo;
938 u32 mlo_offset_hi;
939 u32 mlo_offset_clks;
940 u32 mlo_comp_clks;
941 u32 mlo_comp_timer;
942 };
943
944 struct ath12k_pdev {
945 struct ath12k *ar;
946 u32 pdev_id;
947 u32 hw_link_id;
948 struct ath12k_pdev_cap cap;
949 u8 mac_addr[ETH_ALEN];
950 struct mlo_timestamp timestamp;
951 };
952
953 struct ath12k_fw_pdev {
954 u32 pdev_id;
955 u32 phy_id;
956 u32 supported_bands;
957 };
958
959 struct ath12k_board_data {
960 const struct firmware *fw;
961 const void *data;
962 size_t len;
963 };
964
965 struct ath12k_device_dp_tx_err_stats {
966 /* TCL Ring Descriptor unavailable */
967 u32 desc_na[DP_TCL_NUM_RING_MAX];
968 /* Other failures during dp_tx due to mem allocation failure
969 * idr unavailable etc.
970 */
971 atomic_t misc_fail;
972 };
973
974 struct ath12k_device_dp_stats {
975 u32 err_ring_pkts;
976 u32 invalid_rbm;
977 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
978 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
979 u32 hal_reo_error[DP_REO_DST_RING_MAX];
980 struct ath12k_device_dp_tx_err_stats tx_err;
981 u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES];
982 u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES];
983 u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON];
984 u32 fw_tx_status[MAX_FW_TX_STATUS];
985 u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX];
986 u32 tx_enqueued[DP_TCL_NUM_RING_MAX];
987 u32 tx_completed[DP_TCL_NUM_RING_MAX];
988 u32 reo_excep_msdu_buf_type;
989 };
990
991 struct ath12k_reg_freq {
992 u32 start_freq;
993 u32 end_freq;
994 };
995
996 struct ath12k_mlo_memory {
997 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
998 int mlo_mem_size;
999 bool init_done;
1000 };
1001
1002 struct ath12k_hw_link {
1003 u8 device_id;
1004 u8 pdev_idx;
1005 };
1006
1007 /* Holds info on the group of devices that are registered as a single
1008 * wiphy, protected with struct ath12k_hw_group::mutex.
1009 */
1010 struct ath12k_hw_group {
1011 struct list_head list;
1012 u8 id;
1013 u8 num_devices;
1014 u8 num_probed;
1015 u8 num_started;
1016 unsigned long flags;
1017 struct ath12k_base *ab[ATH12K_MAX_DEVICES];
1018
1019 /* protects access to this struct */
1020 struct mutex mutex;
1021
1022 /* Holds information of wiphy (hw) registration.
1023 *
1024 * In Multi/Single Link Operation case, all pdevs are registered as
1025 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is
1026 * registered as separate wiphys.
1027 */
1028 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO];
1029 u8 num_hw;
1030 bool mlo_capable;
1031 struct device_node *wsi_node[ATH12K_MAX_DEVICES];
1032 struct ath12k_mlo_memory mlo_mem;
1033 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO];
1034 bool hw_link_id_init_done;
1035 };
1036
1037 /* Holds WSI info specific to each device, excluding WSI group info */
1038 struct ath12k_wsi_info {
1039 u32 index;
1040 u32 hw_link_id_base;
1041 };
1042
1043 struct ath12k_dp_profile_params {
1044 u32 tx_comp_ring_size;
1045 u32 rxdma_monitor_buf_ring_size;
1046 u32 rxdma_monitor_dst_ring_size;
1047 u32 num_pool_tx_desc;
1048 u32 rx_desc_count;
1049 };
1050
1051 struct ath12k_mem_profile_based_param {
1052 u32 num_vdevs;
1053 u32 max_client_single;
1054 u32 max_client_dbs;
1055 u32 max_client_dbs_sbs;
1056 struct ath12k_dp_profile_params dp_params;
1057 };
1058
1059 /* Master structure to hold the hw data which may be used in core module */
1060 struct ath12k_base {
1061 enum ath12k_hw_rev hw_rev;
1062 struct platform_device *pdev;
1063 struct device *dev;
1064 struct ath12k_qmi qmi;
1065 struct ath12k_wmi_base wmi_ab;
1066 struct completion fw_ready;
1067 u8 device_id;
1068 int num_radios;
1069 /* HW channel counters frequency value in hertz common to all MACs */
1070 u32 cc_freq_hz;
1071
1072 struct ath12k_dump_file_data *dump_data;
1073 size_t ath12k_coredump_len;
1074 struct work_struct dump_work;
1075
1076 struct ath12k_htc htc;
1077
1078 struct ath12k_dp dp;
1079
1080 void __iomem *mem;
1081 unsigned long mem_len;
1082
1083 void __iomem *mem_ce;
1084 u32 ce_remap_base_addr;
1085 bool ce_remap;
1086
1087 struct {
1088 enum ath12k_bus bus;
1089 const struct ath12k_hif_ops *ops;
1090 } hif;
1091
1092 struct {
1093 struct completion wakeup_completed;
1094 u32 wmi_conf_rx_decap_mode;
1095 } wow;
1096
1097 struct ath12k_ce ce;
1098 struct timer_list rx_replenish_retry;
1099 struct ath12k_hal hal;
1100 /* To synchronize core_start/core_stop */
1101 struct mutex core_lock;
1102 /* Protects data like peers */
1103 spinlock_t base_lock;
1104
1105 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
1106 *
1107 * Firmware maintains data for all bands but advertises a single
1108 * phy to the host which is stored as a single element in this
1109 * array.
1110 *
1111 * Other devices:
1112 *
1113 * This array will contain as many elements as the number of
1114 * radios.
1115 */
1116 struct ath12k_pdev pdevs[MAX_RADIOS];
1117
1118 /* struct ath12k_hw_params::single_pdev_only devices use this to
1119 * store phy specific data
1120 */
1121 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
1122 u8 fw_pdev_count;
1123
1124 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
1125
1126 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
1127 unsigned long long free_vdev_map;
1128 unsigned long long free_vdev_stats_id_map;
1129 struct list_head peers;
1130 wait_queue_head_t peer_mapping_wq;
1131 u8 mac_addr[ETH_ALEN];
1132 bool wmi_ready;
1133 u32 wlan_init_status;
1134 int irq_num[ATH12K_IRQ_NUM_MAX];
1135 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
1136 struct napi_struct *napi;
1137 struct ath12k_wmi_target_cap_arg target_caps;
1138 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
1139 bool pdevs_macaddr_valid;
1140
1141 const struct ath12k_hw_params *hw_params;
1142
1143 const struct firmware *cal_file;
1144
1145 /* Below regd's are protected by ab->data_lock */
1146 /* This is the regd set for every radio
1147 * by the firmware during initialization
1148 */
1149 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
1150 /* This regd is set during dynamic country setting
1151 * This may or may not be used during the runtime
1152 */
1153 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
1154
1155 struct ath12k_reg_info *reg_info[MAX_RADIOS];
1156
1157 /* Current DFS Regulatory */
1158 enum ath12k_dfs_region dfs_region;
1159 struct ath12k_device_dp_stats device_stats;
1160 #ifdef CONFIG_ATH12K_DEBUGFS
1161 struct dentry *debugfs_soc;
1162 #endif
1163
1164 unsigned long dev_flags;
1165 struct completion driver_recovery;
1166 struct workqueue_struct *workqueue;
1167 struct work_struct restart_work;
1168 struct workqueue_struct *workqueue_aux;
1169 struct work_struct reset_work;
1170 atomic_t reset_count;
1171 atomic_t recovery_count;
1172 bool is_reset;
1173 struct completion reset_complete;
1174 /* continuous recovery fail count */
1175 atomic_t fail_cont_count;
1176 unsigned long reset_fail_timeout;
1177 struct work_struct update_11d_work;
1178 u8 new_alpha2[2];
1179 struct {
1180 /* protected by data_lock */
1181 u32 fw_crash_counter;
1182 } stats;
1183 u32 pktlog_defs_checksum;
1184
1185 struct ath12k_dbring_cap *db_caps;
1186 u32 num_db_cap;
1187
1188 struct completion htc_suspend;
1189
1190 u64 fw_soc_drop_count;
1191 bool static_window_map;
1192
1193 struct work_struct rfkill_work;
1194 /* true means radio is on */
1195 bool rfkill_radio_on;
1196
1197 struct {
1198 enum ath12k_bdf_search bdf_search;
1199 u32 vendor;
1200 u32 device;
1201 u32 subsystem_vendor;
1202 u32 subsystem_device;
1203 } id;
1204
1205 struct {
1206 u32 api_version;
1207
1208 const struct firmware *fw;
1209 const u8 *amss_data;
1210 size_t amss_len;
1211 const u8 *amss_dualmac_data;
1212 size_t amss_dualmac_len;
1213 const u8 *m3_data;
1214 size_t m3_len;
1215
1216 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT);
1217 bool fw_features_valid;
1218 } fw;
1219
1220 const struct hal_rx_ops *hal_rx_ops;
1221
1222 struct completion restart_completed;
1223
1224 #ifdef CONFIG_ACPI
1225
1226 struct {
1227 bool started;
1228 u32 func_bit;
1229 bool acpi_tas_enable;
1230 bool acpi_bios_sar_enable;
1231 bool acpi_disable_11be;
1232 bool acpi_disable_rfkill;
1233 bool acpi_cca_enable;
1234 bool acpi_band_edge_enable;
1235 bool acpi_enable_bdf;
1236 u32 bit_flag;
1237 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN];
1238 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE];
1239 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE];
1240 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE];
1241 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE];
1242 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE];
1243 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE];
1244 } acpi;
1245
1246 #endif /* CONFIG_ACPI */
1247
1248 struct notifier_block panic_nb;
1249
1250 struct ath12k_hw_group *ag;
1251 struct ath12k_wsi_info wsi_info;
1252 enum ath12k_firmware_mode fw_mode;
1253 struct ath12k_ftm_event_obj ftm_event_obj;
1254 bool hw_group_ref;
1255
1256 /* Denote whether MLO is possible within the device */
1257 bool single_chip_mlo_support;
1258
1259 struct ath12k_reg_freq reg_freq_2ghz;
1260 struct ath12k_reg_freq reg_freq_5ghz;
1261 struct ath12k_reg_freq reg_freq_6ghz;
1262 const struct ath12k_mem_profile_based_param *profile_param;
1263 enum ath12k_qmi_mem_mode target_mem_mode;
1264
1265 /* must be last */
1266 u8 drv_priv[] __aligned(sizeof(void *));
1267 };
1268
1269 struct ath12k_pdev_map {
1270 struct ath12k_base *ab;
1271 u8 pdev_idx;
1272 };
1273
1274 struct ath12k_fw_stats_vdev {
1275 struct list_head list;
1276
1277 u32 vdev_id;
1278 u32 beacon_snr;
1279 u32 data_snr;
1280 u32 num_tx_frames[WLAN_MAX_AC];
1281 u32 num_rx_frames;
1282 u32 num_tx_frames_retries[WLAN_MAX_AC];
1283 u32 num_tx_frames_failures[WLAN_MAX_AC];
1284 u32 num_rts_fail;
1285 u32 num_rts_success;
1286 u32 num_rx_err;
1287 u32 num_rx_discard;
1288 u32 num_tx_not_acked;
1289 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1290 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1291 };
1292
1293 struct ath12k_fw_stats_bcn {
1294 struct list_head list;
1295
1296 u32 vdev_id;
1297 u32 tx_bcn_succ_cnt;
1298 u32 tx_bcn_outage_cnt;
1299 };
1300
1301 struct ath12k_fw_stats_pdev {
1302 struct list_head list;
1303
1304 /* PDEV stats */
1305 s32 ch_noise_floor;
1306 u32 tx_frame_count;
1307 u32 rx_frame_count;
1308 u32 rx_clear_count;
1309 u32 cycle_count;
1310 u32 phy_err_count;
1311 u32 chan_tx_power;
1312 u32 ack_rx_bad;
1313 u32 rts_bad;
1314 u32 rts_good;
1315 u32 fcs_bad;
1316 u32 no_beacons;
1317 u32 mib_int_count;
1318
1319 /* PDEV TX stats */
1320 s32 comp_queued;
1321 s32 comp_delivered;
1322 s32 msdu_enqued;
1323 s32 mpdu_enqued;
1324 s32 wmm_drop;
1325 s32 local_enqued;
1326 s32 local_freed;
1327 s32 hw_queued;
1328 s32 hw_reaped;
1329 s32 underrun;
1330 s32 tx_abort;
1331 s32 mpdus_requed;
1332 u32 tx_ko;
1333 u32 data_rc;
1334 u32 self_triggers;
1335 u32 sw_retry_failure;
1336 u32 illgl_rate_phy_err;
1337 u32 pdev_cont_xretry;
1338 u32 pdev_tx_timeout;
1339 u32 pdev_resets;
1340 u32 stateless_tid_alloc_failure;
1341 u32 phy_underrun;
1342 u32 txop_ovf;
1343
1344 /* PDEV RX stats */
1345 s32 mid_ppdu_route_change;
1346 s32 status_rcvd;
1347 s32 r0_frags;
1348 s32 r1_frags;
1349 s32 r2_frags;
1350 s32 r3_frags;
1351 s32 htt_msdus;
1352 s32 htt_mpdus;
1353 s32 loc_msdus;
1354 s32 loc_mpdus;
1355 s32 oversize_amsdu;
1356 s32 phy_errs;
1357 s32 phy_err_drop;
1358 s32 mpdu_errs;
1359 };
1360
1361 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
1362 void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag);
1363 int ath12k_core_pre_init(struct ath12k_base *ab);
1364 int ath12k_core_init(struct ath12k_base *ath12k);
1365 void ath12k_core_deinit(struct ath12k_base *ath12k);
1366 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
1367 enum ath12k_bus bus);
1368 void ath12k_core_free(struct ath12k_base *ath12k);
1369 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
1370 struct ath12k_board_data *bd,
1371 char *filename);
1372 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
1373 struct ath12k_board_data *bd);
1374 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
1375 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd);
1376 int ath12k_core_check_dt(struct ath12k_base *ath12k);
1377 int ath12k_core_check_smbios(struct ath12k_base *ab);
1378 void ath12k_core_halt(struct ath12k *ar);
1379 int ath12k_core_resume_early(struct ath12k_base *ab);
1380 int ath12k_core_resume(struct ath12k_base *ab);
1381 int ath12k_core_suspend(struct ath12k_base *ab);
1382 int ath12k_core_suspend_late(struct ath12k_base *ab);
1383 void ath12k_core_hw_group_unassign(struct ath12k_base *ab);
1384 u8 ath12k_get_num_partner_link(struct ath12k *ar);
1385
1386 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
1387 const char *filename);
1388 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab);
1389 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab);
1390
1391 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag);
1392 void ath12k_fw_stats_init(struct ath12k *ar);
1393 void ath12k_fw_stats_bcn_free(struct list_head *head);
1394 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats);
1395 void ath12k_fw_stats_reset(struct ath12k *ar);
1396 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab,
1397 int index);
1398 enum ath12k_qmi_mem_mode ath12k_core_get_memory_mode(struct ath12k_base *ab);
1399
ath12k_scan_state_str(enum ath12k_scan_state state)1400 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
1401 {
1402 switch (state) {
1403 case ATH12K_SCAN_IDLE:
1404 return "idle";
1405 case ATH12K_SCAN_STARTING:
1406 return "starting";
1407 case ATH12K_SCAN_RUNNING:
1408 return "running";
1409 case ATH12K_SCAN_ABORTING:
1410 return "aborting";
1411 }
1412
1413 return "unknown";
1414 }
1415
ATH12K_SKB_CB(struct sk_buff * skb)1416 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
1417 {
1418 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
1419 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1420 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1421 }
1422
ATH12K_SKB_RXCB(struct sk_buff * skb)1423 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
1424 {
1425 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
1426 return (struct ath12k_skb_rxcb *)skb->cb;
1427 }
1428
ath12k_vif_to_ahvif(struct ieee80211_vif * vif)1429 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif)
1430 {
1431 return (struct ath12k_vif *)vif->drv_priv;
1432 }
1433
ath12k_sta_to_ahsta(struct ieee80211_sta * sta)1434 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta)
1435 {
1436 return (struct ath12k_sta *)sta->drv_priv;
1437 }
1438
ath12k_ahsta_to_sta(struct ath12k_sta * ahsta)1439 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta)
1440 {
1441 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv);
1442 }
1443
ath12k_ahvif_to_vif(struct ath12k_vif * ahvif)1444 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif)
1445 {
1446 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv);
1447 }
1448
ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)1449 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
1450 int mac_id)
1451 {
1452 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
1453 }
1454
ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)1455 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
1456 const char *filename,
1457 void *buf, size_t buf_len)
1458 {
1459 const char *fw_name = NULL;
1460
1461 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name);
1462
1463 if (fw_name && strncmp(filename, "board", 5))
1464 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR,
1465 ab->hw_params->fw.dir, fw_name, filename);
1466 else
1467 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
1468 ab->hw_params->fw.dir, filename);
1469 }
1470
ath12k_bus_str(enum ath12k_bus bus)1471 static inline const char *ath12k_bus_str(enum ath12k_bus bus)
1472 {
1473 switch (bus) {
1474 case ATH12K_BUS_PCI:
1475 return "pci";
1476 case ATH12K_BUS_AHB:
1477 return "ahb";
1478 }
1479
1480 return "unknown";
1481 }
1482
ath12k_hw_to_ah(struct ieee80211_hw * hw)1483 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw)
1484 {
1485 return hw->priv;
1486 }
1487
ath12k_ah_to_ar(struct ath12k_hw * ah,u8 hw_link_id)1488 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id)
1489 {
1490 if (WARN(hw_link_id >= ah->num_radio,
1491 "bad hw link id %d, so switch to default link\n", hw_link_id))
1492 hw_link_id = 0;
1493
1494 return &ah->radio[hw_link_id];
1495 }
1496
ath12k_ar_to_ah(struct ath12k * ar)1497 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar)
1498 {
1499 return ar->ah;
1500 }
1501
ath12k_ar_to_hw(struct ath12k * ar)1502 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar)
1503 {
1504 return ar->ah->hw;
1505 }
1506
1507 #define for_each_ar(ah, ar, index) \
1508 for ((index) = 0; ((index) < (ah)->num_radio && \
1509 ((ar) = &(ah)->radio[(index)])); (index)++)
1510
ath12k_ag_to_ah(struct ath12k_hw_group * ag,int idx)1511 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx)
1512 {
1513 return ag->ah[idx];
1514 }
1515
ath12k_ag_set_ah(struct ath12k_hw_group * ag,int idx,struct ath12k_hw * ah)1516 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx,
1517 struct ath12k_hw *ah)
1518 {
1519 ag->ah[idx] = ah;
1520 }
1521
ath12k_ab_to_ag(struct ath12k_base * ab)1522 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab)
1523 {
1524 return ab->ag;
1525 }
1526
ath12k_ag_to_ab(struct ath12k_hw_group * ag,u8 device_id)1527 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag,
1528 u8 device_id)
1529 {
1530 return ag->ab[device_id];
1531 }
1532
ath12k_pdev_get_noise_floor(struct ath12k * ar)1533 static inline s32 ath12k_pdev_get_noise_floor(struct ath12k *ar)
1534 {
1535 lockdep_assert_held(&ar->data_lock);
1536
1537 return ar->rssi_info.noise_floor;
1538 }
1539
1540 #endif /* _CORE_H_ */
1541