1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale DMA ALSA SoC PCM driver 4 // 5 // Author: Timur Tabi <timur@freescale.com> 6 // 7 // Copyright 2007-2010 Freescale Semiconductor, Inc. 8 // 9 // This driver implements ASoC support for the Elo DMA controller, which is 10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 11 // the PCM driver is what handles the DMA buffer. 12 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/gfp.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/list.h> 24 #include <linux/slab.h> 25 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 31 #include <asm/io.h> 32 33 #include "fsl_dma.h" 34 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 35 36 #define DRV_NAME "fsl_dma" 37 38 /* 39 * The formats that the DMA controller supports, which is anything 40 * that is 8, 16, or 32 bits. 41 */ 42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 43 SNDRV_PCM_FMTBIT_U8 | \ 44 SNDRV_PCM_FMTBIT_S16_LE | \ 45 SNDRV_PCM_FMTBIT_S16_BE | \ 46 SNDRV_PCM_FMTBIT_U16_LE | \ 47 SNDRV_PCM_FMTBIT_U16_BE | \ 48 SNDRV_PCM_FMTBIT_S24_LE | \ 49 SNDRV_PCM_FMTBIT_S24_BE | \ 50 SNDRV_PCM_FMTBIT_U24_LE | \ 51 SNDRV_PCM_FMTBIT_U24_BE | \ 52 SNDRV_PCM_FMTBIT_S32_LE | \ 53 SNDRV_PCM_FMTBIT_S32_BE | \ 54 SNDRV_PCM_FMTBIT_U32_LE | \ 55 SNDRV_PCM_FMTBIT_U32_BE) 56 struct dma_object { 57 struct snd_soc_component_driver dai; 58 dma_addr_t ssi_stx_phys; 59 dma_addr_t ssi_srx_phys; 60 unsigned int ssi_fifo_depth; 61 struct ccsr_dma_channel __iomem *channel; 62 unsigned int irq; 63 bool assigned; 64 }; 65 66 /* 67 * The number of DMA links to use. Two is the bare minimum, but if you 68 * have really small links you might need more. 69 */ 70 #define NUM_DMA_LINKS 2 71 72 /** fsl_dma_private: p-substream DMA data 73 * 74 * Each substream has a 1-to-1 association with a DMA channel. 75 * 76 * The link[] array is first because it needs to be aligned on a 32-byte 77 * boundary, so putting it first will ensure alignment without padding the 78 * structure. 79 * 80 * @link[]: array of link descriptors 81 * @dma_channel: pointer to the DMA channel's registers 82 * @irq: IRQ for this DMA channel 83 * @substream: pointer to the substream object, needed by the ISR 84 * @ssi_sxx_phys: bus address of the STX or SRX register to use 85 * @ld_buf_phys: physical address of the LD buffer 86 * @current_link: index into link[] of the link currently being processed 87 * @dma_buf_phys: physical address of the DMA buffer 88 * @dma_buf_next: physical address of the next period to process 89 * @dma_buf_end: physical address of the byte after the end of the DMA 90 * @buffer period_size: the size of a single period 91 * @num_periods: the number of periods in the DMA buffer 92 */ 93 struct fsl_dma_private { 94 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 95 struct ccsr_dma_channel __iomem *dma_channel; 96 unsigned int irq; 97 struct snd_pcm_substream *substream; 98 dma_addr_t ssi_sxx_phys; 99 unsigned int ssi_fifo_depth; 100 dma_addr_t ld_buf_phys; 101 unsigned int current_link; 102 dma_addr_t dma_buf_phys; 103 dma_addr_t dma_buf_next; 104 dma_addr_t dma_buf_end; 105 size_t period_size; 106 unsigned int num_periods; 107 }; 108 109 /** 110 * fsl_dma_hardare: define characteristics of the PCM hardware. 111 * 112 * The PCM hardware is the Freescale DMA controller. This structure defines 113 * the capabilities of that hardware. 114 * 115 * Since the sampling rate and data format are not controlled by the DMA 116 * controller, we specify no limits for those values. The only exception is 117 * period_bytes_min, which is set to a reasonably low value to prevent the 118 * DMA controller from generating too many interrupts per second. 119 * 120 * Since each link descriptor has a 32-bit byte count field, we set 121 * period_bytes_max to the largest 32-bit number. We also have no maximum 122 * number of periods. 123 * 124 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 125 * limitation in the SSI driver requires the sample rates for playback and 126 * capture to be the same. 127 */ 128 static const struct snd_pcm_hardware fsl_dma_hardware = { 129 130 .info = SNDRV_PCM_INFO_INTERLEAVED | 131 SNDRV_PCM_INFO_MMAP | 132 SNDRV_PCM_INFO_MMAP_VALID | 133 SNDRV_PCM_INFO_JOINT_DUPLEX | 134 SNDRV_PCM_INFO_PAUSE, 135 .formats = FSLDMA_PCM_FORMATS, 136 .period_bytes_min = 512, /* A reasonable limit */ 137 .period_bytes_max = (u32) -1, 138 .periods_min = NUM_DMA_LINKS, 139 .periods_max = (unsigned int) -1, 140 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 141 }; 142 143 /** 144 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 145 * 146 * This function should be called by the ISR whenever the DMA controller 147 * halts data transfer. 148 */ 149 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 150 { 151 snd_pcm_stop_xrun(substream); 152 } 153 154 /** 155 * fsl_dma_update_pointers - update LD pointers to point to the next period 156 * 157 * As each period is completed, this function changes the link 158 * descriptor pointers for that period to point to the next period. 159 */ 160 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 161 { 162 struct fsl_dma_link_descriptor *link = 163 &dma_private->link[dma_private->current_link]; 164 165 /* Update our link descriptors to point to the next period. On a 36-bit 166 * system, we also need to update the ESAD bits. We also set (keep) the 167 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 168 */ 169 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 170 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 171 #ifdef CONFIG_PHYS_64BIT 172 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 173 upper_32_bits(dma_private->dma_buf_next)); 174 #endif 175 } else { 176 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 177 #ifdef CONFIG_PHYS_64BIT 178 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 179 upper_32_bits(dma_private->dma_buf_next)); 180 #endif 181 } 182 183 /* Update our variables for next time */ 184 dma_private->dma_buf_next += dma_private->period_size; 185 186 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 187 dma_private->dma_buf_next = dma_private->dma_buf_phys; 188 189 if (++dma_private->current_link >= NUM_DMA_LINKS) 190 dma_private->current_link = 0; 191 } 192 193 /** 194 * fsl_dma_isr: interrupt handler for the DMA controller 195 * 196 * @irq: IRQ of the DMA channel 197 * @dev_id: pointer to the dma_private structure for this DMA channel 198 */ 199 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 200 { 201 struct fsl_dma_private *dma_private = dev_id; 202 struct snd_pcm_substream *substream = dma_private->substream; 203 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 204 struct device *dev = rtd->dev; 205 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 206 irqreturn_t ret = IRQ_NONE; 207 u32 sr, sr2 = 0; 208 209 /* We got an interrupt, so read the status register to see what we 210 were interrupted for. 211 */ 212 sr = in_be32(&dma_channel->sr); 213 214 if (sr & CCSR_DMA_SR_TE) { 215 dev_err(dev, "dma transmit error\n"); 216 fsl_dma_abort_stream(substream); 217 sr2 |= CCSR_DMA_SR_TE; 218 ret = IRQ_HANDLED; 219 } 220 221 if (sr & CCSR_DMA_SR_CH) 222 ret = IRQ_HANDLED; 223 224 if (sr & CCSR_DMA_SR_PE) { 225 dev_err(dev, "dma programming error\n"); 226 fsl_dma_abort_stream(substream); 227 sr2 |= CCSR_DMA_SR_PE; 228 ret = IRQ_HANDLED; 229 } 230 231 if (sr & CCSR_DMA_SR_EOLNI) { 232 sr2 |= CCSR_DMA_SR_EOLNI; 233 ret = IRQ_HANDLED; 234 } 235 236 if (sr & CCSR_DMA_SR_CB) 237 ret = IRQ_HANDLED; 238 239 if (sr & CCSR_DMA_SR_EOSI) { 240 /* Tell ALSA we completed a period. */ 241 snd_pcm_period_elapsed(substream); 242 243 /* 244 * Update our link descriptors to point to the next period. We 245 * only need to do this if the number of periods is not equal to 246 * the number of links. 247 */ 248 if (dma_private->num_periods != NUM_DMA_LINKS) 249 fsl_dma_update_pointers(dma_private); 250 251 sr2 |= CCSR_DMA_SR_EOSI; 252 ret = IRQ_HANDLED; 253 } 254 255 if (sr & CCSR_DMA_SR_EOLSI) { 256 sr2 |= CCSR_DMA_SR_EOLSI; 257 ret = IRQ_HANDLED; 258 } 259 260 /* Clear the bits that we set */ 261 if (sr2) 262 out_be32(&dma_channel->sr, sr2); 263 264 return ret; 265 } 266 267 /** 268 * fsl_dma_new: initialize this PCM driver. 269 * 270 * This function is called by soc_new_pcm(), once for each DAI link 271 * in the machine driver's snd_soc_card structure. 272 * 273 * Regardless of where the memory is actually allocated, since the device can 274 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 275 */ 276 static int fsl_dma_new(struct snd_soc_component *component, 277 struct snd_soc_pcm_runtime *rtd) 278 { 279 struct snd_card *card = rtd->card->snd_card; 280 struct snd_pcm *pcm = rtd->pcm; 281 int ret; 282 283 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36)); 284 if (ret) 285 return ret; 286 287 return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 288 card->dev, 289 fsl_dma_hardware.buffer_bytes_max); 290 } 291 292 /** 293 * fsl_dma_open: open a new substream. 294 * 295 * Each substream has its own DMA buffer. 296 * 297 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 298 * descriptors that ping-pong from one period to the next. For example, if 299 * there are six periods and two link descriptors, this is how they look 300 * before playback starts: 301 * 302 * The last link descriptor 303 * ____________ points back to the first 304 * | | 305 * V | 306 * ___ ___ | 307 * | |->| |->| 308 * |___| |___| 309 * | | 310 * | | 311 * V V 312 * _________________________________________ 313 * | | | | | | | The DMA buffer is 314 * | | | | | | | divided into 6 parts 315 * |______|______|______|______|______|______| 316 * 317 * and here's how they look after the first period is finished playing: 318 * 319 * ____________ 320 * | | 321 * V | 322 * ___ ___ | 323 * | |->| |->| 324 * |___| |___| 325 * | | 326 * |______________ 327 * | | 328 * V V 329 * _________________________________________ 330 * | | | | | | | 331 * | | | | | | | 332 * |______|______|______|______|______|______| 333 * 334 * The first link descriptor now points to the third period. The DMA 335 * controller is currently playing the second period. When it finishes, it 336 * will jump back to the first descriptor and play the third period. 337 * 338 * There are four reasons we do this: 339 * 340 * 1. The only way to get the DMA controller to automatically restart the 341 * transfer when it gets to the end of the buffer is to use chaining 342 * mode. Basic direct mode doesn't offer that feature. 343 * 2. We need to receive an interrupt at the end of every period. The DMA 344 * controller can generate an interrupt at the end of every link transfer 345 * (aka segment). Making each period into a DMA segment will give us the 346 * interrupts we need. 347 * 3. By creating only two link descriptors, regardless of the number of 348 * periods, we do not need to reallocate the link descriptors if the 349 * number of periods changes. 350 * 4. All of the audio data is still stored in a single, contiguous DMA 351 * buffer, which is what ALSA expects. We're just dividing it into 352 * contiguous parts, and creating a link descriptor for each one. 353 */ 354 static int fsl_dma_open(struct snd_soc_component *component, 355 struct snd_pcm_substream *substream) 356 { 357 struct snd_pcm_runtime *runtime = substream->runtime; 358 struct device *dev = component->dev; 359 struct dma_object *dma = 360 container_of(component->driver, struct dma_object, dai); 361 struct fsl_dma_private *dma_private; 362 struct ccsr_dma_channel __iomem *dma_channel; 363 dma_addr_t ld_buf_phys; 364 u64 temp_link; /* Pointer to next link descriptor */ 365 u32 mr; 366 int ret = 0; 367 unsigned int i; 368 369 /* 370 * Reject any DMA buffer whose size is not a multiple of the period 371 * size. We need to make sure that the DMA buffer can be evenly divided 372 * into periods. 373 */ 374 ret = snd_pcm_hw_constraint_integer(runtime, 375 SNDRV_PCM_HW_PARAM_PERIODS); 376 if (ret < 0) { 377 dev_err(dev, "invalid buffer size\n"); 378 return ret; 379 } 380 381 if (dma->assigned) { 382 dev_err(dev, "dma channel already assigned\n"); 383 return -EBUSY; 384 } 385 386 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 387 &ld_buf_phys, GFP_KERNEL); 388 if (!dma_private) { 389 dev_err(dev, "can't allocate dma private data\n"); 390 return -ENOMEM; 391 } 392 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 393 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 394 else 395 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 396 397 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 398 dma_private->dma_channel = dma->channel; 399 dma_private->irq = dma->irq; 400 dma_private->substream = substream; 401 dma_private->ld_buf_phys = ld_buf_phys; 402 dma_private->dma_buf_phys = substream->dma_buffer.addr; 403 404 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 405 dma_private); 406 if (ret) { 407 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 408 dma_private->irq, ret); 409 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 410 dma_private, dma_private->ld_buf_phys); 411 return ret; 412 } 413 414 dma->assigned = true; 415 416 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 417 runtime->private_data = dma_private; 418 419 /* Program the fixed DMA controller parameters */ 420 421 dma_channel = dma_private->dma_channel; 422 423 temp_link = dma_private->ld_buf_phys + 424 sizeof(struct fsl_dma_link_descriptor); 425 426 for (i = 0; i < NUM_DMA_LINKS; i++) { 427 dma_private->link[i].next = cpu_to_be64(temp_link); 428 429 temp_link += sizeof(struct fsl_dma_link_descriptor); 430 } 431 /* The last link descriptor points to the first */ 432 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 433 434 /* Tell the DMA controller where the first link descriptor is */ 435 out_be32(&dma_channel->clndar, 436 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 437 out_be32(&dma_channel->eclndar, 438 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 439 440 /* The manual says the BCR must be clear before enabling EMP */ 441 out_be32(&dma_channel->bcr, 0); 442 443 /* 444 * Program the mode register for interrupts, external master control, 445 * and source/destination hold. Also clear the Channel Abort bit. 446 */ 447 mr = in_be32(&dma_channel->mr) & 448 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 449 450 /* 451 * We want External Master Start and External Master Pause enabled, 452 * because the SSI is controlling the DMA controller. We want the DMA 453 * controller to be set up in advance, and then we signal only the SSI 454 * to start transferring. 455 * 456 * We want End-Of-Segment Interrupts enabled, because this will generate 457 * an interrupt at the end of each segment (each link descriptor 458 * represents one segment). Each DMA segment is the same thing as an 459 * ALSA period, so this is how we get an interrupt at the end of every 460 * period. 461 * 462 * We want Error Interrupt enabled, so that we can get an error if 463 * the DMA controller is mis-programmed somehow. 464 */ 465 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 466 CCSR_DMA_MR_EMS_EN; 467 468 /* For playback, we want the destination address to be held. For 469 capture, set the source address to be held. */ 470 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 471 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 472 473 out_be32(&dma_channel->mr, mr); 474 475 return 0; 476 } 477 478 /** 479 * fsl_dma_hw_params: continue initializing the DMA links 480 * 481 * This function obtains hardware parameters about the opened stream and 482 * programs the DMA controller accordingly. 483 * 484 * One drawback of big-endian is that when copying integers of different 485 * sizes to a fixed-sized register, the address to which the integer must be 486 * copied is dependent on the size of the integer. 487 * 488 * For example, if P is the address of a 32-bit register, and X is a 32-bit 489 * integer, then X should be copied to address P. However, if X is a 16-bit 490 * integer, then it should be copied to P+2. If X is an 8-bit register, 491 * then it should be copied to P+3. 492 * 493 * So for playback of 8-bit samples, the DMA controller must transfer single 494 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 495 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 496 * 497 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 498 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 499 * and 8 bytes at a time). So we do not support packed 24-bit samples. 500 * 24-bit data must be padded to 32 bits. 501 */ 502 static int fsl_dma_hw_params(struct snd_soc_component *component, 503 struct snd_pcm_substream *substream, 504 struct snd_pcm_hw_params *hw_params) 505 { 506 struct snd_pcm_runtime *runtime = substream->runtime; 507 struct fsl_dma_private *dma_private = runtime->private_data; 508 struct device *dev = component->dev; 509 510 /* Number of bits per sample */ 511 unsigned int sample_bits = 512 snd_pcm_format_physical_width(params_format(hw_params)); 513 514 /* Number of bytes per frame */ 515 unsigned int sample_bytes = sample_bits / 8; 516 517 /* Bus address of SSI STX register */ 518 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 519 520 /* Size of the DMA buffer, in bytes */ 521 size_t buffer_size = params_buffer_bytes(hw_params); 522 523 /* Number of bytes per period */ 524 size_t period_size = params_period_bytes(hw_params); 525 526 /* Pointer to next period */ 527 dma_addr_t temp_addr = substream->dma_buffer.addr; 528 529 /* Pointer to DMA controller */ 530 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 531 532 u32 mr; /* DMA Mode Register */ 533 534 unsigned int i; 535 536 /* Initialize our DMA tracking variables */ 537 dma_private->period_size = period_size; 538 dma_private->num_periods = params_periods(hw_params); 539 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 540 dma_private->dma_buf_next = dma_private->dma_buf_phys + 541 (NUM_DMA_LINKS * period_size); 542 543 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 544 /* This happens if the number of periods == NUM_DMA_LINKS */ 545 dma_private->dma_buf_next = dma_private->dma_buf_phys; 546 547 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 548 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 549 550 /* Due to a quirk of the SSI's STX register, the target address 551 * for the DMA operations depends on the sample size. So we calculate 552 * that offset here. While we're at it, also tell the DMA controller 553 * how much data to transfer per sample. 554 */ 555 switch (sample_bits) { 556 case 8: 557 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 558 ssi_sxx_phys += 3; 559 break; 560 case 16: 561 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 562 ssi_sxx_phys += 2; 563 break; 564 case 32: 565 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 566 break; 567 default: 568 /* We should never get here */ 569 dev_err(dev, "unsupported sample size %u\n", sample_bits); 570 return -EINVAL; 571 } 572 573 /* 574 * BWC determines how many bytes are sent/received before the DMA 575 * controller checks the SSI to see if it needs to stop. BWC should 576 * always be a multiple of the frame size, so that we always transmit 577 * whole frames. Each frame occupies two slots in the FIFO. The 578 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 579 * (MR[BWC] can only represent even powers of two). 580 * 581 * To simplify the process, we set BWC to the largest value that is 582 * less than or equal to the FIFO watermark. For playback, this ensures 583 * that we transfer the maximum amount without overrunning the FIFO. 584 * For capture, this ensures that we transfer the maximum amount without 585 * underrunning the FIFO. 586 * 587 * f = SSI FIFO depth 588 * w = SSI watermark value (which equals f - 2) 589 * b = DMA bandwidth count (in bytes) 590 * s = sample size (in bytes, which equals frame_size * 2) 591 * 592 * For playback, we never transmit more than the transmit FIFO 593 * watermark, otherwise we might write more data than the FIFO can hold. 594 * The watermark is equal to the FIFO depth minus two. 595 * 596 * For capture, two equations must hold: 597 * w > f - (b / s) 598 * w >= b / s 599 * 600 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 601 * b = s * w, which is equal to 602 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 603 */ 604 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 605 606 out_be32(&dma_channel->mr, mr); 607 608 for (i = 0; i < NUM_DMA_LINKS; i++) { 609 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 610 611 link->count = cpu_to_be32(period_size); 612 613 /* The snoop bit tells the DMA controller whether it should tell 614 * the ECM to snoop during a read or write to an address. For 615 * audio, we use DMA to transfer data between memory and an I/O 616 * device (the SSI's STX0 or SRX0 register). Snooping is only 617 * needed if there is a cache, so we need to snoop memory 618 * addresses only. For playback, that means we snoop the source 619 * but not the destination. For capture, we snoop the 620 * destination but not the source. 621 * 622 * Note that failing to snoop properly is unlikely to cause 623 * cache incoherency if the period size is larger than the 624 * size of L1 cache. This is because filling in one period will 625 * flush out the data for the previous period. So if you 626 * increased period_bytes_min to a large enough size, you might 627 * get more performance by not snooping, and you'll still be 628 * okay. You'll need to update fsl_dma_update_pointers() also. 629 */ 630 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 631 link->source_addr = cpu_to_be32(temp_addr); 632 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 633 upper_32_bits(temp_addr)); 634 635 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 636 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 637 upper_32_bits(ssi_sxx_phys)); 638 } else { 639 link->source_addr = cpu_to_be32(ssi_sxx_phys); 640 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 641 upper_32_bits(ssi_sxx_phys)); 642 643 link->dest_addr = cpu_to_be32(temp_addr); 644 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 645 upper_32_bits(temp_addr)); 646 } 647 648 temp_addr += period_size; 649 } 650 651 return 0; 652 } 653 654 /** 655 * fsl_dma_pointer: determine the current position of the DMA transfer 656 * 657 * This function is called by ALSA when ALSA wants to know where in the 658 * stream buffer the hardware currently is. 659 * 660 * For playback, the SAR register contains the physical address of the most 661 * recent DMA transfer. For capture, the value is in the DAR register. 662 * 663 * The base address of the buffer is stored in the source_addr field of the 664 * first link descriptor. 665 */ 666 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component, 667 struct snd_pcm_substream *substream) 668 { 669 struct snd_pcm_runtime *runtime = substream->runtime; 670 struct fsl_dma_private *dma_private = runtime->private_data; 671 struct device *dev = component->dev; 672 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 673 dma_addr_t position; 674 snd_pcm_uframes_t frames; 675 676 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 677 * only have 32-bit DMA addresses. This function is typically called 678 * in interrupt context, so we need to optimize it. 679 */ 680 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 681 position = in_be32(&dma_channel->sar); 682 #ifdef CONFIG_PHYS_64BIT 683 position |= (u64)(in_be32(&dma_channel->satr) & 684 CCSR_DMA_ATR_ESAD_MASK) << 32; 685 #endif 686 } else { 687 position = in_be32(&dma_channel->dar); 688 #ifdef CONFIG_PHYS_64BIT 689 position |= (u64)(in_be32(&dma_channel->datr) & 690 CCSR_DMA_ATR_ESAD_MASK) << 32; 691 #endif 692 } 693 694 /* 695 * When capture is started, the SSI immediately starts to fill its FIFO. 696 * This means that the DMA controller is not started until the FIFO is 697 * full. However, ALSA calls this function before that happens, when 698 * MR.DAR is still zero. In this case, just return zero to indicate 699 * that nothing has been received yet. 700 */ 701 if (!position) 702 return 0; 703 704 if ((position < dma_private->dma_buf_phys) || 705 (position > dma_private->dma_buf_end)) { 706 dev_err(dev, "dma pointer is out of range, halting stream\n"); 707 return SNDRV_PCM_POS_XRUN; 708 } 709 710 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 711 712 /* 713 * If the current address is just past the end of the buffer, wrap it 714 * around. 715 */ 716 if (frames == runtime->buffer_size) 717 frames = 0; 718 719 return frames; 720 } 721 722 /** 723 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 724 * 725 * Release the resources allocated in fsl_dma_hw_params() and de-program the 726 * registers. 727 * 728 * This function can be called multiple times. 729 */ 730 static int fsl_dma_hw_free(struct snd_soc_component *component, 731 struct snd_pcm_substream *substream) 732 { 733 struct snd_pcm_runtime *runtime = substream->runtime; 734 struct fsl_dma_private *dma_private = runtime->private_data; 735 736 if (dma_private) { 737 struct ccsr_dma_channel __iomem *dma_channel; 738 739 dma_channel = dma_private->dma_channel; 740 741 /* Stop the DMA */ 742 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 743 out_be32(&dma_channel->mr, 0); 744 745 /* Reset all the other registers */ 746 out_be32(&dma_channel->sr, -1); 747 out_be32(&dma_channel->clndar, 0); 748 out_be32(&dma_channel->eclndar, 0); 749 out_be32(&dma_channel->satr, 0); 750 out_be32(&dma_channel->sar, 0); 751 out_be32(&dma_channel->datr, 0); 752 out_be32(&dma_channel->dar, 0); 753 out_be32(&dma_channel->bcr, 0); 754 out_be32(&dma_channel->nlndar, 0); 755 out_be32(&dma_channel->enlndar, 0); 756 } 757 758 return 0; 759 } 760 761 /** 762 * fsl_dma_close: close the stream. 763 */ 764 static int fsl_dma_close(struct snd_soc_component *component, 765 struct snd_pcm_substream *substream) 766 { 767 struct snd_pcm_runtime *runtime = substream->runtime; 768 struct fsl_dma_private *dma_private = runtime->private_data; 769 struct device *dev = component->dev; 770 struct dma_object *dma = 771 container_of(component->driver, struct dma_object, dai); 772 773 if (dma_private) { 774 if (dma_private->irq) 775 free_irq(dma_private->irq, dma_private); 776 777 /* Deallocate the fsl_dma_private structure */ 778 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 779 dma_private, dma_private->ld_buf_phys); 780 substream->runtime->private_data = NULL; 781 } 782 783 dma->assigned = false; 784 785 return 0; 786 } 787 788 /** 789 * find_ssi_node -- returns the SSI node that points to its DMA channel node 790 * 791 * Although this DMA driver attempts to operate independently of the other 792 * devices, it still needs to determine some information about the SSI device 793 * that it's working with. Unfortunately, the device tree does not contain 794 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 795 * other way. So we need to scan the device tree for SSI nodes until we find 796 * the one that points to the given DMA channel node. It's ugly, but at least 797 * it's contained in this one function. 798 */ 799 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 800 { 801 struct device_node *ssi_np, *np; 802 803 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 804 /* Check each DMA phandle to see if it points to us. We 805 * assume that device_node pointers are a valid comparison. 806 */ 807 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 808 of_node_put(np); 809 if (np == dma_channel_np) 810 return ssi_np; 811 812 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 813 of_node_put(np); 814 if (np == dma_channel_np) 815 return ssi_np; 816 } 817 818 return NULL; 819 } 820 821 static int fsl_soc_dma_probe(struct platform_device *pdev) 822 { 823 struct dma_object *dma; 824 struct device_node *np = pdev->dev.of_node; 825 struct device_node *ssi_np; 826 struct resource res; 827 const uint32_t *iprop; 828 int ret; 829 830 /* Find the SSI node that points to us. */ 831 ssi_np = find_ssi_node(np); 832 if (!ssi_np) { 833 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 834 return -ENODEV; 835 } 836 837 ret = of_address_to_resource(ssi_np, 0, &res); 838 if (ret) { 839 dev_err(&pdev->dev, "could not determine resources for %pOF\n", 840 ssi_np); 841 of_node_put(ssi_np); 842 return ret; 843 } 844 845 dma = kzalloc_obj(*dma); 846 if (!dma) { 847 of_node_put(ssi_np); 848 return -ENOMEM; 849 } 850 851 dma->dai.name = DRV_NAME; 852 dma->dai.open = fsl_dma_open; 853 dma->dai.close = fsl_dma_close; 854 dma->dai.hw_params = fsl_dma_hw_params; 855 dma->dai.hw_free = fsl_dma_hw_free; 856 dma->dai.pointer = fsl_dma_pointer; 857 dma->dai.pcm_new = fsl_dma_new; 858 859 /* Store the SSI-specific information that we need */ 860 dma->ssi_stx_phys = res.start + REG_SSI_STX0; 861 dma->ssi_srx_phys = res.start + REG_SSI_SRX0; 862 863 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 864 if (iprop) 865 dma->ssi_fifo_depth = be32_to_cpup(iprop); 866 else 867 /* Older 8610 DTs didn't have the fifo-depth property */ 868 dma->ssi_fifo_depth = 8; 869 870 of_node_put(ssi_np); 871 872 ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0); 873 if (ret) { 874 dev_err(&pdev->dev, "could not register platform\n"); 875 kfree(dma); 876 return ret; 877 } 878 879 dma->channel = of_iomap(np, 0); 880 dma->irq = irq_of_parse_and_map(np, 0); 881 882 dev_set_drvdata(&pdev->dev, dma); 883 884 return 0; 885 } 886 887 static void fsl_soc_dma_remove(struct platform_device *pdev) 888 { 889 struct dma_object *dma = dev_get_drvdata(&pdev->dev); 890 891 iounmap(dma->channel); 892 irq_dispose_mapping(dma->irq); 893 kfree(dma); 894 } 895 896 static const struct of_device_id fsl_soc_dma_ids[] = { 897 { .compatible = "fsl,ssi-dma-channel", }, 898 {} 899 }; 900 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 901 902 static struct platform_driver fsl_soc_dma_driver = { 903 .driver = { 904 .name = "fsl-pcm-audio", 905 .of_match_table = fsl_soc_dma_ids, 906 }, 907 .probe = fsl_soc_dma_probe, 908 .remove = fsl_soc_dma_remove, 909 }; 910 911 module_platform_driver(fsl_soc_dma_driver); 912 913 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 914 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 915 MODULE_LICENSE("GPL v2"); 916