1 /*
2 * i.MX 8M Plus SoC Implementation
3 *
4 * Based on hw/arm/fsl-imx6.c
5 *
6 * Copyright (c) 2024, Bernhard Beschow <shentey@gmail.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "system/address-spaces.h"
13 #include "hw/arm/bsa.h"
14 #include "hw/arm/fsl-imx8mp.h"
15 #include "hw/intc/arm_gicv3.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/boards.h"
18 #include "system/system.h"
19 #include "target/arm/cpu-qom.h"
20 #include "qapi/error.h"
21 #include "qobject/qlist.h"
22
23 static const struct {
24 hwaddr addr;
25 size_t size;
26 const char *name;
27 } fsl_imx8mp_memmap[] = {
28 [FSL_IMX8MP_RAM] = { FSL_IMX8MP_RAM_START, FSL_IMX8MP_RAM_SIZE_MAX, "ram" },
29 [FSL_IMX8MP_DDR_PHY_BROADCAST] = { 0x3dc00000, 4 * MiB, "ddr_phy_broadcast" },
30 [FSL_IMX8MP_DDR_PERF_MON] = { 0x3d800000, 4 * MiB, "ddr_perf_mon" },
31 [FSL_IMX8MP_DDR_CTL] = { 0x3d400000, 4 * MiB, "ddr_ctl" },
32 [FSL_IMX8MP_DDR_BLK_CTRL] = { 0x3d000000, 1 * MiB, "ddr_blk_ctrl" },
33 [FSL_IMX8MP_DDR_PHY] = { 0x3c000000, 16 * MiB, "ddr_phy" },
34 [FSL_IMX8MP_AUDIO_DSP] = { 0x3b000000, 16 * MiB, "audio_dsp" },
35 [FSL_IMX8MP_GIC_DIST] = { 0x38800000, 512 * KiB, "gic_dist" },
36 [FSL_IMX8MP_GIC_REDIST] = { 0x38880000, 512 * KiB, "gic_redist" },
37 [FSL_IMX8MP_NPU] = { 0x38500000, 2 * MiB, "npu" },
38 [FSL_IMX8MP_VPU] = { 0x38340000, 2 * MiB, "vpu" },
39 [FSL_IMX8MP_VPU_BLK_CTRL] = { 0x38330000, 2 * MiB, "vpu_blk_ctrl" },
40 [FSL_IMX8MP_VPU_VC8000E_ENCODER] = { 0x38320000, 2 * MiB, "vpu_vc8000e_encoder" },
41 [FSL_IMX8MP_VPU_G2_DECODER] = { 0x38310000, 2 * MiB, "vpu_g2_decoder" },
42 [FSL_IMX8MP_VPU_G1_DECODER] = { 0x38300000, 2 * MiB, "vpu_g1_decoder" },
43 [FSL_IMX8MP_USB2_GLUE] = { 0x382f0000, 0x100, "usb2_glue" },
44 [FSL_IMX8MP_USB2_OTG] = { 0x3820cc00, 0x100, "usb2_otg" },
45 [FSL_IMX8MP_USB2_DEV] = { 0x3820c700, 0x500, "usb2_dev" },
46 [FSL_IMX8MP_USB2] = { 0x38200000, 0xc700, "usb2" },
47 [FSL_IMX8MP_USB1_GLUE] = { 0x381f0000, 0x100, "usb1_glue" },
48 [FSL_IMX8MP_USB1_OTG] = { 0x3810cc00, 0x100, "usb1_otg" },
49 [FSL_IMX8MP_USB1_DEV] = { 0x3810c700, 0x500, "usb1_dev" },
50 [FSL_IMX8MP_USB1] = { 0x38100000, 0xc700, "usb1" },
51 [FSL_IMX8MP_GPU2D] = { 0x38008000, 32 * KiB, "gpu2d" },
52 [FSL_IMX8MP_GPU3D] = { 0x38000000, 32 * KiB, "gpu3d" },
53 [FSL_IMX8MP_QSPI1_RX_BUFFER] = { 0x34000000, 32 * MiB, "qspi1_rx_buffer" },
54 [FSL_IMX8MP_PCIE1] = { 0x33800000, 4 * MiB, "pcie1" },
55 [FSL_IMX8MP_QSPI1_TX_BUFFER] = { 0x33008000, 32 * KiB, "qspi1_tx_buffer" },
56 [FSL_IMX8MP_APBH_DMA] = { 0x33000000, 32 * KiB, "apbh_dma" },
57
58 /* AIPS-5 Begin */
59 [FSL_IMX8MP_MU_3_B] = { 0x30e90000, 64 * KiB, "mu_3_b" },
60 [FSL_IMX8MP_MU_3_A] = { 0x30e80000, 64 * KiB, "mu_3_a" },
61 [FSL_IMX8MP_MU_2_B] = { 0x30e70000, 64 * KiB, "mu_2_b" },
62 [FSL_IMX8MP_MU_2_A] = { 0x30e60000, 64 * KiB, "mu_2_a" },
63 [FSL_IMX8MP_EDMA_CHANNELS] = { 0x30e40000, 128 * KiB, "edma_channels" },
64 [FSL_IMX8MP_EDMA_MANAGEMENT_PAGE] = { 0x30e30000, 64 * KiB, "edma_management_page" },
65 [FSL_IMX8MP_AUDIO_BLK_CTRL] = { 0x30e20000, 64 * KiB, "audio_blk_ctrl" },
66 [FSL_IMX8MP_SDMA2] = { 0x30e10000, 64 * KiB, "sdma2" },
67 [FSL_IMX8MP_SDMA3] = { 0x30e00000, 64 * KiB, "sdma3" },
68 [FSL_IMX8MP_AIPS5_CONFIGURATION] = { 0x30df0000, 64 * KiB, "aips5_configuration" },
69 [FSL_IMX8MP_SPBA2] = { 0x30cf0000, 64 * KiB, "spba2" },
70 [FSL_IMX8MP_AUDIO_XCVR_RX] = { 0x30cc0000, 64 * KiB, "audio_xcvr_rx" },
71 [FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR] = { 0x30cb0000, 64 * KiB, "hdmi_tx_audlnk_mstr" },
72 [FSL_IMX8MP_PDM] = { 0x30ca0000, 64 * KiB, "pdm" },
73 [FSL_IMX8MP_ASRC] = { 0x30c90000, 64 * KiB, "asrc" },
74 [FSL_IMX8MP_SAI7] = { 0x30c80000, 64 * KiB, "sai7" },
75 [FSL_IMX8MP_SAI6] = { 0x30c60000, 64 * KiB, "sai6" },
76 [FSL_IMX8MP_SAI5] = { 0x30c50000, 64 * KiB, "sai5" },
77 [FSL_IMX8MP_SAI3] = { 0x30c30000, 64 * KiB, "sai3" },
78 [FSL_IMX8MP_SAI2] = { 0x30c20000, 64 * KiB, "sai2" },
79 [FSL_IMX8MP_SAI1] = { 0x30c10000, 64 * KiB, "sai1" },
80 /* AIPS-5 End */
81
82 /* AIPS-4 Begin */
83 [FSL_IMX8MP_HDMI_TX] = { 0x32fc0000, 128 * KiB, "hdmi_tx" },
84 [FSL_IMX8MP_TZASC] = { 0x32f80000, 64 * KiB, "tzasc" },
85 [FSL_IMX8MP_HSIO_BLK_CTL] = { 0x32f10000, 64 * KiB, "hsio_blk_ctl" },
86 [FSL_IMX8MP_PCIE_PHY1] = { 0x32f00000, 64 * KiB, "pcie_phy1" },
87 [FSL_IMX8MP_MEDIA_BLK_CTL] = { 0x32ec0000, 64 * KiB, "media_blk_ctl" },
88 [FSL_IMX8MP_LCDIF2] = { 0x32e90000, 64 * KiB, "lcdif2" },
89 [FSL_IMX8MP_LCDIF1] = { 0x32e80000, 64 * KiB, "lcdif1" },
90 [FSL_IMX8MP_MIPI_DSI1] = { 0x32e60000, 64 * KiB, "mipi_dsi1" },
91 [FSL_IMX8MP_MIPI_CSI2] = { 0x32e50000, 64 * KiB, "mipi_csi2" },
92 [FSL_IMX8MP_MIPI_CSI1] = { 0x32e40000, 64 * KiB, "mipi_csi1" },
93 [FSL_IMX8MP_IPS_DEWARP] = { 0x32e30000, 64 * KiB, "ips_dewarp" },
94 [FSL_IMX8MP_ISP2] = { 0x32e20000, 64 * KiB, "isp2" },
95 [FSL_IMX8MP_ISP1] = { 0x32e10000, 64 * KiB, "isp1" },
96 [FSL_IMX8MP_ISI] = { 0x32e00000, 64 * KiB, "isi" },
97 [FSL_IMX8MP_AIPS4_CONFIGURATION] = { 0x32df0000, 64 * KiB, "aips4_configuration" },
98 /* AIPS-4 End */
99
100 [FSL_IMX8MP_INTERCONNECT] = { 0x32700000, 1 * MiB, "interconnect" },
101
102 /* AIPS-3 Begin */
103 [FSL_IMX8MP_ENET2_TSN] = { 0x30bf0000, 64 * KiB, "enet2_tsn" },
104 [FSL_IMX8MP_ENET1] = { 0x30be0000, 64 * KiB, "enet1" },
105 [FSL_IMX8MP_SDMA1] = { 0x30bd0000, 64 * KiB, "sdma1" },
106 [FSL_IMX8MP_QSPI] = { 0x30bb0000, 64 * KiB, "qspi" },
107 [FSL_IMX8MP_USDHC3] = { 0x30b60000, 64 * KiB, "usdhc3" },
108 [FSL_IMX8MP_USDHC2] = { 0x30b50000, 64 * KiB, "usdhc2" },
109 [FSL_IMX8MP_USDHC1] = { 0x30b40000, 64 * KiB, "usdhc1" },
110 [FSL_IMX8MP_I2C6] = { 0x30ae0000, 64 * KiB, "i2c6" },
111 [FSL_IMX8MP_I2C5] = { 0x30ad0000, 64 * KiB, "i2c5" },
112 [FSL_IMX8MP_SEMAPHORE_HS] = { 0x30ac0000, 64 * KiB, "semaphore_hs" },
113 [FSL_IMX8MP_MU_1_B] = { 0x30ab0000, 64 * KiB, "mu_1_b" },
114 [FSL_IMX8MP_MU_1_A] = { 0x30aa0000, 64 * KiB, "mu_1_a" },
115 [FSL_IMX8MP_AUD_IRQ_STEER] = { 0x30a80000, 64 * KiB, "aud_irq_steer" },
116 [FSL_IMX8MP_UART4] = { 0x30a60000, 64 * KiB, "uart4" },
117 [FSL_IMX8MP_I2C4] = { 0x30a50000, 64 * KiB, "i2c4" },
118 [FSL_IMX8MP_I2C3] = { 0x30a40000, 64 * KiB, "i2c3" },
119 [FSL_IMX8MP_I2C2] = { 0x30a30000, 64 * KiB, "i2c2" },
120 [FSL_IMX8MP_I2C1] = { 0x30a20000, 64 * KiB, "i2c1" },
121 [FSL_IMX8MP_AIPS3_CONFIGURATION] = { 0x309f0000, 64 * KiB, "aips3_configuration" },
122 [FSL_IMX8MP_CAAM] = { 0x30900000, 256 * KiB, "caam" },
123 [FSL_IMX8MP_SPBA1] = { 0x308f0000, 64 * KiB, "spba1" },
124 [FSL_IMX8MP_FLEXCAN2] = { 0x308d0000, 64 * KiB, "flexcan2" },
125 [FSL_IMX8MP_FLEXCAN1] = { 0x308c0000, 64 * KiB, "flexcan1" },
126 [FSL_IMX8MP_UART2] = { 0x30890000, 64 * KiB, "uart2" },
127 [FSL_IMX8MP_UART3] = { 0x30880000, 64 * KiB, "uart3" },
128 [FSL_IMX8MP_UART1] = { 0x30860000, 64 * KiB, "uart1" },
129 [FSL_IMX8MP_ECSPI3] = { 0x30840000, 64 * KiB, "ecspi3" },
130 [FSL_IMX8MP_ECSPI2] = { 0x30830000, 64 * KiB, "ecspi2" },
131 [FSL_IMX8MP_ECSPI1] = { 0x30820000, 64 * KiB, "ecspi1" },
132 /* AIPS-3 End */
133
134 /* AIPS-2 Begin */
135 [FSL_IMX8MP_QOSC] = { 0x307f0000, 64 * KiB, "qosc" },
136 [FSL_IMX8MP_PERFMON2] = { 0x307d0000, 64 * KiB, "perfmon2" },
137 [FSL_IMX8MP_PERFMON1] = { 0x307c0000, 64 * KiB, "perfmon1" },
138 [FSL_IMX8MP_GPT4] = { 0x30700000, 64 * KiB, "gpt4" },
139 [FSL_IMX8MP_GPT5] = { 0x306f0000, 64 * KiB, "gpt5" },
140 [FSL_IMX8MP_GPT6] = { 0x306e0000, 64 * KiB, "gpt6" },
141 [FSL_IMX8MP_SYSCNT_CTRL] = { 0x306c0000, 64 * KiB, "syscnt_ctrl" },
142 [FSL_IMX8MP_SYSCNT_CMP] = { 0x306b0000, 64 * KiB, "syscnt_cmp" },
143 [FSL_IMX8MP_SYSCNT_RD] = { 0x306a0000, 64 * KiB, "syscnt_rd" },
144 [FSL_IMX8MP_PWM4] = { 0x30690000, 64 * KiB, "pwm4" },
145 [FSL_IMX8MP_PWM3] = { 0x30680000, 64 * KiB, "pwm3" },
146 [FSL_IMX8MP_PWM2] = { 0x30670000, 64 * KiB, "pwm2" },
147 [FSL_IMX8MP_PWM1] = { 0x30660000, 64 * KiB, "pwm1" },
148 [FSL_IMX8MP_AIPS2_CONFIGURATION] = { 0x305f0000, 64 * KiB, "aips2_configuration" },
149 /* AIPS-2 End */
150
151 /* AIPS-1 Begin */
152 [FSL_IMX8MP_CSU] = { 0x303e0000, 64 * KiB, "csu" },
153 [FSL_IMX8MP_RDC] = { 0x303d0000, 64 * KiB, "rdc" },
154 [FSL_IMX8MP_SEMAPHORE2] = { 0x303c0000, 64 * KiB, "semaphore2" },
155 [FSL_IMX8MP_SEMAPHORE1] = { 0x303b0000, 64 * KiB, "semaphore1" },
156 [FSL_IMX8MP_GPC] = { 0x303a0000, 64 * KiB, "gpc" },
157 [FSL_IMX8MP_SRC] = { 0x30390000, 64 * KiB, "src" },
158 [FSL_IMX8MP_CCM] = { 0x30380000, 64 * KiB, "ccm" },
159 [FSL_IMX8MP_SNVS_HP] = { 0x30370000, 64 * KiB, "snvs_hp" },
160 [FSL_IMX8MP_ANA_PLL] = { 0x30360000, 64 * KiB, "ana_pll" },
161 [FSL_IMX8MP_OCOTP_CTRL] = { 0x30350000, 64 * KiB, "ocotp_ctrl" },
162 [FSL_IMX8MP_IOMUXC_GPR] = { 0x30340000, 64 * KiB, "iomuxc_gpr" },
163 [FSL_IMX8MP_IOMUXC] = { 0x30330000, 64 * KiB, "iomuxc" },
164 [FSL_IMX8MP_GPT3] = { 0x302f0000, 64 * KiB, "gpt3" },
165 [FSL_IMX8MP_GPT2] = { 0x302e0000, 64 * KiB, "gpt2" },
166 [FSL_IMX8MP_GPT1] = { 0x302d0000, 64 * KiB, "gpt1" },
167 [FSL_IMX8MP_WDOG3] = { 0x302a0000, 64 * KiB, "wdog3" },
168 [FSL_IMX8MP_WDOG2] = { 0x30290000, 64 * KiB, "wdog2" },
169 [FSL_IMX8MP_WDOG1] = { 0x30280000, 64 * KiB, "wdog1" },
170 [FSL_IMX8MP_ANA_OSC] = { 0x30270000, 64 * KiB, "ana_osc" },
171 [FSL_IMX8MP_ANA_TSENSOR] = { 0x30260000, 64 * KiB, "ana_tsensor" },
172 [FSL_IMX8MP_GPIO5] = { 0x30240000, 64 * KiB, "gpio5" },
173 [FSL_IMX8MP_GPIO4] = { 0x30230000, 64 * KiB, "gpio4" },
174 [FSL_IMX8MP_GPIO3] = { 0x30220000, 64 * KiB, "gpio3" },
175 [FSL_IMX8MP_GPIO2] = { 0x30210000, 64 * KiB, "gpio2" },
176 [FSL_IMX8MP_GPIO1] = { 0x30200000, 64 * KiB, "gpio1" },
177 [FSL_IMX8MP_AIPS1_CONFIGURATION] = { 0x301f0000, 64 * KiB, "aips1_configuration" },
178 /* AIPS-1 End */
179
180 [FSL_IMX8MP_A53_DAP] = { 0x28000000, 16 * MiB, "a53_dap" },
181 [FSL_IMX8MP_PCIE1_MEM] = { 0x18000000, 128 * MiB, "pcie1_mem" },
182 [FSL_IMX8MP_QSPI_MEM] = { 0x08000000, 256 * MiB, "qspi_mem" },
183 [FSL_IMX8MP_OCRAM] = { 0x00900000, 576 * KiB, "ocram" },
184 [FSL_IMX8MP_TCM_DTCM] = { 0x00800000, 128 * KiB, "tcm_dtcm" },
185 [FSL_IMX8MP_TCM_ITCM] = { 0x007e0000, 128 * KiB, "tcm_itcm" },
186 [FSL_IMX8MP_OCRAM_S] = { 0x00180000, 36 * KiB, "ocram_s" },
187 [FSL_IMX8MP_CAAM_MEM] = { 0x00100000, 32 * KiB, "caam_mem" },
188 [FSL_IMX8MP_BOOT_ROM_PROTECTED] = { 0x0003f000, 4 * KiB, "boot_rom_protected" },
189 [FSL_IMX8MP_BOOT_ROM] = { 0x00000000, 252 * KiB, "boot_rom" },
190 };
191
fsl_imx8mp_init(Object * obj)192 static void fsl_imx8mp_init(Object *obj)
193 {
194 MachineState *ms = MACHINE(qdev_get_machine());
195 FslImx8mpState *s = FSL_IMX8MP(obj);
196 int i;
197
198 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX8MP_NUM_CPUS); i++) {
199 g_autofree char *name = g_strdup_printf("cpu%d", i);
200 object_initialize_child(obj, name, &s->cpu[i],
201 ARM_CPU_TYPE_NAME("cortex-a53"));
202 }
203
204 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3);
205
206 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM);
207
208 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG);
209
210 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
211
212 for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
213 g_autofree char *name = g_strdup_printf("uart%d", i + 1);
214 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
215 }
216
217 for (i = 0; i < FSL_IMX8MP_NUM_GPTS; i++) {
218 g_autofree char *name = g_strdup_printf("gpt%d", i + 1);
219 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX8MP_GPT);
220 }
221 object_initialize_child(obj, "gpt5-gpt6-irq", &s->gpt5_gpt6_irq,
222 TYPE_OR_IRQ);
223
224 for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) {
225 g_autofree char *name = g_strdup_printf("i2c%d", i + 1);
226 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
227 }
228
229 for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
230 g_autofree char *name = g_strdup_printf("gpio%d", i + 1);
231 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
232 }
233
234 for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
235 g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
236 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
237 }
238
239 for (i = 0; i < FSL_IMX8MP_NUM_USBS; i++) {
240 g_autofree char *name = g_strdup_printf("usb%d", i);
241 object_initialize_child(obj, name, &s->usb[i], TYPE_USB_DWC3);
242 }
243
244 for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
245 g_autofree char *name = g_strdup_printf("spi%d", i + 1);
246 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
247 }
248
249 for (i = 0; i < FSL_IMX8MP_NUM_WDTS; i++) {
250 g_autofree char *name = g_strdup_printf("wdt%d", i);
251 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
252 }
253
254 object_initialize_child(obj, "eth0", &s->enet, TYPE_IMX_ENET);
255
256 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
257 object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
258 TYPE_FSL_IMX8M_PCIE_PHY);
259 }
260
fsl_imx8mp_realize(DeviceState * dev,Error ** errp)261 static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
262 {
263 MachineState *ms = MACHINE(qdev_get_machine());
264 FslImx8mpState *s = FSL_IMX8MP(dev);
265 DeviceState *gicdev = DEVICE(&s->gic);
266 int i;
267
268 if (ms->smp.cpus > FSL_IMX8MP_NUM_CPUS) {
269 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
270 TYPE_FSL_IMX8MP, FSL_IMX8MP_NUM_CPUS, ms->smp.cpus);
271 return;
272 }
273
274 /* CPUs */
275 for (i = 0; i < ms->smp.cpus; i++) {
276 /* On uniprocessor, the CBAR is set to 0 */
277 if (ms->smp.cpus > 1) {
278 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
279 fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST].addr,
280 &error_abort);
281 }
282
283 /*
284 * CNTFID0 base frequency in Hz of system counter
285 */
286 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000,
287 &error_abort);
288
289 if (i) {
290 /*
291 * Secondary CPUs start in powered-down state (and can be
292 * powered up via the SRC system reset controller)
293 */
294 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
295 true, &error_abort);
296 }
297
298 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
299 return;
300 }
301 }
302
303 /* GIC */
304 {
305 SysBusDevice *gicsbd = SYS_BUS_DEVICE(&s->gic);
306 QList *redist_region_count;
307
308 qdev_prop_set_uint32(gicdev, "num-cpu", ms->smp.cpus);
309 qdev_prop_set_uint32(gicdev, "num-irq",
310 FSL_IMX8MP_NUM_IRQS + GIC_INTERNAL);
311 redist_region_count = qlist_new();
312 qlist_append_int(redist_region_count, ms->smp.cpus);
313 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
314 object_property_set_link(OBJECT(&s->gic), "sysmem",
315 OBJECT(get_system_memory()), &error_fatal);
316 if (!sysbus_realize(gicsbd, errp)) {
317 return;
318 }
319 sysbus_mmio_map(gicsbd, 0, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST].addr);
320 sysbus_mmio_map(gicsbd, 1, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_REDIST].addr);
321
322 /*
323 * Wire the outputs from each CPU's generic timer and the GICv3
324 * maintenance interrupt signal to the appropriate GIC PPI inputs, and
325 * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs.
326 */
327 for (i = 0; i < ms->smp.cpus; i++) {
328 DeviceState *cpudev = DEVICE(&s->cpu[i]);
329 int intidbase = FSL_IMX8MP_NUM_IRQS + i * GIC_INTERNAL;
330 qemu_irq irq;
331
332 /*
333 * Mapping from the output timer irq lines from the CPU to the
334 * GIC PPI inputs.
335 */
336 static const int timer_irqs[] = {
337 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
338 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
339 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
340 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
341 };
342
343 for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) {
344 irq = qdev_get_gpio_in(gicdev, intidbase + timer_irqs[j]);
345 qdev_connect_gpio_out(cpudev, j, irq);
346 }
347
348 irq = qdev_get_gpio_in(gicdev, intidbase + ARCH_GIC_MAINT_IRQ);
349 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
350 0, irq);
351
352 irq = qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ);
353 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq);
354
355 sysbus_connect_irq(gicsbd, i,
356 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
357 sysbus_connect_irq(gicsbd, i + ms->smp.cpus,
358 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
359 }
360 }
361
362 /* CCM */
363 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
364 return;
365 }
366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0,
367 fsl_imx8mp_memmap[FSL_IMX8MP_CCM].addr);
368
369 /* Analog */
370 if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) {
371 return;
372 }
373 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0,
374 fsl_imx8mp_memmap[FSL_IMX8MP_ANA_PLL].addr);
375
376 /* UARTs */
377 for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
378 struct {
379 hwaddr addr;
380 unsigned int irq;
381 } serial_table[FSL_IMX8MP_NUM_UARTS] = {
382 { fsl_imx8mp_memmap[FSL_IMX8MP_UART1].addr, FSL_IMX8MP_UART1_IRQ },
383 { fsl_imx8mp_memmap[FSL_IMX8MP_UART2].addr, FSL_IMX8MP_UART2_IRQ },
384 { fsl_imx8mp_memmap[FSL_IMX8MP_UART3].addr, FSL_IMX8MP_UART3_IRQ },
385 { fsl_imx8mp_memmap[FSL_IMX8MP_UART4].addr, FSL_IMX8MP_UART4_IRQ },
386 };
387
388 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
389 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
390 return;
391 }
392
393 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
394 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
395 qdev_get_gpio_in(gicdev, serial_table[i].irq));
396 }
397
398 /* GPTs */
399 object_property_set_int(OBJECT(&s->gpt5_gpt6_irq), "num-lines", 2,
400 &error_abort);
401 if (!qdev_realize(DEVICE(&s->gpt5_gpt6_irq), NULL, errp)) {
402 return;
403 }
404
405 qdev_connect_gpio_out(DEVICE(&s->gpt5_gpt6_irq), 0,
406 qdev_get_gpio_in(gicdev, FSL_IMX8MP_GPT5_GPT6_IRQ));
407
408 for (i = 0; i < FSL_IMX8MP_NUM_GPTS; i++) {
409 hwaddr gpt_addrs[FSL_IMX8MP_NUM_GPTS] = {
410 fsl_imx8mp_memmap[FSL_IMX8MP_GPT1].addr,
411 fsl_imx8mp_memmap[FSL_IMX8MP_GPT2].addr,
412 fsl_imx8mp_memmap[FSL_IMX8MP_GPT3].addr,
413 fsl_imx8mp_memmap[FSL_IMX8MP_GPT4].addr,
414 fsl_imx8mp_memmap[FSL_IMX8MP_GPT5].addr,
415 fsl_imx8mp_memmap[FSL_IMX8MP_GPT6].addr,
416 };
417
418 s->gpt[i].ccm = IMX_CCM(&s->ccm);
419
420 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) {
421 return;
422 }
423
424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_addrs[i]);
425
426 if (i < FSL_IMX8MP_NUM_GPTS - 2) {
427 static const unsigned int gpt_irqs[FSL_IMX8MP_NUM_GPTS - 2] = {
428 FSL_IMX8MP_GPT1_IRQ,
429 FSL_IMX8MP_GPT2_IRQ,
430 FSL_IMX8MP_GPT3_IRQ,
431 FSL_IMX8MP_GPT4_IRQ,
432 };
433
434 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
435 qdev_get_gpio_in(gicdev, gpt_irqs[i]));
436 } else {
437 int irq = i - FSL_IMX8MP_NUM_GPTS + 2;
438
439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
440 qdev_get_gpio_in(DEVICE(&s->gpt5_gpt6_irq), irq));
441 }
442 }
443
444 /* I2Cs */
445 for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) {
446 struct {
447 hwaddr addr;
448 unsigned int irq;
449 } i2c_table[FSL_IMX8MP_NUM_I2CS] = {
450 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C1].addr, FSL_IMX8MP_I2C1_IRQ },
451 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C2].addr, FSL_IMX8MP_I2C2_IRQ },
452 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C3].addr, FSL_IMX8MP_I2C3_IRQ },
453 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C4].addr, FSL_IMX8MP_I2C4_IRQ },
454 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C5].addr, FSL_IMX8MP_I2C5_IRQ },
455 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C6].addr, FSL_IMX8MP_I2C6_IRQ },
456 };
457
458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
459 return;
460 }
461
462 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
463 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
464 qdev_get_gpio_in(gicdev, i2c_table[i].irq));
465 }
466
467 /* GPIOs */
468 for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
469 struct {
470 hwaddr addr;
471 unsigned int irq_low;
472 unsigned int irq_high;
473 } gpio_table[FSL_IMX8MP_NUM_GPIOS] = {
474 {
475 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO1].addr,
476 FSL_IMX8MP_GPIO1_LOW_IRQ,
477 FSL_IMX8MP_GPIO1_HIGH_IRQ
478 },
479 {
480 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO2].addr,
481 FSL_IMX8MP_GPIO2_LOW_IRQ,
482 FSL_IMX8MP_GPIO2_HIGH_IRQ
483 },
484 {
485 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO3].addr,
486 FSL_IMX8MP_GPIO3_LOW_IRQ,
487 FSL_IMX8MP_GPIO3_HIGH_IRQ
488 },
489 {
490 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO4].addr,
491 FSL_IMX8MP_GPIO4_LOW_IRQ,
492 FSL_IMX8MP_GPIO4_HIGH_IRQ
493 },
494 {
495 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO5].addr,
496 FSL_IMX8MP_GPIO5_LOW_IRQ,
497 FSL_IMX8MP_GPIO5_HIGH_IRQ
498 },
499 };
500
501 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
502 &error_abort);
503 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
504 true, &error_abort);
505 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
506 return;
507 }
508
509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
511 qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));
512 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
513 qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));
514 }
515
516 /* USDHCs */
517 for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
518 struct {
519 hwaddr addr;
520 unsigned int irq;
521 } usdhc_table[FSL_IMX8MP_NUM_USDHCS] = {
522 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC1].addr, FSL_IMX8MP_USDHC1_IRQ },
523 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC2].addr, FSL_IMX8MP_USDHC2_IRQ },
524 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC3].addr, FSL_IMX8MP_USDHC3_IRQ },
525 };
526
527 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) {
528 return;
529 }
530
531 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, usdhc_table[i].addr);
532 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
533 qdev_get_gpio_in(gicdev, usdhc_table[i].irq));
534 }
535
536 /* USBs */
537 for (i = 0; i < FSL_IMX8MP_NUM_USBS; i++) {
538 struct {
539 hwaddr addr;
540 unsigned int irq;
541 } usb_table[FSL_IMX8MP_NUM_USBS] = {
542 { fsl_imx8mp_memmap[FSL_IMX8MP_USB1].addr, FSL_IMX8MP_USB1_IRQ },
543 { fsl_imx8mp_memmap[FSL_IMX8MP_USB2].addr, FSL_IMX8MP_USB2_IRQ },
544 };
545
546 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p2", 1);
547 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p3", 1);
548 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
549 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
550 return;
551 }
552 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
553 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
554 qdev_get_gpio_in(gicdev, usb_table[i].irq));
555 }
556
557 /* ECSPIs */
558 for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
559 struct {
560 hwaddr addr;
561 unsigned int irq;
562 } spi_table[FSL_IMX8MP_NUM_ECSPIS] = {
563 { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI1].addr, FSL_IMX8MP_ECSPI1_IRQ },
564 { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI2].addr, FSL_IMX8MP_ECSPI2_IRQ },
565 { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI3].addr, FSL_IMX8MP_ECSPI3_IRQ },
566 };
567
568 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
569 return;
570 }
571
572 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
573 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
574 qdev_get_gpio_in(gicdev, spi_table[i].irq));
575 }
576
577 /* ENET1 */
578 object_property_set_uint(OBJECT(&s->enet), "phy-num", s->phy_num,
579 &error_abort);
580 object_property_set_uint(OBJECT(&s->enet), "tx-ring-num", 3, &error_abort);
581 qemu_configure_nic_device(DEVICE(&s->enet), true, NULL);
582 if (!sysbus_realize(SYS_BUS_DEVICE(&s->enet), errp)) {
583 return;
584 }
585 sysbus_mmio_map(SYS_BUS_DEVICE(&s->enet), 0,
586 fsl_imx8mp_memmap[FSL_IMX8MP_ENET1].addr);
587 sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 0,
588 qdev_get_gpio_in(gicdev, FSL_IMX8MP_ENET1_MAC_IRQ));
589 sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 1,
590 qdev_get_gpio_in(gicdev, FSL_IMX6_ENET1_MAC_1588_IRQ));
591
592 /* SNVS */
593 if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {
594 return;
595 }
596 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,
597 fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr);
598
599 /* Watchdogs */
600 for (i = 0; i < FSL_IMX8MP_NUM_WDTS; i++) {
601 struct {
602 hwaddr addr;
603 unsigned int irq;
604 } wdog_table[FSL_IMX8MP_NUM_WDTS] = {
605 { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG1].addr, FSL_IMX8MP_WDOG1_IRQ },
606 { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG2].addr, FSL_IMX8MP_WDOG2_IRQ },
607 { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG3].addr, FSL_IMX8MP_WDOG3_IRQ },
608 };
609
610 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
611 true, &error_abort);
612 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
613 return;
614 }
615
616 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr);
617 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
618 qdev_get_gpio_in(gicdev, wdog_table[i].irq));
619 }
620
621 /* PCIe */
622 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
623 return;
624 }
625 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0,
626 fsl_imx8mp_memmap[FSL_IMX8MP_PCIE1].addr);
627
628 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0,
629 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTA_IRQ));
630 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1,
631 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTB_IRQ));
632 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2,
633 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTC_IRQ));
634 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3,
635 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTD_IRQ));
636 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4,
637 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_MSI_IRQ));
638
639 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) {
640 return;
641 }
642 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0,
643 fsl_imx8mp_memmap[FSL_IMX8MP_PCIE_PHY1].addr);
644
645 /* On-Chip RAM */
646 if (!memory_region_init_ram(&s->ocram, NULL, "imx8mp.ocram",
647 fsl_imx8mp_memmap[FSL_IMX8MP_OCRAM].size,
648 errp)) {
649 return;
650 }
651 memory_region_add_subregion(get_system_memory(),
652 fsl_imx8mp_memmap[FSL_IMX8MP_OCRAM].addr,
653 &s->ocram);
654
655 /* Unimplemented devices */
656 for (i = 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) {
657 switch (i) {
658 case FSL_IMX8MP_ANA_PLL:
659 case FSL_IMX8MP_CCM:
660 case FSL_IMX8MP_GIC_DIST:
661 case FSL_IMX8MP_GIC_REDIST:
662 case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5:
663 case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3:
664 case FSL_IMX8MP_ENET1:
665 case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6:
666 case FSL_IMX8MP_OCRAM:
667 case FSL_IMX8MP_PCIE1:
668 case FSL_IMX8MP_PCIE_PHY1:
669 case FSL_IMX8MP_RAM:
670 case FSL_IMX8MP_SNVS_HP:
671 case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4:
672 case FSL_IMX8MP_USB1 ... FSL_IMX8MP_USB2:
673 case FSL_IMX8MP_USDHC1 ... FSL_IMX8MP_USDHC3:
674 case FSL_IMX8MP_WDOG1 ... FSL_IMX8MP_WDOG3:
675 /* device implemented and treated above */
676 break;
677
678 default:
679 create_unimplemented_device(fsl_imx8mp_memmap[i].name,
680 fsl_imx8mp_memmap[i].addr,
681 fsl_imx8mp_memmap[i].size);
682 break;
683 }
684 }
685 }
686
687 static const Property fsl_imx8mp_properties[] = {
688 DEFINE_PROP_UINT32("fec1-phy-num", FslImx8mpState, phy_num, 0),
689 DEFINE_PROP_BOOL("fec1-phy-connected", FslImx8mpState, phy_connected, true),
690 };
691
fsl_imx8mp_class_init(ObjectClass * oc,const void * data)692 static void fsl_imx8mp_class_init(ObjectClass *oc, const void *data)
693 {
694 DeviceClass *dc = DEVICE_CLASS(oc);
695
696 device_class_set_props(dc, fsl_imx8mp_properties);
697 dc->realize = fsl_imx8mp_realize;
698
699 dc->desc = "i.MX 8M Plus SoC";
700 }
701
702 static const TypeInfo fsl_imx8mp_types[] = {
703 {
704 .name = TYPE_FSL_IMX8MP,
705 .parent = TYPE_SYS_BUS_DEVICE,
706 .instance_size = sizeof(FslImx8mpState),
707 .instance_init = fsl_imx8mp_init,
708 .class_init = fsl_imx8mp_class_init,
709 },
710 };
711
712 DEFINE_TYPES(fsl_imx8mp_types)
713