1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2025, Intel Corporation. */ 3 4 #ifndef _ICE_TSPLL_H_ 5 #define _ICE_TSPLL_H_ 6 7 /** 8 * struct ice_tspll_params_e82x - E82X TSPLL parameters 9 * @refclk_pre_div: Reference clock pre-divisor 10 * @post_pll_div: Post PLL divisor 11 * @feedback_div: Feedback divisor 12 * @frac_n_div: Fractional divisor 13 * 14 * Clock Generation Unit parameters used to program the PLL based on the 15 * selected TIME_REF/TCXO frequency. 16 */ 17 struct ice_tspll_params_e82x { 18 u8 refclk_pre_div; 19 u8 post_pll_div; 20 u8 feedback_div; 21 u32 frac_n_div; 22 }; 23 24 #define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F 25 #define ICE_TSPLL_NDIVRATIO_E825 5 26 #define ICE_TSPLL_FBDIV_INTGR_E825 256 27 28 int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable); 29 int ice_tspll_init(struct ice_hw *hw); 30 31 #endif /* _ICE_TSPLL_H_ */ 32