1 /* 2 * s390 PCI BUS definitions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #ifndef HW_S390_PCI_BUS_H 15 #define HW_S390_PCI_BUS_H 16 17 #include "hw/pci/pci.h" 18 #include "hw/pci/pci_host.h" 19 #include "hw/s390x/sclp.h" 20 #include "hw/s390x/s390_flic.h" 21 #include "hw/s390x/css.h" 22 #include "hw/s390x/s390-pci-clp.h" 23 #include "qom/object.h" 24 25 #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost" 26 #define TYPE_S390_PCI_BUS "s390-pcibus" 27 #define TYPE_S390_PCI_DEVICE "zpci" 28 #define TYPE_S390_PCI_IOMMU "s390-pci-iommu" 29 #define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region" 30 #define FH_MASK_ENABLE 0x80000000 31 #define FH_MASK_INSTANCE 0x7f000000 32 #define FH_MASK_SHM 0x00ff0000 33 #define FH_MASK_INDEX 0x0000ffff 34 #define FH_SHM_VFIO 0x00010000 35 #define FH_SHM_EMUL 0x00020000 36 #define ZPCI_MAX_FID 0xffffffff 37 #define ZPCI_MAX_UID 0xffff 38 #define UID_UNDEFINED 0 39 #define UID_CHECKING_ENABLED 0x01 40 #define ZPCI_DTSM 0x40 41 42 /* zPCI Function Types */ 43 #define ZPCI_PFT_ISM 5 44 45 OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE) 46 OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS) 47 OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBusDevice, S390_PCI_DEVICE) 48 OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU) 49 50 #define HP_EVENT_TO_CONFIGURED 0x0301 51 #define HP_EVENT_RESERVED_TO_STANDBY 0x0302 52 #define HP_EVENT_DECONFIGURE_REQUEST 0x0303 53 #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304 54 #define HP_EVENT_STANDBY_TO_RESERVED 0x0308 55 56 #define ERR_EVENT_INVALAS 0x1 57 #define ERR_EVENT_OORANGE 0x2 58 #define ERR_EVENT_INVALTF 0x3 59 #define ERR_EVENT_TPROTE 0x4 60 #define ERR_EVENT_APROTE 0x5 61 #define ERR_EVENT_KEYE 0x6 62 #define ERR_EVENT_INVALTE 0x7 63 #define ERR_EVENT_INVALTL 0x8 64 #define ERR_EVENT_TT 0x9 65 #define ERR_EVENT_INVALMS 0xa 66 #define ERR_EVENT_SERR 0xb 67 #define ERR_EVENT_NOMSI 0x10 68 #define ERR_EVENT_INVALBV 0x11 69 #define ERR_EVENT_AIBV 0x12 70 #define ERR_EVENT_AIRERR 0x13 71 #define ERR_EVENT_FMBA 0x2a 72 #define ERR_EVENT_FMBUP 0x2b 73 #define ERR_EVENT_FMBPRO 0x2c 74 #define ERR_EVENT_CCONF 0x30 75 #define ERR_EVENT_SERVAC 0x3a 76 #define ERR_EVENT_PERMERR 0x3b 77 78 #define ERR_EVENT_Q_BIT 0x2 79 #define ERR_EVENT_MVN_OFFSET 16 80 81 #define ZPCI_MSI_VEC_BITS 11 82 #define ZPCI_MSI_VEC_MASK 0x7ff 83 84 #define ZPCI_MSI_ADDR 0xfe00000000000000ULL 85 #define ZPCI_SDMA_ADDR 0x100000000ULL 86 #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL 87 88 #define PAGE_DEFAULT_ACC 0 89 #define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4) 90 91 /* I/O Translation Anchor (IOTA) */ 92 enum ZpciIoatDtype { 93 ZPCI_IOTA_STO = 0, 94 ZPCI_IOTA_RTTO = 1, 95 ZPCI_IOTA_RSTO = 2, 96 ZPCI_IOTA_RFTO = 3, 97 ZPCI_IOTA_PFAA = 4, 98 ZPCI_IOTA_IOPFAA = 5, 99 ZPCI_IOTA_IOPTO = 7 100 }; 101 102 #define ZPCI_IOTA_IOT_ENABLED 0x800ULL 103 #define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2) 104 #define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2) 105 #define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2) 106 #define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2) 107 #define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2) 108 #define ZPCI_IOTA_FS_4K 0 109 #define ZPCI_IOTA_FS_1M 1 110 #define ZPCI_IOTA_FS_2G 2 111 #define ZPCI_KEY (PAGE_DEFAULT_KEY << 5) 112 113 #define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST) 114 #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT) 115 #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS) 116 #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF) 117 #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\ 118 ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G) 119 120 /* I/O Region and segment tables */ 121 #define ZPCI_INDEX_MASK 0x7ffULL 122 123 #define ZPCI_TABLE_TYPE_MASK 0xc 124 #define ZPCI_TABLE_TYPE_RFX 0xc 125 #define ZPCI_TABLE_TYPE_RSX 0x8 126 #define ZPCI_TABLE_TYPE_RTX 0x4 127 #define ZPCI_TABLE_TYPE_SX 0x0 128 129 #define ZPCI_TABLE_LEN_RFX 0x3 130 #define ZPCI_TABLE_LEN_RSX 0x3 131 #define ZPCI_TABLE_LEN_RTX 0x3 132 133 #define ZPCI_TABLE_OFFSET_MASK 0xc0 134 #define ZPCI_TABLE_SIZE 0x4000 135 #define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE 136 #define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long)) 137 #define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE) 138 139 #define ZPCI_TABLE_BITS 11 140 #define ZPCI_PT_BITS 8 141 #define ZPCI_ST_SHIFT (ZPCI_PT_BITS + TARGET_PAGE_BITS) 142 #define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS) 143 144 #define ZPCI_RTE_FLAG_MASK 0x3fffULL 145 #define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK) 146 #define ZPCI_STE_FLAG_MASK 0x7ffULL 147 #define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK) 148 149 #define ZPCI_SFAA_MASK (~((1ULL << 20) - 1)) 150 151 /* I/O Page tables */ 152 #define ZPCI_PTE_VALID_MASK 0x400 153 #define ZPCI_PTE_INVALID 0x400 154 #define ZPCI_PTE_VALID 0x000 155 #define ZPCI_PT_SIZE 0x800 156 #define ZPCI_PT_ALIGN ZPCI_PT_SIZE 157 #define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE) 158 #define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1) 159 160 #define ZPCI_PTE_FLAG_MASK 0xfffULL 161 #define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK) 162 163 /* Shared bits */ 164 #define ZPCI_TABLE_VALID 0x00 165 #define ZPCI_TABLE_INVALID 0x20 166 #define ZPCI_TABLE_PROTECTED 0x200 167 #define ZPCI_TABLE_UNPROTECTED 0x000 168 #define ZPCI_TABLE_FC 0x400 169 170 #define ZPCI_TABLE_VALID_MASK 0x20 171 #define ZPCI_TABLE_PROT_MASK 0x200 172 173 #define ZPCI_ETT_RT 1 174 #define ZPCI_ETT_ST 0 175 #define ZPCI_ETT_PT -1 176 177 /* PCI Function States 178 * 179 * reserved: default; device has just been plugged or is in progress of being 180 * unplugged 181 * standby: device is present but not configured; transition from any 182 * configured state/to this state via sclp configure/deconfigure 183 * 184 * The following states make up the "configured" meta-state: 185 * disabled: device is configured but not enabled; transition between this 186 * state and enabled via clp enable/disable 187 * enabled: device is ready for use; transition to disabled via clp disable; 188 * may enter an error state 189 * blocked: ignore all DMA and interrupts; transition back to enabled or from 190 * error state via mpcifc 191 * error: an error occurred; transition back to enabled via mpcifc 192 * permanent error: an unrecoverable error occurred; transition to standby via 193 * sclp deconfigure 194 */ 195 typedef enum { 196 ZPCI_FS_RESERVED, 197 ZPCI_FS_STANDBY, 198 ZPCI_FS_DISABLED, 199 ZPCI_FS_ENABLED, 200 ZPCI_FS_BLOCKED, 201 ZPCI_FS_ERROR, 202 ZPCI_FS_PERMANENT_ERROR, 203 } ZpciState; 204 205 typedef struct SeiContainer { 206 QTAILQ_ENTRY(SeiContainer) link; 207 uint32_t fid; 208 uint32_t fh; 209 uint8_t cc; 210 uint16_t pec; 211 uint64_t faddr; 212 uint32_t e; 213 } SeiContainer; 214 215 typedef struct PciCcdfErr { 216 uint32_t reserved1; 217 uint32_t fh; 218 uint32_t fid; 219 uint32_t e; 220 uint64_t faddr; 221 uint32_t reserved3; 222 uint16_t reserved4; 223 uint16_t pec; 224 } QEMU_PACKED PciCcdfErr; 225 226 typedef struct PciCcdfAvail { 227 uint32_t reserved1; 228 uint32_t fh; 229 uint32_t fid; 230 uint32_t reserved2; 231 uint32_t reserved3; 232 uint32_t reserved4; 233 uint32_t reserved5; 234 uint16_t reserved6; 235 uint16_t pec; 236 } QEMU_PACKED PciCcdfAvail; 237 238 typedef struct ChscSeiNt2Res { 239 uint16_t length; 240 uint16_t code; 241 uint16_t reserved1; 242 uint8_t reserved2; 243 uint8_t nt; 244 uint8_t flags; 245 uint8_t reserved3; 246 uint8_t reserved4; 247 uint8_t cc; 248 uint32_t reserved5[13]; 249 uint8_t ccdf[4016]; 250 } QEMU_PACKED ChscSeiNt2Res; 251 252 typedef struct S390MsixInfo { 253 uint8_t table_bar; 254 uint8_t pba_bar; 255 uint16_t entries; 256 uint32_t table_offset; 257 uint32_t pba_offset; 258 } S390MsixInfo; 259 260 typedef struct S390IOTLBEntry { 261 uint64_t iova; 262 uint64_t translated_addr; 263 uint64_t len; 264 uint64_t perm; 265 } S390IOTLBEntry; 266 267 typedef struct S390PCIDMACount { 268 int id; 269 int users; 270 uint32_t avail; 271 QTAILQ_ENTRY(S390PCIDMACount) link; 272 } S390PCIDMACount; 273 274 struct S390PCIIOMMU { 275 Object parent_obj; 276 S390PCIBusDevice *pbdev; 277 AddressSpace as; 278 MemoryRegion mr; 279 IOMMUMemoryRegion iommu_mr; 280 MemoryRegion *dm_mr; 281 bool enabled; 282 uint64_t g_iota; 283 uint64_t pba; 284 uint64_t pal; 285 uint64_t max_dma_limit; 286 GHashTable *iotlb; 287 S390PCIDMACount *dma_limit; 288 }; 289 290 typedef struct S390PCIIOMMUTable { 291 uint64_t key; 292 S390PCIIOMMU *iommu[PCI_SLOT_MAX]; 293 } S390PCIIOMMUTable; 294 295 /* Function Measurement Block */ 296 #define DEFAULT_MUI 4000 297 #define UPDATE_U_BIT 0x1ULL 298 #define FMBK_MASK 0xfULL 299 300 typedef struct ZpciFmbFmt0 { 301 uint64_t dma_rbytes; 302 uint64_t dma_wbytes; 303 } ZpciFmbFmt0; 304 305 #define ZPCI_FMB_CNT_LD 0 306 #define ZPCI_FMB_CNT_ST 1 307 #define ZPCI_FMB_CNT_STB 2 308 #define ZPCI_FMB_CNT_RPCIT 3 309 #define ZPCI_FMB_CNT_MAX 4 310 311 #define ZPCI_FMB_FORMAT 0 312 313 typedef struct ZpciFmb { 314 uint32_t format; 315 uint32_t sample; 316 uint64_t last_update; 317 uint64_t counter[ZPCI_FMB_CNT_MAX]; 318 ZpciFmbFmt0 fmt0; 319 } ZpciFmb; 320 QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb"); 321 322 #define ZPCI_DEFAULT_FN_GRP 0xFF 323 #define ZPCI_SIM_GRP_START 0xF0 324 typedef struct S390PCIGroup { 325 ClpRspQueryPciGrp zpci_group; 326 int id; 327 int host_id; 328 QTAILQ_ENTRY(S390PCIGroup) link; 329 } S390PCIGroup; 330 S390PCIGroup *s390_group_create(int id, int host_id); 331 S390PCIGroup *s390_group_find(int id); 332 S390PCIGroup *s390_group_find_host_sim(int host_id); 333 334 struct S390PCIBusDevice { 335 DeviceState qdev; 336 PCIDevice *pdev; 337 ZpciState state; 338 char *target; 339 uint16_t uid; 340 uint32_t idx; 341 uint32_t fh; 342 uint32_t fid; 343 bool fid_defined; 344 uint64_t fmb_addr; 345 ZpciFmb fmb; 346 QEMUTimer *fmb_timer; 347 uint8_t isc; 348 uint16_t noi; 349 uint16_t maxstbl; 350 uint8_t sum; 351 uint8_t pft; 352 S390PCIGroup *pci_group; 353 ClpRspQueryPci zpci_fn; 354 S390MsixInfo msix; 355 AdapterRoutes routes; 356 S390PCIIOMMU *iommu; 357 MemoryRegion msix_notify_mr; 358 IndAddr *summary_ind; 359 IndAddr *indicator; 360 Notifier shutdown_notifier; 361 bool pci_unplug_request_processed; 362 bool unplug_requested; 363 bool interp; 364 bool forwarding_assist; 365 bool aif; 366 bool rtr_avail; 367 QTAILQ_ENTRY(S390PCIBusDevice) link; 368 }; 369 370 struct S390PCIBus { 371 BusState qbus; 372 }; 373 374 struct S390pciState { 375 PCIHostState parent_obj; 376 uint32_t next_idx; 377 int bus_no; 378 S390PCIBus *bus; 379 GHashTable *iommu_table; 380 GHashTable *zpci_table; 381 QTAILQ_HEAD(, SeiContainer) pending_sei; 382 QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs; 383 QTAILQ_HEAD(, S390PCIDMACount) zpci_dma_limit; 384 QTAILQ_HEAD(, S390PCIGroup) zpci_groups; 385 uint8_t next_sim_grp; 386 }; 387 388 S390pciState *s390_get_phb(void); 389 int pci_chsc_sei_nt2_get_event(void *res); 390 int pci_chsc_sei_nt2_have_event(void); 391 void s390_pci_sclp_configure(SCCB *sccb); 392 void s390_pci_sclp_deconfigure(SCCB *sccb); 393 void s390_pci_iommu_enable(S390PCIIOMMU *iommu); 394 void s390_pci_iommu_direct_map_enable(S390PCIIOMMU *iommu); 395 void s390_pci_iommu_disable(S390PCIIOMMU *iommu); 396 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid, 397 uint64_t faddr, uint32_t e); 398 uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr, 399 S390IOTLBEntry *entry); 400 S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx); 401 S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh); 402 S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid); 403 S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s, 404 const char *target); 405 S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s, 406 S390PCIBusDevice *pbdev); 407 void s390_pci_ism_reset(void); 408 409 #endif 410