1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * (1) Redistributions of source code must retain the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer. 12 * 13 * (2) Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * (3)The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _AQ_HW_H_ 36 #define _AQ_HW_H_ 37 38 #include <sys/types.h> 39 #include <sys/cdefs.h> 40 #include <machine/cpufunc.h> 41 #include <sys/endian.h> 42 #include <net/ethernet.h> 43 #include "aq_common.h" 44 45 #define AQ_WRITE_REG(hw, reg, value) writel(((hw)->hw_addr + (reg)), htole32(value)) 46 47 #define AQ_READ_REG(hw, reg) le32toh(readl((hw)->hw_addr + reg)) 48 49 50 #define AQ_WRITE_REG_BIT(hw, reg, msk, shift, value) do { \ 51 if (msk ^ ~0) { \ 52 uint32_t reg_old, reg_new = 0U; \ 53 reg_old = AQ_READ_REG(hw, reg); \ 54 reg_new = (reg_old & (~msk)) | (value << shift); \ 55 if (reg_old != reg_new) \ 56 AQ_WRITE_REG(hw, reg, reg_new); \ 57 } else { \ 58 AQ_WRITE_REG(hw, reg, value); \ 59 } \ 60 } while(0) 61 62 63 #define AQ_READ_REG_BIT(a, reg, msk, shift) ( \ 64 ((AQ_READ_REG(a, reg) & msk) >> shift)) 65 66 #define AQ_HW_FLUSH() { (void)AQ_READ_REG(hw, 0x10); } 67 68 #define aq_hw_write_reg_bit AQ_WRITE_REG_BIT 69 70 #define aq_hw_write_reg AQ_WRITE_REG 71 72 /* Statistics */ 73 struct aq_hw_stats { 74 uint64_t crcerrs; 75 }; 76 77 struct aq_hw_stats_s { 78 uint32_t uprc; 79 uint32_t mprc; 80 uint32_t bprc; 81 uint32_t erpt; 82 uint32_t uptc; 83 uint32_t mptc; 84 uint32_t bptc; 85 uint32_t erpr; 86 uint32_t mbtc; 87 uint32_t bbtc; 88 uint32_t mbrc; 89 uint32_t bbrc; 90 uint32_t ubrc; 91 uint32_t ubtc; 92 uint32_t ptc; 93 uint32_t prc; 94 uint32_t dpc; 95 uint32_t cprc; 96 } __attribute__((__packed__)); 97 98 union ip_addr { 99 struct { 100 uint8_t addr[16]; 101 } v6; 102 struct { 103 uint8_t padding[12]; 104 uint8_t addr[4]; 105 } v4; 106 } __attribute__((__packed__)); 107 108 struct aq_hw_fw_mbox { 109 uint32_t version; 110 uint32_t transaction_id; 111 int error; 112 struct aq_hw_stats_s stats; 113 } __attribute__((__packed__)); 114 115 typedef struct aq_hw_fw_version { 116 union { 117 struct { 118 uint16_t build_number; 119 uint8_t minor_version; 120 uint8_t major_version; 121 }; 122 uint32_t raw; 123 }; 124 } aq_hw_fw_version; 125 126 enum aq_hw_irq_type { 127 aq_irq_invalid = 0, 128 aq_irq_legacy = 1, 129 aq_irq_msi = 2, 130 aq_irq_msix = 3, 131 }; 132 133 struct aq_hw_fc_info { 134 bool fc_rx; 135 bool fc_tx; 136 }; 137 138 struct aq_hw { 139 void *aq_dev; 140 uint8_t *hw_addr; 141 uint32_t regs_size; 142 143 uint8_t mac_addr[ETHER_ADDR_LEN]; 144 145 enum aq_hw_irq_type irq_type; 146 147 struct aq_hw_fc_info fc; 148 uint16_t link_rate; 149 150 uint16_t device_id; 151 uint16_t subsystem_vendor_id; 152 uint16_t subsystem_device_id; 153 uint16_t vendor_id; 154 uint8_t revision_id; 155 156 /* Interrupt Moderation value. */ 157 int itr; 158 159 /* Firmware-related stuff. */ 160 aq_hw_fw_version fw_version; 161 const struct aq_firmware_ops* fw_ops; 162 bool rbl_enabled; 163 bool fast_start_enabled; 164 bool flash_present; 165 uint32_t chip_features; 166 uint64_t fw_caps; 167 168 bool lro_enabled; 169 170 uint32_t mbox_addr; 171 struct aq_hw_fw_mbox mbox; 172 }; 173 174 #define aq_hw_s aq_hw 175 176 #define AQ_HW_MAC 0U 177 #define AQ_HW_MAC_MIN 1U 178 #define AQ_HW_MAC_MAX 33U 179 180 #define HW_ATL_B0_MIN_RXD 32U 181 #define HW_ATL_B0_MIN_TXD 32U 182 #define HW_ATL_B0_MAX_RXD 4096U /* in fact up to 8184, but closest to power of 2 */ 183 #define HW_ATL_B0_MAX_TXD 4096U /* in fact up to 8184, but closest to power of 2 */ 184 185 #define HW_ATL_B0_MTU_JUMBO 16352U 186 #define HW_ATL_B0_TSO_SIZE (160*1024) 187 #define HW_ATL_B0_RINGS_MAX 32U 188 #define HW_ATL_B0_LRO_RXD_MAX 16U 189 190 #define AQ_HW_FW_SM_RAM 0x2U 191 192 #define AQ_HW_MPI_STATE_MSK 0x00FFU 193 #define AQ_HW_MPI_STATE_SHIFT 0U 194 195 #define AQ_HW_MPI_CONTROL_ADR 0x0368U 196 #define AQ_HW_MPI_STATE_ADR 0x036CU 197 198 #define HW_ATL_RSS_INDIRECTION_TABLE_MAX 64U 199 #define HW_ATL_RSS_HASHKEY_SIZE 40U 200 201 /* PCI core control register */ 202 #define AQ_HW_PCI_REG_CONTROL_6_ADR 0x1014U 203 /* tx dma total request limit */ 204 #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20U 205 206 #define AQ_HW_TXBUF_MAX 160U 207 #define AQ_HW_RXBUF_MAX 320U 208 209 #define L2_FILTER_ACTION_DISCARD (0x0) 210 #define L2_FILTER_ACTION_HOST (0x1) 211 212 #define AQ_HW_UCP_0X370_REG (0x370) 213 #define AQ_HW_CHIP_MIPS 0x00000001U 214 #define AQ_HW_CHIP_TPO2 0x00000002U 215 #define AQ_HW_CHIP_RPF2 0x00000004U 216 #define AQ_HW_CHIP_MPI_AQ 0x00000010U 217 #define AQ_HW_CHIP_REVISION_A0 0x01000000U 218 #define AQ_HW_CHIP_REVISION_B0 0x02000000U 219 #define AQ_HW_CHIP_REVISION_B1 0x04000000U 220 #define IS_CHIP_FEATURE(HW, _F_) (AQ_HW_CHIP_##_F_ & \ 221 (HW)->chip_features) 222 223 #define AQ_HW_FW_VER_EXPECTED 0x01050006U 224 225 #define AQ_RX_RSS_TYPE_NONE 0x0 226 #define AQ_RX_RSS_TYPE_IPV4 0x2 227 #define AQ_RX_RSS_TYPE_IPV6 0x3 228 #define AQ_RX_RSS_TYPE_IPV4_TCP 0x4 229 #define AQ_RX_RSS_TYPE_IPV6_TCP 0x5 230 #define AQ_RX_RSS_TYPE_IPV4_UDP 0x6 231 #define AQ_RX_RSS_TYPE_IPV6_UDP 0x7 232 233 enum hw_atl_rx_action_with_traffic { 234 HW_ATL_RX_DISCARD, 235 HW_ATL_RX_HOST, 236 HW_ATL_RX_MNGMNT, 237 HW_ATL_RX_HOST_AND_MNGMNT, 238 HW_ATL_RX_WOL 239 }; 240 241 struct aq_rx_filter_vlan { 242 uint8_t enable; 243 uint8_t location; 244 uint16_t vlan_id; 245 uint8_t queue; 246 }; 247 248 #define AQ_HW_VLAN_MAX_FILTERS 16U 249 #define AQ_HW_ETYPE_MAX_FILTERS 16U 250 251 struct aq_rx_filter_l2 { 252 uint8_t enable; 253 int8_t queue; 254 uint8_t location; 255 uint8_t user_priority_en; 256 uint8_t user_priority; 257 uint16_t ethertype; 258 }; 259 260 enum hw_atl_rx_ctrl_registers_l2 { 261 HW_ATL_RX_ENABLE_UNICAST_MNGNT_QUEUE_L2 = BIT(19), 262 HW_ATL_RX_ENABLE_UNICAST_FLTR_L2 = BIT(31) 263 }; 264 265 struct aq_rx_filter_l3l4 { 266 uint32_t cmd; 267 uint8_t location; 268 uint32_t ip_dst[4]; 269 uint32_t ip_src[4]; 270 uint16_t p_dst; 271 uint16_t p_src; 272 bool is_ipv6; 273 }; 274 275 enum hw_atl_rx_protocol_value_l3l4 { 276 HW_ATL_RX_TCP, 277 HW_ATL_RX_UDP, 278 HW_ATL_RX_SCTP, 279 HW_ATL_RX_ICMP 280 }; 281 282 enum hw_atl_rx_ctrl_registers_l3l4 { 283 HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22), 284 HW_ATL_RX_ENABLE_QUEUE_L3L4 = BIT(23), 285 HW_ATL_RX_ENABLE_ARP_FLTR_L3 = BIT(24), 286 HW_ATL_RX_ENABLE_CMP_PROT_L4 = BIT(25), 287 HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 = BIT(26), 288 HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4 = BIT(27), 289 HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 = BIT(28), 290 HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3 = BIT(29), 291 HW_ATL_RX_ENABLE_L3_IPv6 = BIT(30), 292 HW_ATL_RX_ENABLE_FLTR_L3L4 = BIT(31) 293 }; 294 295 #define HW_ATL_RX_BOFFSET_PROT_FL3L4 0U 296 #define HW_ATL_RX_BOFFSET_QUEUE_FL3L4 8U 297 #define HW_ATL_RX_BOFFSET_ACTION_FL3F4 16U 298 299 #define HW_ATL_RX_CNT_REG_ADDR_IPV6 4U 300 301 #define HW_ATL_GET_REG_LOCATION_FL3L4(location) \ 302 ((location) - AQ_RX_FIRST_LOC_FL3L4) 303 304 enum aq_hw_fw_mpi_state_e { 305 MPI_DEINIT = 0, 306 MPI_RESET = 1, 307 MPI_INIT = 2, 308 MPI_POWER = 4, 309 }; 310 311 int aq_hw_get_mac_permanent(struct aq_hw *hw, uint8_t *mac); 312 313 int aq_hw_mac_addr_set(struct aq_hw *hw, uint8_t *mac_addr, uint8_t index); 314 315 /* link speed in mbps. "0" - no link detected */ 316 int aq_hw_get_link_state(struct aq_hw *hw, uint32_t *link_speed, 317 struct aq_hw_fc_info *fc_neg); 318 319 int aq_hw_set_link_speed(struct aq_hw *hw, uint32_t speed); 320 321 int aq_hw_fw_downld_dwords(struct aq_hw *hw, uint32_t a, uint32_t *p, uint32_t cnt); 322 323 int aq_hw_reset(struct aq_hw *hw); 324 325 int aq_hw_mpi_create(struct aq_hw *hw); 326 327 int aq_hw_mpi_read_stats(struct aq_hw *hw, struct aq_hw_fw_mbox *pmbox); 328 329 int aq_hw_init(struct aq_hw *hw, uint8_t *mac_addr, uint8_t adm_irq, bool msix); 330 331 int aq_hw_start(struct aq_hw *hw); 332 333 int aq_hw_interrupt_moderation_set(struct aq_hw *hw); 334 335 int aq_hw_get_fw_version(struct aq_hw *hw, uint32_t *fw_version); 336 337 int aq_hw_deinit(struct aq_hw *hw); 338 339 int aq_hw_ver_match(const aq_hw_fw_version* ver_expected, 340 const aq_hw_fw_version* ver_actual); 341 342 void aq_hw_set_promisc(struct aq_hw_s *self, bool l2_promisc, bool vlan_promisc, 343 bool mc_promisc); 344 345 int aq_hw_set_power(struct aq_hw *hw, unsigned int power_state); 346 347 int aq_hw_err_from_flags(struct aq_hw *hw); 348 349 int hw_atl_b0_hw_vlan_promisc_set(struct aq_hw_s *self, bool promisc); 350 351 int hw_atl_b0_hw_vlan_set(struct aq_hw_s *self, 352 struct aq_rx_filter_vlan *aq_vlans); 353 354 int aq_hw_rss_hash_set(struct aq_hw_s *self, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE]); 355 int aq_hw_rss_hash_get(struct aq_hw_s *self, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE]); 356 int aq_hw_rss_set(struct aq_hw_s *self, uint8_t rss_table[HW_ATL_RSS_INDIRECTION_TABLE_MAX]); 357 int aq_hw_udp_rss_enable(struct aq_hw_s *self, bool enable); 358 359 #endif // _AQ_HW_H_ 360