1 /*
2 * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef HEXAGON_MACROS_H
19 #define HEXAGON_MACROS_H
20
21 #include "cpu.h"
22 #include "hex_regs.h"
23 #include "reg_fields.h"
24 #include "accel/tcg/getpc.h"
25
26 #define GET_FIELD(FIELD, REGIN) \
27 fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
28 reg_field_info[FIELD].offset)
29
30 #ifdef QEMU_GENERATE
31 #define GET_USR_FIELD(FIELD, DST) \
32 tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
33 reg_field_info[FIELD].offset, \
34 reg_field_info[FIELD].width)
35
36 #define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int)
37 #define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv)
38 #define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64)
39 #else
40 #define GET_USR_FIELD(FIELD) \
41 fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
42 reg_field_info[FIELD].offset)
43
44 #define SET_USR_FIELD(FIELD, VAL) \
45 do { \
46 if (pkt_need_commit) { \
47 fINSERT_BITS(env->new_value_usr, \
48 reg_field_info[FIELD].width, \
49 reg_field_info[FIELD].offset, (VAL)); \
50 } else { \
51 fINSERT_BITS(env->gpr[HEX_REG_USR], \
52 reg_field_info[FIELD].width, \
53 reg_field_info[FIELD].offset, (VAL)); \
54 } \
55 } while (0)
56 #endif
57
58 #ifdef QEMU_GENERATE
59 /*
60 * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
61 *
62 * Slot 1 store with slot 0 load
63 * A slot 1 store operation with a slot 0 load operation can appear in a packet.
64 * The packet attribute :mem_noshuf inhibits the instruction reordering that
65 * would otherwise be done by the assembler. For example:
66 * {
67 * memw(R5) = R2 // slot 1 store
68 * R3 = memh(R6) // slot 0 load
69 * }:mem_noshuf
70 * Unlike most packetized operations, these memory operations are not executed
71 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
72 * effectively executes first, followed by the load instruction in Slot 0. If
73 * the addresses of the two operations are overlapping, the load will receive
74 * the newly stored data. This feature is supported in processor versions
75 * V65 or greater.
76 *
77 *
78 * For qemu, we look for a load in slot 0 when there is a store in slot 1
79 * in the same packet. When we see this, we call a helper that probes the
80 * load to make sure it doesn't fault. Then, we process the store ahead of
81 * the actual load.
82
83 */
84 #define CHECK_NOSHUF(VA, SIZE) \
85 do { \
86 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
87 probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
88 process_store(ctx, 1); \
89 } \
90 } while (0)
91
92 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
93 do { \
94 TCGLabel *noshuf_label = gen_new_label(); \
95 tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
96 GET_EA; \
97 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
98 probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
99 } \
100 gen_set_label(noshuf_label); \
101 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
102 process_store(ctx, 1); \
103 } \
104 } while (0)
105
106 #define MEM_LOAD1s(DST, VA) \
107 do { \
108 CHECK_NOSHUF(VA, 1); \
109 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
110 } while (0)
111 #define MEM_LOAD1u(DST, VA) \
112 do { \
113 CHECK_NOSHUF(VA, 1); \
114 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
115 } while (0)
116 #define MEM_LOAD2s(DST, VA) \
117 do { \
118 CHECK_NOSHUF(VA, 2); \
119 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_SW); \
120 } while (0)
121 #define MEM_LOAD2u(DST, VA) \
122 do { \
123 CHECK_NOSHUF(VA, 2); \
124 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_UW); \
125 } while (0)
126 #define MEM_LOAD4s(DST, VA) \
127 do { \
128 CHECK_NOSHUF(VA, 4); \
129 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_SL); \
130 } while (0)
131 #define MEM_LOAD4u(DST, VA) \
132 do { \
133 CHECK_NOSHUF(VA, 4); \
134 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_UL); \
135 } while (0)
136 #define MEM_LOAD8u(DST, VA) \
137 do { \
138 CHECK_NOSHUF(VA, 8); \
139 tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_LE | MO_UQ); \
140 } while (0)
141
142 #define MEM_STORE1_FUNC(X) \
143 __builtin_choose_expr(TYPE_INT(X), \
144 gen_store1i, \
145 __builtin_choose_expr(TYPE_TCGV(X), \
146 gen_store1, (void)0))
147 #define MEM_STORE1(VA, DATA, SLOT) \
148 MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
149
150 #define MEM_STORE2_FUNC(X) \
151 __builtin_choose_expr(TYPE_INT(X), \
152 gen_store2i, \
153 __builtin_choose_expr(TYPE_TCGV(X), \
154 gen_store2, (void)0))
155 #define MEM_STORE2(VA, DATA, SLOT) \
156 MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
157
158 #define MEM_STORE4_FUNC(X) \
159 __builtin_choose_expr(TYPE_INT(X), \
160 gen_store4i, \
161 __builtin_choose_expr(TYPE_TCGV(X), \
162 gen_store4, (void)0))
163 #define MEM_STORE4(VA, DATA, SLOT) \
164 MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
165
166 #define MEM_STORE8_FUNC(X) \
167 __builtin_choose_expr(TYPE_INT(X), \
168 gen_store8i, \
169 __builtin_choose_expr(TYPE_TCGV_I64(X), \
170 gen_store8, (void)0))
171 #define MEM_STORE8(VA, DATA, SLOT) \
172 MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
173 #else
174 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
175 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
176 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
177 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
178 #endif
179
180 #ifdef QEMU_GENERATE
gen_cancel(uint32_t slot)181 static inline void gen_cancel(uint32_t slot)
182 {
183 tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
184 }
185
186 #define CANCEL gen_cancel(slot);
187 #else
188 #define CANCEL do { } while (0)
189 #endif
190
191 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
192
193 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
194
195 #define fMAX(A, B) (((A) > (B)) ? (A) : (B))
196
197 #define fMIN(A, B) (((A) < (B)) ? (A) : (B))
198
199 #define fABS(A) (((A) < 0) ? (-(A)) : (A))
200 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
201 REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
202 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
203 ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
204 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
205 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
206 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
207 (((HIBIT) - (LOWBIT) + 1) ? \
208 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
209 0LL)
210 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
211 do { \
212 int width = ((HIBIT) - (LOWBIT) + 1); \
213 INREG = (width >= 0 ? \
214 deposit64((INREG), (LOWBIT), width, (INVAL)) : \
215 INREG); \
216 } while (0)
217
218 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
219
220 #ifdef QEMU_GENERATE
221 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
222 #else
223 #define fLSBOLD(VAL) ((VAL) & 1)
224 #endif
225
226 #ifdef QEMU_GENERATE
227 #define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1)
228 #else
229 #define fLSBNEW(PVAL) ((PVAL) & 1)
230 #endif
231
232 #ifdef QEMU_GENERATE
233 #define fLSBOLDNOT(VAL) \
234 do { \
235 tcg_gen_andi_tl(LSB, (VAL), 1); \
236 tcg_gen_xori_tl(LSB, LSB, 1); \
237 } while (0)
238 #define fLSBNEWNOT(PNUM) \
239 do { \
240 tcg_gen_andi_tl(LSB, (PNUM), 1); \
241 tcg_gen_xori_tl(LSB, LSB, 1); \
242 } while (0)
243 #else
244 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
245 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
246 #define fLSBNEW0NOT (!fLSBNEW0)
247 #define fLSBNEW1NOT (!fLSBNEW1)
248 #endif
249
250 #define fNEWREG(VAL) ((int32_t)(VAL))
251
252 #define fNEWREG_ST(VAL) (VAL)
253
254 #define fVSATUVALN(N, VAL) \
255 ({ \
256 (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \
257 })
258 #define fSATUVALN(N, VAL) \
259 ({ \
260 fSET_OVERFLOW(); \
261 ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
262 })
263 #define fSATVALN(N, VAL) \
264 ({ \
265 fSET_OVERFLOW(); \
266 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
267 })
268 #define fVSATVALN(N, VAL) \
269 ({ \
270 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
271 })
272 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
273 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
274 #define fSATN(N, VAL) \
275 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
276 #define fVSATN(N, VAL) \
277 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL))
278 #define fADDSAT64(DST, A, B) \
279 do { \
280 uint64_t __a = fCAST8u(A); \
281 uint64_t __b = fCAST8u(B); \
282 uint64_t __sum = __a + __b; \
283 uint64_t __xor = __a ^ __b; \
284 const uint64_t __mask = 0x8000000000000000ULL; \
285 if (__xor & __mask) { \
286 DST = __sum; \
287 } \
288 else if ((__a ^ __sum) & __mask) { \
289 if (__sum & __mask) { \
290 DST = 0x7FFFFFFFFFFFFFFFLL; \
291 fSET_OVERFLOW(); \
292 } else { \
293 DST = 0x8000000000000000LL; \
294 fSET_OVERFLOW(); \
295 } \
296 } else { \
297 DST = __sum; \
298 } \
299 } while (0)
300 #define fVSATUN(N, VAL) \
301 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
302 #define fSATUN(N, VAL) \
303 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
304 #define fSATH(VAL) (fSATN(16, VAL))
305 #define fSATUH(VAL) (fSATUN(16, VAL))
306 #define fVSATH(VAL) (fVSATN(16, VAL))
307 #define fVSATUH(VAL) (fVSATUN(16, VAL))
308 #define fSATUB(VAL) (fSATUN(8, VAL))
309 #define fSATB(VAL) (fSATN(8, VAL))
310 #define fVSATUB(VAL) (fVSATUN(8, VAL))
311 #define fVSATB(VAL) (fVSATN(8, VAL))
312 #define fIMMEXT(IMM) (IMM = IMM)
313 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
314
315 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
316
317 #ifdef QEMU_GENERATE
gen_read_ireg(TCGv result,TCGv val,int shift)318 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
319 {
320 /*
321 * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
322 *
323 * The "I" value from a modifier register is divided into two pieces
324 * LSB bits 23:17
325 * MSB bits 31:28
326 * The value is signed
327 *
328 * At the end we shift the result according to the shift argument
329 */
330 TCGv msb = tcg_temp_new();
331 TCGv lsb = tcg_temp_new();
332
333 tcg_gen_extract_tl(lsb, val, 17, 7);
334 tcg_gen_sari_tl(msb, val, 21);
335 tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
336
337 tcg_gen_shli_tl(result, result, shift);
338 return result;
339 }
340 #endif
341
342 #define fREAD_LR() (env->gpr[HEX_REG_LR])
343
344 #define fREAD_SP() (SP)
345 #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
346 #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
347 #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
348 #define fREAD_SA1 (env->gpr[HEX_REG_SA1])
349 #define fREAD_FP() (env->gpr[HEX_REG_FP])
350 #ifdef FIXME
351 /* Figure out how to get insn->extension_valid to helper */
352 #define fREAD_GP() \
353 (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP])
354 #else
355 #define fREAD_GP() (env->gpr[HEX_REG_GP])
356 #endif
357 #define fREAD_PC() (PC)
358
359 #define fREAD_P0() (P0)
360
361 #define fCHECK_PCALIGN(A)
362
363 #define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A)
364
365 #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC)
366 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
367 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
368
369 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
370 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
371 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
372 #define fPART1(WORK) if (part1) { WORK; return; }
373 #define fCAST4u(A) ((uint32_t)(A))
374 #define fCAST4s(A) ((int32_t)(A))
375 #define fCAST8u(A) ((uint64_t)(A))
376 #define fCAST8s(A) ((int64_t)(A))
377 #define fCAST2_2s(A) ((int16_t)(A))
378 #define fCAST2_2u(A) ((uint16_t)(A))
379 #define fCAST4_4s(A) ((int32_t)(A))
380 #define fCAST4_4u(A) ((uint32_t)(A))
381 #define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
382 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
383 #define fCAST8_8s(A) ((int64_t)(A))
384 #define fCAST8_8u(A) ((uint64_t)(A))
385 #define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
386 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
387 #define fZE8_16(A) ((int16_t)((uint8_t)(A)))
388 #define fSE8_16(A) ((int16_t)((int8_t)(A)))
389 #define fSE16_32(A) ((int32_t)((int16_t)(A)))
390 #define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
391 #define fSE32_64(A) ((int64_t)((int32_t)(A)))
392 #define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
393 #define fSE8_32(A) ((int32_t)((int8_t)(A)))
394 #define fZE8_32(A) ((int32_t)((uint8_t)(A)))
395 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
396 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
397 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
398 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
399 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
400 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
401 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
402 #define fMPY16US(A, B) fMPY16SU(B, A)
403 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
404 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
405 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
406 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
407 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
408 #define fROUND(A) (A + 0x8000)
409 #define fCLIP(DST, SRC, U) \
410 do { \
411 int32_t maxv = (1 << U) - 1; \
412 int32_t minv = -(1 << U); \
413 DST = fMIN(maxv, fMAX(SRC, minv)); \
414 } while (0)
415 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
416 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
417 #define fCRNDN(A, N) (conv_round(A, N))
418 #define fADD128(A, B) (int128_add(A, B))
419 #define fSUB128(A, B) (int128_sub(A, B))
420 #define fSHIFTR128(A, B) (int128_rshift(A, B))
421 #define fSHIFTL128(A, B) (int128_lshift(A, B))
422 #define fAND128(A, B) (int128_and(A, B))
423 #define fCAST8S_16S(A) (int128_exts64(A))
424 #define fCAST16S_8S(A) (int128_getlo(A))
425
426 #ifdef QEMU_GENERATE
427 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
428 #define fEA_RRs(REG, REG2, SCALE) \
429 do { \
430 TCGv tmp = tcg_temp_new(); \
431 tcg_gen_shli_tl(tmp, REG2, SCALE); \
432 tcg_gen_add_tl(EA, REG, tmp); \
433 } while (0)
434 #define fEA_IRs(IMM, REG, SCALE) \
435 do { \
436 tcg_gen_shli_tl(EA, REG, SCALE); \
437 tcg_gen_addi_tl(EA, EA, IMM); \
438 } while (0)
439 #else
440 #define fEA_RI(REG, IMM) \
441 do { \
442 EA = REG + IMM; \
443 } while (0)
444 #define fEA_RRs(REG, REG2, SCALE) \
445 do { \
446 EA = REG + (REG2 << SCALE); \
447 } while (0)
448 #define fEA_IRs(IMM, REG, SCALE) \
449 do { \
450 EA = IMM + (REG << SCALE); \
451 } while (0)
452 #endif
453
454 #ifdef QEMU_GENERATE
455 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
456 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
457 #define fEA_BREVR(REG) gen_helper_fbrev(EA, REG)
458 #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM)
459 #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL)
460 #define fPM_CIRI(REG, IMM, MVAL) \
461 do { \
462 TCGv tcgv_siV = tcg_constant_tl(siV); \
463 gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, CS); \
464 } while (0)
465 #else
466 #define fEA_IMM(IMM) do { EA = (IMM); } while (0)
467 #define fEA_REG(REG) do { EA = (REG); } while (0)
468 #define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0)
469 #define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0)
470 #define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0)
471 #endif
472 #define fSCALE(N, A) (((int64_t)(A)) << N)
473 #define fVSATW(A) fVSATN(32, ((long long)A))
474 #define fSATW(A) fSATN(32, ((long long)A))
475 #define fVSAT(A) fVSATN(32, (A))
476 #define fSAT(A) fSATN(32, (A))
477 #define fSAT_ORIG_SHL(A, ORIG_REG) \
478 ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
479 ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
480 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
481 : fSAT(A)))
482 #define fPASS(A) A
483 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
484 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
485 : (fCAST##REGSTYPE(SRC) << (SHAMT)))
486 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
487 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
488 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
489 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
490 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
491 (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
492 : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
493 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
494 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
495 : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
496 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
497 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
498 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
499 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
500 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
501 (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
502 << ((-(SHAMT)) - 1)) << 1, (SRC)) \
503 : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
504 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
505 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
506 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
507 #define fROTL(SRC, SHAMT, REGSTYPE) \
508 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
509 ((fCAST##REGSTYPE##u(SRC) >> \
510 ((sizeof(SRC) * 8) - (SHAMT))))))
511 #define fROTR(SRC, SHAMT, REGSTYPE) \
512 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
513 ((fCAST##REGSTYPE##u(SRC) << \
514 ((sizeof(SRC) * 8) - (SHAMT))))))
515 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \
516 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
517
518 #ifdef QEMU_GENERATE
519 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
520 #else
521 #define MEM_LOAD1 cpu_ldub_data_ra
522 #define MEM_LOAD2 cpu_lduw_data_ra
523 #define MEM_LOAD4 cpu_ldl_data_ra
524 #define MEM_LOAD8 cpu_ldq_data_ra
525
526 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
527 do { \
528 check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
529 DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
530 } while (0)
531 #endif
532
533 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
534
535 #define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY])
536 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
537 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
538
539 #ifdef CONFIG_USER_ONLY
540 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
541 #else
542 /* System mode not implemented yet */
543 #define fFRAMECHECK(ADDR, EA) g_assert_not_reached();
544 #endif
545
546 #ifdef QEMU_GENERATE
547 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
548 gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
549 #endif
550
551 #ifdef QEMU_GENERATE
552 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
553 #else
554 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
555 #endif
556
557 #ifdef QEMU_GENERATE
558 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
559 gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
560 #endif
561
562 #ifdef QEMU_GENERATE
563 #define GETBYTE_FUNC(X) \
564 __builtin_choose_expr(TYPE_TCGV(X), \
565 gen_get_byte, \
566 __builtin_choose_expr(TYPE_TCGV_I64(X), \
567 gen_get_byte_i64, (void)0))
568 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
569 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
570 #else
571 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
572 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
573 #endif
574
575 #define fSETBYTE(N, DST, VAL) \
576 do { \
577 DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
578 (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
579 } while (0)
580
581 #ifdef QEMU_GENERATE
582 #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true)
583 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
584 #else
585 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
586 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
587 #endif
588 #define fSETHALF(N, DST, VAL) \
589 do { \
590 DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
591 (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
592 } while (0)
593 #define fSETHALFw fSETHALF
594 #define fSETHALFd fSETHALF
595
596 #define fGETWORD(N, SRC) \
597 ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
598 #define fGETUWORD(N, SRC) \
599 ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
600
601 #define fSETWORD(N, DST, VAL) \
602 do { \
603 DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
604 (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
605 } while (0)
606
607 #define fSETBIT(N, DST, VAL) \
608 do { \
609 DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
610 } while (0)
611
612 #define fGETBIT(N, SRC) (((SRC) >> N) & 1)
613 #define fSETBITS(HI, LO, DST, VAL) \
614 do { \
615 int j; \
616 for (j = LO; j <= HI; j++) { \
617 fSETBIT(j, DST, VAL); \
618 } \
619 } while (0)
620 #define fCOUNTONES_2(VAL) ctpop16(VAL)
621 #define fCOUNTONES_4(VAL) ctpop32(VAL)
622 #define fCOUNTONES_8(VAL) ctpop64(VAL)
623 #define fBREV_8(VAL) revbit64(VAL)
624 #define fBREV_4(VAL) revbit32(VAL)
625 #define fCL1_8(VAL) clo64(VAL)
626 #define fCL1_4(VAL) clo32(VAL)
627 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16)
628 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
629 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
630 #define fHIDE(A) A
631 #define fCONSTLL(A) A##LL
632 #define fECHO(A) (A)
633
634 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
635 #define fPAUSE(IMM)
636
637 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
638 ((VAL) << reg_field_info[FIELD].offset)
639 #define fGET_REG_FIELD_MASK(FIELD) \
640 (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
641 #define fREAD_REG_FIELD(REG, FIELD) \
642 fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
643 reg_field_info[FIELD].width, \
644 reg_field_info[FIELD].offset)
645
646 #ifdef QEMU_GENERATE
647 #define fDCZEROA(REG) \
648 do { \
649 ctx->dczero_addr = tcg_temp_new(); \
650 tcg_gen_mov_tl(ctx->dczero_addr, (REG)); \
651 } while (0)
652 #endif
653
654 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
655 STRBITNUM) /* Nothing */
656
657
658 #endif
659