1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_GUC_TYPES_H_ 7 #define _XE_GUC_TYPES_H_ 8 9 #include <linux/idr.h> 10 #include <linux/xarray.h> 11 12 #include "regs/xe_reg_defs.h" 13 #include "xe_guc_ads_types.h" 14 #include "xe_guc_buf_types.h" 15 #include "xe_guc_ct_types.h" 16 #include "xe_guc_engine_activity_types.h" 17 #include "xe_guc_fwif.h" 18 #include "xe_guc_log_types.h" 19 #include "xe_guc_pc_types.h" 20 #include "xe_guc_relay_types.h" 21 #include "xe_uc_fw_types.h" 22 23 /** 24 * struct xe_guc_db_mgr - GuC Doorbells Manager. 25 * 26 * Note: GuC Doorbells Manager is relying on &xe_guc::submission_state.lock 27 * to protect its members. 28 */ 29 struct xe_guc_db_mgr { 30 /** @count: number of doorbells to manage */ 31 unsigned int count; 32 /** @bitmap: bitmap to track allocated doorbells */ 33 unsigned long *bitmap; 34 }; 35 36 /** 37 * struct xe_guc_id_mgr - GuC context ID Manager. 38 * 39 * Note: GuC context ID Manager is relying on &xe_guc::submission_state.lock 40 * to protect its members. 41 */ 42 struct xe_guc_id_mgr { 43 /** @bitmap: bitmap to track allocated IDs */ 44 unsigned long *bitmap; 45 /** @total: total number of IDs being managed */ 46 unsigned int total; 47 /** @used: number of IDs currently in use */ 48 unsigned int used; 49 }; 50 51 /** 52 * struct xe_guc - Graphic micro controller 53 */ 54 struct xe_guc { 55 /** @fw: Generic uC firmware management */ 56 struct xe_uc_fw fw; 57 /** @log: GuC log */ 58 struct xe_guc_log log; 59 /** @ads: GuC ads */ 60 struct xe_guc_ads ads; 61 /** @ct: GuC ct */ 62 struct xe_guc_ct ct; 63 /** @buf: GuC Buffer Cache manager */ 64 struct xe_guc_buf_cache buf; 65 /** @capture: the error-state-capture module's data and objects */ 66 struct xe_guc_state_capture *capture; 67 /** @pc: GuC Power Conservation */ 68 struct xe_guc_pc pc; 69 /** @dbm: GuC Doorbell Manager */ 70 struct xe_guc_db_mgr dbm; 71 72 /** @g2g: GuC to GuC communication state */ 73 struct { 74 /** @g2g.bo: Storage for GuC to GuC communication channels */ 75 struct xe_bo *bo; 76 /** @g2g.owned: Is the BO owned by this GT or just mapped in */ 77 bool owned; 78 } g2g; 79 80 /** @submission_state: GuC submission state */ 81 struct { 82 /** @submission_state.idm: GuC context ID Manager */ 83 struct xe_guc_id_mgr idm; 84 /** @submission_state.exec_queue_lookup: Lookup an xe_engine from guc_id */ 85 struct xarray exec_queue_lookup; 86 /** @submission_state.stopped: submissions are stopped */ 87 atomic_t stopped; 88 /** 89 * @submission_state.reset_blocked: reset attempts are blocked; 90 * blocking reset in order to delay it may be required if running 91 * an operation which is sensitive to resets. 92 */ 93 atomic_t reset_blocked; 94 /** @submission_state.lock: protects submission state */ 95 struct mutex lock; 96 /** @submission_state.enabled: submission is enabled */ 97 bool enabled; 98 /** 99 * @submission_state.initialized: mark when submission state is 100 * even initialized - before that not even the lock is valid 101 */ 102 bool initialized; 103 /** @submission_state.fini_wq: submit fini wait queue */ 104 wait_queue_head_t fini_wq; 105 } submission_state; 106 107 /** @hwconfig: Hardware config state */ 108 struct { 109 /** @hwconfig.bo: buffer object of the hardware config */ 110 struct xe_bo *bo; 111 /** @hwconfig.size: size of the hardware config */ 112 u32 size; 113 } hwconfig; 114 115 /** @relay: GuC Relay Communication used in SR-IOV */ 116 struct xe_guc_relay relay; 117 118 /** @engine_activity: Device specific engine activity */ 119 struct xe_guc_engine_activity engine_activity; 120 121 /** 122 * @notify_reg: Register which is written to notify GuC of H2G messages 123 */ 124 struct xe_reg notify_reg; 125 /** @params: Control params for fw initialization */ 126 u32 params[GUC_CTL_MAX_DWORDS]; 127 }; 128 129 #endif 130