1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/delay.h>
22
23 #include <asm/byteorder.h>
24
25 #include "8250.h"
26
27 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
28 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
29 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
30 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
31 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
32 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
33 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
34
35 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
36 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
37 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
38 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
39 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
40 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
41 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
42
43 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
44 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
45
46 #define PCI_SUBDEVICE_ID_USR_2980 0x0128
47 #define PCI_SUBDEVICE_ID_USR_2981 0x0129
48
49 #define UART_EXAR_INT0 0x80
50 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
51 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
52 #define UART_EXAR_DVID 0x8d /* Device identification */
53
54 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
55 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
56 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
57 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
58 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
59 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
60 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
61
62 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
63 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
64
65 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
66 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
67 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
68 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
69 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
70 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
71 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
72 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
73 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
74 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
75 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
76 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
77
78 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
79
80 #define UART_EXAR_DLD 0x02 /* Divisor Fractional */
81 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
82
83 /*
84 * IOT2040 MPIO wiring semantics:
85 *
86 * MPIO Port Function
87 * ---- ---- --------
88 * 0 2 Mode bit 0
89 * 1 2 Mode bit 1
90 * 2 2 Terminate bus
91 * 3 - <reserved>
92 * 4 3 Mode bit 0
93 * 5 3 Mode bit 1
94 * 6 3 Terminate bus
95 * 7 - <reserved>
96 * 8 2 Enable
97 * 9 3 Enable
98 * 10 - Red LED
99 * 11..15 - <unused>
100 */
101
102 /* IOT2040 MPIOs 0..7 */
103 #define IOT2040_UART_MODE_RS232 0x01
104 #define IOT2040_UART_MODE_RS485 0x02
105 #define IOT2040_UART_MODE_RS422 0x03
106 #define IOT2040_UART_TERMINATE_BUS 0x04
107
108 #define IOT2040_UART1_MASK 0x0f
109 #define IOT2040_UART2_SHIFT 4
110
111 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
112 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
113
114 /* IOT2040 MPIOs 8..15 */
115 #define IOT2040_UARTS_ENABLE 0x03
116 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
117
118 struct exar8250;
119
120 struct exar8250_platform {
121 int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
122 struct serial_rs485 *rs485);
123 const struct serial_rs485 *rs485_supported;
124 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
125 void (*unregister_gpio)(struct uart_8250_port *);
126 };
127
128 /**
129 * struct exar8250_board - board information
130 * @num_ports: number of serial ports
131 * @reg_shift: describes UART register mapping in PCI memory
132 * @setup: quirk run at ->probe() stage
133 * @exit: quirk run at ->remove() stage
134 */
135 struct exar8250_board {
136 unsigned int num_ports;
137 unsigned int reg_shift;
138 int (*setup)(struct exar8250 *, struct pci_dev *,
139 struct uart_8250_port *, int);
140 void (*exit)(struct pci_dev *pcidev);
141 };
142
143 struct exar8250 {
144 unsigned int nr;
145 struct exar8250_board *board;
146 void __iomem *virt;
147 int line[];
148 };
149
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)150 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
151 {
152 /*
153 * Exar UARTs have a SLEEP register that enables or disables each UART
154 * to enter sleep mode separately. On the XR17V35x the register
155 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
156 * the UART channel may only write to the corresponding bit.
157 */
158 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
159 }
160
161 /*
162 * XR17V35x UARTs have an extra fractional divisor register (DLD)
163 * Calculate divisor with extra 4-bit fractional portion
164 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)165 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
166 unsigned int *frac)
167 {
168 unsigned int quot_16;
169
170 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
171 *frac = quot_16 & 0x0f;
172
173 return quot_16 >> 4;
174 }
175
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)176 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
177 unsigned int quot, unsigned int quot_frac)
178 {
179 serial8250_do_set_divisor(p, baud, quot, quot_frac);
180
181 /* Preserve bits not related to baudrate; DLD[7:4]. */
182 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
183 serial_port_out(p, 0x2, quot_frac);
184 }
185
xr17v35x_startup(struct uart_port * port)186 static int xr17v35x_startup(struct uart_port *port)
187 {
188 /*
189 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
190 * MCR [7:5] and MSR [7:0]
191 */
192 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
193
194 /*
195 * Make sure all interrups are masked until initialization is
196 * complete and the FIFOs are cleared
197 *
198 * Synchronize UART_IER access against the console.
199 */
200 uart_port_lock_irq(port);
201 serial_port_out(port, UART_IER, 0);
202 uart_port_unlock_irq(port);
203
204 return serial8250_do_startup(port);
205 }
206
exar_shutdown(struct uart_port * port)207 static void exar_shutdown(struct uart_port *port)
208 {
209 bool tx_complete = false;
210 struct uart_8250_port *up = up_to_u8250p(port);
211 struct circ_buf *xmit = &port->state->xmit;
212 int i = 0;
213 u16 lsr;
214
215 do {
216 lsr = serial_in(up, UART_LSR);
217 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
218 tx_complete = true;
219 else
220 tx_complete = false;
221 usleep_range(1000, 1100);
222 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
223
224 serial8250_do_shutdown(port);
225 }
226
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)227 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
228 int idx, unsigned int offset,
229 struct uart_8250_port *port)
230 {
231 const struct exar8250_board *board = priv->board;
232 unsigned int bar = 0;
233 unsigned char status;
234
235 port->port.iotype = UPIO_MEM;
236 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
237 port->port.membase = priv->virt + offset;
238 port->port.regshift = board->reg_shift;
239
240 /*
241 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
242 * with when DLAB is set which will cause the device to incorrectly match
243 * and assign port type to PORT_16650. The EFR for this UART is found
244 * at offset 0x09. Instead check the Deice ID (DVID) register
245 * for a 2, 4 or 8 port UART.
246 */
247 status = readb(port->port.membase + UART_EXAR_DVID);
248 if (status == 0x82 || status == 0x84 || status == 0x88) {
249 port->port.type = PORT_XR17V35X;
250
251 port->port.get_divisor = xr17v35x_get_divisor;
252 port->port.set_divisor = xr17v35x_set_divisor;
253
254 port->port.startup = xr17v35x_startup;
255 } else {
256 port->port.type = PORT_XR17D15X;
257 }
258
259 port->port.pm = exar_pm;
260 port->port.shutdown = exar_shutdown;
261
262 return 0;
263 }
264
265 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)266 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
267 struct uart_8250_port *port, int idx)
268 {
269 unsigned int offset = idx * 0x200;
270 unsigned int baud = 1843200;
271 u8 __iomem *p;
272 int err;
273
274 port->port.uartclk = baud * 16;
275
276 err = default_setup(priv, pcidev, idx, offset, port);
277 if (err)
278 return err;
279
280 p = port->port.membase;
281
282 writeb(0x00, p + UART_EXAR_8XMODE);
283 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
284 writeb(32, p + UART_EXAR_TXTRG);
285 writeb(32, p + UART_EXAR_RXTRG);
286
287 /*
288 * Setup Multipurpose Input/Output pins.
289 */
290 if (idx == 0) {
291 switch (pcidev->device) {
292 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
293 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
294 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
295 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
296 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
297 break;
298 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
299 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
300 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
301 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
302 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
303 break;
304 }
305 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
306 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
307 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
308 }
309
310 return 0;
311 }
312
313 static int
pci_connect_tech_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)314 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
315 struct uart_8250_port *port, int idx)
316 {
317 unsigned int offset = idx * 0x200;
318 unsigned int baud = 1843200;
319
320 port->port.uartclk = baud * 16;
321 return default_setup(priv, pcidev, idx, offset, port);
322 }
323
324 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)325 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
326 struct uart_8250_port *port, int idx)
327 {
328 unsigned int offset = idx * 0x200;
329 unsigned int baud = 921600;
330
331 port->port.uartclk = baud * 16;
332 return default_setup(priv, pcidev, idx, offset, port);
333 }
334
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)335 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
336 {
337 /*
338 * The Commtech adapters required the MPIOs to be driven low. The Exar
339 * devices will export them as GPIOs, so we pre-configure them safely
340 * as inputs.
341 */
342
343 u8 dir = 0x00;
344
345 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
346 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
347 // Configure GPIO as inputs for Commtech adapters
348 dir = 0xff;
349 } else {
350 // Configure GPIO as outputs for SeaLevel adapters
351 dir = 0x00;
352 }
353
354 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
355 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
356 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
357 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
358 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
359 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
360 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
361 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
362 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
363 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
364 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
365 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
366 }
367
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct software_node * node)368 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
369 const struct software_node *node)
370 {
371 struct platform_device *pdev;
372
373 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
374 if (!pdev)
375 return NULL;
376
377 pdev->dev.parent = &pcidev->dev;
378 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
379
380 if (device_add_software_node(&pdev->dev, node) < 0 ||
381 platform_device_add(pdev) < 0) {
382 platform_device_put(pdev);
383 return NULL;
384 }
385
386 return pdev;
387 }
388
__xr17v35x_unregister_gpio(struct platform_device * pdev)389 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
390 {
391 device_remove_software_node(&pdev->dev);
392 platform_device_unregister(pdev);
393 }
394
395 static const struct property_entry exar_gpio_properties[] = {
396 PROPERTY_ENTRY_U32("exar,first-pin", 0),
397 PROPERTY_ENTRY_U32("ngpios", 16),
398 { }
399 };
400
401 static const struct software_node exar_gpio_node = {
402 .properties = exar_gpio_properties,
403 };
404
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)405 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
406 {
407 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
408 port->port.private_data =
409 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
410
411 return 0;
412 }
413
xr17v35x_unregister_gpio(struct uart_8250_port * port)414 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
415 {
416 if (!port->port.private_data)
417 return;
418
419 __xr17v35x_unregister_gpio(port->port.private_data);
420 port->port.private_data = NULL;
421 }
422
generic_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)423 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
424 struct serial_rs485 *rs485)
425 {
426 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
427 u8 __iomem *p = port->membase;
428 u8 value;
429
430 value = readb(p + UART_EXAR_FCTR);
431 if (is_rs485)
432 value |= UART_FCTR_EXAR_485;
433 else
434 value &= ~UART_FCTR_EXAR_485;
435
436 writeb(value, p + UART_EXAR_FCTR);
437
438 if (is_rs485)
439 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
440
441 return 0;
442 }
443
sealevel_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)444 static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios,
445 struct serial_rs485 *rs485)
446 {
447 u8 __iomem *p = port->membase;
448 u8 old_lcr;
449 u8 efr;
450 u8 dld;
451 int ret;
452
453 ret = generic_rs485_config(port, termios, rs485);
454 if (ret)
455 return ret;
456
457 if (rs485->flags & SER_RS485_ENABLED) {
458 old_lcr = readb(p + UART_LCR);
459
460 /* Set EFR[4]=1 to enable enhanced feature registers */
461 efr = readb(p + UART_XR_EFR);
462 efr |= UART_EFR_ECB;
463 writeb(efr, p + UART_XR_EFR);
464
465 /* Set MCR to use DTR as Auto-RS485 Enable signal */
466 writeb(UART_MCR_OUT1, p + UART_MCR);
467
468 /* Set LCR[7]=1 to enable access to DLD register */
469 writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR);
470
471 /* Set DLD[7]=1 for inverted RS485 Enable logic */
472 dld = readb(p + UART_EXAR_DLD);
473 dld |= UART_EXAR_DLD_485_POLARITY;
474 writeb(dld, p + UART_EXAR_DLD);
475
476 writeb(old_lcr, p + UART_LCR);
477 }
478
479 return 0;
480 }
481
482 static const struct serial_rs485 generic_rs485_supported = {
483 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
484 };
485
486 static const struct exar8250_platform exar8250_default_platform = {
487 .register_gpio = xr17v35x_register_gpio,
488 .unregister_gpio = xr17v35x_unregister_gpio,
489 .rs485_config = generic_rs485_config,
490 .rs485_supported = &generic_rs485_supported,
491 };
492
iot2040_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)493 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
494 struct serial_rs485 *rs485)
495 {
496 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
497 u8 __iomem *p = port->membase;
498 u8 mask = IOT2040_UART1_MASK;
499 u8 mode, value;
500
501 if (is_rs485) {
502 if (rs485->flags & SER_RS485_RX_DURING_TX)
503 mode = IOT2040_UART_MODE_RS422;
504 else
505 mode = IOT2040_UART_MODE_RS485;
506
507 if (rs485->flags & SER_RS485_TERMINATE_BUS)
508 mode |= IOT2040_UART_TERMINATE_BUS;
509 } else {
510 mode = IOT2040_UART_MODE_RS232;
511 }
512
513 if (port->line == 3) {
514 mask <<= IOT2040_UART2_SHIFT;
515 mode <<= IOT2040_UART2_SHIFT;
516 }
517
518 value = readb(p + UART_EXAR_MPIOLVL_7_0);
519 value &= ~mask;
520 value |= mode;
521 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
522
523 return generic_rs485_config(port, termios, rs485);
524 }
525
526 static const struct serial_rs485 iot2040_rs485_supported = {
527 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
528 SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
529 };
530
531 static const struct property_entry iot2040_gpio_properties[] = {
532 PROPERTY_ENTRY_U32("exar,first-pin", 10),
533 PROPERTY_ENTRY_U32("ngpios", 1),
534 { }
535 };
536
537 static const struct software_node iot2040_gpio_node = {
538 .properties = iot2040_gpio_properties,
539 };
540
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)541 static int iot2040_register_gpio(struct pci_dev *pcidev,
542 struct uart_8250_port *port)
543 {
544 u8 __iomem *p = port->port.membase;
545
546 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
547 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
548 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
549 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
550
551 port->port.private_data =
552 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
553
554 return 0;
555 }
556
557 static const struct exar8250_platform iot2040_platform = {
558 .rs485_config = iot2040_rs485_config,
559 .rs485_supported = &iot2040_rs485_supported,
560 .register_gpio = iot2040_register_gpio,
561 .unregister_gpio = xr17v35x_unregister_gpio,
562 };
563
564 /*
565 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
566 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
567 * board name after the device was found.
568 */
569 static const struct dmi_system_id exar_platforms[] = {
570 {
571 .matches = {
572 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
573 },
574 .driver_data = (void *)&iot2040_platform,
575 },
576 {}
577 };
578
exar_get_platform(void)579 static const struct exar8250_platform *exar_get_platform(void)
580 {
581 const struct dmi_system_id *dmi_match;
582
583 dmi_match = dmi_first_match(exar_platforms);
584 if (dmi_match)
585 return dmi_match->driver_data;
586
587 return &exar8250_default_platform;
588 }
589
590 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)591 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
592 struct uart_8250_port *port, int idx)
593 {
594 const struct exar8250_platform *platform = exar_get_platform();
595 unsigned int offset = idx * 0x400;
596 unsigned int baud = 7812500;
597 u8 __iomem *p;
598 int ret;
599
600 port->port.uartclk = baud * 16;
601 port->port.rs485_config = platform->rs485_config;
602 port->port.rs485_supported = *(platform->rs485_supported);
603
604 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL)
605 port->port.rs485_config = sealevel_rs485_config;
606
607 /*
608 * Setup the UART clock for the devices on expansion slot to
609 * half the clock speed of the main chip (which is 125MHz)
610 */
611 if (idx >= 8)
612 port->port.uartclk /= 2;
613
614 ret = default_setup(priv, pcidev, idx, offset, port);
615 if (ret)
616 return ret;
617
618 p = port->port.membase;
619
620 writeb(0x00, p + UART_EXAR_8XMODE);
621 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
622 writeb(128, p + UART_EXAR_TXTRG);
623 writeb(128, p + UART_EXAR_RXTRG);
624
625 if (idx == 0) {
626 /* Setup Multipurpose Input/Output pins. */
627 setup_gpio(pcidev, p);
628
629 ret = platform->register_gpio(pcidev, port);
630 }
631
632 return ret;
633 }
634
pci_xr17v35x_exit(struct pci_dev * pcidev)635 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
636 {
637 const struct exar8250_platform *platform = exar_get_platform();
638 struct exar8250 *priv = pci_get_drvdata(pcidev);
639 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
640
641 platform->unregister_gpio(port);
642 }
643
exar_misc_clear(struct exar8250 * priv)644 static inline void exar_misc_clear(struct exar8250 *priv)
645 {
646 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
647 readb(priv->virt + UART_EXAR_INT0);
648
649 /* Clear INT0 for Expansion Interface slave ports, too */
650 if (priv->board->num_ports > 8)
651 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
652 }
653
654 /*
655 * These Exar UARTs have an extra interrupt indicator that could fire for a
656 * few interrupts that are not presented/cleared through IIR. One of which is
657 * a wakeup interrupt when coming out of sleep. These interrupts are only
658 * cleared by reading global INT0 or INT1 registers as interrupts are
659 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
660 * channel's address space, but for the sake of bus efficiency we register a
661 * dedicated handler at the PCI device level to handle them.
662 */
exar_misc_handler(int irq,void * data)663 static irqreturn_t exar_misc_handler(int irq, void *data)
664 {
665 exar_misc_clear(data);
666
667 return IRQ_HANDLED;
668 }
669
670 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)671 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
672 {
673 unsigned int nr_ports, i, bar = 0, maxnr;
674 struct exar8250_board *board;
675 struct uart_8250_port uart;
676 struct exar8250 *priv;
677 int rc;
678
679 board = (struct exar8250_board *)ent->driver_data;
680 if (!board)
681 return -EINVAL;
682
683 rc = pcim_enable_device(pcidev);
684 if (rc)
685 return rc;
686
687 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
688
689 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
690 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
691 else if (board->num_ports)
692 nr_ports = board->num_ports;
693 else
694 nr_ports = pcidev->device & 0x0f;
695
696 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
697 if (!priv)
698 return -ENOMEM;
699
700 priv->board = board;
701 priv->virt = pcim_iomap(pcidev, bar, 0);
702 if (!priv->virt)
703 return -ENOMEM;
704
705 pci_set_master(pcidev);
706
707 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
708 if (rc < 0)
709 return rc;
710
711 memset(&uart, 0, sizeof(uart));
712 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
713 uart.port.irq = pci_irq_vector(pcidev, 0);
714 uart.port.dev = &pcidev->dev;
715
716 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
717 IRQF_SHARED, "exar_uart", priv);
718 if (rc)
719 return rc;
720
721 /* Clear interrupts */
722 exar_misc_clear(priv);
723
724 for (i = 0; i < nr_ports && i < maxnr; i++) {
725 rc = board->setup(priv, pcidev, &uart, i);
726 if (rc) {
727 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
728 break;
729 }
730
731 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
732 uart.port.iobase, uart.port.irq, uart.port.iotype);
733
734 priv->line[i] = serial8250_register_8250_port(&uart);
735 if (priv->line[i] < 0) {
736 dev_err(&pcidev->dev,
737 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
738 uart.port.iobase, uart.port.irq,
739 uart.port.iotype, priv->line[i]);
740 break;
741 }
742 }
743 priv->nr = i;
744 pci_set_drvdata(pcidev, priv);
745 return 0;
746 }
747
exar_pci_remove(struct pci_dev * pcidev)748 static void exar_pci_remove(struct pci_dev *pcidev)
749 {
750 struct exar8250 *priv = pci_get_drvdata(pcidev);
751 unsigned int i;
752
753 for (i = 0; i < priv->nr; i++)
754 serial8250_unregister_port(priv->line[i]);
755
756 if (priv->board->exit)
757 priv->board->exit(pcidev);
758 }
759
exar_suspend(struct device * dev)760 static int __maybe_unused exar_suspend(struct device *dev)
761 {
762 struct pci_dev *pcidev = to_pci_dev(dev);
763 struct exar8250 *priv = pci_get_drvdata(pcidev);
764 unsigned int i;
765
766 for (i = 0; i < priv->nr; i++)
767 if (priv->line[i] >= 0)
768 serial8250_suspend_port(priv->line[i]);
769
770 /* Ensure that every init quirk is properly torn down */
771 if (priv->board->exit)
772 priv->board->exit(pcidev);
773
774 return 0;
775 }
776
exar_resume(struct device * dev)777 static int __maybe_unused exar_resume(struct device *dev)
778 {
779 struct exar8250 *priv = dev_get_drvdata(dev);
780 unsigned int i;
781
782 exar_misc_clear(priv);
783
784 for (i = 0; i < priv->nr; i++)
785 if (priv->line[i] >= 0)
786 serial8250_resume_port(priv->line[i]);
787
788 return 0;
789 }
790
791 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
792
793 static const struct exar8250_board pbn_fastcom335_2 = {
794 .num_ports = 2,
795 .setup = pci_fastcom335_setup,
796 };
797
798 static const struct exar8250_board pbn_fastcom335_4 = {
799 .num_ports = 4,
800 .setup = pci_fastcom335_setup,
801 };
802
803 static const struct exar8250_board pbn_fastcom335_8 = {
804 .num_ports = 8,
805 .setup = pci_fastcom335_setup,
806 };
807
808 static const struct exar8250_board pbn_connect = {
809 .setup = pci_connect_tech_setup,
810 };
811
812 static const struct exar8250_board pbn_exar_ibm_saturn = {
813 .num_ports = 1,
814 .setup = pci_xr17c154_setup,
815 };
816
817 static const struct exar8250_board pbn_exar_XR17C15x = {
818 .setup = pci_xr17c154_setup,
819 };
820
821 static const struct exar8250_board pbn_exar_XR17V35x = {
822 .setup = pci_xr17v35x_setup,
823 .exit = pci_xr17v35x_exit,
824 };
825
826 static const struct exar8250_board pbn_fastcom35x_2 = {
827 .num_ports = 2,
828 .setup = pci_xr17v35x_setup,
829 .exit = pci_xr17v35x_exit,
830 };
831
832 static const struct exar8250_board pbn_fastcom35x_4 = {
833 .num_ports = 4,
834 .setup = pci_xr17v35x_setup,
835 .exit = pci_xr17v35x_exit,
836 };
837
838 static const struct exar8250_board pbn_fastcom35x_8 = {
839 .num_ports = 8,
840 .setup = pci_xr17v35x_setup,
841 .exit = pci_xr17v35x_exit,
842 };
843
844 static const struct exar8250_board pbn_exar_XR17V4358 = {
845 .num_ports = 12,
846 .setup = pci_xr17v35x_setup,
847 .exit = pci_xr17v35x_exit,
848 };
849
850 static const struct exar8250_board pbn_exar_XR17V8358 = {
851 .num_ports = 16,
852 .setup = pci_xr17v35x_setup,
853 .exit = pci_xr17v35x_exit,
854 };
855
856 #define CONNECT_DEVICE(devid, sdevid, bd) { \
857 PCI_DEVICE_SUB( \
858 PCI_VENDOR_ID_EXAR, \
859 PCI_DEVICE_ID_EXAR_##devid, \
860 PCI_SUBVENDOR_ID_CONNECT_TECH, \
861 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
862 (kernel_ulong_t)&bd \
863 }
864
865 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
866
867 #define IBM_DEVICE(devid, sdevid, bd) { \
868 PCI_DEVICE_SUB( \
869 PCI_VENDOR_ID_EXAR, \
870 PCI_DEVICE_ID_EXAR_##devid, \
871 PCI_VENDOR_ID_IBM, \
872 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
873 (kernel_ulong_t)&bd \
874 }
875
876 #define USR_DEVICE(devid, sdevid, bd) { \
877 PCI_DEVICE_SUB( \
878 PCI_VENDOR_ID_USR, \
879 PCI_DEVICE_ID_EXAR_##devid, \
880 PCI_VENDOR_ID_EXAR, \
881 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
882 (kernel_ulong_t)&bd \
883 }
884
885 static const struct pci_device_id exar_pci_tbl[] = {
886 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
887 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
888 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
889 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
890 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
891 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
892 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
893
894 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
895 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
896 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
897 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
898 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
899 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
900 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
901 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
902 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
903 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
904 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
905 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
906
907 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
908
909 /* USRobotics USR298x-OEM PCI Modems */
910 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
911 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
912
913 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
914 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
915 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
916 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
917
918 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
919 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
920 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
921 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
922 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
923 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
924 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
925 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
926 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
927
928 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
929 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
930 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
931 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
932 { 0, }
933 };
934 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
935
936 static struct pci_driver exar_pci_driver = {
937 .name = "exar_serial",
938 .probe = exar_pci_probe,
939 .remove = exar_pci_remove,
940 .driver = {
941 .pm = &exar_pci_pm,
942 },
943 .id_table = exar_pci_tbl,
944 };
945 module_pci_driver(exar_pci_driver);
946
947 MODULE_LICENSE("GPL");
948 MODULE_DESCRIPTION("Exar Serial Driver");
949 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
950