1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mediatek,mt8188-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/mailbox/mediatek,mt8188-gce.h> 12#include <dt-bindings/memory/mediatek,mt8188-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 15#include <dt-bindings/power/mediatek,mt8188-power.h> 16#include <dt-bindings/reset/mt8188-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8188"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 dsc0 = &dsc0; 30 ethdr0 = ðdr0; 31 gce0 = &gce0; 32 gce1 = &gce1; 33 merge0 = &merge0; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 mutex0 = &mutex0; 40 mutex1 = &mutex1; 41 padding0 = &padding0; 42 padding1 = &padding1; 43 padding2 = &padding2; 44 padding3 = &padding3; 45 padding4 = &padding4; 46 padding5 = &padding5; 47 padding6 = &padding6; 48 padding7 = &padding7; 49 vdo1-rdma0 = &vdo1_rdma0; 50 vdo1-rdma1 = &vdo1_rdma1; 51 vdo1-rdma2 = &vdo1_rdma2; 52 vdo1-rdma3 = &vdo1_rdma3; 53 vdo1-rdma4 = &vdo1_rdma4; 54 vdo1-rdma5 = &vdo1_rdma5; 55 vdo1-rdma6 = &vdo1_rdma6; 56 vdo1-rdma7 = &vdo1_rdma7; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 reg = <0x000>; 67 enable-method = "psci"; 68 clock-frequency = <2000000000>; 69 capacity-dmips-mhz = <282>; 70 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 71 i-cache-size = <32768>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <128>; 74 d-cache-size = <32768>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&l2_0>; 78 performance-domains = <&performance 0>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a55"; 85 reg = <0x100>; 86 enable-method = "psci"; 87 clock-frequency = <2000000000>; 88 capacity-dmips-mhz = <282>; 89 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 90 i-cache-size = <32768>; 91 i-cache-line-size = <64>; 92 i-cache-sets = <128>; 93 d-cache-size = <32768>; 94 d-cache-line-size = <64>; 95 d-cache-sets = <128>; 96 next-level-cache = <&l2_0>; 97 performance-domains = <&performance 0>; 98 #cooling-cells = <2>; 99 }; 100 101 cpu2: cpu@200 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x200>; 105 enable-method = "psci"; 106 clock-frequency = <2000000000>; 107 capacity-dmips-mhz = <282>; 108 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 109 i-cache-size = <32768>; 110 i-cache-line-size = <64>; 111 i-cache-sets = <128>; 112 d-cache-size = <32768>; 113 d-cache-line-size = <64>; 114 d-cache-sets = <128>; 115 next-level-cache = <&l2_0>; 116 performance-domains = <&performance 0>; 117 #cooling-cells = <2>; 118 }; 119 120 cpu3: cpu@300 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a55"; 123 reg = <0x300>; 124 enable-method = "psci"; 125 clock-frequency = <2000000000>; 126 capacity-dmips-mhz = <282>; 127 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 128 i-cache-size = <32768>; 129 i-cache-line-size = <64>; 130 i-cache-sets = <128>; 131 d-cache-size = <32768>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <128>; 134 next-level-cache = <&l2_0>; 135 performance-domains = <&performance 0>; 136 #cooling-cells = <2>; 137 }; 138 139 cpu4: cpu@400 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a55"; 142 reg = <0x400>; 143 enable-method = "psci"; 144 clock-frequency = <2000000000>; 145 capacity-dmips-mhz = <282>; 146 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 147 i-cache-size = <32768>; 148 i-cache-line-size = <64>; 149 i-cache-sets = <128>; 150 d-cache-size = <32768>; 151 d-cache-line-size = <64>; 152 d-cache-sets = <128>; 153 next-level-cache = <&l2_0>; 154 performance-domains = <&performance 0>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu5: cpu@500 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a55"; 161 reg = <0x500>; 162 enable-method = "psci"; 163 clock-frequency = <2000000000>; 164 capacity-dmips-mhz = <282>; 165 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 166 i-cache-size = <32768>; 167 i-cache-line-size = <64>; 168 i-cache-sets = <128>; 169 d-cache-size = <32768>; 170 d-cache-line-size = <64>; 171 d-cache-sets = <128>; 172 next-level-cache = <&l2_0>; 173 performance-domains = <&performance 0>; 174 #cooling-cells = <2>; 175 }; 176 177 cpu6: cpu@600 { 178 device_type = "cpu"; 179 compatible = "arm,cortex-a78"; 180 reg = <0x600>; 181 enable-method = "psci"; 182 clock-frequency = <2600000000>; 183 capacity-dmips-mhz = <1024>; 184 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 185 i-cache-size = <65536>; 186 i-cache-line-size = <64>; 187 i-cache-sets = <256>; 188 d-cache-size = <65536>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <256>; 191 next-level-cache = <&l2_1>; 192 performance-domains = <&performance 1>; 193 #cooling-cells = <2>; 194 }; 195 196 cpu7: cpu@700 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a78"; 199 reg = <0x700>; 200 enable-method = "psci"; 201 clock-frequency = <2600000000>; 202 capacity-dmips-mhz = <1024>; 203 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 204 i-cache-size = <65536>; 205 i-cache-line-size = <64>; 206 i-cache-sets = <256>; 207 d-cache-size = <65536>; 208 d-cache-line-size = <64>; 209 d-cache-sets = <256>; 210 next-level-cache = <&l2_1>; 211 performance-domains = <&performance 1>; 212 #cooling-cells = <2>; 213 }; 214 215 cpu-map { 216 cluster0 { 217 core0 { 218 cpu = <&cpu0>; 219 }; 220 221 core1 { 222 cpu = <&cpu1>; 223 }; 224 225 core2 { 226 cpu = <&cpu2>; 227 }; 228 229 core3 { 230 cpu = <&cpu3>; 231 }; 232 233 core4 { 234 cpu = <&cpu4>; 235 }; 236 237 core5 { 238 cpu = <&cpu5>; 239 }; 240 241 core6 { 242 cpu = <&cpu6>; 243 }; 244 245 core7 { 246 cpu = <&cpu7>; 247 }; 248 }; 249 }; 250 251 idle-states { 252 entry-method = "psci"; 253 254 cpu_off_l: cpu-off-l { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x00010000>; 257 local-timer-stop; 258 entry-latency-us = <50>; 259 exit-latency-us = <95>; 260 min-residency-us = <580>; 261 }; 262 263 cpu_off_b: cpu-off-b { 264 compatible = "arm,idle-state"; 265 arm,psci-suspend-param = <0x00010000>; 266 local-timer-stop; 267 entry-latency-us = <45>; 268 exit-latency-us = <140>; 269 min-residency-us = <740>; 270 }; 271 272 cluster_off_l: cluster-off-l { 273 compatible = "arm,idle-state"; 274 arm,psci-suspend-param = <0x01010010>; 275 local-timer-stop; 276 entry-latency-us = <55>; 277 exit-latency-us = <155>; 278 min-residency-us = <840>; 279 }; 280 281 cluster_off_b: cluster-off-b { 282 compatible = "arm,idle-state"; 283 arm,psci-suspend-param = <0x01010010>; 284 local-timer-stop; 285 entry-latency-us = <50>; 286 exit-latency-us = <200>; 287 min-residency-us = <1000>; 288 }; 289 }; 290 291 l2_0: l2-cache0 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <131072>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l2_1: l2-cache1 { 302 compatible = "cache"; 303 cache-level = <2>; 304 cache-size = <262144>; 305 cache-line-size = <64>; 306 cache-sets = <512>; 307 next-level-cache = <&l3_0>; 308 cache-unified; 309 }; 310 311 l3_0: l3-cache { 312 compatible = "cache"; 313 cache-level = <3>; 314 cache-size = <2097152>; 315 cache-line-size = <64>; 316 cache-sets = <2048>; 317 cache-unified; 318 }; 319 }; 320 321 clk13m: oscillator-13m { 322 compatible = "fixed-clock"; 323 #clock-cells = <0>; 324 clock-frequency = <13000000>; 325 clock-output-names = "clk13m"; 326 }; 327 328 clk26m: oscillator-26m { 329 compatible = "fixed-clock"; 330 #clock-cells = <0>; 331 clock-frequency = <26000000>; 332 clock-output-names = "clk26m"; 333 }; 334 335 clk32k: oscillator-32k { 336 compatible = "fixed-clock"; 337 #clock-cells = <0>; 338 clock-frequency = <32768>; 339 clock-output-names = "clk32k"; 340 }; 341 342 gpu_opp_table: opp-table-gpu { 343 compatible = "operating-points-v2"; 344 opp-shared; 345 346 opp-390000000 { 347 opp-hz = /bits/ 64 <390000000>; 348 opp-microvolt = <575000>; 349 opp-supported-hw = <0xff>; 350 }; 351 opp-431000000 { 352 opp-hz = /bits/ 64 <431000000>; 353 opp-microvolt = <587500>; 354 opp-supported-hw = <0xff>; 355 }; 356 opp-473000000 { 357 opp-hz = /bits/ 64 <473000000>; 358 opp-microvolt = <600000>; 359 opp-supported-hw = <0xff>; 360 }; 361 opp-515000000 { 362 opp-hz = /bits/ 64 <515000000>; 363 opp-microvolt = <612500>; 364 opp-supported-hw = <0xff>; 365 }; 366 opp-556000000 { 367 opp-hz = /bits/ 64 <556000000>; 368 opp-microvolt = <625000>; 369 opp-supported-hw = <0xff>; 370 }; 371 opp-598000000 { 372 opp-hz = /bits/ 64 <598000000>; 373 opp-microvolt = <637500>; 374 opp-supported-hw = <0xff>; 375 }; 376 opp-640000000 { 377 opp-hz = /bits/ 64 <640000000>; 378 opp-microvolt = <650000>; 379 opp-supported-hw = <0xff>; 380 }; 381 opp-670000000 { 382 opp-hz = /bits/ 64 <670000000>; 383 opp-microvolt = <662500>; 384 opp-supported-hw = <0xff>; 385 }; 386 opp-700000000 { 387 opp-hz = /bits/ 64 <700000000>; 388 opp-microvolt = <675000>; 389 opp-supported-hw = <0xff>; 390 }; 391 opp-730000000 { 392 opp-hz = /bits/ 64 <730000000>; 393 opp-microvolt = <687500>; 394 opp-supported-hw = <0xff>; 395 }; 396 opp-760000000 { 397 opp-hz = /bits/ 64 <760000000>; 398 opp-microvolt = <700000>; 399 opp-supported-hw = <0xff>; 400 }; 401 opp-790000000 { 402 opp-hz = /bits/ 64 <790000000>; 403 opp-microvolt = <712500>; 404 opp-supported-hw = <0xff>; 405 }; 406 opp-835000000 { 407 opp-hz = /bits/ 64 <835000000>; 408 opp-microvolt = <731250>; 409 opp-supported-hw = <0xff>; 410 }; 411 opp-880000000 { 412 opp-hz = /bits/ 64 <880000000>; 413 opp-microvolt = <750000>; 414 opp-supported-hw = <0xff>; 415 }; 416 opp-915000000 { 417 opp-hz = /bits/ 64 <915000000>; 418 opp-microvolt = <775000>; 419 opp-supported-hw = <0x8f>; 420 }; 421 opp-915000000-5 { 422 opp-hz = /bits/ 64 <915000000>; 423 opp-microvolt = <762500>; 424 opp-supported-hw = <0x30>; 425 }; 426 opp-915000000-6 { 427 opp-hz = /bits/ 64 <915000000>; 428 opp-microvolt = <750000>; 429 opp-supported-hw = <0x70>; 430 }; 431 opp-950000000 { 432 opp-hz = /bits/ 64 <950000000>; 433 opp-microvolt = <800000>; 434 opp-supported-hw = <0x8f>; 435 }; 436 opp-950000000-5 { 437 opp-hz = /bits/ 64 <950000000>; 438 opp-microvolt = <775000>; 439 opp-supported-hw = <0x30>; 440 }; 441 opp-950000000-6 { 442 opp-hz = /bits/ 64 <950000000>; 443 opp-microvolt = <750000>; 444 opp-supported-hw = <0x70>; 445 }; 446 }; 447 448 pmu-a55 { 449 compatible = "arm,cortex-a55-pmu"; 450 interrupt-parent = <&gic>; 451 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 452 }; 453 454 pmu-a78 { 455 compatible = "arm,cortex-a78-pmu"; 456 interrupt-parent = <&gic>; 457 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 458 }; 459 460 psci { 461 compatible = "arm,psci-1.0"; 462 method = "smc"; 463 }; 464 465 sound: sound { 466 mediatek,platform = <&afe>; 467 status = "disabled"; 468 }; 469 470 thermal_zones: thermal-zones { 471 cpu-little0-thermal { 472 polling-delay = <1000>; 473 polling-delay-passive = <150>; 474 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; 475 476 trips { 477 cpu_little0_alert0: trip-alert0 { 478 temperature = <85000>; 479 hysteresis = <2000>; 480 type = "passive"; 481 }; 482 483 cpu_little0_alert1: trip-alert1 { 484 temperature = <95000>; 485 hysteresis = <2000>; 486 type = "hot"; 487 }; 488 489 cpu_little0_crit: trip-crit { 490 temperature = <100000>; 491 hysteresis = <0>; 492 type = "critical"; 493 }; 494 }; 495 496 cooling-maps { 497 cpu_little0_cooling_map0: map0 { 498 trip = <&cpu_little0_alert0>; 499 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 500 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 501 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 502 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 503 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 504 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 505 }; 506 }; 507 }; 508 509 cpu-little1-thermal { 510 polling-delay = <1000>; 511 polling-delay-passive = <150>; 512 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; 513 514 trips { 515 cpu_little1_alert0: trip-alert0 { 516 temperature = <85000>; 517 hysteresis = <2000>; 518 type = "passive"; 519 }; 520 521 cpu_little1_alert1: trip-alert1 { 522 temperature = <95000>; 523 hysteresis = <2000>; 524 type = "hot"; 525 }; 526 527 cpu_little1_crit: trip-crit { 528 temperature = <100000>; 529 hysteresis = <0>; 530 type = "critical"; 531 }; 532 }; 533 534 cooling-maps { 535 cpu_little1_cooling_map0: map0 { 536 trip = <&cpu_little1_alert0>; 537 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 541 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 542 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 543 }; 544 }; 545 }; 546 547 cpu-little2-thermal { 548 polling-delay = <1000>; 549 polling-delay-passive = <150>; 550 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; 551 552 trips { 553 cpu_little2_alert0: trip-alert0 { 554 temperature = <85000>; 555 hysteresis = <2000>; 556 type = "passive"; 557 }; 558 559 cpu_little2_alert1: trip-alert1 { 560 temperature = <95000>; 561 hysteresis = <2000>; 562 type = "hot"; 563 }; 564 565 cpu_little2_crit: trip-crit { 566 temperature = <100000>; 567 hysteresis = <0>; 568 type = "critical"; 569 }; 570 }; 571 572 cooling-maps { 573 cpu_little2_cooling_map0: map0 { 574 trip = <&cpu_little2_alert0>; 575 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 576 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 577 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 578 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 579 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 580 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 581 }; 582 }; 583 }; 584 585 cpu-little3-thermal { 586 polling-delay = <1000>; 587 polling-delay-passive = <150>; 588 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; 589 590 trips { 591 cpu_little3_alert0: trip-alert0 { 592 temperature = <85000>; 593 hysteresis = <2000>; 594 type = "passive"; 595 }; 596 597 cpu_little3_alert1: trip-alert1 { 598 temperature = <95000>; 599 hysteresis = <2000>; 600 type = "hot"; 601 }; 602 603 cpu_little3_crit: trip-crit { 604 temperature = <100000>; 605 hysteresis = <0>; 606 type = "critical"; 607 }; 608 }; 609 610 cooling-maps { 611 cpu_little3_cooling_map0: map0 { 612 trip = <&cpu_little3_alert0>; 613 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 614 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 615 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 616 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 617 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 618 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 619 }; 620 }; 621 }; 622 623 cpu-big0-thermal { 624 polling-delay = <1000>; 625 polling-delay-passive = <100>; 626 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>; 627 628 trips { 629 cpu_big0_alert0: trip-alert0 { 630 temperature = <85000>; 631 hysteresis = <2000>; 632 type = "passive"; 633 }; 634 635 cpu_big0_alert1: trip-alert1 { 636 temperature = <95000>; 637 hysteresis = <2000>; 638 type = "hot"; 639 }; 640 641 cpu_big0_crit: trip-crit { 642 temperature = <100000>; 643 hysteresis = <0>; 644 type = "critical"; 645 }; 646 }; 647 648 cooling-maps { 649 map0 { 650 trip = <&cpu_big0_alert0>; 651 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 652 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 653 }; 654 }; 655 }; 656 657 cpu-big1-thermal { 658 polling-delay = <1000>; 659 polling-delay-passive = <100>; 660 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>; 661 662 trips { 663 cpu_big1_alert0: trip-alert0 { 664 temperature = <85000>; 665 hysteresis = <2000>; 666 type = "passive"; 667 }; 668 669 cpu_big1_alert1: trip-alert1 { 670 temperature = <95000>; 671 hysteresis = <2000>; 672 type = "hot"; 673 }; 674 675 cpu_big1_crit: trip-crit { 676 temperature = <100000>; 677 hysteresis = <0>; 678 type = "critical"; 679 }; 680 }; 681 682 cooling-maps { 683 map0 { 684 trip = <&cpu_big1_alert0>; 685 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 686 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 687 }; 688 }; 689 }; 690 691 apu-thermal { 692 polling-delay = <1000>; 693 polling-delay-passive = <250>; 694 thermal-sensors = <&lvts_ap MT8188_AP_APU>; 695 696 trips { 697 apu_alert0: trip-alert0 { 698 temperature = <85000>; 699 hysteresis = <2000>; 700 type = "passive"; 701 }; 702 703 apu_alert1: trip-alert1 { 704 temperature = <95000>; 705 hysteresis = <2000>; 706 type = "hot"; 707 }; 708 709 apu_crit: trip-crit { 710 temperature = <100000>; 711 hysteresis = <0>; 712 type = "critical"; 713 }; 714 }; 715 }; 716 717 gpu-thermal { 718 polling-delay = <1000>; 719 polling-delay-passive = <250>; 720 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>; 721 722 trips { 723 gpu_alert0: trip-alert0 { 724 temperature = <85000>; 725 hysteresis = <2000>; 726 type = "passive"; 727 }; 728 729 gpu_alert1: trip-alert1 { 730 temperature = <95000>; 731 hysteresis = <2000>; 732 type = "hot"; 733 }; 734 735 gpu_crit: trip-crit { 736 temperature = <100000>; 737 hysteresis = <0>; 738 type = "critical"; 739 }; 740 }; 741 742 cooling-maps { 743 map0 { 744 trip = <&gpu_alert0>; 745 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 746 }; 747 }; 748 }; 749 750 gpu1-thermal { 751 polling-delay = <1000>; 752 polling-delay-passive = <250>; 753 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>; 754 755 trips { 756 gpu1_alert0: trip-alert0 { 757 temperature = <85000>; 758 hysteresis = <2000>; 759 type = "passive"; 760 }; 761 762 gpu1_alert1: trip-alert1 { 763 temperature = <95000>; 764 hysteresis = <2000>; 765 type = "hot"; 766 }; 767 768 gpu1_crit: trip-crit { 769 temperature = <100000>; 770 hysteresis = <0>; 771 type = "critical"; 772 }; 773 }; 774 775 cooling-maps { 776 map0 { 777 trip = <&gpu1_alert0>; 778 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 779 }; 780 }; 781 }; 782 783 adsp-thermal { 784 polling-delay = <1000>; 785 polling-delay-passive = <250>; 786 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>; 787 788 trips { 789 soc_alert0: trip-alert0 { 790 temperature = <85000>; 791 hysteresis = <2000>; 792 type = "passive"; 793 }; 794 795 soc_alert1: trip-alert1 { 796 temperature = <95000>; 797 hysteresis = <2000>; 798 type = "hot"; 799 }; 800 801 soc_crit: trip-crit { 802 temperature = <100000>; 803 hysteresis = <0>; 804 type = "critical"; 805 }; 806 }; 807 }; 808 809 vdo-thermal { 810 polling-delay = <1000>; 811 polling-delay-passive = <250>; 812 thermal-sensors = <&lvts_ap MT8188_AP_VDO>; 813 814 trips { 815 soc1_alert0: trip-alert0 { 816 temperature = <85000>; 817 hysteresis = <2000>; 818 type = "passive"; 819 }; 820 821 soc1_alert1: trip-alert1 { 822 temperature = <95000>; 823 hysteresis = <2000>; 824 type = "hot"; 825 }; 826 827 soc1_crit: trip-crit { 828 temperature = <100000>; 829 hysteresis = <0>; 830 type = "critical"; 831 }; 832 }; 833 }; 834 835 infra-thermal { 836 polling-delay = <1000>; 837 polling-delay-passive = <250>; 838 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>; 839 840 trips { 841 soc2_alert0: trip-alert0 { 842 temperature = <85000>; 843 hysteresis = <2000>; 844 type = "passive"; 845 }; 846 847 soc2_alert1: trip-alert1 { 848 temperature = <95000>; 849 hysteresis = <2000>; 850 type = "hot"; 851 }; 852 853 soc2_crit: trip-crit { 854 temperature = <100000>; 855 hysteresis = <0>; 856 type = "critical"; 857 }; 858 }; 859 }; 860 861 cam1-thermal { 862 polling-delay = <1000>; 863 polling-delay-passive = <250>; 864 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>; 865 866 trips { 867 cam1_alert0: trip-alert0 { 868 temperature = <85000>; 869 hysteresis = <2000>; 870 type = "passive"; 871 }; 872 873 cam1_alert1: trip-alert1 { 874 temperature = <95000>; 875 hysteresis = <2000>; 876 type = "hot"; 877 }; 878 879 cam1_crit: trip-crit { 880 temperature = <100000>; 881 hysteresis = <0>; 882 type = "critical"; 883 }; 884 }; 885 }; 886 887 cam2-thermal { 888 polling-delay = <1000>; 889 polling-delay-passive = <250>; 890 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>; 891 892 trips { 893 cam2_alert0: trip-alert0 { 894 temperature = <85000>; 895 hysteresis = <2000>; 896 type = "passive"; 897 }; 898 899 cam2_alert1: trip-alert1 { 900 temperature = <95000>; 901 hysteresis = <2000>; 902 type = "hot"; 903 }; 904 905 cam2_crit: trip-crit { 906 temperature = <100000>; 907 hysteresis = <0>; 908 type = "critical"; 909 }; 910 }; 911 }; 912 }; 913 914 timer: timer { 915 compatible = "arm,armv8-timer"; 916 interrupt-parent = <&gic>; 917 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 918 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 919 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 920 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 921 clock-frequency = <13000000>; 922 }; 923 924 soc { 925 #address-cells = <2>; 926 #size-cells = <2>; 927 compatible = "simple-bus"; 928 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 929 ranges; 930 931 performance: performance-controller@11bc10 { 932 compatible = "mediatek,cpufreq-hw"; 933 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 934 #performance-domain-cells = <1>; 935 }; 936 937 gic: interrupt-controller@c000000 { 938 compatible = "arm,gic-v3"; 939 #interrupt-cells = <4>; 940 #redistributor-regions = <1>; 941 interrupt-parent = <&gic>; 942 interrupt-controller; 943 reg = <0 0x0c000000 0 0x40000>, 944 <0 0x0c040000 0 0x200000>; 945 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 946 947 ppi-partitions { 948 ppi_cluster0: interrupt-partition-0 { 949 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 950 }; 951 952 ppi_cluster1: interrupt-partition-1 { 953 affinity = <&cpu6 &cpu7>; 954 }; 955 }; 956 }; 957 958 topckgen: syscon@10000000 { 959 compatible = "mediatek,mt8188-topckgen", "syscon"; 960 reg = <0 0x10000000 0 0x1000>; 961 #clock-cells = <1>; 962 }; 963 964 infracfg_ao: syscon@10001000 { 965 compatible = "mediatek,mt8188-infracfg-ao", "syscon"; 966 reg = <0 0x10001000 0 0x1000>; 967 #clock-cells = <1>; 968 #reset-cells = <1>; 969 }; 970 971 pericfg: syscon@10003000 { 972 compatible = "mediatek,mt8188-pericfg", "syscon"; 973 reg = <0 0x10003000 0 0x1000>; 974 #clock-cells = <1>; 975 }; 976 977 pio: pinctrl@10005000 { 978 compatible = "mediatek,mt8188-pinctrl"; 979 reg = <0 0x10005000 0 0x1000>, 980 <0 0x11c00000 0 0x1000>, 981 <0 0x11e10000 0 0x1000>, 982 <0 0x11e20000 0 0x1000>, 983 <0 0x11ea0000 0 0x1000>, 984 <0 0x1000b000 0 0x1000>; 985 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt", 986 "iocfg_lm", "iocfg_rt", "eint"; 987 gpio-controller; 988 #gpio-cells = <2>; 989 gpio-ranges = <&pio 0 0 176>; 990 interrupt-controller; 991 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 992 #interrupt-cells = <2>; 993 }; 994 995 scpsys: syscon@10006000 { 996 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; 997 reg = <0 0x10006000 0 0x1000>; 998 999 /* System Power Manager */ 1000 spm: power-controller { 1001 compatible = "mediatek,mt8188-power-controller"; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 #power-domain-cells = <1>; 1005 1006 /* power domain of the SoC */ 1007 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { 1008 reg = <MT8188_POWER_DOMAIN_MFG0>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 #power-domain-cells = <1>; 1012 1013 mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { 1014 reg = <MT8188_POWER_DOMAIN_MFG1>; 1015 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 1016 <&topckgen CLK_TOP_MFG_CORE_TMP>; 1017 clock-names = "mfg", "alt"; 1018 mediatek,infracfg = <&infracfg_ao>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 #power-domain-cells = <1>; 1022 1023 power-domain@MT8188_POWER_DOMAIN_MFG2 { 1024 reg = <MT8188_POWER_DOMAIN_MFG2>; 1025 #power-domain-cells = <0>; 1026 }; 1027 1028 power-domain@MT8188_POWER_DOMAIN_MFG3 { 1029 reg = <MT8188_POWER_DOMAIN_MFG3>; 1030 #power-domain-cells = <0>; 1031 }; 1032 1033 power-domain@MT8188_POWER_DOMAIN_MFG4 { 1034 reg = <MT8188_POWER_DOMAIN_MFG4>; 1035 #power-domain-cells = <0>; 1036 }; 1037 }; 1038 }; 1039 1040 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { 1041 reg = <MT8188_POWER_DOMAIN_VPPSYS0>; 1042 clocks = <&topckgen CLK_TOP_VPP>, 1043 <&topckgen CLK_TOP_CAM>, 1044 <&topckgen CLK_TOP_CCU>, 1045 <&topckgen CLK_TOP_IMG>, 1046 <&topckgen CLK_TOP_VENC>, 1047 <&topckgen CLK_TOP_VDEC>, 1048 <&topckgen CLK_TOP_WPE_VPP>, 1049 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, 1050 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, 1051 <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, 1052 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, 1053 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, 1054 <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, 1055 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, 1056 <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, 1057 <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, 1058 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, 1059 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, 1060 <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, 1061 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 1062 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 1063 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 1064 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 1065 <&vppsys0 CLK_VPP0_SMI_RSI>, 1066 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1067 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1068 <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, 1069 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 1070 clock-names = "top", "cam", "ccu", "img", "venc", 1071 "vdec", "wpe", "cfgck", "cfgxo", 1072 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", 1073 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", 1074 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", 1075 "ss-sram-rdr", "ss-iommu", "ss-imgcam", 1076 "ss-emi", "ss-subcmn-rdr", "ss-rsi", 1077 "ss-cmn-l4", "ss-vdec1", "ss-wpe", 1078 "ss-cvdo-ve1"; 1079 mediatek,infracfg = <&infracfg_ao>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 #power-domain-cells = <1>; 1083 1084 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { 1085 reg = <MT8188_POWER_DOMAIN_VDOSYS0>; 1086 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, 1087 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, 1088 <&vdosys0 CLK_VDO0_SMI_GALS>, 1089 <&vdosys0 CLK_VDO0_SMI_COMMON>, 1090 <&vdosys0 CLK_VDO0_SMI_EMI>, 1091 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 1092 <&vdosys0 CLK_VDO0_SMI_LARB>, 1093 <&vdosys0 CLK_VDO0_SMI_RSI>, 1094 <&vdosys0 CLK_VDO0_APB_BUS>; 1095 clock-names = "cfgck", "cfgxo", "ss-gals", 1096 "ss-cmn", "ss-emi", "ss-iommu", 1097 "ss-larb", "ss-rsi", "ss-bus"; 1098 mediatek,infracfg = <&infracfg_ao>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 #power-domain-cells = <1>; 1102 1103 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { 1104 reg = <MT8188_POWER_DOMAIN_VPPSYS1>; 1105 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, 1106 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, 1107 <&vppsys1 CLK_VPP1_GALS5>, 1108 <&vppsys1 CLK_VPP1_GALS6>, 1109 <&vppsys1 CLK_VPP1_LARB5>, 1110 <&vppsys1 CLK_VPP1_LARB6>; 1111 clock-names = "cfgck", "cfgxo", 1112 "ss-vpp1-g5", "ss-vpp1-g6", 1113 "ss-vpp1-l5", "ss-vpp1-l6"; 1114 mediatek,infracfg = <&infracfg_ao>; 1115 #power-domain-cells = <0>; 1116 }; 1117 1118 power-domain@MT8188_POWER_DOMAIN_VDEC0 { 1119 reg = <MT8188_POWER_DOMAIN_VDEC0>; 1120 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 1121 clock-names = "ss-vdec1-soc-l1"; 1122 mediatek,infracfg = <&infracfg_ao>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 #power-domain-cells = <1>; 1126 1127 power-domain@MT8188_POWER_DOMAIN_VDEC1 { 1128 reg = <MT8188_POWER_DOMAIN_VDEC1>; 1129 clocks = <&vdecsys CLK_VDEC2_LARB1>; 1130 clock-names = "ss-vdec2-l1"; 1131 mediatek,infracfg = <&infracfg_ao>; 1132 #power-domain-cells = <0>; 1133 }; 1134 }; 1135 1136 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { 1137 reg = <MT8188_POWER_DOMAIN_CAM_VCORE>; 1138 clocks = <&topckgen CLK_TOP_CAM>, 1139 <&topckgen CLK_TOP_CCU>, 1140 <&topckgen CLK_TOP_CCU_AHB>, 1141 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; 1142 clock-names = "cam", "ccu", "bus", "cfgck"; 1143 mediatek,infracfg = <&infracfg_ao>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 #power-domain-cells = <1>; 1147 1148 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { 1149 reg = <MT8188_POWER_DOMAIN_CAM_MAIN>; 1150 clocks = <&camsys CLK_CAM_MAIN_LARB13>, 1151 <&camsys CLK_CAM_MAIN_LARB14>, 1152 <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, 1153 <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, 1154 <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; 1155 clock-names= "ss-cam-l13", "ss-cam-l14", 1156 "ss-cam-mm0", "ss-cam-mm1", 1157 "ss-camsys"; 1158 mediatek,infracfg = <&infracfg_ao>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 #power-domain-cells = <1>; 1162 1163 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { 1164 reg = <MT8188_POWER_DOMAIN_CAM_SUBB>; 1165 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, 1166 <&camsys_rawb CLK_CAM_RAWB_LARBX>, 1167 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 1168 clock-names = "ss-camb-sub", 1169 "ss-camb-raw", 1170 "ss-camb-yuv"; 1171 #power-domain-cells = <0>; 1172 }; 1173 1174 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { 1175 reg =<MT8188_POWER_DOMAIN_CAM_SUBA>; 1176 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, 1177 <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1178 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 1179 clock-names = "ss-cama-sub", 1180 "ss-cama-raw", 1181 "ss-cama-yuv"; 1182 #power-domain-cells = <0>; 1183 }; 1184 }; 1185 }; 1186 1187 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { 1188 reg = <MT8188_POWER_DOMAIN_VDOSYS1>; 1189 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, 1190 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, 1191 <&vdosys1 CLK_VDO1_SMI_LARB2>, 1192 <&vdosys1 CLK_VDO1_SMI_LARB3>, 1193 <&vdosys1 CLK_VDO1_GALS>; 1194 clock-names = "cfgck", "cfgxo", "ss-larb2", 1195 "ss-larb3", "ss-gals"; 1196 mediatek,infracfg = <&infracfg_ao>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 #power-domain-cells = <1>; 1200 1201 power-domain@MT8188_POWER_DOMAIN_HDMI_TX { 1202 reg = <MT8188_POWER_DOMAIN_HDMI_TX>; 1203 clocks = <&topckgen CLK_TOP_HDMI_APB>, 1204 <&topckgen CLK_TOP_HDCP_24M>; 1205 clock-names = "bus", "hdcp"; 1206 mediatek,infracfg = <&infracfg_ao>; 1207 #power-domain-cells = <0>; 1208 }; 1209 1210 power-domain@MT8188_POWER_DOMAIN_DP_TX { 1211 reg = <MT8188_POWER_DOMAIN_DP_TX>; 1212 mediatek,infracfg = <&infracfg_ao>; 1213 #power-domain-cells = <0>; 1214 }; 1215 1216 power-domain@MT8188_POWER_DOMAIN_EDP_TX { 1217 reg = <MT8188_POWER_DOMAIN_EDP_TX>; 1218 mediatek,infracfg = <&infracfg_ao>; 1219 #power-domain-cells = <0>; 1220 }; 1221 }; 1222 1223 power-domain@MT8188_POWER_DOMAIN_VENC { 1224 reg = <MT8188_POWER_DOMAIN_VENC>; 1225 clocks = <&vencsys CLK_VENC1_LARB>, 1226 <&vencsys CLK_VENC1_VENC>, 1227 <&vencsys CLK_VENC1_GALS>, 1228 <&vencsys CLK_VENC1_GALS_SRAM>; 1229 clock-names = "ss-ve1-larb", "ss-ve1-core", 1230 "ss-ve1-gals", "ss-ve1-sram"; 1231 mediatek,infracfg = <&infracfg_ao>; 1232 #power-domain-cells = <0>; 1233 }; 1234 1235 power-domain@MT8188_POWER_DOMAIN_WPE { 1236 reg = <MT8188_POWER_DOMAIN_WPE>; 1237 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 1238 <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; 1239 clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; 1240 mediatek,infracfg = <&infracfg_ao>; 1241 #power-domain-cells = <0>; 1242 }; 1243 }; 1244 }; 1245 1246 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { 1247 reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1248 mediatek,infracfg = <&infracfg_ao>; 1249 clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1250 clock-names = "ss-pextp-fmem"; 1251 #power-domain-cells = <0>; 1252 }; 1253 1254 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { 1255 reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>; 1256 clocks = <&topckgen CLK_TOP_SENINF>, 1257 <&topckgen CLK_TOP_SENINF1>; 1258 clock-names = "seninf0", "seninf1"; 1259 #power-domain-cells = <0>; 1260 }; 1261 1262 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { 1263 reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 1264 #power-domain-cells = <0>; 1265 }; 1266 1267 power-domain@MT8188_POWER_DOMAIN_ADSP_AO { 1268 reg = <MT8188_POWER_DOMAIN_ADSP_AO>; 1269 clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1270 <&topckgen CLK_TOP_ADSP>; 1271 clock-names = "bus", "main"; 1272 mediatek,infracfg = <&infracfg_ao>; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 #power-domain-cells = <1>; 1276 1277 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { 1278 reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>; 1279 mediatek,infracfg = <&infracfg_ao>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 #power-domain-cells = <1>; 1283 1284 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { 1285 reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>; 1286 clocks = <&topckgen CLK_TOP_ASM_H>; 1287 clock-names = "asm"; 1288 mediatek,infracfg = <&infracfg_ao>; 1289 #power-domain-cells = <0>; 1290 }; 1291 1292 power-domain@MT8188_POWER_DOMAIN_AUDIO { 1293 reg = <MT8188_POWER_DOMAIN_AUDIO>; 1294 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 1295 <&topckgen CLK_TOP_AUD_INTBUS>, 1296 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; 1297 clock-names = "a1sys", "intbus", "adspck"; 1298 mediatek,infracfg = <&infracfg_ao>; 1299 #power-domain-cells = <0>; 1300 }; 1301 1302 power-domain@MT8188_POWER_DOMAIN_ADSP { 1303 reg = <MT8188_POWER_DOMAIN_ADSP>; 1304 mediatek,infracfg = <&infracfg_ao>; 1305 #power-domain-cells = <0>; 1306 }; 1307 }; 1308 }; 1309 1310 power-domain@MT8188_POWER_DOMAIN_ETHER { 1311 reg = <MT8188_POWER_DOMAIN_ETHER>; 1312 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1313 clock-names = "ethermac"; 1314 mediatek,infracfg = <&infracfg_ao>; 1315 #power-domain-cells = <0>; 1316 }; 1317 }; 1318 }; 1319 1320 watchdog: watchdog@10007000 { 1321 compatible = "mediatek,mt8188-wdt"; 1322 reg = <0 0x10007000 0 0x100>; 1323 mediatek,disable-extrst; 1324 #reset-cells = <1>; 1325 }; 1326 1327 apmixedsys: syscon@1000c000 { 1328 compatible = "mediatek,mt8188-apmixedsys", "syscon"; 1329 reg = <0 0x1000c000 0 0x1000>; 1330 #clock-cells = <1>; 1331 }; 1332 1333 systimer: timer@10017000 { 1334 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer"; 1335 reg = <0 0x10017000 0 0x1000>; 1336 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1337 clocks = <&clk13m>; 1338 }; 1339 1340 pwrap: pwrap@10024000 { 1341 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon"; 1342 reg = <0 0x10024000 0 0x1000>; 1343 reg-names = "pwrap"; 1344 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 1345 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1346 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 1347 clock-names = "spi", "wrap"; 1348 }; 1349 1350 spmi: spmi@10027000 { 1351 compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi"; 1352 reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>; 1353 reg-names = "pmif", "spmimst"; 1354 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>; 1355 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 1356 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1357 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 1358 <&topckgen CLK_TOP_SPMI_M_MST>; 1359 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 1360 }; 1361 1362 infra_iommu: iommu@10315000 { 1363 compatible = "mediatek,mt8188-iommu-infra"; 1364 reg = <0 0x10315000 0 0x1000>; 1365 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>; 1366 #iommu-cells = <1>; 1367 }; 1368 1369 gce0: mailbox@10320000 { 1370 compatible = "mediatek,mt8188-gce"; 1371 reg = <0 0x10320000 0 0x4000>; 1372 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 1373 #mbox-cells = <2>; 1374 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 1375 }; 1376 1377 gce1: mailbox@10330000 { 1378 compatible = "mediatek,mt8188-gce"; 1379 reg = <0 0x10330000 0 0x4000>; 1380 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 1381 #mbox-cells = <2>; 1382 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 1383 }; 1384 1385 scp: scp@10500000 { 1386 compatible = "mediatek,mt8188-scp"; 1387 reg = <0 0x10500000 0 0x100000>, 1388 <0 0x10720000 0 0xe0000>; 1389 reg-names = "sram", "cfg"; 1390 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1391 }; 1392 1393 afe: audio-controller@10b10000 { 1394 compatible = "mediatek,mt8188-afe"; 1395 reg = <0 0x10b10000 0 0x10000>; 1396 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; 1397 assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>; 1398 clocks = <&clk26m>, 1399 <&apmixedsys CLK_APMIXED_APLL1>, 1400 <&apmixedsys CLK_APMIXED_APLL2>, 1401 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1402 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1403 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1404 <&topckgen CLK_TOP_APLL12_CK_DIV3>, 1405 <&topckgen CLK_TOP_APLL12_CK_DIV9>, 1406 <&topckgen CLK_TOP_A1SYS_HP>, 1407 <&topckgen CLK_TOP_AUD_INTBUS>, 1408 <&topckgen CLK_TOP_AUDIO_H>, 1409 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1410 <&topckgen CLK_TOP_DPTX>, 1411 <&topckgen CLK_TOP_I2SO1>, 1412 <&topckgen CLK_TOP_I2SO2>, 1413 <&topckgen CLK_TOP_I2SI1>, 1414 <&topckgen CLK_TOP_I2SI2>, 1415 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>, 1416 <&topckgen CLK_TOP_APLL1_D4>, 1417 <&topckgen CLK_TOP_APLL2_D4>, 1418 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1419 <&topckgen CLK_TOP_A2SYS>, 1420 <&topckgen CLK_TOP_AUD_IEC>; 1421 clock-names = "clk26m", 1422 "apll1", 1423 "apll2", 1424 "apll12_div0", 1425 "apll12_div1", 1426 "apll12_div2", 1427 "apll12_div3", 1428 "apll12_div9", 1429 "top_a1sys_hp", 1430 "top_aud_intbus", 1431 "top_audio_h", 1432 "top_audio_local_bus", 1433 "top_dptx", 1434 "top_i2so1", 1435 "top_i2so2", 1436 "top_i2si1", 1437 "top_i2si2", 1438 "adsp_audio_26m", 1439 "apll1_d4", 1440 "apll2_d4", 1441 "apll12_div4", 1442 "top_a2sys", 1443 "top_aud_iec"; 1444 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 1445 power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>; 1446 resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>; 1447 reset-names = "audiosys"; 1448 mediatek,infracfg = <&infracfg_ao>; 1449 mediatek,topckgen = <&topckgen>; 1450 status = "disabled"; 1451 }; 1452 1453 adsp: adsp@10b80000 { 1454 compatible = "mediatek,mt8188-dsp"; 1455 reg = <0 0x10b80000 0 0x2000>, 1456 <0 0x10d00000 0 0x80000>, 1457 <0 0x10b8b000 0 0x100>, 1458 <0 0x10b8f000 0 0x1000>; 1459 reg-names = "cfg", "sram", "sec", "bus"; 1460 assigned-clocks = <&topckgen CLK_TOP_ADSP>; 1461 clocks = <&topckgen CLK_TOP_ADSP>, 1462 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 1463 clock-names = "audiodsp", "adsp_bus"; 1464 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1465 mbox-names = "rx", "tx"; 1466 power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>; 1467 status = "disabled"; 1468 }; 1469 1470 adsp_mailbox0: mailbox@10b86100 { 1471 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1472 reg = <0 0x10b86100 0 0x1000>; 1473 interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>; 1474 #mbox-cells = <0>; 1475 }; 1476 1477 adsp_mailbox1: mailbox@10b87100 { 1478 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1479 reg = <0 0x10b87100 0 0x1000>; 1480 interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>; 1481 #mbox-cells = <0>; 1482 }; 1483 1484 adsp_audio26m: clock-controller@10b91100 { 1485 compatible = "mediatek,mt8188-adsp-audio26m"; 1486 reg = <0 0x10b91100 0 0x100>; 1487 #clock-cells = <1>; 1488 }; 1489 1490 uart0: serial@11001100 { 1491 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1492 reg = <0 0x11001100 0 0x100>; 1493 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1494 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1495 clock-names = "baud", "bus"; 1496 status = "disabled"; 1497 }; 1498 1499 uart1: serial@11001200 { 1500 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1501 reg = <0 0x11001200 0 0x100>; 1502 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1503 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1504 clock-names = "baud", "bus"; 1505 status = "disabled"; 1506 }; 1507 1508 uart2: serial@11001300 { 1509 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1510 reg = <0 0x11001300 0 0x100>; 1511 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1512 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1513 clock-names = "baud", "bus"; 1514 status = "disabled"; 1515 }; 1516 1517 uart3: serial@11001400 { 1518 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1519 reg = <0 0x11001400 0 0x100>; 1520 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1521 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1522 clock-names = "baud", "bus"; 1523 status = "disabled"; 1524 }; 1525 1526 auxadc: adc@11002000 { 1527 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; 1528 reg = <0 0x11002000 0 0x1000>; 1529 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1530 clock-names = "main"; 1531 #io-channel-cells = <1>; 1532 status = "disabled"; 1533 }; 1534 1535 pericfg_ao: syscon@11003000 { 1536 compatible = "mediatek,mt8188-pericfg-ao", "syscon"; 1537 reg = <0 0x11003000 0 0x1000>; 1538 #clock-cells = <1>; 1539 }; 1540 1541 spi0: spi@1100a000 { 1542 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 reg = <0 0x1100a000 0 0x1000>; 1546 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1547 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1548 <&topckgen CLK_TOP_SPI>, 1549 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1550 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1551 status = "disabled"; 1552 }; 1553 1554 lvts_ap: thermal-sensor@1100b000 { 1555 compatible = "mediatek,mt8188-lvts-ap"; 1556 reg = <0 0x1100b000 0 0xc00>; 1557 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>; 1558 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1559 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; 1560 nvmem-cells = <&lvts_efuse_data1>; 1561 nvmem-cell-names = "lvts-calib-data-1"; 1562 #thermal-sensor-cells = <1>; 1563 }; 1564 1565 disp_pwm0: pwm@1100e000 { 1566 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1567 reg = <0 0x1100e000 0 0x1000>; 1568 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1569 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1570 clock-names = "main", "mm"; 1571 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1572 #pwm-cells = <2>; 1573 status = "disabled"; 1574 }; 1575 1576 disp_pwm1: pwm@1100f000 { 1577 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1578 reg = <0 0x1100f000 0 0x1000>; 1579 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1580 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1581 clock-names = "main", "mm"; 1582 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1583 #pwm-cells = <2>; 1584 status = "disabled"; 1585 }; 1586 1587 spi1: spi@11010000 { 1588 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 reg = <0 0x11010000 0 0x1000>; 1592 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1593 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1594 <&topckgen CLK_TOP_SPI>, 1595 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1596 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1597 status = "disabled"; 1598 }; 1599 1600 spi2: spi@11012000 { 1601 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 reg = <0 0x11012000 0 0x1000>; 1605 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1606 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1607 <&topckgen CLK_TOP_SPI>, 1608 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1609 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1610 status = "disabled"; 1611 }; 1612 1613 spi3: spi@11013000 { 1614 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 reg = <0 0x11013000 0 0x1000>; 1618 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1619 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1620 <&topckgen CLK_TOP_SPI>, 1621 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1622 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1623 status = "disabled"; 1624 }; 1625 1626 spi4: spi@11018000 { 1627 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 reg = <0 0x11018000 0 0x1000>; 1631 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1632 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1633 <&topckgen CLK_TOP_SPI>, 1634 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1635 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1636 status = "disabled"; 1637 }; 1638 1639 spi5: spi@11019000 { 1640 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 reg = <0 0x11019000 0 0x1000>; 1644 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1645 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1646 <&topckgen CLK_TOP_SPI>, 1647 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1648 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1649 status = "disabled"; 1650 }; 1651 1652 ssusb1: usb@11201000 { 1653 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1654 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1655 reg-names = "mac", "ippc"; 1656 ranges = <0 0 0 0x11200000 0 0x3f00>; 1657 #address-cells = <2>; 1658 #size-cells = <2>; 1659 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1660 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>; 1661 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1662 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, 1663 <&topckgen CLK_TOP_SSUSB_TOP_REF>, 1664 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1665 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1666 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1667 wakeup-source; 1668 mediatek,syscon-wakeup = <&pericfg 0x468 2>; 1669 status = "disabled"; 1670 1671 xhci1: usb@0 { 1672 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1673 reg = <0 0 0 0x1000>; 1674 reg-names = "mac"; 1675 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1676 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>; 1677 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1678 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1679 clock-names = "sys_ck"; 1680 status = "disabled"; 1681 }; 1682 }; 1683 1684 eth: ethernet@11021000 { 1685 compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", 1686 "snps,dwmac-5.10a"; 1687 reg = <0 0x11021000 0 0x4000>; 1688 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1689 interrupt-names = "macirq"; 1690 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1691 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1692 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1693 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1694 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1695 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1696 clock-names = "axi", "apb", "mac_main", "ptp_ref", 1697 "rmii_internal", "mac_cg"; 1698 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1699 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1700 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1701 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1702 <&topckgen CLK_TOP_ETHPLL_D8>, 1703 <&topckgen CLK_TOP_ETHPLL_D10>; 1704 power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>; 1705 mediatek,pericfg = <&infracfg_ao>; 1706 snps,axi-config = <&stmmac_axi_setup>; 1707 snps,mtl-rx-config = <&mtl_rx_setup>; 1708 snps,mtl-tx-config = <&mtl_tx_setup>; 1709 snps,txpbl = <16>; 1710 snps,rxpbl = <16>; 1711 snps,clk-csr = <0>; 1712 status = "disabled"; 1713 1714 eth_mdio: mdio { 1715 compatible = "snps,dwmac-mdio"; 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 }; 1719 1720 stmmac_axi_setup: stmmac-axi-config { 1721 snps,blen = <0 0 0 0 16 8 4>; 1722 snps,rd_osr_lmt = <0x7>; 1723 snps,wr_osr_lmt = <0x7>; 1724 }; 1725 1726 mtl_rx_setup: rx-queues-config { 1727 snps,rx-queues-to-use = <4>; 1728 snps,rx-sched-sp; 1729 1730 queue0 { 1731 snps,dcb-algorithm; 1732 snps,map-to-dma-channel = <0x0>; 1733 }; 1734 1735 queue1 { 1736 snps,dcb-algorithm; 1737 snps,map-to-dma-channel = <0x0>; 1738 }; 1739 1740 queue2 { 1741 snps,dcb-algorithm; 1742 snps,map-to-dma-channel = <0x0>; 1743 }; 1744 1745 queue3 { 1746 snps,dcb-algorithm; 1747 snps,map-to-dma-channel = <0x0>; 1748 }; 1749 }; 1750 1751 mtl_tx_setup: tx-queues-config { 1752 snps,tx-queues-to-use = <4>; 1753 snps,tx-sched-wrr; 1754 1755 queue0 { 1756 snps,dcb-algorithm; 1757 snps,priority = <0x0>; 1758 snps,weight = <0x10>; 1759 }; 1760 1761 queue1 { 1762 snps,dcb-algorithm; 1763 snps,priority = <0x1>; 1764 snps,weight = <0x11>; 1765 }; 1766 1767 queue2 { 1768 snps,dcb-algorithm; 1769 snps,priority = <0x2>; 1770 snps,weight = <0x12>; 1771 }; 1772 1773 queue3 { 1774 snps,dcb-algorithm; 1775 snps,priority = <0x3>; 1776 snps,weight = <0x13>; 1777 }; 1778 }; 1779 }; 1780 1781 mmc0: mmc@11230000 { 1782 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1783 reg = <0 0x11230000 0 0x10000>, 1784 <0 0x11f50000 0 0x1000>; 1785 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1786 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1787 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1788 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1789 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; 1790 clock-names = "source", "hclk", "source_cg", "crypto_clk"; 1791 status = "disabled"; 1792 }; 1793 1794 mmc1: mmc@11240000 { 1795 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1796 reg = <0 0x11240000 0 0x1000>, 1797 <0 0x11eb0000 0 0x1000>; 1798 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1799 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1800 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1801 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1802 clock-names = "source", "hclk", "source_cg"; 1803 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1804 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1805 status = "disabled"; 1806 }; 1807 1808 mmc2: mmc@11250000 { 1809 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1810 reg = <0 0x11250000 0 0x1000>, 1811 <0 0x11e60000 0 0x1000>; 1812 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1813 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1814 <&infracfg_ao CLK_INFRA_AO_MSDC2>, 1815 <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; 1816 clock-names = "source", "hclk", "source_cg"; 1817 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1818 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1819 status = "disabled"; 1820 }; 1821 1822 lvts_mcu: thermal-sensor@11278000 { 1823 compatible = "mediatek,mt8188-lvts-mcu"; 1824 reg = <0 0x11278000 0 0x1000>; 1825 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 1826 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1827 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; 1828 nvmem-cells = <&lvts_efuse_data1>; 1829 nvmem-cell-names = "lvts-calib-data-1"; 1830 #thermal-sensor-cells = <1>; 1831 }; 1832 1833 i2c0: i2c@11280000 { 1834 compatible = "mediatek,mt8188-i2c"; 1835 reg = <0 0x11280000 0 0x1000>, 1836 <0 0x10220080 0 0x80>; 1837 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; 1838 clock-div = <1>; 1839 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, 1840 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1841 clock-names = "main", "dma"; 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 status = "disabled"; 1845 }; 1846 1847 i2c2: i2c@11281000 { 1848 compatible = "mediatek,mt8188-i2c"; 1849 reg = <0 0x11281000 0 0x1000>, 1850 <0 0x10220180 0 0x80>; 1851 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1852 clock-div = <1>; 1853 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, 1854 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1855 clock-names = "main", "dma"; 1856 #address-cells = <1>; 1857 #size-cells = <0>; 1858 status = "disabled"; 1859 }; 1860 1861 i2c3: i2c@11282000 { 1862 compatible = "mediatek,mt8188-i2c"; 1863 reg = <0 0x11282000 0 0x1000>, 1864 <0 0x10220280 0 0x80>; 1865 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1866 clock-div = <1>; 1867 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, 1868 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1869 clock-names = "main", "dma"; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 status = "disabled"; 1873 }; 1874 1875 imp_iic_wrap_c: clock-controller@11283000 { 1876 compatible = "mediatek,mt8188-imp-iic-wrap-c"; 1877 reg = <0 0x11283000 0 0x1000>; 1878 #clock-cells = <1>; 1879 }; 1880 1881 ssusb2: usb@112a1000 { 1882 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1883 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; 1884 reg-names = "mac", "ippc"; 1885 ranges = <0 0 0 0x112a0000 0 0x3f00>; 1886 #address-cells = <2>; 1887 #size-cells = <2>; 1888 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1889 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; 1890 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1891 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1892 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, 1893 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1894 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1895 phys = <&u2port2 PHY_TYPE_USB2>; 1896 wakeup-source; 1897 mediatek,syscon-wakeup = <&pericfg 0x470 2>; 1898 status = "disabled"; 1899 1900 xhci2: usb@0 { 1901 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1902 reg = <0 0 0 0x1000>; 1903 reg-names = "mac"; 1904 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1905 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1906 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1907 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1908 clock-names = "sys_ck"; 1909 status = "disabled"; 1910 }; 1911 }; 1912 1913 ssusb0: usb@112b1000 { 1914 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1915 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; 1916 reg-names = "mac", "ippc"; 1917 ranges = <0 0 0 0x112b0000 0 0x3f00>; 1918 #address-cells = <2>; 1919 #size-cells = <2>; 1920 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1921 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1922 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1923 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1924 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, 1925 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1926 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1927 phys = <&u2port0 PHY_TYPE_USB2>; 1928 wakeup-source; 1929 mediatek,syscon-wakeup = <&pericfg 0x460 2>; 1930 status = "disabled"; 1931 1932 xhci0: usb@0 { 1933 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1934 reg = <0 0 0 0x1000>; 1935 reg-names = "mac"; 1936 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1937 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; 1938 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1939 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1940 clock-names = "sys_ck"; 1941 status = "disabled"; 1942 }; 1943 }; 1944 1945 pcie: pcie@112f0000 { 1946 compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; 1947 reg = <0 0x112f0000 0 0x2000>; 1948 reg-names = "pcie-mac"; 1949 ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; 1950 bus-range = <0 0xff>; 1951 device_type = "pci"; 1952 linux,pci-domain = <0>; 1953 #address-cells = <3>; 1954 #size-cells = <2>; 1955 1956 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1957 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1958 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1959 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1960 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1961 <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1962 clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", 1963 "peri_26m", "peri_mem"; 1964 1965 #interrupt-cells = <1>; 1966 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1967 interrupt-map = <0 0 0 1 &pcie_intc 0>, 1968 <0 0 0 2 &pcie_intc 1>, 1969 <0 0 0 3 &pcie_intc 2>, 1970 <0 0 0 4 &pcie_intc 3>; 1971 interrupt-map-mask = <0 0 0 7>; 1972 1973 iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; 1974 iommu-map-mask = <0>; 1975 1976 phys = <&pcieport PHY_TYPE_PCIE>; 1977 phy-names = "pcie-phy"; 1978 1979 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1980 1981 resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; 1982 reset-names = "mac"; 1983 1984 status = "disabled"; 1985 1986 pcie_intc: interrupt-controller { 1987 #address-cells = <0>; 1988 #interrupt-cells = <1>; 1989 interrupt-controller; 1990 }; 1991 }; 1992 1993 nor_flash: spi@1132c000 { 1994 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; 1995 reg = <0 0x1132c000 0 0x1000>; 1996 clocks = <&topckgen CLK_TOP_SPINOR>, 1997 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, 1998 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1999 clock-names = "spi", "sf", "axi"; 2000 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 2001 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 2002 #address-cells = <1>; 2003 #size-cells = <0>; 2004 status = "disabled"; 2005 }; 2006 2007 pciephy: t-phy@11c20700 { 2008 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2009 ranges = <0 0 0x11c20700 0x700>; 2010 #address-cells = <1>; 2011 #size-cells = <1>; 2012 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 2013 status = "disabled"; 2014 2015 pcieport: pcie-phy@0 { 2016 reg = <0 0x700>; 2017 clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; 2018 clock-names = "ref"; 2019 #phy-cells = <1>; 2020 }; 2021 }; 2022 2023 mipi_tx_config0: dsi-phy@11c80000 { 2024 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 2025 reg = <0 0x11c80000 0 0x1000>; 2026 clocks = <&clk26m>; 2027 clock-output-names = "mipi_tx0_pll"; 2028 #clock-cells = <0>; 2029 #phy-cells = <0>; 2030 status = "disabled"; 2031 }; 2032 2033 mipi_tx_config1: dsi-phy@11c90000 { 2034 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 2035 reg = <0 0x11c90000 0 0x1000>; 2036 clocks = <&clk26m>; 2037 clock-output-names = "mipi_tx0_pll"; 2038 #clock-cells = <0>; 2039 #phy-cells = <0>; 2040 status = "disabled"; 2041 }; 2042 2043 i2c1: i2c@11e00000 { 2044 compatible = "mediatek,mt8188-i2c"; 2045 reg = <0 0x11e00000 0 0x1000>, 2046 <0 0x10220100 0 0x80>; 2047 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 2048 clock-div = <1>; 2049 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, 2050 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2051 clock-names = "main", "dma"; 2052 #address-cells = <1>; 2053 #size-cells = <0>; 2054 status = "disabled"; 2055 }; 2056 2057 i2c4: i2c@11e01000 { 2058 compatible = "mediatek,mt8188-i2c"; 2059 reg = <0 0x11e01000 0 0x1000>, 2060 <0 0x10220380 0 0x80>; 2061 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; 2062 clock-div = <1>; 2063 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, 2064 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2065 clock-names = "main", "dma"; 2066 #address-cells = <1>; 2067 #size-cells = <0>; 2068 status = "disabled"; 2069 }; 2070 2071 imp_iic_wrap_w: clock-controller@11e02000 { 2072 compatible = "mediatek,mt8188-imp-iic-wrap-w"; 2073 reg = <0 0x11e02000 0 0x1000>; 2074 #clock-cells = <1>; 2075 }; 2076 2077 u3phy0: t-phy@11e30000 { 2078 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2079 #address-cells = <1>; 2080 #size-cells = <1>; 2081 ranges = <0x0 0x0 0x11e30000 0x1000>; 2082 status = "disabled"; 2083 2084 u2port0: usb-phy@0 { 2085 reg = <0x0 0x700>; 2086 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, 2087 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2088 clock-names = "ref", "da_ref"; 2089 #phy-cells = <1>; 2090 }; 2091 }; 2092 2093 u3phy1: t-phy@11e40000 { 2094 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2095 #address-cells = <1>; 2096 #size-cells = <1>; 2097 ranges = <0x0 0x0 0x11e40000 0x1000>; 2098 status = "disabled"; 2099 2100 u2port1: usb-phy@0 { 2101 reg = <0x0 0x700>; 2102 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 2103 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2104 clock-names = "ref", "da_ref"; 2105 #phy-cells = <1>; 2106 }; 2107 2108 u3port1: usb-phy@700 { 2109 reg = <0x700 0x700>; 2110 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, 2111 <&clk26m>; 2112 clock-names = "ref", "da_ref"; 2113 #phy-cells = <1>; 2114 }; 2115 }; 2116 2117 u3phy2: t-phy@11e80000 { 2118 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2119 #address-cells = <1>; 2120 #size-cells = <1>; 2121 ranges = <0x0 0x0 0x11e80000 0x1000>; 2122 status = "disabled"; 2123 2124 u2port2: usb-phy@0 { 2125 reg = <0x0 0x700>; 2126 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, 2127 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2128 clock-names = "ref", "da_ref"; 2129 #phy-cells = <1>; 2130 }; 2131 }; 2132 2133 i2c5: i2c@11ec0000 { 2134 compatible = "mediatek,mt8188-i2c"; 2135 reg = <0 0x11ec0000 0 0x1000>, 2136 <0 0x10220480 0 0x80>; 2137 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; 2138 clock-div = <1>; 2139 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, 2140 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2141 clock-names = "main", "dma"; 2142 #address-cells = <1>; 2143 #size-cells = <0>; 2144 status = "disabled"; 2145 }; 2146 2147 i2c6: i2c@11ec1000 { 2148 compatible = "mediatek,mt8188-i2c"; 2149 reg = <0 0x11ec1000 0 0x1000>, 2150 <0 0x10220600 0 0x80>; 2151 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 2152 clock-div = <1>; 2153 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, 2154 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2155 clock-names = "main", "dma"; 2156 #address-cells = <1>; 2157 #size-cells = <0>; 2158 status = "disabled"; 2159 }; 2160 2161 imp_iic_wrap_en: clock-controller@11ec2000 { 2162 compatible = "mediatek,mt8188-imp-iic-wrap-en"; 2163 reg = <0 0x11ec2000 0 0x1000>; 2164 #clock-cells = <1>; 2165 }; 2166 2167 efuse: efuse@11f20000 { 2168 compatible = "mediatek,mt8188-efuse", "mediatek,efuse"; 2169 reg = <0 0x11f20000 0 0x1000>; 2170 #address-cells = <1>; 2171 #size-cells = <1>; 2172 2173 dp_calib_data: dp-calib@1a0 { 2174 reg = <0x1a0 0xc>; 2175 }; 2176 2177 lvts_efuse_data1: lvts1-calib@1ac { 2178 reg = <0x1ac 0x40>; 2179 }; 2180 2181 gpu_speedbin: gpu-speedbin@581 { 2182 reg = <0x581 0x1>; 2183 bits = <0 3>; 2184 }; 2185 2186 socinfo-data1@7a0 { 2187 reg = <0x7a0 0x4>; 2188 }; 2189 2190 socinfo-data2@7e0 { 2191 reg = <0x7e0 0x4>; 2192 }; 2193 }; 2194 2195 gpu: gpu@13000000 { 2196 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; 2197 reg = <0 0x13000000 0 0x4000>; 2198 2199 clocks = <&mfgcfg CLK_MFGCFG_BG3D>; 2200 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 2201 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>, 2202 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>; 2203 interrupt-names = "job", "mmu", "gpu"; 2204 nvmem-cells = <&gpu_speedbin>; 2205 nvmem-cell-names = "speed-bin"; 2206 operating-points-v2 = <&gpu_opp_table>; 2207 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, 2208 <&spm MT8188_POWER_DOMAIN_MFG3>, 2209 <&spm MT8188_POWER_DOMAIN_MFG4>; 2210 power-domain-names = "core0", "core1", "core2"; 2211 #cooling-cells = <2>; 2212 status = "disabled"; 2213 }; 2214 2215 mfgcfg: clock-controller@13fbf000 { 2216 compatible = "mediatek,mt8188-mfgcfg"; 2217 reg = <0 0x13fbf000 0 0x1000>; 2218 #clock-cells = <1>; 2219 }; 2220 2221 vppsys0: syscon@14000000 { 2222 compatible = "mediatek,mt8188-vppsys0", "syscon"; 2223 reg = <0 0x14000000 0 0x1000>; 2224 #clock-cells = <1>; 2225 }; 2226 2227 vpp_smi_common: smi@14012000 { 2228 compatible = "mediatek,mt8188-smi-common-vpp"; 2229 reg = <0 0x14012000 0 0x1000>; 2230 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2231 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>; 2232 clock-names = "apb", "smi"; 2233 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2234 }; 2235 2236 larb4: smi@14013000 { 2237 compatible = "mediatek,mt8188-smi-larb"; 2238 reg = <0 0x14013000 0 0x1000>; 2239 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2240 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2241 clock-names = "apb", "smi"; 2242 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2243 mediatek,larb-id = <SMI_L4_ID>; 2244 mediatek,smi = <&vpp_smi_common>; 2245 }; 2246 2247 vpp_iommu: iommu@14018000 { 2248 compatible = "mediatek,mt8188-iommu-vpp"; 2249 reg = <0 0x14018000 0 0x5000>; 2250 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2251 clock-names = "bclk"; 2252 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2253 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2254 #iommu-cells = <1>; 2255 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>; 2256 }; 2257 2258 wpesys: clock-controller@14e00000 { 2259 compatible = "mediatek,mt8188-wpesys"; 2260 reg = <0 0x14e00000 0 0x1000>; 2261 #clock-cells = <1>; 2262 }; 2263 2264 wpesys_vpp0: clock-controller@14e02000 { 2265 compatible = "mediatek,mt8188-wpesys-vpp0"; 2266 reg = <0 0x14e02000 0 0x1000>; 2267 #clock-cells = <1>; 2268 }; 2269 2270 larb7: smi@14e04000 { 2271 compatible = "mediatek,mt8188-smi-larb"; 2272 reg = <0 0x14e04000 0 0x1000>; 2273 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 2274 <&wpesys CLK_WPE_TOP_SMI_LARB7>; 2275 clock-names = "apb", "smi"; 2276 power-domains = <&spm MT8188_POWER_DOMAIN_WPE>; 2277 mediatek,larb-id = <SMI_L7_ID>; 2278 mediatek,smi = <&vpp_smi_common>; 2279 }; 2280 2281 vppsys1: syscon@14f00000 { 2282 compatible = "mediatek,mt8188-vppsys1", "syscon"; 2283 reg = <0 0x14f00000 0 0x1000>; 2284 #clock-cells = <1>; 2285 }; 2286 2287 larb5: smi@14f02000 { 2288 compatible = "mediatek,mt8188-smi-larb"; 2289 reg = <0 0x14f02000 0 0x1000>; 2290 clocks = <&vppsys1 CLK_VPP1_GALS5>, 2291 <&vppsys1 CLK_VPP1_LARB5>; 2292 clock-names = "apb", "smi"; 2293 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2294 mediatek,larb-id = <SMI_L5_ID>; 2295 mediatek,smi = <&vdo_smi_common>; 2296 }; 2297 2298 larb6: smi@14f03000 { 2299 compatible = "mediatek,mt8188-smi-larb"; 2300 reg = <0 0x14f03000 0 0x1000>; 2301 clocks = <&vppsys1 CLK_VPP1_GALS6>, 2302 <&vppsys1 CLK_VPP1_LARB6>; 2303 clock-names = "apb", "smi"; 2304 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2305 mediatek,larb-id = <SMI_L6_ID>; 2306 mediatek,smi = <&vpp_smi_common>; 2307 }; 2308 2309 imgsys: clock-controller@15000000 { 2310 compatible = "mediatek,mt8188-imgsys"; 2311 reg = <0 0x15000000 0 0x1000>; 2312 #clock-cells = <1>; 2313 }; 2314 2315 imgsys1_dip_top: clock-controller@15110000 { 2316 compatible = "mediatek,mt8188-imgsys1-dip-top"; 2317 reg = <0 0x15110000 0 0x1000>; 2318 #clock-cells = <1>; 2319 }; 2320 2321 imgsys1_dip_nr: clock-controller@15130000 { 2322 compatible = "mediatek,mt8188-imgsys1-dip-nr"; 2323 reg = <0 0x15130000 0 0x1000>; 2324 #clock-cells = <1>; 2325 }; 2326 2327 imgsys_wpe1: clock-controller@15220000 { 2328 compatible = "mediatek,mt8188-imgsys-wpe1"; 2329 reg = <0 0x15220000 0 0x1000>; 2330 #clock-cells = <1>; 2331 }; 2332 2333 ipesys: clock-controller@15330000 { 2334 compatible = "mediatek,mt8188-ipesys"; 2335 reg = <0 0x15330000 0 0x1000>; 2336 #clock-cells = <1>; 2337 }; 2338 2339 imgsys_wpe2: clock-controller@15520000 { 2340 compatible = "mediatek,mt8188-imgsys-wpe2"; 2341 reg = <0 0x15520000 0 0x1000>; 2342 #clock-cells = <1>; 2343 }; 2344 2345 imgsys_wpe3: clock-controller@15620000 { 2346 compatible = "mediatek,mt8188-imgsys-wpe3"; 2347 reg = <0 0x15620000 0 0x1000>; 2348 #clock-cells = <1>; 2349 }; 2350 2351 camsys: clock-controller@16000000 { 2352 compatible = "mediatek,mt8188-camsys"; 2353 reg = <0 0x16000000 0 0x1000>; 2354 #clock-cells = <1>; 2355 }; 2356 2357 camsys_rawa: clock-controller@1604f000 { 2358 compatible = "mediatek,mt8188-camsys-rawa"; 2359 reg = <0 0x1604f000 0 0x1000>; 2360 #clock-cells = <1>; 2361 }; 2362 2363 camsys_yuva: clock-controller@1606f000 { 2364 compatible = "mediatek,mt8188-camsys-yuva"; 2365 reg = <0 0x1606f000 0 0x1000>; 2366 #clock-cells = <1>; 2367 }; 2368 2369 camsys_rawb: clock-controller@1608f000 { 2370 compatible = "mediatek,mt8188-camsys-rawb"; 2371 reg = <0 0x1608f000 0 0x1000>; 2372 #clock-cells = <1>; 2373 }; 2374 2375 camsys_yuvb: clock-controller@160af000 { 2376 compatible = "mediatek,mt8188-camsys-yuvb"; 2377 reg = <0 0x160af000 0 0x1000>; 2378 #clock-cells = <1>; 2379 }; 2380 2381 ccusys: clock-controller@17200000 { 2382 compatible = "mediatek,mt8188-ccusys"; 2383 reg = <0 0x17200000 0 0x1000>; 2384 #clock-cells = <1>; 2385 }; 2386 2387 video_decoder: video-decoder@18000000 { 2388 compatible = "mediatek,mt8188-vcodec-dec"; 2389 reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; 2390 ranges = <0 0 0 0x18000000 0 0x26000>; 2391 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; 2392 #address-cells = <2>; 2393 #size-cells = <2>; 2394 mediatek,scp = <&scp>; 2395 2396 video-codec@10000 { 2397 compatible = "mediatek,mtk-vcodec-lat"; 2398 reg = <0 0x10000 0 0x800>; 2399 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2400 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2401 clocks = <&topckgen CLK_TOP_VDEC>, 2402 <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, 2403 <&vdecsys_soc CLK_VDEC1_SOC_LAT>, 2404 <&topckgen CLK_TOP_UNIVPLL_D6>; 2405 clock-names = "sel", "vdec", "lat", "top"; 2406 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2407 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, 2408 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, 2409 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, 2410 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, 2411 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, 2412 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, 2413 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, 2414 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, 2415 <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; 2416 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2417 }; 2418 2419 video-codec@25000 { 2420 compatible = "mediatek,mtk-vcodec-core"; 2421 reg = <0 0x25000 0 0x1000>; 2422 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2423 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2424 clocks = <&topckgen CLK_TOP_VDEC>, 2425 <&vdecsys CLK_VDEC2_VDEC>, 2426 <&vdecsys CLK_VDEC2_LAT>, 2427 <&topckgen CLK_TOP_UNIVPLL_D6>; 2428 clock-names = "sel", "vdec", "lat", "top"; 2429 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2430 iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, 2431 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, 2432 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, 2433 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, 2434 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, 2435 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, 2436 <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, 2437 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, 2438 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, 2439 <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, 2440 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; 2441 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2442 }; 2443 }; 2444 2445 larb23: smi@1800d000 { 2446 compatible = "mediatek,mt8188-smi-larb"; 2447 reg = <0 0x1800d000 0 0x1000>; 2448 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>, 2449 <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 2450 clock-names = "apb", "smi"; 2451 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2452 mediatek,larb-id = <SMI_L23_ID>; 2453 mediatek,smi = <&vpp_smi_common>; 2454 }; 2455 2456 vdecsys_soc: clock-controller@1800f000 { 2457 compatible = "mediatek,mt8188-vdecsys-soc"; 2458 reg = <0 0x1800f000 0 0x1000>; 2459 #clock-cells = <1>; 2460 }; 2461 2462 larb21: smi@1802e000 { 2463 compatible = "mediatek,mt8188-smi-larb"; 2464 reg = <0 0x1802e000 0 0x1000>; 2465 clocks = <&vdecsys CLK_VDEC2_LARB1>, 2466 <&vdecsys CLK_VDEC2_LARB1>; 2467 clock-names = "apb", "smi"; 2468 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2469 mediatek,larb-id = <SMI_L21_ID>; 2470 mediatek,smi = <&vdo_smi_common>; 2471 }; 2472 2473 vdecsys: clock-controller@1802f000 { 2474 compatible = "mediatek,mt8188-vdecsys"; 2475 reg = <0 0x1802f000 0 0x1000>; 2476 #clock-cells = <1>; 2477 }; 2478 2479 vencsys: clock-controller@1a000000 { 2480 compatible = "mediatek,mt8188-vencsys"; 2481 reg = <0 0x1a000000 0 0x1000>; 2482 #clock-cells = <1>; 2483 }; 2484 2485 larb19: smi@1a010000 { 2486 compatible = "mediatek,mt8188-smi-larb"; 2487 reg = <0 0x1a010000 0 0x1000>; 2488 clocks = <&vencsys CLK_VENC1_VENC>, 2489 <&vencsys CLK_VENC1_VENC>; 2490 clock-names = "apb", "smi"; 2491 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2492 mediatek,larb-id = <SMI_L19_ID>; 2493 mediatek,smi = <&vdo_smi_common>; 2494 }; 2495 2496 video_encoder: video-encoder@1a020000 { 2497 compatible = "mediatek,mt8188-vcodec-enc"; 2498 reg = <0 0x1a020000 0 0x10000>; 2499 #address-cells = <2>; 2500 #size-cells = <2>; 2501 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2502 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2503 clocks = <&vencsys CLK_VENC1_VENC>; 2504 clock-names = "venc_sel"; 2505 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2506 iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, 2507 <&vdo_iommu M4U_PORT_L19_VENC_REC>, 2508 <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, 2509 <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, 2510 <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, 2511 <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, 2512 <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, 2513 <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, 2514 <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, 2515 <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, 2516 <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; 2517 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2518 mediatek,scp = <&scp>; 2519 }; 2520 2521 jpeg_encoder: jpeg-encoder@1a030000 { 2522 compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; 2523 reg = <0 0x1a030000 0 0x10000>; 2524 clocks = <&vencsys CLK_VENC1_JPGENC>; 2525 clock-names = "jpgenc"; 2526 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 2527 iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, 2528 <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, 2529 <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, 2530 <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; 2531 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2532 }; 2533 2534 jpeg_decoder: jpeg-decoder@1a040000 { 2535 compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; 2536 reg = <0 0x1a040000 0 0x10000>; 2537 clocks = <&vencsys CLK_VENC1_LARB>, 2538 <&vencsys CLK_VENC1_JPGDEC>; 2539 clock-names = "jpgdec-smi", "jpgdec"; 2540 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 2541 iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>, 2542 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>, 2543 <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>, 2544 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>, 2545 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>, 2546 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>; 2547 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2548 }; 2549 2550 ovl0: ovl@1c000000 { 2551 compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl"; 2552 reg = <0 0x1c000000 0 0x1000>; 2553 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2554 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2555 iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; 2556 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2557 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2558 2559 ports { 2560 #address-cells = <1>; 2561 #size-cells = <0>; 2562 2563 port@0 { 2564 reg = <0>; 2565 ovl0_in: endpoint { }; 2566 }; 2567 2568 port@1 { 2569 reg = <1>; 2570 ovl0_out: endpoint { 2571 remote-endpoint = <&rdma0_in>; 2572 }; 2573 }; 2574 }; 2575 }; 2576 2577 rdma0: rdma@1c002000 { 2578 compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; 2579 reg = <0 0x1c002000 0 0x1000>; 2580 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2581 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2582 iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; 2583 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2584 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2585 2586 ports { 2587 #address-cells = <1>; 2588 #size-cells = <0>; 2589 2590 port@0 { 2591 reg = <0>; 2592 rdma0_in: endpoint { 2593 remote-endpoint = <&ovl0_out>; 2594 }; 2595 }; 2596 2597 port@1 { 2598 reg = <1>; 2599 rdma0_out: endpoint { 2600 remote-endpoint = <&color0_in>; 2601 }; 2602 }; 2603 }; 2604 }; 2605 2606 color0: color@1c003000 { 2607 compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color"; 2608 reg = <0 0x1c003000 0 0x1000>; 2609 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2610 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2611 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2612 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2613 2614 ports { 2615 #address-cells = <1>; 2616 #size-cells = <0>; 2617 2618 port@0 { 2619 reg = <0>; 2620 color0_in: endpoint { 2621 remote-endpoint = <&rdma0_out>; 2622 }; 2623 }; 2624 2625 port@1 { 2626 reg = <1>; 2627 color0_out: endpoint { 2628 remote-endpoint = <&ccorr0_in>; 2629 }; 2630 }; 2631 }; 2632 }; 2633 2634 ccorr0: ccorr@1c004000 { 2635 compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2636 reg = <0 0x1c004000 0 0x1000>; 2637 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2638 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2639 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2640 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2641 2642 ports { 2643 #address-cells = <1>; 2644 #size-cells = <0>; 2645 2646 port@0 { 2647 reg = <0>; 2648 ccorr0_in: endpoint { 2649 remote-endpoint = <&color0_out>; 2650 }; 2651 }; 2652 2653 port@1 { 2654 reg = <1>; 2655 ccorr0_out: endpoint { 2656 remote-endpoint = <&aal0_in>; 2657 }; 2658 }; 2659 }; 2660 }; 2661 2662 aal0: aal@1c005000 { 2663 compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; 2664 reg = <0 0x1c005000 0 0x1000>; 2665 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2666 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2667 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2668 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2669 2670 ports { 2671 #address-cells = <1>; 2672 #size-cells = <0>; 2673 2674 port@0 { 2675 reg = <0>; 2676 aal0_in: endpoint { 2677 remote-endpoint = <&ccorr0_out>; 2678 }; 2679 }; 2680 2681 port@1 { 2682 reg = <1>; 2683 aal0_out: endpoint { 2684 remote-endpoint = <&gamma0_in>; 2685 }; 2686 }; 2687 }; 2688 }; 2689 2690 gamma0: gamma@1c006000 { 2691 compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma"; 2692 reg = <0 0x1c006000 0 0x1000>; 2693 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2694 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2695 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2696 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2697 2698 ports { 2699 #address-cells = <1>; 2700 #size-cells = <0>; 2701 2702 port@0 { 2703 reg = <0>; 2704 gamma0_in: endpoint { 2705 remote-endpoint = <&aal0_out>; 2706 }; 2707 }; 2708 2709 port@1 { 2710 reg = <1>; 2711 gamma0_out: endpoint { }; 2712 }; 2713 }; 2714 }; 2715 2716 dither0: dither@1c007000 { 2717 compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither"; 2718 reg = <0 0x1c007000 0 0x1000>; 2719 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2720 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2721 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2722 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2723 2724 ports { 2725 #address-cells = <1>; 2726 #size-cells = <0>; 2727 2728 port@0 { 2729 reg = <0>; 2730 dither0_in: endpoint { }; 2731 }; 2732 2733 port@1 { 2734 reg = <1>; 2735 dither0_out: endpoint { }; 2736 }; 2737 }; 2738 }; 2739 2740 disp_dsi0: dsi@1c008000 { 2741 compatible = "mediatek,mt8188-dsi"; 2742 reg = <0 0x1c008000 0 0x1000>; 2743 clocks = <&vdosys0 CLK_VDO0_DSI0>, 2744 <&vdosys0 CLK_VDO0_DSI0_DSI>, 2745 <&mipi_tx_config0>; 2746 clock-names = "engine", "digital", "hs"; 2747 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 2748 phys = <&mipi_tx_config0>; 2749 phy-names = "dphy"; 2750 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2751 resets = <&vdosys0 MT8188_VDO0_RST_DSI0>; 2752 status = "disabled"; 2753 }; 2754 2755 dsc0: dsc@1c009000 { 2756 compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc"; 2757 reg = <0 0x1c009000 0 0x1000>; 2758 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2759 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2760 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2761 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2762 }; 2763 2764 disp_dsi1: dsi@1c012000 { 2765 compatible = "mediatek,mt8188-dsi"; 2766 reg = <0 0x1c012000 0 0x1000>; 2767 clocks = <&vdosys0 CLK_VDO0_DSI1>, 2768 <&vdosys0 CLK_VDO0_DSI1_DSI>, 2769 <&mipi_tx_config1>; 2770 clock-names = "engine", "digital", "hs"; 2771 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 2772 phys = <&mipi_tx_config1>; 2773 phy-names = "dphy"; 2774 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2775 resets = <&vdosys0 MT8188_VDO0_RST_DSI1>; 2776 status = "disabled"; 2777 }; 2778 2779 merge0: merge0@1c014000 { 2780 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 2781 reg = <0 0x1c014000 0 0x1000>; 2782 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>, 2783 <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>; 2784 clock-names = "merge", "merge_async"; 2785 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2786 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2787 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2788 }; 2789 2790 dp_intf0: dp-intf@1c015000 { 2791 compatible = "mediatek,mt8188-dp-intf"; 2792 reg = <0 0x1c015000 0 0x1000>; 2793 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2794 <&vdosys0 CLK_VDO0_DP_INTF0>, 2795 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2796 clock-names = "pixel", "engine", "pll"; 2797 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2798 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2799 status = "disabled"; 2800 }; 2801 2802 mutex0: mutex@1c016000 { 2803 compatible = "mediatek,mt8188-disp-mutex"; 2804 reg = <0 0x1c016000 0 0x1000>; 2805 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2806 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2807 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2808 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 2809 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2810 }; 2811 2812 postmask0: postmask@1c01a000 { 2813 compatible = "mediatek,mt8188-disp-postmask", 2814 "mediatek,mt8192-disp-postmask"; 2815 reg = <0 0x1c01a000 0 0x1000>; 2816 clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; 2817 interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>; 2818 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2819 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 2820 2821 ports { 2822 #address-cells = <1>; 2823 #size-cells = <0>; 2824 2825 port@0 { 2826 reg = <0>; 2827 postmask0_in: endpoint { }; 2828 }; 2829 2830 port@1 { 2831 reg = <1>; 2832 postmask0_out: endpoint { }; 2833 }; 2834 }; 2835 }; 2836 2837 vdosys0: syscon@1c01d000 { 2838 compatible = "mediatek,mt8188-vdosys0", "syscon"; 2839 reg = <0 0x1c01d000 0 0x1000>; 2840 #clock-cells = <1>; 2841 #reset-cells = <1>; 2842 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2843 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; 2844 }; 2845 2846 larb0: smi@1c022000 { 2847 compatible = "mediatek,mt8188-smi-larb"; 2848 reg = <0 0x1c022000 0 0x1000>; 2849 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2850 <&vdosys0 CLK_VDO0_SMI_LARB>; 2851 clock-names = "apb", "smi"; 2852 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2853 mediatek,larb-id = <SMI_L0_ID>; 2854 mediatek,smi = <&vdo_smi_common>; 2855 }; 2856 2857 larb1: smi@1c023000 { 2858 compatible = "mediatek,mt8188-smi-larb"; 2859 reg = <0 0x1c023000 0 0x1000>; 2860 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2861 <&vdosys0 CLK_VDO0_SMI_LARB>; 2862 clock-names = "apb", "smi"; 2863 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2864 mediatek,larb-id = <SMI_L1_ID>; 2865 mediatek,smi = <&vpp_smi_common>; 2866 }; 2867 2868 vdo_smi_common: smi@1c024000 { 2869 compatible = "mediatek,mt8188-smi-common-vdo"; 2870 reg = <0 0x1c024000 0 0x1000>; 2871 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2872 <&vdosys0 CLK_VDO0_SMI_GALS>; 2873 clock-names = "apb", "smi"; 2874 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2875 }; 2876 2877 vdo_iommu: iommu@1c028000 { 2878 compatible = "mediatek,mt8188-iommu-vdo"; 2879 reg = <0 0x1c028000 0 0x5000>; 2880 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2881 clock-names = "bclk"; 2882 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; 2883 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2884 #iommu-cells = <1>; 2885 mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>; 2886 }; 2887 2888 vdosys1: syscon@1c100000 { 2889 compatible = "mediatek,mt8188-vdosys1", "syscon"; 2890 reg = <0 0x1c100000 0 0x1000>; 2891 #clock-cells = <1>; 2892 #reset-cells = <1>; 2893 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 2894 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; 2895 }; 2896 2897 mutex1: mutex@1c101000 { 2898 compatible = "mediatek,mt8188-disp-mutex"; 2899 reg = <0 0x1c101000 0 0x1000>; 2900 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 2901 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 2902 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2903 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 2904 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 2905 }; 2906 2907 larb2: smi@1c102000 { 2908 compatible = "mediatek,mt8188-smi-larb"; 2909 reg = <0 0x1c102000 0 0x1000>; 2910 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2911 <&vdosys1 CLK_VDO1_SMI_LARB2>; 2912 clock-names = "apb", "smi"; 2913 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2914 mediatek,larb-id = <SMI_L2_ID>; 2915 mediatek,smi = <&vdo_smi_common>; 2916 }; 2917 2918 larb3: smi@1c103000 { 2919 compatible = "mediatek,mt8188-smi-larb"; 2920 reg = <0 0x1c103000 0 0x1000>; 2921 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2922 <&vdosys1 CLK_VDO1_SMI_LARB3>; 2923 clock-names = "apb", "smi"; 2924 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2925 mediatek,larb-id = <SMI_L3_ID>; 2926 mediatek,smi = <&vpp_smi_common>; 2927 }; 2928 2929 vdo1_rdma0: rdma@1c104000 { 2930 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2931 reg = <0 0x1c104000 0 0x1000>; 2932 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 2933 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 2934 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; 2935 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2936 #dma-cells = <1>; 2937 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 2938 }; 2939 2940 vdo1_rdma1: rdma@1c105000 { 2941 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2942 reg = <0 0x1c105000 0 0x1000>; 2943 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 2944 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 2945 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; 2946 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2947 #dma-cells = <1>; 2948 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 2949 }; 2950 2951 vdo1_rdma2: rdma@1c106000 { 2952 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2953 reg = <0 0x1c106000 0 0x1000>; 2954 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 2955 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 2956 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; 2957 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2958 #dma-cells = <1>; 2959 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 2960 }; 2961 2962 vdo1_rdma3: rdma@1c107000 { 2963 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2964 reg = <0 0x1c107000 0 0x1000>; 2965 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 2966 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 2967 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; 2968 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2969 #dma-cells = <1>; 2970 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 2971 }; 2972 2973 vdo1_rdma4: rdma@1c108000 { 2974 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2975 reg = <0 0x1c108000 0 0x1000>; 2976 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 2977 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 2978 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; 2979 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2980 #dma-cells = <1>; 2981 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 2982 }; 2983 2984 vdo1_rdma5: rdma@1c109000 { 2985 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2986 reg = <0 0x1c109000 0 0x1000>; 2987 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 2988 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 2989 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; 2990 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2991 #dma-cells = <1>; 2992 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 2993 }; 2994 2995 vdo1_rdma6: rdma@1c10a000 { 2996 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2997 reg = <0 0x1c10a000 0 0x1000>; 2998 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 2999 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3000 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; 3001 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3002 #dma-cells = <1>; 3003 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3004 }; 3005 3006 vdo1_rdma7: rdma@1c10b000 { 3007 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3008 reg = <0 0x1c10b000 0 0x1000>; 3009 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3010 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3011 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; 3012 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3013 #dma-cells = <1>; 3014 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3015 }; 3016 3017 merge1: merge@1c10c000 { 3018 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3019 reg = <0 0x1c10c000 0 0x1000>; 3020 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3021 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3022 clock-names = "merge", "merge_async"; 3023 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3024 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3025 resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; 3026 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3027 mediatek,merge-mute; 3028 }; 3029 3030 merge2: merge@1c10d000 { 3031 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3032 reg = <0 0x1c10d000 0 0x1000>; 3033 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3034 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3035 clock-names = "merge", "merge_async"; 3036 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3037 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3038 resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; 3039 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3040 mediatek,merge-mute; 3041 }; 3042 3043 merge3: merge@1c10e000 { 3044 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3045 reg = <0 0x1c10e000 0 0x1000>; 3046 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3047 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3048 clock-names = "merge", "merge_async"; 3049 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3050 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3051 resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; 3052 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3053 mediatek,merge-mute; 3054 }; 3055 3056 merge4: merge@1c10f000 { 3057 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3058 reg = <0 0x1c10f000 0 0x1000>; 3059 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3060 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3061 clock-names = "merge", "merge_async"; 3062 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3063 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3064 resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; 3065 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3066 mediatek,merge-mute; 3067 }; 3068 3069 merge5: merge@1c110000 { 3070 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3071 reg = <0 0x1c110000 0 0x1000>; 3072 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3073 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3074 clock-names = "merge", "merge_async"; 3075 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3076 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3077 resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; 3078 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3079 mediatek,merge-fifo-en; 3080 }; 3081 3082 dp_intf1: dp-intf@1c113000 { 3083 compatible = "mediatek,mt8188-dp-intf"; 3084 reg = <0 0x1c113000 0 0x1000>; 3085 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3086 <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>, 3087 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3088 clock-names = "pixel", "engine", "pll"; 3089 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3090 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3091 status = "disabled"; 3092 }; 3093 3094 ethdr0: ethdr@1c114000 { 3095 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr"; 3096 reg = <0 0x1c114000 0 0x1000>, 3097 <0 0x1c115000 0 0x1000>, 3098 <0 0x1c117000 0 0x1000>, 3099 <0 0x1c119000 0 0x1000>, 3100 <0 0x1c11a000 0 0x1000>, 3101 <0 0x1c11b000 0 0x1000>, 3102 <0 0x1c11c000 0 0x1000>; 3103 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3104 "vdo_be", "adl_ds"; 3105 3106 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3107 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3108 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3109 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3110 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3111 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3112 <&vdosys1 CLK_VDO1_26M_SLOW>, 3113 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3114 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3115 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3116 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3117 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3118 <&topckgen CLK_TOP_ETHDR>; 3119 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3120 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3121 "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; 3122 3123 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>; 3124 iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, 3125 <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; 3126 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3127 resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, 3128 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, 3129 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, 3130 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, 3131 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; 3132 3133 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3134 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3135 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3136 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3137 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3138 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3139 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3140 }; 3141 3142 padding0: padding@1c11d000 { 3143 compatible = "mediatek,mt8188-disp-padding"; 3144 reg = <0 0x1c11d000 0 0x1000>; 3145 clocks = <&vdosys1 CLK_VDO1_PADDING0>; 3146 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3147 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; 3148 }; 3149 3150 padding1: padding@1c11e000 { 3151 compatible = "mediatek,mt8188-disp-padding"; 3152 reg = <0 0x1c11e000 0 0x1000>; 3153 clocks = <&vdosys1 CLK_VDO1_PADDING1>; 3154 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3155 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; 3156 }; 3157 3158 padding2: padding@1c11f000 { 3159 compatible = "mediatek,mt8188-disp-padding"; 3160 reg = <0 0x1c11f000 0 0x1000>; 3161 clocks = <&vdosys1 CLK_VDO1_PADDING2>; 3162 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3163 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; 3164 }; 3165 3166 padding3: padding@1c120000 { 3167 compatible = "mediatek,mt8188-disp-padding"; 3168 reg = <0 0x1c120000 0 0x1000>; 3169 clocks = <&vdosys1 CLK_VDO1_PADDING3>; 3170 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3171 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; 3172 }; 3173 3174 padding4: padding@1c121000 { 3175 compatible = "mediatek,mt8188-disp-padding"; 3176 reg = <0 0x1c121000 0 0x1000>; 3177 clocks = <&vdosys1 CLK_VDO1_PADDING4>; 3178 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3179 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; 3180 }; 3181 3182 padding5: padding@1c122000 { 3183 compatible = "mediatek,mt8188-disp-padding"; 3184 reg = <0 0x1c122000 0 0x1000>; 3185 clocks = <&vdosys1 CLK_VDO1_PADDING5>; 3186 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3187 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; 3188 }; 3189 3190 padding6: padding@1c123000 { 3191 compatible = "mediatek,mt8188-disp-padding"; 3192 reg = <0 0x1c123000 0 0x1000>; 3193 clocks = <&vdosys1 CLK_VDO1_PADDING6>; 3194 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3195 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; 3196 }; 3197 3198 padding7: padding@1c124000 { 3199 compatible = "mediatek,mt8188-disp-padding"; 3200 reg = <0 0x1c124000 0 0x1000>; 3201 clocks = <&vdosys1 CLK_VDO1_PADDING7>; 3202 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3203 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; 3204 }; 3205 3206 edp_tx: edp-tx@1c500000 { 3207 compatible = "mediatek,mt8188-edp-tx"; 3208 reg = <0 0x1c500000 0 0x8000>; 3209 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3210 nvmem-cells = <&dp_calib_data>; 3211 nvmem-cell-names = "dp_calibration_data"; 3212 power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>; 3213 max-linkrate-mhz = <8100>; 3214 status = "disabled"; 3215 }; 3216 3217 dp_tx: dp-tx@1c600000 { 3218 compatible = "mediatek,mt8188-dp-tx"; 3219 reg = <0 0x1c600000 0 0x8000>; 3220 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3221 nvmem-cells = <&dp_calib_data>; 3222 nvmem-cell-names = "dp_calibration_data"; 3223 power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>; 3224 max-linkrate-mhz = <5400>; 3225 status = "disabled"; 3226 }; 3227 }; 3228}; 3229