xref: /qemu/hw/vfio/pci.h (revision 7be29f2f1a3f5b037d27eedbd5df9f441e8c8c16)
1 /*
2  * vfio based device assignment support - PCI devices
3  *
4  * Copyright Red Hat, Inc. 2012-2015
5  *
6  * Authors:
7  *  Alex Williamson <alex.williamson@redhat.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2.  See
10  * the COPYING file in the top-level directory.
11  */
12 #ifndef HW_VFIO_VFIO_PCI_H
13 #define HW_VFIO_VFIO_PCI_H
14 
15 #include "system/memory.h"
16 #include "hw/pci/pci_device.h"
17 #include "hw/vfio/vfio-device.h"
18 #include "hw/vfio/vfio-region.h"
19 #include "qemu/event_notifier.h"
20 #include "qemu/queue.h"
21 #include "qemu/timer.h"
22 #include "qom/object.h"
23 #include "system/kvm.h"
24 #include "vfio-display.h"
25 
26 #define PCI_ANY_ID (~0)
27 
28 struct VFIOPCIDevice;
29 
30 typedef struct VFIOIOEventFD {
31     QLIST_ENTRY(VFIOIOEventFD) next;
32     MemoryRegion *mr;
33     hwaddr addr;
34     unsigned size;
35     uint64_t data;
36     EventNotifier e;
37     VFIORegion *region;
38     hwaddr region_addr;
39     bool dynamic; /* Added runtime, removed on device reset */
40     bool vfio;
41 } VFIOIOEventFD;
42 
43 typedef struct VFIOQuirk {
44     QLIST_ENTRY(VFIOQuirk) next;
45     void *data;
46     QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
47     int nr_mem;
48     MemoryRegion *mem;
49     void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk);
50 } VFIOQuirk;
51 
52 typedef struct VFIOBAR {
53     VFIORegion region;
54     MemoryRegion *mr;
55     size_t size;
56     uint8_t type;
57     bool ioport;
58     bool mem64;
59     QLIST_HEAD(, VFIOQuirk) quirks;
60 } VFIOBAR;
61 
62 typedef struct VFIOVGARegion {
63     MemoryRegion mem;
64     off_t offset;
65     int nr;
66     QLIST_HEAD(, VFIOQuirk) quirks;
67 } VFIOVGARegion;
68 
69 typedef struct VFIOVGA {
70     off_t fd_offset;
71     int fd;
72     VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
73 } VFIOVGA;
74 
75 typedef struct VFIOINTx {
76     bool pending; /* interrupt pending */
77     bool kvm_accel; /* set when QEMU bypass through KVM enabled */
78     uint8_t pin; /* which pin to pull for qemu_set_irq */
79     EventNotifier interrupt; /* eventfd triggered on interrupt */
80     EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
81     PCIINTxRoute route; /* routing info for QEMU bypass */
82     uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
83     QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */
84 } VFIOINTx;
85 
86 typedef struct VFIOMSIVector {
87     /*
88      * Two interrupt paths are configured per vector.  The first, is only used
89      * for interrupts injected via QEMU.  This is typically the non-accel path,
90      * but may also be used when we want QEMU to handle masking and pending
91      * bits.  The KVM path bypasses QEMU and is therefore higher performance,
92      * but requires masking at the device.  virq is used to track the MSI route
93      * through KVM, thus kvm_interrupt is only available when virq is set to a
94      * valid (>= 0) value.
95      */
96     EventNotifier interrupt;
97     EventNotifier kvm_interrupt;
98     struct VFIOPCIDevice *vdev; /* back pointer to device */
99     int virq;
100     bool use;
101 } VFIOMSIVector;
102 
103 enum {
104     VFIO_INT_NONE = 0,
105     VFIO_INT_INTx = 1,
106     VFIO_INT_MSI  = 2,
107     VFIO_INT_MSIX = 3,
108 };
109 
110 /* Cache of MSI-X setup */
111 typedef struct VFIOMSIXInfo {
112     uint8_t table_bar;
113     uint8_t pba_bar;
114     uint16_t entries;
115     uint32_t table_offset;
116     uint32_t pba_offset;
117     unsigned long *pending;
118     bool noresize;
119 } VFIOMSIXInfo;
120 
121 /*
122  * TYPE_VFIO_PCI_BASE is an abstract type used to share code
123  * between VFIO implementations that use a kernel driver
124  * with those that use user sockets.
125  */
126 #define TYPE_VFIO_PCI_BASE "vfio-pci-base"
127 OBJECT_DECLARE_SIMPLE_TYPE(VFIOPCIDevice, VFIO_PCI_BASE)
128 
129 #define TYPE_VFIO_PCI "vfio-pci"
130 /* TYPE_VFIO_PCI shares struct VFIOPCIDevice. */
131 
132 struct VFIOPCIDevice {
133     PCIDevice pdev;
134     VFIODevice vbasedev;
135     VFIOINTx intx;
136     unsigned int config_size;
137     uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */
138     off_t config_offset; /* Offset of config space region within device fd */
139     unsigned int rom_size;
140     off_t rom_offset; /* Offset of ROM region within device fd */
141     void *rom;
142     int msi_cap_size;
143     VFIOMSIVector *msi_vectors;
144     VFIOMSIXInfo *msix;
145     int nr_vectors; /* Number of MSI/MSIX vectors currently in use */
146     int interrupt; /* Current interrupt type */
147     VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */
148     VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */
149     void *igd_opregion;
150     PCIHostDeviceAddress host;
151     QemuUUID vf_token;
152     EventNotifier err_notifier;
153     EventNotifier req_notifier;
154     int (*resetfn)(struct VFIOPCIDevice *);
155     uint32_t vendor_id;
156     uint32_t device_id;
157     uint32_t sub_vendor_id;
158     uint32_t sub_device_id;
159     uint32_t features;
160 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
161 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
162 #define VFIO_FEATURE_ENABLE_REQ_BIT 1
163 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
164 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
165 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \
166                                 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
167 #define VFIO_FEATURE_ENABLE_IGD_LPC_BIT 3
168 #define VFIO_FEATURE_ENABLE_IGD_LPC \
169                                 (1 << VFIO_FEATURE_ENABLE_IGD_LPC_BIT)
170     OnOffAuto display;
171     uint32_t display_xres;
172     uint32_t display_yres;
173     int32_t bootindex;
174     OnOffAuto igd_legacy_mode;
175     uint32_t igd_gms;
176     OffAutoPCIBAR msix_relo;
177     uint8_t nv_gpudirect_clique;
178     bool pci_aer;
179     bool req_enabled;
180     bool has_flr;
181     bool has_pm_reset;
182     bool rom_read_failed;
183     bool no_kvm_intx;
184     bool no_kvm_msi;
185     bool no_kvm_msix;
186     bool no_geforce_quirks;
187     bool no_kvm_ioeventfd;
188     bool no_vfio_ioeventfd;
189     bool enable_ramfb;
190     OnOffAuto ramfb_migrate;
191     bool defer_kvm_irq_routing;
192     bool clear_parent_atomics_on_exit;
193     bool skip_vsc_check;
194     VFIODisplay *dpy;
195     Notifier irqchip_change_notifier;
196 };
197 
198 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */
vfio_pci_is(VFIOPCIDevice * vdev,uint32_t vendor,uint32_t device)199 static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device)
200 {
201     return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) &&
202            (device == PCI_ANY_ID || device == vdev->device_id);
203 }
204 
vfio_is_vga(VFIOPCIDevice * vdev)205 static inline bool vfio_is_vga(VFIOPCIDevice *vdev)
206 {
207     PCIDevice *pdev = &vdev->pdev;
208     uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
209 
210     return class == PCI_CLASS_DISPLAY_VGA;
211 }
212 
213 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
214 void vfio_pci_write_config(PCIDevice *pdev,
215                            uint32_t addr, uint32_t val, int len);
216 
217 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
218 void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);
219 
220 bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev);
221 bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp);
222 void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
223 void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
224 void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
225 void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
226 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
227 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
228 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
229 bool vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
230 void vfio_quirk_reset(VFIOPCIDevice *vdev);
231 VFIOQuirk *vfio_quirk_alloc(int nr_mem);
232 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr);
233 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp);
234 
235 extern const PropertyInfo qdev_prop_nv_gpudirect_clique;
236 
237 void vfio_pci_pre_reset(VFIOPCIDevice *vdev);
238 void vfio_pci_post_reset(VFIOPCIDevice *vdev);
239 bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name);
240 int vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice *vdev,
241                                     struct vfio_pci_hot_reset_info **info_p);
242 
243 bool vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp);
244 
245 void vfio_display_reset(VFIOPCIDevice *vdev);
246 bool vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
247 void vfio_display_finalize(VFIOPCIDevice *vdev);
248 
249 extern const VMStateDescription vfio_display_vmstate;
250 
251 #endif /* HW_VFIO_VFIO_PCI_H */
252