1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019 Intel Corporation */
3
4 #include <linux/gpio/driver.h>
5 #include <linux/module.h>
6 #include <linux/of.h>
7 #include <linux/of_address.h>
8 #include <linux/of_irq.h>
9 #include <linux/pinctrl/pinctrl.h>
10 #include <linux/pinctrl/pinconf.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinmux.h>
13 #include <linux/platform_device.h>
14 #include <linux/property.h>
15
16 #include "core.h"
17 #include "pinconf.h"
18 #include "pinmux.h"
19 #include "pinctrl-equilibrium.h"
20
21 #define PIN_NAME_FMT "io-%d"
22 #define PIN_NAME_LEN 10
23 #define PAD_REG_OFF 0x100
24
eqbr_gpio_disable_irq(struct irq_data * d)25 static void eqbr_gpio_disable_irq(struct irq_data *d)
26 {
27 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
28 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
29 unsigned int offset = irqd_to_hwirq(d);
30 unsigned long flags;
31
32 raw_spin_lock_irqsave(&gctrl->lock, flags);
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
35 gpiochip_disable_irq(gc, offset);
36 }
37
eqbr_gpio_enable_irq(struct irq_data * d)38 static void eqbr_gpio_enable_irq(struct irq_data *d)
39 {
40 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
41 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
42 unsigned int offset = irqd_to_hwirq(d);
43 unsigned long flags;
44
45 gc->direction_input(gc, offset);
46 gpiochip_enable_irq(gc, offset);
47 raw_spin_lock_irqsave(&gctrl->lock, flags);
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
49 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
50 }
51
eqbr_gpio_ack_irq(struct irq_data * d)52 static void eqbr_gpio_ack_irq(struct irq_data *d)
53 {
54 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
55 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
56 unsigned int offset = irqd_to_hwirq(d);
57 unsigned long flags;
58
59 raw_spin_lock_irqsave(&gctrl->lock, flags);
60 writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
61 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
62 }
63
eqbr_gpio_mask_ack_irq(struct irq_data * d)64 static void eqbr_gpio_mask_ack_irq(struct irq_data *d)
65 {
66 eqbr_gpio_disable_irq(d);
67 eqbr_gpio_ack_irq(d);
68 }
69
eqbr_cfg_bit(void __iomem * addr,unsigned int offset,unsigned int set)70 static inline void eqbr_cfg_bit(void __iomem *addr,
71 unsigned int offset, unsigned int set)
72 {
73 if (set)
74 writel(readl(addr) | BIT(offset), addr);
75 else
76 writel(readl(addr) & ~BIT(offset), addr);
77 }
78
eqbr_irq_type_cfg(struct gpio_irq_type * type,struct eqbr_gpio_ctrl * gctrl,unsigned int offset)79 static int eqbr_irq_type_cfg(struct gpio_irq_type *type,
80 struct eqbr_gpio_ctrl *gctrl,
81 unsigned int offset)
82 {
83 unsigned long flags;
84
85 raw_spin_lock_irqsave(&gctrl->lock, flags);
86 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);
87 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);
88 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);
89 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
90
91 return 0;
92 }
93
eqbr_gpio_set_irq_type(struct irq_data * d,unsigned int type)94 static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type)
95 {
96 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
97 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
98 unsigned int offset = irqd_to_hwirq(d);
99 struct gpio_irq_type it;
100
101 memset(&it, 0, sizeof(it));
102
103 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
104 return 0;
105
106 switch (type) {
107 case IRQ_TYPE_EDGE_RISING:
108 it.trig_type = GPIO_EDGE_TRIG;
109 it.edge_type = GPIO_SINGLE_EDGE;
110 it.logic_type = GPIO_POSITIVE_TRIG;
111 break;
112
113 case IRQ_TYPE_EDGE_FALLING:
114 it.trig_type = GPIO_EDGE_TRIG;
115 it.edge_type = GPIO_SINGLE_EDGE;
116 it.logic_type = GPIO_NEGATIVE_TRIG;
117 break;
118
119 case IRQ_TYPE_EDGE_BOTH:
120 it.trig_type = GPIO_EDGE_TRIG;
121 it.edge_type = GPIO_BOTH_EDGE;
122 it.logic_type = GPIO_POSITIVE_TRIG;
123 break;
124
125 case IRQ_TYPE_LEVEL_HIGH:
126 it.trig_type = GPIO_LEVEL_TRIG;
127 it.edge_type = GPIO_SINGLE_EDGE;
128 it.logic_type = GPIO_POSITIVE_TRIG;
129 break;
130
131 case IRQ_TYPE_LEVEL_LOW:
132 it.trig_type = GPIO_LEVEL_TRIG;
133 it.edge_type = GPIO_SINGLE_EDGE;
134 it.logic_type = GPIO_NEGATIVE_TRIG;
135 break;
136
137 default:
138 return -EINVAL;
139 }
140
141 eqbr_irq_type_cfg(&it, gctrl, offset);
142 if (it.trig_type == GPIO_EDGE_TRIG)
143 irq_set_handler_locked(d, handle_edge_irq);
144 else
145 irq_set_handler_locked(d, handle_level_irq);
146
147 return 0;
148 }
149
eqbr_irq_handler(struct irq_desc * desc)150 static void eqbr_irq_handler(struct irq_desc *desc)
151 {
152 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
153 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
154 struct irq_chip *ic = irq_desc_get_chip(desc);
155 unsigned long pins, offset;
156
157 chained_irq_enter(ic, desc);
158 pins = readl(gctrl->membase + GPIO_IRNCR);
159
160 for_each_set_bit(offset, &pins, gc->ngpio)
161 generic_handle_domain_irq(gc->irq.domain, offset);
162
163 chained_irq_exit(ic, desc);
164 }
165
166 static const struct irq_chip eqbr_irq_chip = {
167 .name = "gpio_irq",
168 .irq_mask = eqbr_gpio_disable_irq,
169 .irq_unmask = eqbr_gpio_enable_irq,
170 .irq_ack = eqbr_gpio_ack_irq,
171 .irq_mask_ack = eqbr_gpio_mask_ack_irq,
172 .irq_set_type = eqbr_gpio_set_irq_type,
173 .flags = IRQCHIP_IMMUTABLE,
174 GPIOCHIP_IRQ_RESOURCE_HELPERS,
175 };
176
gpiochip_setup(struct device * dev,struct eqbr_gpio_ctrl * gctrl)177 static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
178 {
179 struct gpio_irq_chip *girq;
180 struct gpio_chip *gc;
181
182 gc = &gctrl->chip;
183 gc->label = gctrl->name;
184 gc->fwnode = gctrl->fwnode;
185 gc->request = gpiochip_generic_request;
186 gc->free = gpiochip_generic_free;
187
188 if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) {
189 dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
190 gctrl->name);
191 return 0;
192 }
193
194 girq = &gctrl->chip.irq;
195 gpio_irq_chip_set_chip(girq, &eqbr_irq_chip);
196 girq->parent_handler = eqbr_irq_handler;
197 girq->num_parents = 1;
198 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);
199 if (!girq->parents)
200 return -ENOMEM;
201
202 girq->default_type = IRQ_TYPE_NONE;
203 girq->handler = handle_bad_irq;
204 girq->parents[0] = gctrl->virq;
205
206 return 0;
207 }
208
gpiolib_reg(struct eqbr_pinctrl_drv_data * drvdata)209 static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata)
210 {
211 struct device *dev = drvdata->dev;
212 struct eqbr_gpio_ctrl *gctrl;
213 struct device_node *np;
214 struct resource res;
215 int i, ret;
216
217 for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {
218 gctrl = drvdata->gpio_ctrls + i;
219 np = to_of_node(gctrl->fwnode);
220
221 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
222 if (!gctrl->name)
223 return -ENOMEM;
224
225 if (of_address_to_resource(np, 0, &res)) {
226 dev_err(dev, "Failed to get GPIO register address\n");
227 return -ENXIO;
228 }
229
230 gctrl->membase = devm_ioremap_resource(dev, &res);
231 if (IS_ERR(gctrl->membase))
232 return PTR_ERR(gctrl->membase);
233
234 gctrl->virq = irq_of_parse_and_map(np, 0);
235 if (!gctrl->virq) {
236 dev_err(dev, "%s: failed to parse and map irq\n",
237 gctrl->name);
238 return -ENXIO;
239 }
240 raw_spin_lock_init(&gctrl->lock);
241
242 ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
243 gctrl->membase + GPIO_IN,
244 gctrl->membase + GPIO_OUTSET,
245 gctrl->membase + GPIO_OUTCLR,
246 gctrl->membase + GPIO_DIR,
247 NULL, 0);
248 if (ret) {
249 dev_err(dev, "unable to init generic GPIO\n");
250 return ret;
251 }
252
253 ret = gpiochip_setup(dev, gctrl);
254 if (ret)
255 return ret;
256
257 ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);
258 if (ret)
259 return ret;
260 }
261
262 return 0;
263 }
264
265 static inline struct eqbr_pin_bank
find_pinbank_via_pin(struct eqbr_pinctrl_drv_data * pctl,unsigned int pin)266 *find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin)
267 {
268 struct eqbr_pin_bank *bank;
269 int i;
270
271 for (i = 0; i < pctl->nr_banks; i++) {
272 bank = &pctl->pin_banks[i];
273 if (pin >= bank->pin_base &&
274 (pin - bank->pin_base) < bank->nr_pins)
275 return bank;
276 }
277
278 return NULL;
279 }
280
281 static const struct pinctrl_ops eqbr_pctl_ops = {
282 .get_groups_count = pinctrl_generic_get_group_count,
283 .get_group_name = pinctrl_generic_get_group_name,
284 .get_group_pins = pinctrl_generic_get_group_pins,
285 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
286 .dt_free_map = pinconf_generic_dt_free_map,
287 };
288
eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data * pctl,unsigned int pmx,unsigned int pin)289 static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl,
290 unsigned int pmx, unsigned int pin)
291 {
292 struct eqbr_pin_bank *bank;
293 unsigned long flags;
294 unsigned int offset;
295 void __iomem *mem;
296
297 bank = find_pinbank_via_pin(pctl, pin);
298 if (!bank) {
299 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
300 return -ENODEV;
301 }
302 mem = bank->membase;
303 offset = pin - bank->pin_base;
304
305 if (!(bank->aval_pinmap & BIT(offset))) {
306 dev_err(pctl->dev,
307 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
308 pin, bank->pin_base, bank->aval_pinmap);
309 return -ENODEV;
310 }
311
312 raw_spin_lock_irqsave(&pctl->lock, flags);
313 writel(pmx, mem + (offset * 4));
314 raw_spin_unlock_irqrestore(&pctl->lock, flags);
315 return 0;
316 }
317
eqbr_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)318 static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev,
319 unsigned int selector, unsigned int group)
320 {
321 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
322 struct function_desc *func;
323 struct group_desc *grp;
324 unsigned int *pinmux;
325 int i;
326
327 func = pinmux_generic_get_function(pctldev, selector);
328 if (!func)
329 return -EINVAL;
330
331 grp = pinctrl_generic_get_group(pctldev, group);
332 if (!grp)
333 return -EINVAL;
334
335 pinmux = grp->data;
336 for (i = 0; i < grp->grp.npins; i++)
337 eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]);
338
339 return 0;
340 }
341
eqbr_pinmux_gpio_request(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin)342 static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev,
343 struct pinctrl_gpio_range *range,
344 unsigned int pin)
345 {
346 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
347
348 return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin);
349 }
350
351 static const struct pinmux_ops eqbr_pinmux_ops = {
352 .get_functions_count = pinmux_generic_get_function_count,
353 .get_function_name = pinmux_generic_get_function_name,
354 .get_function_groups = pinmux_generic_get_function_groups,
355 .set_mux = eqbr_pinmux_set_mux,
356 .gpio_request_enable = eqbr_pinmux_gpio_request,
357 .strict = true,
358 };
359
get_drv_cur(void __iomem * mem,unsigned int offset)360 static int get_drv_cur(void __iomem *mem, unsigned int offset)
361 {
362 unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/
363 unsigned int pin_offset = offset % DRV_CUR_PINS;
364
365 return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset);
366 }
367
368 static struct eqbr_gpio_ctrl
get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data * pctl,struct eqbr_pin_bank * bank)369 *get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl,
370 struct eqbr_pin_bank *bank)
371 {
372 int i;
373
374 for (i = 0; i < pctl->nr_gpio_ctrls; i++) {
375 if (pctl->gpio_ctrls[i].bank == bank)
376 return &pctl->gpio_ctrls[i];
377 }
378
379 return NULL;
380 }
381
eqbr_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)382 static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
383 unsigned long *config)
384 {
385 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
386 enum pin_config_param param = pinconf_to_config_param(*config);
387 struct eqbr_gpio_ctrl *gctrl;
388 struct eqbr_pin_bank *bank;
389 unsigned long flags;
390 unsigned int offset;
391 void __iomem *mem;
392 u32 val;
393
394 bank = find_pinbank_via_pin(pctl, pin);
395 if (!bank) {
396 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
397 return -ENODEV;
398 }
399 mem = bank->membase;
400 offset = pin - bank->pin_base;
401
402 if (!(bank->aval_pinmap & BIT(offset))) {
403 dev_err(pctl->dev,
404 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
405 pin, bank->pin_base, bank->aval_pinmap);
406 return -ENODEV;
407 }
408
409 raw_spin_lock_irqsave(&pctl->lock, flags);
410 switch (param) {
411 case PIN_CONFIG_BIAS_PULL_UP:
412 val = !!(readl(mem + REG_PUEN) & BIT(offset));
413 break;
414 case PIN_CONFIG_BIAS_PULL_DOWN:
415 val = !!(readl(mem + REG_PDEN) & BIT(offset));
416 break;
417 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
418 val = !!(readl(mem + REG_OD) & BIT(offset));
419 break;
420 case PIN_CONFIG_DRIVE_STRENGTH:
421 val = get_drv_cur(mem, offset);
422 break;
423 case PIN_CONFIG_SLEW_RATE:
424 val = !!(readl(mem + REG_SRC) & BIT(offset));
425 break;
426 case PIN_CONFIG_OUTPUT_ENABLE:
427 gctrl = get_gpio_ctrls_via_bank(pctl, bank);
428 if (!gctrl) {
429 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
430 bank->pin_base, pin);
431 raw_spin_unlock_irqrestore(&pctl->lock, flags);
432 return -ENODEV;
433 }
434 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));
435 break;
436 default:
437 raw_spin_unlock_irqrestore(&pctl->lock, flags);
438 return -ENOTSUPP;
439 }
440 raw_spin_unlock_irqrestore(&pctl->lock, flags);
441 *config = pinconf_to_config_packed(param, val);
442 ;
443 return 0;
444 }
445
eqbr_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)446 static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
447 unsigned long *configs, unsigned int num_configs)
448 {
449 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
450 struct eqbr_gpio_ctrl *gctrl;
451 enum pin_config_param param;
452 struct eqbr_pin_bank *bank;
453 unsigned int val, offset;
454 struct gpio_chip *gc;
455 unsigned long flags;
456 void __iomem *mem;
457 u32 regval, mask;
458 int i;
459
460 for (i = 0; i < num_configs; i++) {
461 param = pinconf_to_config_param(configs[i]);
462 val = pinconf_to_config_argument(configs[i]);
463
464 bank = find_pinbank_via_pin(pctl, pin);
465 if (!bank) {
466 dev_err(pctl->dev,
467 "Couldn't find pin bank for pin %u\n", pin);
468 return -ENODEV;
469 }
470 mem = bank->membase;
471 offset = pin - bank->pin_base;
472
473 switch (param) {
474 case PIN_CONFIG_BIAS_PULL_UP:
475 mem += REG_PUEN;
476 mask = BIT(offset);
477 break;
478 case PIN_CONFIG_BIAS_PULL_DOWN:
479 mem += REG_PDEN;
480 mask = BIT(offset);
481 break;
482 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
483 mem += REG_OD;
484 mask = BIT(offset);
485 break;
486 case PIN_CONFIG_DRIVE_STRENGTH:
487 mem += REG_DRCC(offset / DRV_CUR_PINS);
488 offset = (offset % DRV_CUR_PINS) * 2;
489 mask = GENMASK(1, 0) << offset;
490 break;
491 case PIN_CONFIG_SLEW_RATE:
492 mem += REG_SRC;
493 mask = BIT(offset);
494 break;
495 case PIN_CONFIG_OUTPUT_ENABLE:
496 gctrl = get_gpio_ctrls_via_bank(pctl, bank);
497 if (!gctrl) {
498 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
499 bank->pin_base, pin);
500 return -ENODEV;
501 }
502 gc = &gctrl->chip;
503 gc->direction_output(gc, offset, 0);
504 continue;
505 default:
506 return -ENOTSUPP;
507 }
508
509 raw_spin_lock_irqsave(&pctl->lock, flags);
510 regval = readl(mem);
511 regval = (regval & ~mask) | ((val << offset) & mask);
512 writel(regval, mem);
513 raw_spin_unlock_irqrestore(&pctl->lock, flags);
514 }
515
516 return 0;
517 }
518
eqbr_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)519 static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,
520 unsigned int group, unsigned long *config)
521 {
522 unsigned int i, npins, old = 0;
523 const unsigned int *pins;
524 int ret;
525
526 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
527 if (ret)
528 return ret;
529
530 for (i = 0; i < npins; i++) {
531 if (eqbr_pinconf_get(pctldev, pins[i], config))
532 return -ENOTSUPP;
533
534 if (i && old != *config)
535 return -ENOTSUPP;
536
537 old = *config;
538 }
539 return 0;
540 }
541
eqbr_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)542 static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev,
543 unsigned int group, unsigned long *configs,
544 unsigned int num_configs)
545 {
546 const unsigned int *pins;
547 unsigned int i, npins;
548 int ret;
549
550 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
551 if (ret)
552 return ret;
553
554 for (i = 0; i < npins; i++) {
555 ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs);
556 if (ret)
557 return ret;
558 }
559 return 0;
560 }
561
562 static const struct pinconf_ops eqbr_pinconf_ops = {
563 .is_generic = true,
564 .pin_config_get = eqbr_pinconf_get,
565 .pin_config_set = eqbr_pinconf_set,
566 .pin_config_group_get = eqbr_pinconf_group_get,
567 .pin_config_group_set = eqbr_pinconf_group_set,
568 .pin_config_config_dbg_show = pinconf_generic_dump_config,
569 };
570
is_func_exist(struct pinfunction * funcs,const char * name,unsigned int nr_funcs,unsigned int * idx)571 static bool is_func_exist(struct pinfunction *funcs, const char *name,
572 unsigned int nr_funcs, unsigned int *idx)
573 {
574 int i;
575
576 if (!funcs)
577 return false;
578
579 for (i = 0; i < nr_funcs; i++) {
580 if (funcs[i].name && !strcmp(funcs[i].name, name)) {
581 *idx = i;
582 return true;
583 }
584 }
585
586 return false;
587 }
588
funcs_utils(struct device * dev,struct pinfunction * funcs,unsigned int * nr_funcs,funcs_util_ops op)589 static int funcs_utils(struct device *dev, struct pinfunction *funcs,
590 unsigned int *nr_funcs, funcs_util_ops op)
591 {
592 struct device_node *node = dev->of_node;
593 struct property *prop;
594 const char *fn_name;
595 const char **groups;
596 unsigned int fid;
597 int i, j;
598
599 i = 0;
600 for_each_child_of_node_scoped(node, np) {
601 prop = of_find_property(np, "groups", NULL);
602 if (!prop)
603 continue;
604
605 if (of_property_read_string(np, "function", &fn_name)) {
606 /* some groups may not have function, it's OK */
607 dev_dbg(dev, "Group %s: not function binded!\n",
608 (char *)prop->value);
609 continue;
610 }
611
612 switch (op) {
613 case OP_COUNT_NR_FUNCS:
614 if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
615 *nr_funcs = *nr_funcs + 1;
616 break;
617
618 case OP_ADD_FUNCS:
619 if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
620 funcs[i].name = fn_name;
621 break;
622
623 case OP_COUNT_NR_FUNC_GRPS:
624 if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
625 funcs[fid].ngroups++;
626 break;
627
628 case OP_ADD_FUNC_GRPS:
629 if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
630 groups = (const char **)funcs[fid].groups;
631 for (j = 0; j < funcs[fid].ngroups; j++)
632 if (!groups[j])
633 break;
634 groups[j] = prop->value;
635 }
636 break;
637
638 default:
639 return -EINVAL;
640 }
641 i++;
642 }
643
644 return 0;
645 }
646
eqbr_build_functions(struct eqbr_pinctrl_drv_data * drvdata)647 static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
648 {
649 struct device *dev = drvdata->dev;
650 struct pinfunction *funcs = NULL;
651 unsigned int nr_funcs = 0;
652 int i, ret;
653
654 ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS);
655 if (ret)
656 return ret;
657
658 funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL);
659 if (!funcs)
660 return -ENOMEM;
661
662 ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS);
663 if (ret)
664 return ret;
665
666 ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS);
667 if (ret)
668 return ret;
669
670 for (i = 0; i < nr_funcs; i++) {
671 if (!funcs[i].ngroups)
672 continue;
673 funcs[i].groups = devm_kcalloc(dev, funcs[i].ngroups,
674 sizeof(*(funcs[i].groups)),
675 GFP_KERNEL);
676 if (!funcs[i].groups)
677 return -ENOMEM;
678 }
679
680 ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS);
681 if (ret)
682 return ret;
683
684 for (i = 0; i < nr_funcs; i++) {
685
686 /* Ignore the same function with multiple groups */
687 if (funcs[i].name == NULL)
688 continue;
689
690 ret = pinmux_generic_add_pinfunction(drvdata->pctl_dev,
691 &funcs[i], drvdata);
692 if (ret < 0) {
693 dev_err(dev, "Failed to register function %s\n",
694 funcs[i].name);
695 return ret;
696 }
697 }
698
699 return 0;
700 }
701
eqbr_build_groups(struct eqbr_pinctrl_drv_data * drvdata)702 static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
703 {
704 struct device *dev = drvdata->dev;
705 struct device_node *node = dev->of_node;
706 unsigned int *pins, *pinmux, pin_id, pinmux_id;
707 struct pingroup group, *grp = &group;
708 struct property *prop;
709 int j, err;
710
711 for_each_child_of_node_scoped(node, np) {
712 prop = of_find_property(np, "groups", NULL);
713 if (!prop)
714 continue;
715
716 err = of_property_count_u32_elems(np, "pins");
717 if (err < 0) {
718 dev_err(dev, "No pins in the group: %s\n", prop->name);
719 return err;
720 }
721 grp->npins = err;
722 grp->name = prop->value;
723 pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL);
724 if (!pins)
725 return -ENOMEM;
726
727 grp->pins = pins;
728
729 pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL);
730 if (!pinmux)
731 return -ENOMEM;
732
733 for (j = 0; j < grp->npins; j++) {
734 if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
735 dev_err(dev, "Group %s: Read intel pins id failed\n",
736 grp->name);
737 return -EINVAL;
738 }
739 if (pin_id >= drvdata->pctl_desc.npins) {
740 dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
741 grp->name, j, pin_id);
742 return -EINVAL;
743 }
744 pins[j] = pin_id;
745 if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
746 dev_err(dev, "Group %s: Read intel pinmux id failed\n",
747 grp->name);
748 return -EINVAL;
749 }
750 pinmux[j] = pinmux_id;
751 }
752
753 err = pinctrl_generic_add_group(drvdata->pctl_dev,
754 grp->name, grp->pins, grp->npins,
755 pinmux);
756 if (err < 0) {
757 dev_err(dev, "Failed to register group %s\n", grp->name);
758 return err;
759 }
760 memset(&group, 0, sizeof(group));
761 pinmux = NULL;
762 }
763
764 return 0;
765 }
766
pinctrl_reg(struct eqbr_pinctrl_drv_data * drvdata)767 static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata)
768 {
769 struct pinctrl_desc *pctl_desc;
770 struct pinctrl_pin_desc *pdesc;
771 struct device *dev;
772 unsigned int nr_pins;
773 char *pin_names;
774 int i, ret;
775
776 dev = drvdata->dev;
777 pctl_desc = &drvdata->pctl_desc;
778 pctl_desc->name = "eqbr-pinctrl";
779 pctl_desc->owner = THIS_MODULE;
780 pctl_desc->pctlops = &eqbr_pctl_ops;
781 pctl_desc->pmxops = &eqbr_pinmux_ops;
782 pctl_desc->confops = &eqbr_pinconf_ops;
783 raw_spin_lock_init(&drvdata->lock);
784
785 for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++)
786 nr_pins += drvdata->pin_banks[i].nr_pins;
787
788 pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL);
789 if (!pdesc)
790 return -ENOMEM;
791 pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL);
792 if (!pin_names)
793 return -ENOMEM;
794
795 for (i = 0; i < nr_pins; i++) {
796 sprintf(pin_names, PIN_NAME_FMT, i);
797 pdesc[i].number = i;
798 pdesc[i].name = pin_names;
799 pin_names += PIN_NAME_LEN;
800 }
801 pctl_desc->pins = pdesc;
802 pctl_desc->npins = nr_pins;
803 dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins);
804
805 ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata,
806 &drvdata->pctl_dev);
807 if (ret)
808 return ret;
809
810 ret = eqbr_build_groups(drvdata);
811 if (ret) {
812 dev_err(dev, "Failed to build groups\n");
813 return ret;
814 }
815
816 ret = eqbr_build_functions(drvdata);
817 if (ret) {
818 dev_err(dev, "Failed to build functions\n");
819 return ret;
820 }
821
822 return pinctrl_enable(drvdata->pctl_dev);
823 }
824
pinbank_init(struct device_node * np,struct eqbr_pinctrl_drv_data * drvdata,struct eqbr_pin_bank * bank,unsigned int id)825 static int pinbank_init(struct device_node *np,
826 struct eqbr_pinctrl_drv_data *drvdata,
827 struct eqbr_pin_bank *bank, unsigned int id)
828 {
829 struct device *dev = drvdata->dev;
830 struct of_phandle_args spec;
831 int ret;
832
833 bank->membase = drvdata->membase + id * PAD_REG_OFF;
834
835 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec);
836 if (ret) {
837 dev_err(dev, "gpio-range not available!\n");
838 return ret;
839 }
840
841 bank->pin_base = spec.args[1];
842 bank->nr_pins = spec.args[2];
843
844 bank->aval_pinmap = readl(bank->membase + REG_AVAIL);
845 bank->id = id;
846
847 dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n",
848 id, bank->membase, bank->pin_base,
849 bank->nr_pins, bank->aval_pinmap);
850
851 return ret;
852 }
853
pinbank_probe(struct eqbr_pinctrl_drv_data * drvdata)854 static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata)
855 {
856 struct device *dev = drvdata->dev;
857 struct device_node *np_gpio;
858 struct eqbr_gpio_ctrl *gctrls;
859 struct eqbr_pin_bank *banks;
860 int i, nr_gpio;
861
862 /* Count gpio bank number */
863 nr_gpio = 0;
864 for_each_node_by_name(np_gpio, "gpio") {
865 if (of_device_is_available(np_gpio))
866 nr_gpio++;
867 }
868
869 if (!nr_gpio) {
870 dev_err(dev, "NO pin bank available!\n");
871 return -ENODEV;
872 }
873
874 /* Count pin bank number and gpio controller number */
875 banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL);
876 if (!banks)
877 return -ENOMEM;
878
879 gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL);
880 if (!gctrls)
881 return -ENOMEM;
882
883 dev_dbg(dev, "found %d gpio controller!\n", nr_gpio);
884
885 /* Initialize Pin bank */
886 i = 0;
887 for_each_node_by_name(np_gpio, "gpio") {
888 if (!of_device_is_available(np_gpio))
889 continue;
890
891 pinbank_init(np_gpio, drvdata, banks + i, i);
892
893 gctrls[i].fwnode = of_fwnode_handle(np_gpio);
894 gctrls[i].bank = banks + i;
895 i++;
896 }
897
898 drvdata->pin_banks = banks;
899 drvdata->nr_banks = nr_gpio;
900 drvdata->gpio_ctrls = gctrls;
901 drvdata->nr_gpio_ctrls = nr_gpio;
902
903 return 0;
904 }
905
eqbr_pinctrl_probe(struct platform_device * pdev)906 static int eqbr_pinctrl_probe(struct platform_device *pdev)
907 {
908 struct eqbr_pinctrl_drv_data *drvdata;
909 struct device *dev = &pdev->dev;
910 int ret;
911
912 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
913 if (!drvdata)
914 return -ENOMEM;
915
916 drvdata->dev = dev;
917
918 drvdata->membase = devm_platform_ioremap_resource(pdev, 0);
919 if (IS_ERR(drvdata->membase))
920 return PTR_ERR(drvdata->membase);
921
922 ret = pinbank_probe(drvdata);
923 if (ret)
924 return ret;
925
926 ret = pinctrl_reg(drvdata);
927 if (ret)
928 return ret;
929
930 ret = gpiolib_reg(drvdata);
931 if (ret)
932 return ret;
933
934 platform_set_drvdata(pdev, drvdata);
935 return 0;
936 }
937
938 static const struct of_device_id eqbr_pinctrl_dt_match[] = {
939 { .compatible = "intel,lgm-io" },
940 {}
941 };
942 MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match);
943
944 static struct platform_driver eqbr_pinctrl_driver = {
945 .probe = eqbr_pinctrl_probe,
946 .driver = {
947 .name = "eqbr-pinctrl",
948 .of_match_table = eqbr_pinctrl_dt_match,
949 },
950 };
951
952 module_platform_driver(eqbr_pinctrl_driver);
953
954 MODULE_AUTHOR("Zhu Yixin <yixin.zhu@intel.com>, Rahul Tanwar <rahul.tanwar@intel.com>");
955 MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)");
956 MODULE_LICENSE("GPL v2");
957