1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc_bios_types.h"
28 #include "dcn10_stream_encoder.h"
29 #include "reg_helper.h"
30 #include "hw_shared.h"
31 #include "link.h"
32 #include "dpcd_defs.h"
33 #include "dcn30/dcn30_afmt.h"
34
35 #define DC_LOGGER \
36 enc1->base.ctx->logger
37
38 #define REG(reg)\
39 (enc1->regs->reg)
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 enc1->se_shift->field_name, enc1->se_mask->field_name
44
45 #define VBI_LINE_0 0
46 #define DP_BLANK_MAX_RETRY 20
47 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
48
49
50 enum {
51 DP_MST_UPDATE_MAX_RETRY = 50
52 };
53
54 #define CTX \
55 enc1->base.ctx
56
enc1_update_generic_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)57 void enc1_update_generic_info_packet(
58 struct dcn10_stream_encoder *enc1,
59 uint32_t packet_index,
60 const struct dc_info_packet *info_packet)
61 {
62 /* TODOFPGA Figure out a proper number for max_retries polling for lock
63 * use 50 for now.
64 */
65 uint32_t max_retries = 50;
66
67 /*we need turn on clock before programming AFMT block*/
68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
69
70 if (packet_index >= 8)
71 ASSERT(0);
72
73 /* poll dig_update_lock is not locked -> asic internal signal
74 * assume otg master lock will unlock it
75 */
76 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
77 0, 10, max_retries);*/
78
79 /* check if HW reading GSP memory */
80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
81 0, 10, max_retries);
82
83 /* HW does is not reading GSP memory not reading too long ->
84 * something wrong. clear GPS memory access and notify?
85 * hw SW is writing to GSP memory
86 */
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
88
89 /* choose which generic packet to use */
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
91 AFMT_GENERIC_INDEX, packet_index);
92
93 /* write generic packet header
94 * (4th byte is for GENERIC0 only)
95 */
96 REG_SET_4(AFMT_GENERIC_HDR, 0,
97 AFMT_GENERIC_HB0, info_packet->hb0,
98 AFMT_GENERIC_HB1, info_packet->hb1,
99 AFMT_GENERIC_HB2, info_packet->hb2,
100 AFMT_GENERIC_HB3, info_packet->hb3);
101
102 /* write generic packet contents
103 * (we never use last 4 bytes)
104 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
105 */
106 {
107 const uint32_t *content =
108 (const uint32_t *) &info_packet->sb[0];
109
110 REG_WRITE(AFMT_GENERIC_0, *content++);
111 REG_WRITE(AFMT_GENERIC_1, *content++);
112 REG_WRITE(AFMT_GENERIC_2, *content++);
113 REG_WRITE(AFMT_GENERIC_3, *content++);
114 REG_WRITE(AFMT_GENERIC_4, *content++);
115 REG_WRITE(AFMT_GENERIC_5, *content++);
116 REG_WRITE(AFMT_GENERIC_6, *content++);
117 REG_WRITE(AFMT_GENERIC_7, *content);
118 }
119
120 switch (packet_index) {
121 case 0:
122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
123 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
124 break;
125 case 1:
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
127 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
128 break;
129 case 2:
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
131 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
132 break;
133 case 3:
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
135 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
136 break;
137 case 4:
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
139 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
140 break;
141 case 5:
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
143 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
144 break;
145 case 6:
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
147 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
148 break;
149 case 7:
150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
151 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
152 break;
153 default:
154 break;
155 }
156 }
157
enc1_update_hdmi_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)158 static void enc1_update_hdmi_info_packet(
159 struct dcn10_stream_encoder *enc1,
160 uint32_t packet_index,
161 const struct dc_info_packet *info_packet)
162 {
163 uint32_t cont, send, line;
164
165 if (info_packet->valid) {
166 enc1_update_generic_info_packet(
167 enc1,
168 packet_index,
169 info_packet);
170
171 /* enable transmission of packet(s) -
172 * packet transmission begins on the next frame
173 */
174 cont = 1;
175 /* send packet(s) every frame */
176 send = 1;
177 /* select line number to send packets on */
178 line = 2;
179 } else {
180 cont = 0;
181 send = 0;
182 line = 0;
183 }
184
185 /* choose which generic packet control to use */
186 switch (packet_index) {
187 case 0:
188 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
189 HDMI_GENERIC0_CONT, cont,
190 HDMI_GENERIC0_SEND, send,
191 HDMI_GENERIC0_LINE, line);
192 break;
193 case 1:
194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
195 HDMI_GENERIC1_CONT, cont,
196 HDMI_GENERIC1_SEND, send,
197 HDMI_GENERIC1_LINE, line);
198 break;
199 case 2:
200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
201 HDMI_GENERIC0_CONT, cont,
202 HDMI_GENERIC0_SEND, send,
203 HDMI_GENERIC0_LINE, line);
204 break;
205 case 3:
206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
207 HDMI_GENERIC1_CONT, cont,
208 HDMI_GENERIC1_SEND, send,
209 HDMI_GENERIC1_LINE, line);
210 break;
211 case 4:
212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
213 HDMI_GENERIC0_CONT, cont,
214 HDMI_GENERIC0_SEND, send,
215 HDMI_GENERIC0_LINE, line);
216 break;
217 case 5:
218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
219 HDMI_GENERIC1_CONT, cont,
220 HDMI_GENERIC1_SEND, send,
221 HDMI_GENERIC1_LINE, line);
222 break;
223 case 6:
224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
225 HDMI_GENERIC0_CONT, cont,
226 HDMI_GENERIC0_SEND, send,
227 HDMI_GENERIC0_LINE, line);
228 break;
229 case 7:
230 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
231 HDMI_GENERIC1_CONT, cont,
232 HDMI_GENERIC1_SEND, send,
233 HDMI_GENERIC1_LINE, line);
234 break;
235 default:
236 /* invalid HW packet index */
237 DC_LOG_WARNING(
238 "Invalid HW packet index: %s()\n",
239 __func__);
240 return;
241 }
242 }
243
244 /* setup stream encoder in dp mode */
enc1_stream_encoder_dp_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,enum dc_color_space output_color_space,bool use_vsc_sdp_for_colorimetry,uint32_t enable_sdp_splitting)245 void enc1_stream_encoder_dp_set_stream_attribute(
246 struct stream_encoder *enc,
247 struct dc_crtc_timing *crtc_timing,
248 enum dc_color_space output_color_space,
249 bool use_vsc_sdp_for_colorimetry,
250 uint32_t enable_sdp_splitting)
251 {
252 uint32_t h_active_start;
253 uint32_t v_active_start;
254 uint32_t misc0 = 0;
255 uint32_t misc1 = 0;
256 uint32_t h_blank;
257 uint32_t h_back_porch;
258 uint8_t colorimetry_bpc;
259 uint8_t dp_pixel_encoding = 0;
260 uint8_t dp_component_depth = 0;
261
262 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
263 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
264
265 if (hw_crtc_timing.flags.INTERLACE) {
266 /*the input timing is in VESA spec format with Interlace flag =1*/
267 hw_crtc_timing.v_total /= 2;
268 hw_crtc_timing.v_border_top /= 2;
269 hw_crtc_timing.v_addressable /= 2;
270 hw_crtc_timing.v_border_bottom /= 2;
271 hw_crtc_timing.v_front_porch /= 2;
272 hw_crtc_timing.v_sync_width /= 2;
273 }
274
275
276 /* set pixel encoding */
277 switch (hw_crtc_timing.pixel_encoding) {
278 case PIXEL_ENCODING_YCBCR422:
279 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
280 break;
281 case PIXEL_ENCODING_YCBCR444:
282 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
283
284 if (hw_crtc_timing.flags.Y_ONLY)
285 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
286 /* HW testing only, no use case yet.
287 * Color depth of Y-only could be
288 * 8, 10, 12, 16 bits
289 */
290 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
291
292 /* Note: DP_MSA_MISC1 bit 7 is the indicator
293 * of Y-only mode.
294 * This bit is set in HW if register
295 * DP_PIXEL_ENCODING is programmed to 0x4
296 */
297 break;
298 case PIXEL_ENCODING_YCBCR420:
299 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
300 break;
301 default:
302 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
303 break;
304 }
305
306 misc1 = REG_READ(DP_MSA_MISC);
307 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
308 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
309 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
310 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
311 */
312 if (use_vsc_sdp_for_colorimetry)
313 misc1 = misc1 | 0x40;
314 else
315 misc1 = misc1 & ~0x40;
316
317 /* set color depth */
318 switch (hw_crtc_timing.display_color_depth) {
319 case COLOR_DEPTH_666:
320 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
321 break;
322 case COLOR_DEPTH_888:
323 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
324 break;
325 case COLOR_DEPTH_101010:
326 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
327 break;
328 case COLOR_DEPTH_121212:
329 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
330 break;
331 case COLOR_DEPTH_161616:
332 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
333 break;
334 default:
335 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
336 break;
337 }
338
339 /* Set DP pixel encoding and component depth */
340 REG_UPDATE_2(DP_PIXEL_FORMAT,
341 DP_PIXEL_ENCODING, dp_pixel_encoding,
342 DP_COMPONENT_DEPTH, dp_component_depth);
343
344 /* set dynamic range and YCbCr range */
345
346 switch (hw_crtc_timing.display_color_depth) {
347 case COLOR_DEPTH_666:
348 colorimetry_bpc = 0;
349 break;
350 case COLOR_DEPTH_888:
351 colorimetry_bpc = 1;
352 break;
353 case COLOR_DEPTH_101010:
354 colorimetry_bpc = 2;
355 break;
356 case COLOR_DEPTH_121212:
357 colorimetry_bpc = 3;
358 break;
359 default:
360 colorimetry_bpc = 0;
361 break;
362 }
363
364 misc0 = colorimetry_bpc << 5;
365
366 switch (output_color_space) {
367 case COLOR_SPACE_SRGB:
368 misc1 = misc1 & ~0x80; /* bit7 = 0*/
369 break;
370 case COLOR_SPACE_SRGB_LIMITED:
371 misc0 = misc0 | 0x8; /* bit3=1 */
372 misc1 = misc1 & ~0x80; /* bit7 = 0*/
373 break;
374 case COLOR_SPACE_YCBCR601:
375 case COLOR_SPACE_YCBCR601_LIMITED:
376 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
377 misc1 = misc1 & ~0x80; /* bit7 = 0*/
378 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
379 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
380 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
381 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
382 break;
383 case COLOR_SPACE_YCBCR709:
384 case COLOR_SPACE_YCBCR709_LIMITED:
385 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
386 misc1 = misc1 & ~0x80; /* bit7 = 0*/
387 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
388 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
389 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
390 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
391 break;
392 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
393 case COLOR_SPACE_2020_RGB_FULLRANGE:
394 case COLOR_SPACE_2020_YCBCR_LIMITED:
395 case COLOR_SPACE_XR_RGB:
396 case COLOR_SPACE_MSREF_SCRGB:
397 case COLOR_SPACE_ADOBERGB:
398 case COLOR_SPACE_DCIP3:
399 case COLOR_SPACE_XV_YCC_709:
400 case COLOR_SPACE_XV_YCC_601:
401 case COLOR_SPACE_DISPLAYNATIVE:
402 case COLOR_SPACE_DOLBYVISION:
403 case COLOR_SPACE_APPCTRL:
404 case COLOR_SPACE_CUSTOMPOINTS:
405 case COLOR_SPACE_UNKNOWN:
406 case COLOR_SPACE_YCBCR709_BLACK:
407 default:
408 /* do nothing */
409 break;
410 }
411
412 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
413 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
414
415 /* dcn new register
416 * dc_crtc_timing is vesa dmt struct. data from edid
417 */
418 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
419 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
420 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
421
422 /* calculate from vesa timing parameters
423 * h_active_start related to leading edge of sync
424 */
425
426 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
427 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
428
429 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
430 hw_crtc_timing.h_sync_width;
431
432 /* start at beginning of left border */
433 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
434
435
436 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
437 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
438 hw_crtc_timing.v_front_porch;
439
440
441 /* start at beginning of left border */
442 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
443 DP_MSA_HSTART, h_active_start,
444 DP_MSA_VSTART, v_active_start);
445
446 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
447 DP_MSA_HSYNCWIDTH,
448 hw_crtc_timing.h_sync_width,
449 DP_MSA_HSYNCPOLARITY,
450 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
451 DP_MSA_VSYNCWIDTH,
452 hw_crtc_timing.v_sync_width,
453 DP_MSA_VSYNCPOLARITY,
454 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
455
456 /* HWDITH include border or overscan */
457 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
458 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
459 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
460 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
461 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
462 }
463
enc1_stream_encoder_set_stream_attribute_helper(struct dcn10_stream_encoder * enc1,struct dc_crtc_timing * crtc_timing)464 void enc1_stream_encoder_set_stream_attribute_helper(
465 struct dcn10_stream_encoder *enc1,
466 struct dc_crtc_timing *crtc_timing)
467 {
468 switch (crtc_timing->pixel_encoding) {
469 case PIXEL_ENCODING_YCBCR422:
470 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
471 break;
472 default:
473 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
474 break;
475 }
476 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
477 }
478
479 /* setup stream encoder in hdmi mode */
enc1_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)480 void enc1_stream_encoder_hdmi_set_stream_attribute(
481 struct stream_encoder *enc,
482 struct dc_crtc_timing *crtc_timing,
483 int actual_pix_clk_khz,
484 bool enable_audio)
485 {
486 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
487 struct bp_encoder_control cntl = {0};
488
489 cntl.action = ENCODER_CONTROL_SETUP;
490 cntl.engine_id = enc1->base.id;
491 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
492 cntl.enable_dp_audio = enable_audio;
493 cntl.pixel_clock = actual_pix_clk_khz;
494 cntl.lanes_number = LANE_COUNT_FOUR;
495
496 if (enc1->base.bp->funcs->encoder_control(
497 enc1->base.bp, &cntl) != BP_RESULT_OK)
498 return;
499
500 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
501
502 /* setup HDMI engine */
503 REG_UPDATE_6(HDMI_CONTROL,
504 HDMI_PACKET_GEN_VERSION, 1,
505 HDMI_KEEPOUT_MODE, 1,
506 HDMI_DEEP_COLOR_ENABLE, 0,
507 HDMI_DATA_SCRAMBLE_EN, 0,
508 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
509 HDMI_CLOCK_CHANNEL_RATE, 0);
510
511
512 switch (crtc_timing->display_color_depth) {
513 case COLOR_DEPTH_888:
514 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
515 DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n");
516 break;
517 case COLOR_DEPTH_101010:
518 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
519 REG_UPDATE_2(HDMI_CONTROL,
520 HDMI_DEEP_COLOR_DEPTH, 1,
521 HDMI_DEEP_COLOR_ENABLE, 0);
522 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
523 "disabled for YCBCR422 pixel encoding\n");
524 } else {
525 REG_UPDATE_2(HDMI_CONTROL,
526 HDMI_DEEP_COLOR_DEPTH, 1,
527 HDMI_DEEP_COLOR_ENABLE, 1);
528 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
529 "enabled for YCBCR422 non-pixel encoding\n");
530 }
531 break;
532 case COLOR_DEPTH_121212:
533 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
534 REG_UPDATE_2(HDMI_CONTROL,
535 HDMI_DEEP_COLOR_DEPTH, 2,
536 HDMI_DEEP_COLOR_ENABLE, 0);
537 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
538 "disabled for YCBCR422 pixel encoding\n");
539 } else {
540 REG_UPDATE_2(HDMI_CONTROL,
541 HDMI_DEEP_COLOR_DEPTH, 2,
542 HDMI_DEEP_COLOR_ENABLE, 1);
543 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
544 "enabled for non-pixel YCBCR422 encoding\n");
545 }
546 break;
547 case COLOR_DEPTH_161616:
548 REG_UPDATE_2(HDMI_CONTROL,
549 HDMI_DEEP_COLOR_DEPTH, 3,
550 HDMI_DEEP_COLOR_ENABLE, 1);
551 DC_LOG_DEBUG("HDMI source deep color depth enabled in" \
552 "reserved mode\n");
553 break;
554 default:
555 break;
556 }
557
558 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
559 /* enable HDMI data scrambler
560 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
561 * Clock channel frequency is 1/4 of character rate.
562 */
563 REG_UPDATE_2(HDMI_CONTROL,
564 HDMI_DATA_SCRAMBLE_EN, 1,
565 HDMI_CLOCK_CHANNEL_RATE, 1);
566 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
567
568 /* TODO: New feature for DCE11, still need to implement */
569
570 /* enable HDMI data scrambler
571 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
572 * Clock channel frequency is the same
573 * as character rate
574 */
575 REG_UPDATE_2(HDMI_CONTROL,
576 HDMI_DATA_SCRAMBLE_EN, 1,
577 HDMI_CLOCK_CHANNEL_RATE, 0);
578 }
579
580
581 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
582 HDMI_GC_CONT, 1,
583 HDMI_GC_SEND, 1,
584 HDMI_NULL_SEND, 1);
585
586 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
587
588 /* following belongs to audio */
589 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
590
591 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
592
593 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
594 VBI_LINE_0 + 2);
595
596 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
597 }
598
599 /* setup stream encoder in dvi mode */
enc1_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)600 void enc1_stream_encoder_dvi_set_stream_attribute(
601 struct stream_encoder *enc,
602 struct dc_crtc_timing *crtc_timing,
603 bool is_dual_link)
604 {
605 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
606 struct bp_encoder_control cntl = {0};
607
608 cntl.action = ENCODER_CONTROL_SETUP;
609 cntl.engine_id = enc1->base.id;
610 cntl.signal = is_dual_link ?
611 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
612 cntl.enable_dp_audio = false;
613 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
614 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
615
616 if (enc1->base.bp->funcs->encoder_control(
617 enc1->base.bp, &cntl) != BP_RESULT_OK)
618 return;
619
620 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
621 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
622 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
623 }
624
enc1_stream_encoder_set_throttled_vcp_size(struct stream_encoder * enc,struct fixed31_32 avg_time_slots_per_mtp)625 void enc1_stream_encoder_set_throttled_vcp_size(
626 struct stream_encoder *enc,
627 struct fixed31_32 avg_time_slots_per_mtp)
628 {
629 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
630 uint32_t x = dc_fixpt_floor(
631 avg_time_slots_per_mtp);
632 uint32_t y = dc_fixpt_ceil(
633 dc_fixpt_shl(
634 dc_fixpt_sub_int(
635 avg_time_slots_per_mtp,
636 x),
637 26));
638
639 // If y rounds up to integer, carry it over to x.
640 if (y >> 26) {
641 x += 1;
642 y = 0;
643 }
644
645 REG_SET_2(DP_MSE_RATE_CNTL, 0,
646 DP_MSE_RATE_X, x,
647 DP_MSE_RATE_Y, y);
648
649 /* wait for update to be completed on the link */
650 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
651 /* is reset to 0 (not pending) */
652 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
653 0,
654 10, DP_MST_UPDATE_MAX_RETRY);
655 }
656
enc1_stream_encoder_update_hdmi_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)657 static void enc1_stream_encoder_update_hdmi_info_packets(
658 struct stream_encoder *enc,
659 const struct encoder_info_frame *info_frame)
660 {
661 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
662
663 /* for bring up, disable dp double TODO */
664 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
665
666 /*Always add mandatory packets first followed by optional ones*/
667 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
668 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
669 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
670 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
671 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
672 enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
673 }
674
enc1_stream_encoder_stop_hdmi_info_packets(struct stream_encoder * enc)675 static void enc1_stream_encoder_stop_hdmi_info_packets(
676 struct stream_encoder *enc)
677 {
678 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
679
680 /* stop generic packets 0 & 1 on HDMI */
681 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
682 HDMI_GENERIC1_CONT, 0,
683 HDMI_GENERIC1_LINE, 0,
684 HDMI_GENERIC1_SEND, 0,
685 HDMI_GENERIC0_CONT, 0,
686 HDMI_GENERIC0_LINE, 0,
687 HDMI_GENERIC0_SEND, 0);
688
689 /* stop generic packets 2 & 3 on HDMI */
690 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
691 HDMI_GENERIC0_CONT, 0,
692 HDMI_GENERIC0_LINE, 0,
693 HDMI_GENERIC0_SEND, 0,
694 HDMI_GENERIC1_CONT, 0,
695 HDMI_GENERIC1_LINE, 0,
696 HDMI_GENERIC1_SEND, 0);
697
698 /* stop generic packets 2 & 3 on HDMI */
699 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
700 HDMI_GENERIC0_CONT, 0,
701 HDMI_GENERIC0_LINE, 0,
702 HDMI_GENERIC0_SEND, 0,
703 HDMI_GENERIC1_CONT, 0,
704 HDMI_GENERIC1_LINE, 0,
705 HDMI_GENERIC1_SEND, 0);
706
707 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
708 HDMI_GENERIC0_CONT, 0,
709 HDMI_GENERIC0_LINE, 0,
710 HDMI_GENERIC0_SEND, 0,
711 HDMI_GENERIC1_CONT, 0,
712 HDMI_GENERIC1_LINE, 0,
713 HDMI_GENERIC1_SEND, 0);
714 }
715
enc1_stream_encoder_update_dp_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)716 void enc1_stream_encoder_update_dp_info_packets(
717 struct stream_encoder *enc,
718 const struct encoder_info_frame *info_frame)
719 {
720 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
721 uint32_t value = 0;
722
723 if (info_frame->vsc.valid)
724 enc1_update_generic_info_packet(
725 enc1,
726 0, /* packetIndex */
727 &info_frame->vsc);
728
729 /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW.
730 * Note that the enablement of GSP1 is not done below,
731 * it's done in FW.
732 */
733 if (info_frame->vsc.valid)
734 enc1_update_generic_info_packet(
735 enc1,
736 1, /* packetIndex */
737 &info_frame->vsc);
738
739 if (info_frame->spd.valid)
740 enc1_update_generic_info_packet(
741 enc1,
742 2, /* packetIndex */
743 &info_frame->spd);
744
745 if (info_frame->hdrsmd.valid)
746 enc1_update_generic_info_packet(
747 enc1,
748 3, /* packetIndex */
749 &info_frame->hdrsmd);
750
751 /* packetIndex 4 is used for send immediate sdp message, and please
752 * use other packetIndex (such as 5,6) for other info packet
753 */
754
755 if (info_frame->adaptive_sync.valid)
756 enc1_update_generic_info_packet(
757 enc1,
758 5, /* packetIndex */
759 &info_frame->adaptive_sync);
760
761 /* enable/disable transmission of packet(s).
762 * If enabled, packet transmission begins on the next frame
763 */
764 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
765 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
766 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
767 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid);
768
769 /* This bit is the master enable bit.
770 * When enabling secondary stream engine,
771 * this master bit must also be set.
772 * This register shared with audio info frame.
773 * Therefore we need to enable master bit
774 * if at least on of the fields is not 0
775 */
776 value = REG_READ(DP_SEC_CNTL);
777 if (value)
778 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
779 }
780
enc1_stream_encoder_send_immediate_sdp_message(struct stream_encoder * enc,const uint8_t * custom_sdp_message,unsigned int sdp_message_size)781 void enc1_stream_encoder_send_immediate_sdp_message(
782 struct stream_encoder *enc,
783 const uint8_t *custom_sdp_message,
784 unsigned int sdp_message_size)
785 {
786 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
787 uint32_t value = 0;
788
789 /* TODOFPGA Figure out a proper number for max_retries polling for lock
790 * use 50 for now.
791 */
792 uint32_t max_retries = 50;
793
794 /* check if GSP4 is transmitted */
795 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
796 0, 10, max_retries);
797
798 /* disable GSP4 transmitting */
799 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
800
801 /* transmit GSP4 at the earliest time in a frame */
802 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
803
804 /*we need turn on clock before programming AFMT block*/
805 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
806
807 /* check if HW reading GSP memory */
808 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
809 0, 10, max_retries);
810
811 /* HW does is not reading GSP memory not reading too long ->
812 * something wrong. clear GPS memory access and notify?
813 * hw SW is writing to GSP memory
814 */
815 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
816
817 /* use generic packet 4 for immediate sdp message */
818 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
819 AFMT_GENERIC_INDEX, 4);
820
821 /* write generic packet header
822 * (4th byte is for GENERIC0 only)
823 */
824 REG_SET_4(AFMT_GENERIC_HDR, 0,
825 AFMT_GENERIC_HB0, custom_sdp_message[0],
826 AFMT_GENERIC_HB1, custom_sdp_message[1],
827 AFMT_GENERIC_HB2, custom_sdp_message[2],
828 AFMT_GENERIC_HB3, custom_sdp_message[3]);
829
830 /* write generic packet contents
831 * (we never use last 4 bytes)
832 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
833 */
834 {
835 const uint32_t *content =
836 (const uint32_t *) &custom_sdp_message[4];
837
838 REG_WRITE(AFMT_GENERIC_0, *content++);
839 REG_WRITE(AFMT_GENERIC_1, *content++);
840 REG_WRITE(AFMT_GENERIC_2, *content++);
841 REG_WRITE(AFMT_GENERIC_3, *content++);
842 REG_WRITE(AFMT_GENERIC_4, *content++);
843 REG_WRITE(AFMT_GENERIC_5, *content++);
844 REG_WRITE(AFMT_GENERIC_6, *content++);
845 REG_WRITE(AFMT_GENERIC_7, *content);
846 }
847
848 /* check whether GENERIC4 registers double buffer update in immediate mode
849 * is pending
850 */
851 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
852 0, 10, max_retries);
853
854 /* atomically update double-buffered GENERIC4 registers in immediate mode
855 * (update immediately)
856 */
857 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
858 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
859
860 /* enable GSP4 transmitting */
861 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
862
863 /* This bit is the master enable bit.
864 * When enabling secondary stream engine,
865 * this master bit must also be set.
866 * This register shared with audio info frame.
867 * Therefore we need to enable master bit
868 * if at least on of the fields is not 0
869 */
870 value = REG_READ(DP_SEC_CNTL);
871 if (value)
872 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
873 }
874
enc1_stream_encoder_stop_dp_info_packets(struct stream_encoder * enc)875 void enc1_stream_encoder_stop_dp_info_packets(
876 struct stream_encoder *enc)
877 {
878 /* stop generic packets on DP */
879 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
880 uint32_t value = 0;
881
882 REG_SET_10(DP_SEC_CNTL, 0,
883 DP_SEC_GSP0_ENABLE, 0,
884 DP_SEC_GSP1_ENABLE, 0,
885 DP_SEC_GSP2_ENABLE, 0,
886 DP_SEC_GSP3_ENABLE, 0,
887 DP_SEC_GSP4_ENABLE, 0,
888 DP_SEC_GSP5_ENABLE, 0,
889 DP_SEC_GSP6_ENABLE, 0,
890 DP_SEC_GSP7_ENABLE, 0,
891 DP_SEC_MPG_ENABLE, 0,
892 DP_SEC_STREAM_ENABLE, 0);
893
894 /* this register shared with audio info frame.
895 * therefore we need to keep master enabled
896 * if at least one of the fields is not 0 */
897 value = REG_READ(DP_SEC_CNTL);
898 if (value)
899 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
900
901 }
902
enc1_stream_encoder_dp_blank(struct dc_link * link,struct stream_encoder * enc)903 void enc1_stream_encoder_dp_blank(
904 struct dc_link *link,
905 struct stream_encoder *enc)
906 {
907 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
908 uint32_t reg1 = 0;
909 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
910
911 /* Note: For CZ, we are changing driver default to disable
912 * stream deferred to next VBLANK. If results are positive, we
913 * will make the same change to all DCE versions. There are a
914 * handful of panels that cannot handle disable stream at
915 * HBLANK and will result in a white line flash across the
916 * screen on stream disable.
917 */
918 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
919 if ((reg1 & 0x1) == 0)
920 /*stream not enabled*/
921 return;
922 /* Specify the video stream disable point
923 * (2 = start of the next vertical blank)
924 */
925 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
926 /* Larger delay to wait until VBLANK - use max retry of
927 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
928 * a little more because we may not trust delay accuracy.
929 */
930 max_retries = DP_BLANK_MAX_RETRY * 501;
931
932 /* disable DP stream */
933 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
934
935 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);
936
937 /* the encoder stops sending the video stream
938 * at the start of the vertical blanking.
939 * Poll for DP_VID_STREAM_STATUS == 0
940 */
941
942 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
943 0,
944 10, max_retries);
945
946 /* Tell the DP encoder to ignore timing from CRTC, must be done after
947 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
948 * complete, stream status will be stuck in video stream enabled state,
949 * i.e. DP_VID_STREAM_STATUS stuck at 1.
950 */
951
952 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
953
954 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);
955 }
956
957 /* output video stream to link encoder */
enc1_stream_encoder_dp_unblank(struct dc_link * link,struct stream_encoder * enc,const struct encoder_unblank_param * param)958 void enc1_stream_encoder_dp_unblank(
959 struct dc_link *link,
960 struct stream_encoder *enc,
961 const struct encoder_unblank_param *param)
962 {
963 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
964
965 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
966 uint32_t n_vid = 0x8000;
967 uint32_t m_vid;
968 uint32_t n_multiply = 0;
969 uint64_t m_vid_l = n_vid;
970
971 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
972 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
973 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
974 n_multiply = 1;
975 }
976 /* M / N = Fstream / Flink
977 * m_vid / n_vid = pixel rate / link rate
978 */
979
980 m_vid_l *= param->timing.pix_clk_100hz / 10;
981 m_vid_l = div_u64(m_vid_l,
982 param->link_settings.link_rate
983 * LINK_RATE_REF_FREQ_IN_KHZ);
984
985 m_vid = (uint32_t) m_vid_l;
986
987 /* enable auto measurement */
988
989 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
990
991 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
992 * therefore program initial value for Mvid and Nvid
993 */
994
995 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
996
997 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
998
999 REG_UPDATE_2(DP_VID_TIMING,
1000 DP_VID_M_N_GEN_EN, 1,
1001 DP_VID_N_MUL, n_multiply);
1002 }
1003
1004 /* set DIG_START to 0x1 to resync FIFO */
1005
1006 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1007
1008 /* switch DP encoder to CRTC data */
1009
1010 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1011
1012 /* wait 100us for DIG/DP logic to prime
1013 * (i.e. a few video lines)
1014 */
1015 udelay(100);
1016
1017 /* the hardware would start sending video at the start of the next DP
1018 * frame (i.e. rising edge of the vblank).
1019 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1020 * register has no effect on enable transition! HW always guarantees
1021 * VID_STREAM enable at start of next frame, and this is not
1022 * programmable
1023 */
1024
1025 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1026
1027 link->dc->link_srv->dp_trace_source_sequence(link,
1028 DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
1029 }
1030
enc1_stream_encoder_set_avmute(struct stream_encoder * enc,bool enable)1031 void enc1_stream_encoder_set_avmute(
1032 struct stream_encoder *enc,
1033 bool enable)
1034 {
1035 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1036 unsigned int value = enable ? 1 : 0;
1037
1038 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1039 }
1040
enc1_reset_hdmi_stream_attribute(struct stream_encoder * enc)1041 void enc1_reset_hdmi_stream_attribute(
1042 struct stream_encoder *enc)
1043 {
1044 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1045
1046 REG_UPDATE_5(HDMI_CONTROL,
1047 HDMI_PACKET_GEN_VERSION, 1,
1048 HDMI_KEEPOUT_MODE, 1,
1049 HDMI_DEEP_COLOR_ENABLE, 0,
1050 HDMI_DATA_SCRAMBLE_EN, 0,
1051 HDMI_CLOCK_CHANNEL_RATE, 0);
1052 }
1053
1054
1055 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1056 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1057
1058 #include "include/audio_types.h"
1059
1060
1061 /* 25.2MHz/1.001*/
1062 /* 25.2MHz/1.001*/
1063 /* 25.2MHz*/
1064 /* 27MHz */
1065 /* 27MHz*1.001*/
1066 /* 27MHz*1.001*/
1067 /* 54MHz*/
1068 /* 54MHz*1.001*/
1069 /* 74.25MHz/1.001*/
1070 /* 74.25MHz*/
1071 /* 148.5MHz/1.001*/
1072 /* 148.5MHz*/
1073
1074 static const struct audio_clock_info audio_clock_info_table[16] = {
1075 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1076 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1077 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1078 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1079 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1080 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1081 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1082 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1083 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1084 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1085 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1086 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1087 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1088 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1089 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1090 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1091 };
1092
1093 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1094 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1095 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1096 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1097 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1098 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1099 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1100 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1101 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1102 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1103 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1104 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1105 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1106 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1107 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1108 };
1109
1110 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1111 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1112 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1113 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1114 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1115 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1116 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1117 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1118 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1119 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1120 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1121 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1122 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1123 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1124 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1125
1126
1127 };
1128
speakers_to_channels(struct audio_speaker_flags speaker_flags)1129 static union audio_cea_channels speakers_to_channels(
1130 struct audio_speaker_flags speaker_flags)
1131 {
1132 union audio_cea_channels cea_channels = {0};
1133
1134 /* these are one to one */
1135 cea_channels.channels.FL = speaker_flags.FL_FR;
1136 cea_channels.channels.FR = speaker_flags.FL_FR;
1137 cea_channels.channels.LFE = speaker_flags.LFE;
1138 cea_channels.channels.FC = speaker_flags.FC;
1139
1140 /* if Rear Left and Right exist move RC speaker to channel 7
1141 * otherwise to channel 5
1142 */
1143 if (speaker_flags.RL_RR) {
1144 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1145 cea_channels.channels.RR = speaker_flags.RL_RR;
1146 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1147 } else {
1148 cea_channels.channels.RL_RC = speaker_flags.RC;
1149 }
1150
1151 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1152 if (speaker_flags.FLC_FRC) {
1153 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1154 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1155 } else {
1156 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1157 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1158 }
1159
1160 return cea_channels;
1161 }
1162
get_audio_clock_info(enum dc_color_depth color_depth,uint32_t crtc_pixel_clock_100Hz,uint32_t actual_pixel_clock_100Hz,struct audio_clock_info * audio_clock_info)1163 void get_audio_clock_info(
1164 enum dc_color_depth color_depth,
1165 uint32_t crtc_pixel_clock_100Hz,
1166 uint32_t actual_pixel_clock_100Hz,
1167 struct audio_clock_info *audio_clock_info)
1168 {
1169 const struct audio_clock_info *clock_info;
1170 uint32_t index;
1171 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1172 uint32_t audio_array_size;
1173
1174 switch (color_depth) {
1175 case COLOR_DEPTH_161616:
1176 clock_info = audio_clock_info_table_48bpc;
1177 audio_array_size = ARRAY_SIZE(
1178 audio_clock_info_table_48bpc);
1179 break;
1180 case COLOR_DEPTH_121212:
1181 clock_info = audio_clock_info_table_36bpc;
1182 audio_array_size = ARRAY_SIZE(
1183 audio_clock_info_table_36bpc);
1184 break;
1185 default:
1186 clock_info = audio_clock_info_table;
1187 audio_array_size = ARRAY_SIZE(
1188 audio_clock_info_table);
1189 break;
1190 }
1191
1192 if (clock_info != NULL) {
1193 /* search for exact pixel clock in table */
1194 for (index = 0; index < audio_array_size; index++) {
1195 if (clock_info[index].pixel_clock_in_10khz >
1196 crtc_pixel_clock_in_10khz)
1197 break; /* not match */
1198 else if (clock_info[index].pixel_clock_in_10khz ==
1199 crtc_pixel_clock_in_10khz) {
1200 /* match found */
1201 *audio_clock_info = clock_info[index];
1202 return;
1203 }
1204 }
1205 }
1206
1207 /* not found */
1208 if (actual_pixel_clock_100Hz == 0)
1209 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1210
1211 /* See HDMI spec the table entry under
1212 * pixel clock of "Other". */
1213 audio_clock_info->pixel_clock_in_10khz =
1214 actual_pixel_clock_100Hz / 100;
1215 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1216 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1217 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1218
1219 audio_clock_info->n_32khz = 4096;
1220 audio_clock_info->n_44khz = 6272;
1221 audio_clock_info->n_48khz = 6144;
1222 }
1223
enc1_se_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * audio_info)1224 static void enc1_se_audio_setup(
1225 struct stream_encoder *enc,
1226 unsigned int az_inst,
1227 struct audio_info *audio_info)
1228 {
1229 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1230
1231 uint32_t channels = 0;
1232
1233 ASSERT(audio_info);
1234 if (audio_info == NULL)
1235 /* This should not happen.it does so we don't get BSOD*/
1236 return;
1237
1238 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1239
1240 /* setup the audio stream source select (audio -> dig mapping) */
1241 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1242
1243 /* Channel allocation */
1244 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1245 }
1246
enc1_se_setup_hdmi_audio(struct stream_encoder * enc,const struct audio_crtc_info * crtc_info)1247 static void enc1_se_setup_hdmi_audio(
1248 struct stream_encoder *enc,
1249 const struct audio_crtc_info *crtc_info)
1250 {
1251 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1252
1253 struct audio_clock_info audio_clock_info = {0};
1254
1255 /* HDMI_AUDIO_PACKET_CONTROL */
1256 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1257 HDMI_AUDIO_DELAY_EN, 1);
1258
1259 /* AFMT_AUDIO_PACKET_CONTROL */
1260 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1261
1262 /* AFMT_AUDIO_PACKET_CONTROL2 */
1263 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1264 AFMT_AUDIO_LAYOUT_OVRD, 0,
1265 AFMT_60958_OSF_OVRD, 0);
1266
1267 /* HDMI_ACR_PACKET_CONTROL */
1268 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1269 HDMI_ACR_AUTO_SEND, 1,
1270 HDMI_ACR_SOURCE, 0,
1271 HDMI_ACR_AUDIO_PRIORITY, 0);
1272
1273 /* Program audio clock sample/regeneration parameters */
1274 get_audio_clock_info(crtc_info->color_depth,
1275 crtc_info->requested_pixel_clock_100Hz,
1276 crtc_info->calculated_pixel_clock_100Hz,
1277 &audio_clock_info);
1278 DC_LOG_HW_AUDIO(
1279 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
1280 "calculated_pixel_clock_100Hz = %d \n", __func__, \
1281 crtc_info->requested_pixel_clock_100Hz, \
1282 crtc_info->calculated_pixel_clock_100Hz);
1283
1284 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1285 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1286
1287 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1288 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1289
1290 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1291 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1292
1293 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1294 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1295
1296 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1297 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1298
1299 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1300 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1301
1302 /* Video driver cannot know in advance which sample rate will
1303 * be used by HD Audio driver
1304 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1305 * programmed below in interruppt callback
1306 */
1307
1308 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1309 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1310 */
1311 REG_UPDATE_2(AFMT_60958_0,
1312 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1313 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1314
1315 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1316 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1317
1318 /* AFMT_60958_2 now keep this settings until
1319 * Programming guide comes out
1320 */
1321 REG_UPDATE_6(AFMT_60958_2,
1322 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1323 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1324 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1325 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1326 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1327 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1328 }
1329
enc1_se_setup_dp_audio(struct stream_encoder * enc)1330 static void enc1_se_setup_dp_audio(
1331 struct stream_encoder *enc)
1332 {
1333 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1334
1335 /* --- DP Audio packet configurations --- */
1336
1337 /* ATP Configuration */
1338 REG_SET(DP_SEC_AUD_N, 0,
1339 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1340
1341 /* Async/auto-calc timestamp mode */
1342 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1343 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1344
1345 /* --- The following are the registers
1346 * copied from the SetupHDMI ---
1347 */
1348
1349 /* AFMT_AUDIO_PACKET_CONTROL */
1350 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1351
1352 /* AFMT_AUDIO_PACKET_CONTROL2 */
1353 /* Program the ATP and AIP next */
1354 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1355 AFMT_AUDIO_LAYOUT_OVRD, 0,
1356 AFMT_60958_OSF_OVRD, 0);
1357
1358 /* AFMT_INFOFRAME_CONTROL0 */
1359 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1360
1361 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1362 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1363 }
1364
enc1_se_enable_audio_clock(struct stream_encoder * enc,bool enable)1365 void enc1_se_enable_audio_clock(
1366 struct stream_encoder *enc,
1367 bool enable)
1368 {
1369 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1370
1371 if (REG(AFMT_CNTL) == 0)
1372 return; /* DCE8/10 does not have this register */
1373
1374 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1375
1376 /* wait for AFMT clock to turn on,
1377 * expectation: this should complete in 1-2 reads
1378 *
1379 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1380 *
1381 * TODO: wait for clock_on does not work well. May need HW
1382 * program sequence. But audio seems work normally even without wait
1383 * for clock_on status change
1384 */
1385 }
1386
enc1_se_enable_dp_audio(struct stream_encoder * enc)1387 void enc1_se_enable_dp_audio(
1388 struct stream_encoder *enc)
1389 {
1390 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1391
1392 /* Enable Audio packets */
1393 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1394
1395 /* Program the ATP and AIP next */
1396 REG_UPDATE_2(DP_SEC_CNTL,
1397 DP_SEC_ATP_ENABLE, 1,
1398 DP_SEC_AIP_ENABLE, 1);
1399
1400 /* Program STREAM_ENABLE after all the other enables. */
1401 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1402 }
1403
enc1_se_disable_dp_audio(struct stream_encoder * enc)1404 static void enc1_se_disable_dp_audio(
1405 struct stream_encoder *enc)
1406 {
1407 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1408 uint32_t value = 0;
1409
1410 /* Disable Audio packets */
1411 REG_UPDATE_5(DP_SEC_CNTL,
1412 DP_SEC_ASP_ENABLE, 0,
1413 DP_SEC_ATP_ENABLE, 0,
1414 DP_SEC_AIP_ENABLE, 0,
1415 DP_SEC_ACM_ENABLE, 0,
1416 DP_SEC_STREAM_ENABLE, 0);
1417
1418 /* This register shared with encoder info frame. Therefore we need to
1419 * keep master enabled if at least on of the fields is not 0
1420 */
1421 value = REG_READ(DP_SEC_CNTL);
1422 if (value != 0)
1423 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1424
1425 }
1426
enc1_se_audio_mute_control(struct stream_encoder * enc,bool mute)1427 void enc1_se_audio_mute_control(
1428 struct stream_encoder *enc,
1429 bool mute)
1430 {
1431 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1432
1433 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1434 }
1435
enc1_se_dp_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info)1436 void enc1_se_dp_audio_setup(
1437 struct stream_encoder *enc,
1438 unsigned int az_inst,
1439 struct audio_info *info)
1440 {
1441 enc1_se_audio_setup(enc, az_inst, info);
1442 }
1443
enc1_se_dp_audio_enable(struct stream_encoder * enc)1444 void enc1_se_dp_audio_enable(
1445 struct stream_encoder *enc)
1446 {
1447 enc1_se_enable_audio_clock(enc, true);
1448 enc1_se_setup_dp_audio(enc);
1449 enc1_se_enable_dp_audio(enc);
1450 }
1451
enc1_se_dp_audio_disable(struct stream_encoder * enc)1452 void enc1_se_dp_audio_disable(
1453 struct stream_encoder *enc)
1454 {
1455 enc1_se_disable_dp_audio(enc);
1456 enc1_se_enable_audio_clock(enc, false);
1457 }
1458
enc1_se_hdmi_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info,struct audio_crtc_info * audio_crtc_info)1459 void enc1_se_hdmi_audio_setup(
1460 struct stream_encoder *enc,
1461 unsigned int az_inst,
1462 struct audio_info *info,
1463 struct audio_crtc_info *audio_crtc_info)
1464 {
1465 enc1_se_enable_audio_clock(enc, true);
1466 enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1467 enc1_se_audio_setup(enc, az_inst, info);
1468 }
1469
enc1_se_hdmi_audio_disable(struct stream_encoder * enc)1470 void enc1_se_hdmi_audio_disable(
1471 struct stream_encoder *enc)
1472 {
1473 if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
1474 enc->afmt->funcs->afmt_powerdown(enc->afmt);
1475
1476 enc1_se_enable_audio_clock(enc, false);
1477 }
1478
1479
enc1_setup_stereo_sync(struct stream_encoder * enc,int tg_inst,bool enable)1480 void enc1_setup_stereo_sync(
1481 struct stream_encoder *enc,
1482 int tg_inst, bool enable)
1483 {
1484 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1485 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1486 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1487 }
1488
enc1_dig_connect_to_otg(struct stream_encoder * enc,int tg_inst)1489 void enc1_dig_connect_to_otg(
1490 struct stream_encoder *enc,
1491 int tg_inst)
1492 {
1493 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1494
1495 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1496 }
1497
enc1_dig_source_otg(struct stream_encoder * enc)1498 unsigned int enc1_dig_source_otg(
1499 struct stream_encoder *enc)
1500 {
1501 uint32_t tg_inst = 0;
1502 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1503
1504 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1505
1506 return tg_inst;
1507 }
1508
enc1_stream_encoder_dp_get_pixel_format(struct stream_encoder * enc,enum dc_pixel_encoding * encoding,enum dc_color_depth * depth)1509 bool enc1_stream_encoder_dp_get_pixel_format(
1510 struct stream_encoder *enc,
1511 enum dc_pixel_encoding *encoding,
1512 enum dc_color_depth *depth)
1513 {
1514 uint32_t hw_encoding = 0;
1515 uint32_t hw_depth = 0;
1516 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1517
1518 if (enc == NULL ||
1519 encoding == NULL ||
1520 depth == NULL)
1521 return false;
1522
1523 REG_GET_2(DP_PIXEL_FORMAT,
1524 DP_PIXEL_ENCODING, &hw_encoding,
1525 DP_COMPONENT_DEPTH, &hw_depth);
1526
1527 switch (hw_depth) {
1528 case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1529 *depth = COLOR_DEPTH_666;
1530 break;
1531 case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1532 *depth = COLOR_DEPTH_888;
1533 break;
1534 case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1535 *depth = COLOR_DEPTH_101010;
1536 break;
1537 case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1538 *depth = COLOR_DEPTH_121212;
1539 break;
1540 case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1541 *depth = COLOR_DEPTH_161616;
1542 break;
1543 default:
1544 *depth = COLOR_DEPTH_UNDEFINED;
1545 break;
1546 }
1547
1548 switch (hw_encoding) {
1549 case DP_PIXEL_ENCODING_TYPE_RGB444:
1550 *encoding = PIXEL_ENCODING_RGB;
1551 break;
1552 case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1553 *encoding = PIXEL_ENCODING_YCBCR422;
1554 break;
1555 case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1556 case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1557 *encoding = PIXEL_ENCODING_YCBCR444;
1558 break;
1559 case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1560 *encoding = PIXEL_ENCODING_YCBCR420;
1561 break;
1562 default:
1563 *encoding = PIXEL_ENCODING_UNDEFINED;
1564 break;
1565 }
1566 return true;
1567 }
1568
1569 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1570 .dp_set_stream_attribute =
1571 enc1_stream_encoder_dp_set_stream_attribute,
1572 .hdmi_set_stream_attribute =
1573 enc1_stream_encoder_hdmi_set_stream_attribute,
1574 .dvi_set_stream_attribute =
1575 enc1_stream_encoder_dvi_set_stream_attribute,
1576 .set_throttled_vcp_size =
1577 enc1_stream_encoder_set_throttled_vcp_size,
1578 .update_hdmi_info_packets =
1579 enc1_stream_encoder_update_hdmi_info_packets,
1580 .stop_hdmi_info_packets =
1581 enc1_stream_encoder_stop_hdmi_info_packets,
1582 .update_dp_info_packets =
1583 enc1_stream_encoder_update_dp_info_packets,
1584 .send_immediate_sdp_message =
1585 enc1_stream_encoder_send_immediate_sdp_message,
1586 .stop_dp_info_packets =
1587 enc1_stream_encoder_stop_dp_info_packets,
1588 .dp_blank =
1589 enc1_stream_encoder_dp_blank,
1590 .dp_unblank =
1591 enc1_stream_encoder_dp_unblank,
1592 .audio_mute_control = enc1_se_audio_mute_control,
1593
1594 .dp_audio_setup = enc1_se_dp_audio_setup,
1595 .dp_audio_enable = enc1_se_dp_audio_enable,
1596 .dp_audio_disable = enc1_se_dp_audio_disable,
1597
1598 .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1599 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1600 .setup_stereo_sync = enc1_setup_stereo_sync,
1601 .set_avmute = enc1_stream_encoder_set_avmute,
1602 .dig_connect_to_otg = enc1_dig_connect_to_otg,
1603 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1604 .dig_source_otg = enc1_dig_source_otg,
1605
1606 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
1607 };
1608
dcn10_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)1609 void dcn10_stream_encoder_construct(
1610 struct dcn10_stream_encoder *enc1,
1611 struct dc_context *ctx,
1612 struct dc_bios *bp,
1613 enum engine_id eng_id,
1614 const struct dcn10_stream_enc_registers *regs,
1615 const struct dcn10_stream_encoder_shift *se_shift,
1616 const struct dcn10_stream_encoder_mask *se_mask)
1617 {
1618 enc1->base.funcs = &dcn10_str_enc_funcs;
1619 enc1->base.ctx = ctx;
1620 enc1->base.id = eng_id;
1621 enc1->base.bp = bp;
1622 enc1->regs = regs;
1623 enc1->se_shift = se_shift;
1624 enc1->se_mask = se_mask;
1625 enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
1626 }
1627
1628