1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_ring_ops.h"
7
8 #include <generated/xe_wa_oob.h>
9
10 #include "instructions/xe_gpu_commands.h"
11 #include "instructions/xe_mi_commands.h"
12 #include "regs/xe_engine_regs.h"
13 #include "regs/xe_gt_regs.h"
14 #include "regs/xe_lrc_layout.h"
15 #include "xe_exec_queue_types.h"
16 #include "xe_gt.h"
17 #include "xe_lrc.h"
18 #include "xe_macros.h"
19 #include "xe_sched_job.h"
20 #include "xe_sriov.h"
21 #include "xe_vm_types.h"
22 #include "xe_vm.h"
23 #include "xe_wa.h"
24
25 /*
26 * 3D-related flags that can't be set on _engines_ that lack access to the 3D
27 * pipeline (i.e., CCS engines).
28 */
29 #define PIPE_CONTROL_3D_ENGINE_FLAGS (\
30 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
31 PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
32 PIPE_CONTROL_TILE_CACHE_FLUSH | \
33 PIPE_CONTROL_DEPTH_STALL | \
34 PIPE_CONTROL_STALL_AT_SCOREBOARD | \
35 PIPE_CONTROL_PSD_SYNC | \
36 PIPE_CONTROL_AMFS_FLUSH | \
37 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
38 PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
39
40 /* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
41 #define PIPE_CONTROL_3D_ARCH_FLAGS ( \
42 PIPE_CONTROL_3D_ENGINE_FLAGS | \
43 PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
44 PIPE_CONTROL_FLUSH_ENABLE | \
45 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
46 PIPE_CONTROL_DC_FLUSH_ENABLE)
47
preparser_disable(bool state)48 static u32 preparser_disable(bool state)
49 {
50 return MI_ARB_CHECK | BIT(8) | state;
51 }
52
emit_aux_table_inv(struct xe_gt * gt,struct xe_reg reg,u32 * dw,int i)53 static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
54 u32 *dw, int i)
55 {
56 dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;
57 dw[i++] = reg.addr + gt->mmio.adj_offset;
58 dw[i++] = AUX_INV;
59 dw[i++] = MI_NOOP;
60
61 return i;
62 }
63
emit_user_interrupt(u32 * dw,int i)64 static int emit_user_interrupt(u32 *dw, int i)
65 {
66 dw[i++] = MI_USER_INTERRUPT;
67 dw[i++] = MI_ARB_ON_OFF | MI_ARB_ENABLE;
68 dw[i++] = MI_ARB_CHECK;
69
70 return i;
71 }
72
emit_store_imm_ggtt(u32 addr,u32 value,u32 * dw,int i)73 static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
74 {
75 dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1);
76 dw[i++] = addr;
77 dw[i++] = 0;
78 dw[i++] = value;
79
80 return i;
81 }
82
emit_flush_dw(u32 * dw,int i)83 static int emit_flush_dw(u32 *dw, int i)
84 {
85 dw[i++] = MI_FLUSH_DW | MI_FLUSH_IMM_DW;
86 dw[i++] = 0;
87 dw[i++] = 0;
88 dw[i++] = 0;
89
90 return i;
91 }
92
emit_flush_imm_ggtt(u32 addr,u32 value,u32 flags,u32 * dw,int i)93 static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32 *dw, int i)
94 {
95 dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
96 flags;
97 dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
98 dw[i++] = 0;
99 dw[i++] = value;
100
101 return i;
102 }
103
emit_bb_start(u64 batch_addr,u32 ppgtt_flag,u32 * dw,int i)104 static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
105 {
106 dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3);
107 dw[i++] = lower_32_bits(batch_addr);
108 dw[i++] = upper_32_bits(batch_addr);
109
110 return i;
111 }
112
emit_flush_invalidate(u32 addr,u32 val,u32 * dw,int i)113 static int emit_flush_invalidate(u32 addr, u32 val, u32 *dw, int i)
114 {
115 dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW |
116 MI_FLUSH_IMM_DW;
117
118 dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
119 dw[i++] = 0;
120 dw[i++] = val;
121
122 return i;
123 }
124
125 static int
emit_pipe_control(u32 * dw,int i,u32 bit_group_0,u32 bit_group_1,u32 offset,u32 value)126 emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset, u32 value)
127 {
128 dw[i++] = GFX_OP_PIPE_CONTROL(6) | bit_group_0;
129 dw[i++] = bit_group_1;
130 dw[i++] = offset;
131 dw[i++] = 0;
132 dw[i++] = value;
133 dw[i++] = 0;
134
135 return i;
136 }
137
emit_pipe_invalidate(u32 mask_flags,bool invalidate_tlb,u32 * dw,int i)138 static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
139 int i)
140 {
141 u32 flags0 = 0;
142 u32 flags1 = PIPE_CONTROL_CS_STALL |
143 PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |
144 PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
145 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
146 PIPE_CONTROL_VF_CACHE_INVALIDATE |
147 PIPE_CONTROL_CONST_CACHE_INVALIDATE |
148 PIPE_CONTROL_STATE_CACHE_INVALIDATE |
149 PIPE_CONTROL_QW_WRITE |
150 PIPE_CONTROL_STORE_DATA_INDEX;
151
152 if (invalidate_tlb)
153 flags1 |= PIPE_CONTROL_TLB_INVALIDATE;
154
155 flags1 &= ~mask_flags;
156
157 if (flags1 & PIPE_CONTROL_VF_CACHE_INVALIDATE)
158 flags0 |= PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE;
159
160 return emit_pipe_control(dw, i, flags0, flags1,
161 LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
162 }
163
emit_store_imm_ppgtt_posted(u64 addr,u64 value,u32 * dw,int i)164 static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
165 u32 *dw, int i)
166 {
167 dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1);
168 dw[i++] = lower_32_bits(addr);
169 dw[i++] = upper_32_bits(addr);
170 dw[i++] = lower_32_bits(value);
171 dw[i++] = upper_32_bits(value);
172
173 return i;
174 }
175
emit_render_cache_flush(struct xe_sched_job * job,u32 * dw,int i)176 static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
177 {
178 struct xe_gt *gt = job->q->gt;
179 bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
180 u32 flags;
181
182 if (XE_WA(gt, 14016712196))
183 i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
184 LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
185
186 flags = (PIPE_CONTROL_CS_STALL |
187 PIPE_CONTROL_TILE_CACHE_FLUSH |
188 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
189 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
190 PIPE_CONTROL_DC_FLUSH_ENABLE |
191 PIPE_CONTROL_FLUSH_ENABLE);
192
193 if (XE_WA(gt, 1409600907))
194 flags |= PIPE_CONTROL_DEPTH_STALL;
195
196 if (lacks_render)
197 flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
198 else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
199 flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
200
201 return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);
202 }
203
emit_pipe_control_to_ring_end(struct xe_hw_engine * hwe,u32 * dw,int i)204 static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i)
205 {
206 if (hwe->class != XE_ENGINE_CLASS_RENDER)
207 return i;
208
209 if (XE_WA(hwe->gt, 16020292621))
210 i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_LRI_POST_SYNC,
211 RING_NOPID(hwe->mmio_base).addr, 0);
212
213 return i;
214 }
215
emit_pipe_imm_ggtt(u32 addr,u32 value,bool stall_only,u32 * dw,int i)216 static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw,
217 int i)
218 {
219 u32 flags = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_GLOBAL_GTT_IVB |
220 PIPE_CONTROL_QW_WRITE;
221
222 if (!stall_only)
223 flags |= PIPE_CONTROL_FLUSH_ENABLE;
224
225 return emit_pipe_control(dw, i, 0, flags, addr, value);
226 }
227
get_ppgtt_flag(struct xe_sched_job * job)228 static u32 get_ppgtt_flag(struct xe_sched_job *job)
229 {
230 if (job->q->vm && !job->ggtt)
231 return BIT(8);
232
233 return 0;
234 }
235
emit_copy_timestamp(struct xe_lrc * lrc,u32 * dw,int i)236 static int emit_copy_timestamp(struct xe_lrc *lrc, u32 *dw, int i)
237 {
238 dw[i++] = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT | MI_SRM_ADD_CS_OFFSET;
239 dw[i++] = RING_CTX_TIMESTAMP(0).addr;
240 dw[i++] = xe_lrc_ctx_job_timestamp_ggtt_addr(lrc);
241 dw[i++] = 0;
242
243 return i;
244 }
245
246 /* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */
__emit_job_gen12_simple(struct xe_sched_job * job,struct xe_lrc * lrc,u64 batch_addr,u32 seqno)247 static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc,
248 u64 batch_addr, u32 seqno)
249 {
250 u32 dw[MAX_JOB_SIZE_DW], i = 0;
251 u32 ppgtt_flag = get_ppgtt_flag(job);
252 struct xe_gt *gt = job->q->gt;
253
254 i = emit_copy_timestamp(lrc, dw, i);
255
256 if (job->ring_ops_flush_tlb) {
257 dw[i++] = preparser_disable(true);
258 i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
259 seqno, MI_INVALIDATE_TLB, dw, i);
260 dw[i++] = preparser_disable(false);
261 } else {
262 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
263 seqno, dw, i);
264 }
265
266 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
267
268 if (job->user_fence.used) {
269 i = emit_flush_dw(dw, i);
270 i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
271 job->user_fence.value,
272 dw, i);
273 }
274
275 i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
276
277 i = emit_user_interrupt(dw, i);
278
279 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
280
281 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
282 }
283
has_aux_ccs(struct xe_device * xe)284 static bool has_aux_ccs(struct xe_device *xe)
285 {
286 /*
287 * PVC is a special case that has no compression of either type
288 * (FlatCCS or AuxCCS). Also, AuxCCS is no longer used from Xe2
289 * onward, so any future platforms with no FlatCCS will not have
290 * AuxCCS either.
291 */
292 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
293 return false;
294
295 return !xe->info.has_flat_ccs;
296 }
297
__emit_job_gen12_video(struct xe_sched_job * job,struct xe_lrc * lrc,u64 batch_addr,u32 seqno)298 static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
299 u64 batch_addr, u32 seqno)
300 {
301 u32 dw[MAX_JOB_SIZE_DW], i = 0;
302 u32 ppgtt_flag = get_ppgtt_flag(job);
303 struct xe_gt *gt = job->q->gt;
304 struct xe_device *xe = gt_to_xe(gt);
305 bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE;
306
307 i = emit_copy_timestamp(lrc, dw, i);
308
309 dw[i++] = preparser_disable(true);
310
311 /* hsdes: 1809175790 */
312 if (has_aux_ccs(xe)) {
313 if (decode)
314 i = emit_aux_table_inv(gt, VD0_AUX_INV, dw, i);
315 else
316 i = emit_aux_table_inv(gt, VE0_AUX_INV, dw, i);
317 }
318
319 if (job->ring_ops_flush_tlb)
320 i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
321 seqno, MI_INVALIDATE_TLB, dw, i);
322
323 dw[i++] = preparser_disable(false);
324
325 if (!job->ring_ops_flush_tlb)
326 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
327 seqno, dw, i);
328
329 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
330
331 if (job->user_fence.used) {
332 i = emit_flush_dw(dw, i);
333 i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
334 job->user_fence.value,
335 dw, i);
336 }
337
338 i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
339
340 i = emit_user_interrupt(dw, i);
341
342 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
343
344 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
345 }
346
__emit_job_gen12_render_compute(struct xe_sched_job * job,struct xe_lrc * lrc,u64 batch_addr,u32 seqno)347 static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
348 struct xe_lrc *lrc,
349 u64 batch_addr, u32 seqno)
350 {
351 u32 dw[MAX_JOB_SIZE_DW], i = 0;
352 u32 ppgtt_flag = get_ppgtt_flag(job);
353 struct xe_gt *gt = job->q->gt;
354 struct xe_device *xe = gt_to_xe(gt);
355 bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
356 u32 mask_flags = 0;
357
358 i = emit_copy_timestamp(lrc, dw, i);
359
360 dw[i++] = preparser_disable(true);
361 if (lacks_render)
362 mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
363 else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
364 mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS;
365
366 /* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */
367 i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
368
369 /* hsdes: 1809175790 */
370 if (has_aux_ccs(xe))
371 i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
372
373 dw[i++] = preparser_disable(false);
374
375 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
376 seqno, dw, i);
377
378 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
379
380 i = emit_render_cache_flush(job, dw, i);
381
382 if (job->user_fence.used)
383 i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
384 job->user_fence.value,
385 dw, i);
386
387 i = emit_pipe_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, lacks_render, dw, i);
388
389 i = emit_user_interrupt(dw, i);
390
391 i = emit_pipe_control_to_ring_end(job->q->hwe, dw, i);
392
393 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
394
395 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
396 }
397
emit_migration_job_gen12(struct xe_sched_job * job,struct xe_lrc * lrc,u32 seqno)398 static void emit_migration_job_gen12(struct xe_sched_job *job,
399 struct xe_lrc *lrc, u32 seqno)
400 {
401 u32 saddr = xe_lrc_start_seqno_ggtt_addr(lrc);
402 u32 dw[MAX_JOB_SIZE_DW], i = 0;
403
404 i = emit_copy_timestamp(lrc, dw, i);
405
406 i = emit_store_imm_ggtt(saddr, seqno, dw, i);
407
408 dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */
409
410 i = emit_bb_start(job->ptrs[0].batch_addr, BIT(8), dw, i);
411
412 dw[i++] = preparser_disable(true);
413 i = emit_flush_invalidate(saddr, seqno, dw, i);
414 dw[i++] = preparser_disable(false);
415
416 i = emit_bb_start(job->ptrs[1].batch_addr, BIT(8), dw, i);
417
418 dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | job->migrate_flush_flags |
419 MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW;
420 dw[i++] = xe_lrc_seqno_ggtt_addr(lrc) | MI_FLUSH_DW_USE_GTT;
421 dw[i++] = 0;
422 dw[i++] = seqno; /* value */
423
424 i = emit_user_interrupt(dw, i);
425
426 xe_gt_assert(job->q->gt, i <= MAX_JOB_SIZE_DW);
427
428 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
429 }
430
emit_job_gen12_gsc(struct xe_sched_job * job)431 static void emit_job_gen12_gsc(struct xe_sched_job *job)
432 {
433 struct xe_gt *gt = job->q->gt;
434
435 xe_gt_assert(gt, job->q->width <= 1); /* no parallel submission for GSCCS */
436
437 __emit_job_gen12_simple(job, job->q->lrc[0],
438 job->ptrs[0].batch_addr,
439 xe_sched_job_lrc_seqno(job));
440 }
441
emit_job_gen12_copy(struct xe_sched_job * job)442 static void emit_job_gen12_copy(struct xe_sched_job *job)
443 {
444 int i;
445
446 if (xe_sched_job_is_migration(job->q)) {
447 emit_migration_job_gen12(job, job->q->lrc[0],
448 xe_sched_job_lrc_seqno(job));
449 return;
450 }
451
452 for (i = 0; i < job->q->width; ++i)
453 __emit_job_gen12_simple(job, job->q->lrc[i],
454 job->ptrs[i].batch_addr,
455 xe_sched_job_lrc_seqno(job));
456 }
457
emit_job_gen12_video(struct xe_sched_job * job)458 static void emit_job_gen12_video(struct xe_sched_job *job)
459 {
460 int i;
461
462 /* FIXME: Not doing parallel handshake for now */
463 for (i = 0; i < job->q->width; ++i)
464 __emit_job_gen12_video(job, job->q->lrc[i],
465 job->ptrs[i].batch_addr,
466 xe_sched_job_lrc_seqno(job));
467 }
468
emit_job_gen12_render_compute(struct xe_sched_job * job)469 static void emit_job_gen12_render_compute(struct xe_sched_job *job)
470 {
471 int i;
472
473 for (i = 0; i < job->q->width; ++i)
474 __emit_job_gen12_render_compute(job, job->q->lrc[i],
475 job->ptrs[i].batch_addr,
476 xe_sched_job_lrc_seqno(job));
477 }
478
479 static const struct xe_ring_ops ring_ops_gen12_gsc = {
480 .emit_job = emit_job_gen12_gsc,
481 };
482
483 static const struct xe_ring_ops ring_ops_gen12_copy = {
484 .emit_job = emit_job_gen12_copy,
485 };
486
487 static const struct xe_ring_ops ring_ops_gen12_video = {
488 .emit_job = emit_job_gen12_video,
489 };
490
491 static const struct xe_ring_ops ring_ops_gen12_render_compute = {
492 .emit_job = emit_job_gen12_render_compute,
493 };
494
495 const struct xe_ring_ops *
xe_ring_ops_get(struct xe_gt * gt,enum xe_engine_class class)496 xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class)
497 {
498 switch (class) {
499 case XE_ENGINE_CLASS_OTHER:
500 return &ring_ops_gen12_gsc;
501 case XE_ENGINE_CLASS_COPY:
502 return &ring_ops_gen12_copy;
503 case XE_ENGINE_CLASS_VIDEO_DECODE:
504 case XE_ENGINE_CLASS_VIDEO_ENHANCE:
505 return &ring_ops_gen12_video;
506 case XE_ENGINE_CLASS_RENDER:
507 case XE_ENGINE_CLASS_COMPUTE:
508 return &ring_ops_gen12_render_compute;
509 default:
510 return NULL;
511 }
512 }
513