1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Copyright (c) 2012 Linaro Ltd 8 * http://www.linaro.org 9 * 10 * Author: Thomas Abraham <thomas.ab@samsung.com> 11 */ 12 13 #ifndef __PINCTRL_SAMSUNG_H 14 #define __PINCTRL_SAMSUNG_H 15 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/machine.h> 21 22 #include <linux/gpio/driver.h> 23 24 /** 25 * enum pincfg_type - possible pin configuration types supported. 26 * @PINCFG_TYPE_FUNC: Function configuration. 27 * @PINCFG_TYPE_DAT: Pin value configuration. 28 * @PINCFG_TYPE_PUD: Pull up/down configuration. 29 * @PINCFG_TYPE_DRV: Drive strength configuration. 30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode. 31 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode. 32 */ 33 enum pincfg_type { 34 PINCFG_TYPE_FUNC, 35 PINCFG_TYPE_DAT, 36 PINCFG_TYPE_PUD, 37 PINCFG_TYPE_DRV, 38 PINCFG_TYPE_CON_PDN, 39 PINCFG_TYPE_PUD_PDN, 40 41 PINCFG_TYPE_NUM 42 }; 43 44 /* 45 * pin configuration (pull up/down and drive strength) type and its value are 46 * packed together into a 16-bits. The upper 8-bits represent the configuration 47 * type and the lower 8-bits hold the value of the configuration type. 48 */ 49 #define PINCFG_TYPE_MASK 0xFF 50 #define PINCFG_VALUE_SHIFT 8 51 #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) 52 #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) 53 #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) 54 #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ 55 PINCFG_VALUE_SHIFT) 56 /* 57 * Values for the pin CON register, choosing pin function. 58 * The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210, 59 * Exynos ARMv7, Exynos ARMv8, Tesla FSD. 60 */ 61 #define PIN_CON_FUNC_INPUT 0x0 62 #define PIN_CON_FUNC_OUTPUT 0x1 63 64 /* Values for the pin PUD register */ 65 #define EXYNOS_PIN_PUD_PULL_DISABLE 0x0 66 #define EXYNOS_PIN_PID_PULL_DOWN 0x1 67 #define EXYNOS_PIN_PID_PULL_UP 0x3 68 69 /* 70 * enum pud_index - Possible index values to access the pud_val array. 71 * @PUD_PULL_DISABLE: Index for the value of pud disable 72 * @PUD_PULL_DOWN: Index for the value of pull down enable 73 * @PUD_PULL_UP: Index for the value of pull up enable 74 * @PUD_MAX: Maximum value of the index 75 */ 76 enum pud_index { 77 PUD_PULL_DISABLE, 78 PUD_PULL_DOWN, 79 PUD_PULL_UP, 80 PUD_MAX, 81 }; 82 83 /** 84 * enum eint_type - possible external interrupt types. 85 * @EINT_TYPE_NONE: bank does not support external interrupts 86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts 87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts 88 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts 89 * 90 * Samsung GPIO controller groups all the available pins into banks. The pins 91 * in a pin bank can support external gpio interrupts or external wakeup 92 * interrupts or no interrupts at all. From a software perspective, the only 93 * difference between external gpio and external wakeup interrupts is that 94 * the wakeup interrupts can additionally wakeup the system if it is in 95 * suspended state. 96 */ 97 enum eint_type { 98 EINT_TYPE_NONE, 99 EINT_TYPE_GPIO, 100 EINT_TYPE_WKUP, 101 EINT_TYPE_WKUP_MUX, 102 }; 103 104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ 105 #define PIN_NAME_LENGTH 10 106 107 #define PIN_GROUP(n, p, f) \ 108 { \ 109 .name = n, \ 110 .pins = p, \ 111 .num_pins = ARRAY_SIZE(p), \ 112 .func = f \ 113 } 114 115 #define PMX_FUNC(n, g) \ 116 { \ 117 .name = n, \ 118 .groups = g, \ 119 .num_groups = ARRAY_SIZE(g), \ 120 } 121 122 struct samsung_pinctrl_drv_data; 123 124 /** 125 * struct samsung_pin_bank_type: pin bank type description 126 * @fld_width: widths of configuration bitfields (0 if unavailable) 127 * @reg_offset: offsets of configuration registers (don't care of width is 0) 128 */ 129 struct samsung_pin_bank_type { 130 u8 fld_width[PINCFG_TYPE_NUM]; 131 u8 reg_offset[PINCFG_TYPE_NUM]; 132 }; 133 134 /** 135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data). 136 * @type: type of the bank (register offsets and bitfield widths) 137 * @pctl_offset: starting offset of the pin-bank registers. 138 * @pctl_res_idx: index of base address for pin-bank registers. 139 * @nr_pins: number of pins included in this bank. 140 * @eint_func: function to set in CON register to configure pin as EINT. 141 * @eint_type: type of the external interrupt supported by the bank. 142 * @eint_mask: bit mask of pins which support EINT function. 143 * @eint_offset: SoC-specific EINT register or interrupt offset of bank. 144 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank. 145 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. 146 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. 147 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset. 148 * @name: name to be prefixed for each pin in this pin bank. 149 */ 150 struct samsung_pin_bank_data { 151 const struct samsung_pin_bank_type *type; 152 u32 pctl_offset; 153 u8 pctl_res_idx; 154 u8 nr_pins; 155 u8 eint_func; 156 enum eint_type eint_type; 157 u32 eint_mask; 158 u32 eint_offset; 159 u32 eint_con_offset; 160 u32 eint_mask_offset; 161 u32 eint_pend_offset; 162 u32 eint_fltcon_offset; 163 const char *name; 164 }; 165 166 /** 167 * struct samsung_pin_bank: represent a controller pin-bank. 168 * @type: type of the bank (register offsets and bitfield widths) 169 * @pctl_base: base address of the pin-bank registers 170 * @pctl_offset: starting offset of the pin-bank registers. 171 * @nr_pins: number of pins included in this bank. 172 * @eint_base: base address of the pin-bank EINT registers. 173 * @eint_func: function to set in CON register to configure pin as EINT. 174 * @eint_type: type of the external interrupt supported by the bank. 175 * @eint_mask: bit mask of pins which support EINT function. 176 * @eint_offset: SoC-specific EINT register or interrupt offset of bank. 177 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank. 178 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. 179 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. 180 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset. 181 * @name: name to be prefixed for each pin in this pin bank. 182 * @id: id of the bank, propagated to the pin range. 183 * @pin_base: starting pin number of the bank. 184 * @soc_priv: per-bank private data for SoC-specific code. 185 * @of_node: OF node of the bank. 186 * @drvdata: link to controller driver data 187 * @irq_domain: IRQ domain of the bank. 188 * @gpio_chip: GPIO chip of the bank. 189 * @grange: linux gpio pin range supported by this bank. 190 * @irq_chip: link to irq chip for external gpio and wakeup interrupts. 191 * @slock: spinlock protecting bank registers 192 * @pm_save: saved register values during suspend 193 */ 194 struct samsung_pin_bank { 195 const struct samsung_pin_bank_type *type; 196 void __iomem *pctl_base; 197 u32 pctl_offset; 198 u8 nr_pins; 199 void __iomem *eint_base; 200 u8 eint_func; 201 enum eint_type eint_type; 202 u32 eint_mask; 203 u32 eint_offset; 204 u32 eint_con_offset; 205 u32 eint_mask_offset; 206 u32 eint_pend_offset; 207 u32 eint_fltcon_offset; 208 const char *name; 209 u32 id; 210 211 u32 pin_base; 212 void *soc_priv; 213 struct fwnode_handle *fwnode; 214 struct samsung_pinctrl_drv_data *drvdata; 215 struct irq_domain *irq_domain; 216 struct gpio_chip gpio_chip; 217 struct pinctrl_gpio_range grange; 218 struct exynos_irq_chip *irq_chip; 219 raw_spinlock_t slock; 220 221 u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ 222 }; 223 224 /** 225 * struct samsung_retention_data: runtime pin-bank retention control data. 226 * @regs: array of PMU registers to control pad retention. 227 * @nr_regs: number of registers in @regs array. 228 * @value: value to store to registers to turn off retention. 229 * @refcnt: atomic counter if retention control affects more than one bank. 230 * @priv: retention control code private data 231 * @enable: platform specific callback to enter retention mode. 232 * @disable: platform specific callback to exit retention mode. 233 **/ 234 struct samsung_retention_ctrl { 235 const u32 *regs; 236 int nr_regs; 237 u32 value; 238 atomic_t *refcnt; 239 void *priv; 240 void (*enable)(struct samsung_pinctrl_drv_data *); 241 void (*disable)(struct samsung_pinctrl_drv_data *); 242 }; 243 244 /** 245 * struct samsung_retention_data: represent a pin-bank retention control data. 246 * @regs: array of PMU registers to control pad retention. 247 * @nr_regs: number of registers in @regs array. 248 * @value: value to store to registers to turn off retention. 249 * @refcnt: atomic counter if retention control affects more than one bank. 250 * @init: platform specific callback to initialize retention control. 251 **/ 252 struct samsung_retention_data { 253 const u32 *regs; 254 int nr_regs; 255 u32 value; 256 atomic_t *refcnt; 257 struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *, 258 const struct samsung_retention_data *); 259 }; 260 261 /** 262 * struct samsung_pin_ctrl: represent a pin controller. 263 * @pin_banks: list of pin banks included in this controller. 264 * @nr_banks: number of pin banks. 265 * @nr_ext_resources: number of the extra base address for pin banks. 266 * @retention_data: configuration data for retention control. 267 * @eint_gpio_init: platform specific callback to setup the external gpio 268 * interrupts for the controller. 269 * @eint_wkup_init: platform specific callback to setup the external wakeup 270 * interrupts for the controller. 271 * @suspend: platform specific suspend callback, executed during pin controller 272 * device suspend, see samsung_pinctrl_suspend() 273 * @resume: platform specific resume callback, executed during pin controller 274 * device suspend, see samsung_pinctrl_resume() 275 * 276 * External wakeup interrupts must define at least eint_wkup_init, 277 * retention_data and suspend in order for proper suspend/resume to work. 278 */ 279 struct samsung_pin_ctrl { 280 const struct samsung_pin_bank_data *pin_banks; 281 unsigned int nr_banks; 282 unsigned int nr_ext_resources; 283 const struct samsung_retention_data *retention_data; 284 285 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 286 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); 287 void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata); 288 void (*suspend)(struct samsung_pinctrl_drv_data *); 289 void (*resume)(struct samsung_pinctrl_drv_data *); 290 }; 291 292 /** 293 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. 294 * @node: global list node 295 * @virt_base: register base address of the controller; this will be equal 296 * to each bank samsung_pin_bank->pctl_base and used on legacy 297 * platforms (like S3C24XX or S3C64XX) which has to access the base 298 * through samsung_pinctrl_drv_data, not samsung_pin_bank). 299 * @dev: device instance representing the controller. 300 * @irq: interrpt number used by the controller to notify gpio interrupts. 301 * @pclk: optional bus clock if required for accessing registers 302 * @ctrl: pin controller instance managed by the driver. 303 * @pctl: pin controller descriptor registered with the pinctrl subsystem. 304 * @pctl_dev: cookie representing pinctrl device instance. 305 * @pin_groups: list of pin groups available to the driver. 306 * @nr_groups: number of such pin groups. 307 * @pmx_functions: list of pin functions available to the driver. 308 * @nr_function: number of such pin functions. 309 * @nr_pins: number of pins supported by the controller. 310 * @retention_ctrl: retention control runtime data. 311 * @suspend: platform specific suspend callback, executed during pin controller 312 * device suspend, see samsung_pinctrl_suspend() 313 * @resume: platform specific resume callback, executed during pin controller 314 * device suspend, see samsung_pinctrl_resume() 315 */ 316 struct samsung_pinctrl_drv_data { 317 struct list_head node; 318 void __iomem *virt_base; 319 struct device *dev; 320 int irq; 321 struct clk *pclk; 322 323 struct pinctrl_desc pctl; 324 struct pinctrl_dev *pctl_dev; 325 326 const struct samsung_pin_group *pin_groups; 327 unsigned int nr_groups; 328 const struct samsung_pmx_func *pmx_functions; 329 unsigned int nr_functions; 330 331 struct samsung_pin_bank *pin_banks; 332 unsigned int nr_banks; 333 unsigned int nr_pins; 334 unsigned int pud_val[PUD_MAX]; 335 336 struct samsung_retention_ctrl *retention_ctrl; 337 338 void (*suspend)(struct samsung_pinctrl_drv_data *); 339 void (*resume)(struct samsung_pinctrl_drv_data *); 340 }; 341 342 /** 343 * struct samsung_pinctrl_of_match_data: OF match device specific configuration data. 344 * @ctrl: array of pin controller data. 345 * @num_ctrl: size of array @ctrl. 346 */ 347 struct samsung_pinctrl_of_match_data { 348 const struct samsung_pin_ctrl *ctrl; 349 unsigned int num_ctrl; 350 }; 351 352 /** 353 * struct samsung_pin_group: represent group of pins of a pinmux function. 354 * @name: name of the pin group, used to lookup the group. 355 * @pins: the pins included in this group. 356 * @num_pins: number of pins included in this group. 357 * @func: the function number to be programmed when selected. 358 */ 359 struct samsung_pin_group { 360 const char *name; 361 const unsigned int *pins; 362 u8 num_pins; 363 u8 func; 364 }; 365 366 /** 367 * struct samsung_pmx_func: represent a pin function. 368 * @name: name of the pin function, used to lookup the function. 369 * @groups: one or more names of pin groups that provide this function. 370 * @num_groups: number of groups included in @groups. 371 */ 372 struct samsung_pmx_func { 373 const char *name; 374 const char **groups; 375 u8 num_groups; 376 u32 val; 377 }; 378 379 /* list of all exported SoC specific data */ 380 extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; 381 extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; 382 extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; 383 extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data; 384 extern const struct samsung_pinctrl_of_match_data exynos5250_of_data; 385 extern const struct samsung_pinctrl_of_match_data exynos5260_of_data; 386 extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; 387 extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; 388 extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; 389 extern const struct samsung_pinctrl_of_match_data exynos7_of_data; 390 extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; 391 extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; 392 extern const struct samsung_pinctrl_of_match_data exynos850_of_data; 393 extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; 394 extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; 395 extern const struct samsung_pinctrl_of_match_data exynos990_of_data; 396 extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; 397 extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; 398 extern const struct samsung_pinctrl_of_match_data fsd_of_data; 399 extern const struct samsung_pinctrl_of_match_data gs101_of_data; 400 extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; 401 extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; 402 extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; 403 extern const struct samsung_pinctrl_of_match_data s3c2440_of_data; 404 extern const struct samsung_pinctrl_of_match_data s3c2450_of_data; 405 extern const struct samsung_pinctrl_of_match_data s5pv210_of_data; 406 407 #endif /* __PINCTRL_SAMSUNG_H */ 408