1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
10 */
11
12 #include "ef100_nic.h"
13 #include "efx_common.h"
14 #include "efx_channels.h"
15 #include "io.h"
16 #include "selftest.h"
17 #include "ef100_regs.h"
18 #include "mcdi.h"
19 #include "mcdi_pcol.h"
20 #include "mcdi_port_common.h"
21 #include "mcdi_functions.h"
22 #include "mcdi_filters.h"
23 #include "ef100_rx.h"
24 #include "ef100_tx.h"
25 #include "ef100_netdev.h"
26
27 #define EF100_MAX_VIS 4096
28 #define EF100_NUM_MCDI_BUFFERS 1
29 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
30
31 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
32
33 /* MCDI
34 */
ef100_mcdi_buf(struct efx_nic * efx,u8 bufid,dma_addr_t * dma_addr)35 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
36 {
37 struct ef100_nic_data *nic_data = efx->nic_data;
38
39 if (dma_addr)
40 *dma_addr = nic_data->mcdi_buf.dma_addr +
41 bufid * ALIGN(MCDI_BUF_LEN, 256);
42 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
43 }
44
ef100_get_warm_boot_count(struct efx_nic * efx)45 static int ef100_get_warm_boot_count(struct efx_nic *efx)
46 {
47 efx_dword_t reg;
48
49 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
50
51 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
52 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
53 efx->state = STATE_DISABLED;
54 return -ENETDOWN;
55 } else {
56 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
57 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
58 }
59 }
60
ef100_mcdi_request(struct efx_nic * efx,const efx_dword_t * hdr,size_t hdr_len,const efx_dword_t * sdu,size_t sdu_len)61 static void ef100_mcdi_request(struct efx_nic *efx,
62 const efx_dword_t *hdr, size_t hdr_len,
63 const efx_dword_t *sdu, size_t sdu_len)
64 {
65 dma_addr_t dma_addr;
66 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
67
68 memcpy(pdu, hdr, hdr_len);
69 memcpy(pdu + hdr_len, sdu, sdu_len);
70 wmb();
71
72 /* The hardware provides 'low' and 'high' (doorbell) registers
73 * for passing the 64-bit address of an MCDI request to
74 * firmware. However the dwords are swapped by firmware. The
75 * least significant bits of the doorbell are then 0 for all
76 * MCDI requests due to alignment.
77 */
78 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD));
79 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD));
80 }
81
ef100_mcdi_poll_response(struct efx_nic * efx)82 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
83 {
84 const efx_dword_t hdr =
85 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
86
87 rmb();
88 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
89 }
90
ef100_mcdi_read_response(struct efx_nic * efx,efx_dword_t * outbuf,size_t offset,size_t outlen)91 static void ef100_mcdi_read_response(struct efx_nic *efx,
92 efx_dword_t *outbuf, size_t offset,
93 size_t outlen)
94 {
95 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
96
97 memcpy(outbuf, pdu + offset, outlen);
98 }
99
ef100_mcdi_poll_reboot(struct efx_nic * efx)100 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
101 {
102 struct ef100_nic_data *nic_data = efx->nic_data;
103 int rc;
104
105 rc = ef100_get_warm_boot_count(efx);
106 if (rc < 0) {
107 /* The firmware is presumably in the process of
108 * rebooting. However, we are supposed to report each
109 * reboot just once, so we must only do that once we
110 * can read and store the updated warm boot count.
111 */
112 return 0;
113 }
114
115 if (rc == nic_data->warm_boot_count)
116 return 0;
117
118 nic_data->warm_boot_count = rc;
119
120 return -EIO;
121 }
122
ef100_mcdi_reboot_detected(struct efx_nic * efx)123 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
124 {
125 }
126
127 /* MCDI calls
128 */
ef100_get_mac_address(struct efx_nic * efx,u8 * mac_address)129 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
130 {
131 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
132 size_t outlen;
133 int rc;
134
135 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
136
137 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
138 outbuf, sizeof(outbuf), &outlen);
139 if (rc)
140 return rc;
141 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
142 return -EIO;
143
144 ether_addr_copy(mac_address,
145 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
146 return 0;
147 }
148
efx_ef100_init_datapath_caps(struct efx_nic * efx)149 static int efx_ef100_init_datapath_caps(struct efx_nic *efx)
150 {
151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
152 struct ef100_nic_data *nic_data = efx->nic_data;
153 u8 vi_window_mode;
154 size_t outlen;
155 int rc;
156
157 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
158
159 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
160 outbuf, sizeof(outbuf), &outlen);
161 if (rc)
162 return rc;
163 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
164 netif_err(efx, drv, efx->net_dev,
165 "unable to read datapath firmware capabilities\n");
166 return -EIO;
167 }
168
169 nic_data->datapath_caps = MCDI_DWORD(outbuf,
170 GET_CAPABILITIES_OUT_FLAGS1);
171 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
172 GET_CAPABILITIES_V2_OUT_FLAGS2);
173 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
174 nic_data->datapath_caps3 = 0;
175 else
176 nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
177 GET_CAPABILITIES_V7_OUT_FLAGS3);
178
179 vi_window_mode = MCDI_BYTE(outbuf,
180 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
181 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
182 if (rc)
183 return rc;
184
185 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3))
186 efx->net_dev->features |= NETIF_F_TSO | NETIF_F_TSO6;
187 efx->num_mac_stats = MCDI_WORD(outbuf,
188 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
189 netif_dbg(efx, probe, efx->net_dev,
190 "firmware reports num_mac_stats = %u\n",
191 efx->num_mac_stats);
192 return 0;
193 }
194
195 /* Event handling
196 */
ef100_ev_probe(struct efx_channel * channel)197 static int ef100_ev_probe(struct efx_channel *channel)
198 {
199 /* Allocate an extra descriptor for the QMDA status completion entry */
200 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
201 (channel->eventq_mask + 2) *
202 sizeof(efx_qword_t),
203 GFP_KERNEL);
204 }
205
ef100_ev_init(struct efx_channel * channel)206 static int ef100_ev_init(struct efx_channel *channel)
207 {
208 struct ef100_nic_data *nic_data = channel->efx->nic_data;
209
210 /* initial phase is 0 */
211 clear_bit(channel->channel, nic_data->evq_phases);
212
213 return efx_mcdi_ev_init(channel, false, false);
214 }
215
ef100_ev_read_ack(struct efx_channel * channel)216 static void ef100_ev_read_ack(struct efx_channel *channel)
217 {
218 efx_dword_t evq_prime;
219
220 EFX_POPULATE_DWORD_2(evq_prime,
221 ERF_GZ_EVQ_ID, channel->channel,
222 ERF_GZ_IDX, channel->eventq_read_ptr &
223 channel->eventq_mask);
224
225 efx_writed(channel->efx, &evq_prime,
226 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
227 }
228
ef100_ev_process(struct efx_channel * channel,int quota)229 static int ef100_ev_process(struct efx_channel *channel, int quota)
230 {
231 struct efx_nic *efx = channel->efx;
232 struct ef100_nic_data *nic_data;
233 bool evq_phase, old_evq_phase;
234 unsigned int read_ptr;
235 efx_qword_t *p_event;
236 int spent = 0;
237 bool ev_phase;
238 int ev_type;
239
240 if (unlikely(!channel->enabled))
241 return 0;
242
243 nic_data = efx->nic_data;
244 evq_phase = test_bit(channel->channel, nic_data->evq_phases);
245 old_evq_phase = evq_phase;
246 read_ptr = channel->eventq_read_ptr;
247 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
248
249 while (spent < quota) {
250 p_event = efx_event(channel, read_ptr);
251
252 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
253 if (ev_phase != evq_phase)
254 break;
255
256 netif_vdbg(efx, drv, efx->net_dev,
257 "processing event on %d " EFX_QWORD_FMT "\n",
258 channel->channel, EFX_QWORD_VAL(*p_event));
259
260 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
261
262 switch (ev_type) {
263 case ESE_GZ_EF100_EV_RX_PKTS:
264 efx_ef100_ev_rx(channel, p_event);
265 ++spent;
266 break;
267 case ESE_GZ_EF100_EV_MCDI:
268 efx_mcdi_process_event(channel, p_event);
269 break;
270 case ESE_GZ_EF100_EV_TX_COMPLETION:
271 ef100_ev_tx(channel, p_event);
272 break;
273 case ESE_GZ_EF100_EV_DRIVER:
274 netif_info(efx, drv, efx->net_dev,
275 "Driver initiated event " EFX_QWORD_FMT "\n",
276 EFX_QWORD_VAL(*p_event));
277 break;
278 default:
279 netif_info(efx, drv, efx->net_dev,
280 "Unhandled event " EFX_QWORD_FMT "\n",
281 EFX_QWORD_VAL(*p_event));
282 }
283
284 ++read_ptr;
285 if ((read_ptr & channel->eventq_mask) == 0)
286 evq_phase = !evq_phase;
287 }
288
289 channel->eventq_read_ptr = read_ptr;
290 if (evq_phase != old_evq_phase)
291 change_bit(channel->channel, nic_data->evq_phases);
292
293 return spent;
294 }
295
ef100_msi_interrupt(int irq,void * dev_id)296 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
297 {
298 struct efx_msi_context *context = dev_id;
299 struct efx_nic *efx = context->efx;
300
301 netif_vdbg(efx, intr, efx->net_dev,
302 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
303
304 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
305 /* Note test interrupts */
306 if (context->index == efx->irq_level)
307 efx->last_irq_cpu = raw_smp_processor_id();
308
309 /* Schedule processing of the channel */
310 efx_schedule_channel_irq(efx->channel[context->index]);
311 }
312
313 return IRQ_HANDLED;
314 }
315
ef100_phy_probe(struct efx_nic * efx)316 static int ef100_phy_probe(struct efx_nic *efx)
317 {
318 struct efx_mcdi_phy_data *phy_data;
319 int rc;
320
321 /* Probe for the PHY */
322 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
323 if (!efx->phy_data)
324 return -ENOMEM;
325
326 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
327 if (rc)
328 return rc;
329
330 /* Populate driver and ethtool settings */
331 phy_data = efx->phy_data;
332 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
333 efx->link_advertising);
334 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
335 false);
336
337 /* Default to Autonegotiated flow control if the PHY supports it */
338 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
339 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
340 efx->wanted_fc |= EFX_FC_AUTO;
341 efx_link_set_wanted_fc(efx, efx->wanted_fc);
342
343 /* Push settings to the PHY. Failure is not fatal, the user can try to
344 * fix it using ethtool.
345 */
346 rc = efx_mcdi_port_reconfigure(efx);
347 if (rc && rc != -EPERM)
348 netif_warn(efx, drv, efx->net_dev,
349 "could not initialise PHY settings\n");
350
351 return 0;
352 }
353
ef100_filter_table_probe(struct efx_nic * efx)354 static int ef100_filter_table_probe(struct efx_nic *efx)
355 {
356 return efx_mcdi_filter_table_probe(efx, true);
357 }
358
ef100_filter_table_up(struct efx_nic * efx)359 static int ef100_filter_table_up(struct efx_nic *efx)
360 {
361 int rc;
362
363 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
364 if (rc) {
365 efx_mcdi_filter_table_down(efx);
366 return rc;
367 }
368
369 rc = efx_mcdi_filter_add_vlan(efx, 0);
370 if (rc) {
371 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
372 efx_mcdi_filter_table_down(efx);
373 }
374
375 return rc;
376 }
377
ef100_filter_table_down(struct efx_nic * efx)378 static void ef100_filter_table_down(struct efx_nic *efx)
379 {
380 efx_mcdi_filter_del_vlan(efx, 0);
381 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
382 efx_mcdi_filter_table_down(efx);
383 }
384
385 /* Other
386 */
ef100_reconfigure_mac(struct efx_nic * efx,bool mtu_only)387 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
388 {
389 WARN_ON(!mutex_is_locked(&efx->mac_lock));
390
391 efx_mcdi_filter_sync_rx_mode(efx);
392
393 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
394 return efx_mcdi_set_mtu(efx);
395 return efx_mcdi_set_mac(efx);
396 }
397
ef100_map_reset_reason(enum reset_type reason)398 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
399 {
400 if (reason == RESET_TYPE_TX_WATCHDOG)
401 return reason;
402 return RESET_TYPE_DISABLE;
403 }
404
ef100_map_reset_flags(u32 * flags)405 static int ef100_map_reset_flags(u32 *flags)
406 {
407 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
408 if ((*flags & EF100_RESET_PORT)) {
409 *flags &= ~EF100_RESET_PORT;
410 return RESET_TYPE_ALL;
411 }
412 if (*flags & ETH_RESET_MGMT) {
413 *flags &= ~ETH_RESET_MGMT;
414 return RESET_TYPE_DISABLE;
415 }
416
417 return -EINVAL;
418 }
419
ef100_reset(struct efx_nic * efx,enum reset_type reset_type)420 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
421 {
422 int rc;
423
424 dev_close(efx->net_dev);
425
426 if (reset_type == RESET_TYPE_TX_WATCHDOG) {
427 netif_device_attach(efx->net_dev);
428 __clear_bit(reset_type, &efx->reset_pending);
429 rc = dev_open(efx->net_dev, NULL);
430 } else if (reset_type == RESET_TYPE_ALL) {
431 rc = efx_mcdi_reset(efx, reset_type);
432 if (rc)
433 return rc;
434
435 netif_device_attach(efx->net_dev);
436
437 rc = dev_open(efx->net_dev, NULL);
438 } else {
439 rc = 1; /* Leave the device closed */
440 }
441 return rc;
442 }
443
ef100_common_stat_mask(unsigned long * mask)444 static void ef100_common_stat_mask(unsigned long *mask)
445 {
446 __set_bit(EF100_STAT_port_rx_packets, mask);
447 __set_bit(EF100_STAT_port_tx_packets, mask);
448 __set_bit(EF100_STAT_port_rx_bytes, mask);
449 __set_bit(EF100_STAT_port_tx_bytes, mask);
450 __set_bit(EF100_STAT_port_rx_multicast, mask);
451 __set_bit(EF100_STAT_port_rx_bad, mask);
452 __set_bit(EF100_STAT_port_rx_align_error, mask);
453 __set_bit(EF100_STAT_port_rx_overflow, mask);
454 }
455
ef100_ethtool_stat_mask(unsigned long * mask)456 static void ef100_ethtool_stat_mask(unsigned long *mask)
457 {
458 __set_bit(EF100_STAT_port_tx_pause, mask);
459 __set_bit(EF100_STAT_port_tx_unicast, mask);
460 __set_bit(EF100_STAT_port_tx_multicast, mask);
461 __set_bit(EF100_STAT_port_tx_broadcast, mask);
462 __set_bit(EF100_STAT_port_tx_lt64, mask);
463 __set_bit(EF100_STAT_port_tx_64, mask);
464 __set_bit(EF100_STAT_port_tx_65_to_127, mask);
465 __set_bit(EF100_STAT_port_tx_128_to_255, mask);
466 __set_bit(EF100_STAT_port_tx_256_to_511, mask);
467 __set_bit(EF100_STAT_port_tx_512_to_1023, mask);
468 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
469 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
470 __set_bit(EF100_STAT_port_rx_good, mask);
471 __set_bit(EF100_STAT_port_rx_pause, mask);
472 __set_bit(EF100_STAT_port_rx_unicast, mask);
473 __set_bit(EF100_STAT_port_rx_broadcast, mask);
474 __set_bit(EF100_STAT_port_rx_lt64, mask);
475 __set_bit(EF100_STAT_port_rx_64, mask);
476 __set_bit(EF100_STAT_port_rx_65_to_127, mask);
477 __set_bit(EF100_STAT_port_rx_128_to_255, mask);
478 __set_bit(EF100_STAT_port_rx_256_to_511, mask);
479 __set_bit(EF100_STAT_port_rx_512_to_1023, mask);
480 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
481 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
482 __set_bit(EF100_STAT_port_rx_gtjumbo, mask);
483 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
484 __set_bit(EF100_STAT_port_rx_length_error, mask);
485 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
486 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
487 __set_bit(GENERIC_STAT_rx_noskb_drops, mask);
488 }
489
490 #define EF100_DMA_STAT(ext_name, mcdi_name) \
491 [EF100_STAT_ ## ext_name] = \
492 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
493
494 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
495 EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
496 EF100_DMA_STAT(port_tx_packets, TX_PKTS),
497 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
498 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
499 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
500 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
501 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
502 EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
503 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
504 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
505 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
506 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
507 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
508 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
509 EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
510 EF100_DMA_STAT(port_rx_packets, RX_PKTS),
511 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
512 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
513 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
514 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
515 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
516 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
517 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
518 EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
519 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
520 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
521 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
522 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
523 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
524 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
525 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
526 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
527 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
528 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
529 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
530 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
531 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
532 EFX_GENERIC_SW_STAT(rx_noskb_drops),
533 };
534
ef100_describe_stats(struct efx_nic * efx,u8 * names)535 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
536 {
537 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
538
539 ef100_ethtool_stat_mask(mask);
540 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
541 mask, names);
542 }
543
ef100_update_stats_common(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)544 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
545 struct rtnl_link_stats64 *core_stats)
546 {
547 struct ef100_nic_data *nic_data = efx->nic_data;
548 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
549 size_t stats_count = 0, index;
550 u64 *stats = nic_data->stats;
551
552 ef100_ethtool_stat_mask(mask);
553
554 if (full_stats) {
555 for_each_set_bit(index, mask, EF100_STAT_COUNT) {
556 if (ef100_stat_desc[index].name) {
557 *full_stats++ = stats[index];
558 ++stats_count;
559 }
560 }
561 }
562
563 if (!core_stats)
564 return stats_count;
565
566 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
567 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
568 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
569 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
570 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
571 stats[GENERIC_STAT_rx_nodesc_trunc] +
572 stats[GENERIC_STAT_rx_noskb_drops];
573 core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
574 core_stats->rx_length_errors =
575 stats[EF100_STAT_port_rx_gtjumbo] +
576 stats[EF100_STAT_port_rx_length_error];
577 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
578 core_stats->rx_frame_errors =
579 stats[EF100_STAT_port_rx_align_error];
580 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
581 core_stats->rx_errors = (core_stats->rx_length_errors +
582 core_stats->rx_crc_errors +
583 core_stats->rx_frame_errors);
584
585 return stats_count;
586 }
587
ef100_update_stats(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)588 static size_t ef100_update_stats(struct efx_nic *efx,
589 u64 *full_stats,
590 struct rtnl_link_stats64 *core_stats)
591 {
592 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
593 struct ef100_nic_data *nic_data = efx->nic_data;
594 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
595 u64 *stats = nic_data->stats;
596
597 ef100_common_stat_mask(mask);
598 ef100_ethtool_stat_mask(mask);
599
600 efx_nic_copy_stats(efx, mc_stats);
601 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
602 stats, mc_stats, false);
603
604 kfree(mc_stats);
605
606 return ef100_update_stats_common(efx, full_stats, core_stats);
607 }
608
efx_ef100_get_phys_port_id(struct efx_nic * efx,struct netdev_phys_item_id * ppid)609 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
610 struct netdev_phys_item_id *ppid)
611 {
612 struct ef100_nic_data *nic_data = efx->nic_data;
613
614 if (!is_valid_ether_addr(nic_data->port_id))
615 return -EOPNOTSUPP;
616
617 ppid->id_len = ETH_ALEN;
618 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
619
620 return 0;
621 }
622
efx_ef100_irq_test_generate(struct efx_nic * efx)623 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
624 {
625 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
626
627 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
628
629 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
630 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
631 inbuf, sizeof(inbuf), NULL, 0, NULL);
632 }
633
634 #define EFX_EF100_TEST 1
635
efx_ef100_ev_test_generate(struct efx_channel * channel)636 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
637 {
638 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
639 struct efx_nic *efx = channel->efx;
640 efx_qword_t event;
641 int rc;
642
643 EFX_POPULATE_QWORD_2(event,
644 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
645 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
646
647 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
648
649 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
650 * already swapped the data to little-endian order.
651 */
652 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
653 sizeof(efx_qword_t));
654
655 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
656 NULL, 0, NULL);
657 if (rc && (rc != -ENETDOWN))
658 goto fail;
659
660 return;
661
662 fail:
663 WARN_ON(true);
664 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
665 }
666
ef100_check_caps(const struct efx_nic * efx,u8 flag,u32 offset)667 static unsigned int ef100_check_caps(const struct efx_nic *efx,
668 u8 flag, u32 offset)
669 {
670 const struct ef100_nic_data *nic_data = efx->nic_data;
671
672 switch (offset) {
673 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
674 return nic_data->datapath_caps & BIT_ULL(flag);
675 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
676 return nic_data->datapath_caps2 & BIT_ULL(flag);
677 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
678 return nic_data->datapath_caps3 & BIT_ULL(flag);
679 default:
680 return 0;
681 }
682 }
683
684 /* NIC level access functions
685 */
686 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \
687 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
688 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
689 NETIF_F_TSO_MANGLEID | NETIF_F_HW_VLAN_CTAG_TX)
690
691 const struct efx_nic_type ef100_pf_nic_type = {
692 .revision = EFX_REV_EF100,
693 .is_vf = false,
694 .probe = ef100_probe_pf,
695 .offload_features = EF100_OFFLOAD_FEATURES,
696 .mcdi_max_ver = 2,
697 .mcdi_request = ef100_mcdi_request,
698 .mcdi_poll_response = ef100_mcdi_poll_response,
699 .mcdi_read_response = ef100_mcdi_read_response,
700 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
701 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
702 .irq_enable_master = efx_port_dummy_op_void,
703 .irq_test_generate = efx_ef100_irq_test_generate,
704 .irq_disable_non_ev = efx_port_dummy_op_void,
705 .push_irq_moderation = efx_channel_dummy_op_void,
706 .min_interrupt_mode = EFX_INT_MODE_MSIX,
707 .map_reset_reason = ef100_map_reset_reason,
708 .map_reset_flags = ef100_map_reset_flags,
709 .reset = ef100_reset,
710
711 .check_caps = ef100_check_caps,
712
713 .ev_probe = ef100_ev_probe,
714 .ev_init = ef100_ev_init,
715 .ev_fini = efx_mcdi_ev_fini,
716 .ev_remove = efx_mcdi_ev_remove,
717 .irq_handle_msi = ef100_msi_interrupt,
718 .ev_process = ef100_ev_process,
719 .ev_read_ack = ef100_ev_read_ack,
720 .ev_test_generate = efx_ef100_ev_test_generate,
721 .tx_probe = ef100_tx_probe,
722 .tx_init = ef100_tx_init,
723 .tx_write = ef100_tx_write,
724 .tx_enqueue = ef100_enqueue_skb,
725 .rx_probe = efx_mcdi_rx_probe,
726 .rx_init = efx_mcdi_rx_init,
727 .rx_remove = efx_mcdi_rx_remove,
728 .rx_write = ef100_rx_write,
729 .rx_packet = __ef100_rx_packet,
730 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
731 .fini_dmaq = efx_fini_dmaq,
732 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
733 .filter_table_probe = ef100_filter_table_up,
734 .filter_table_restore = efx_mcdi_filter_table_restore,
735 .filter_table_remove = ef100_filter_table_down,
736 .filter_insert = efx_mcdi_filter_insert,
737 .filter_remove_safe = efx_mcdi_filter_remove_safe,
738 .filter_get_safe = efx_mcdi_filter_get_safe,
739 .filter_clear_rx = efx_mcdi_filter_clear_rx,
740 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
741 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
742 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
743 #ifdef CONFIG_RFS_ACCEL
744 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
745 #endif
746
747 .get_phys_port_id = efx_ef100_get_phys_port_id,
748
749 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
750 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
751 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
752 .rx_hash_key_size = 40,
753 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
754 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
755 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
756 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
757 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
758
759 .reconfigure_mac = ef100_reconfigure_mac,
760 .reconfigure_port = efx_mcdi_port_reconfigure,
761 .test_nvram = efx_new_mcdi_nvram_test_all,
762 .describe_stats = ef100_describe_stats,
763 .start_stats = efx_mcdi_mac_start_stats,
764 .update_stats = ef100_update_stats,
765 .pull_stats = efx_mcdi_mac_pull_stats,
766 .stop_stats = efx_mcdi_mac_stop_stats,
767
768 /* Per-type bar/size configuration not used on ef100. Location of
769 * registers is defined by extended capabilities.
770 */
771 .mem_bar = NULL,
772 .mem_map_size = NULL,
773
774 };
775
776 const struct efx_nic_type ef100_vf_nic_type = {
777 .revision = EFX_REV_EF100,
778 .is_vf = true,
779 .probe = ef100_probe_vf,
780 .offload_features = EF100_OFFLOAD_FEATURES,
781 .mcdi_max_ver = 2,
782 .mcdi_request = ef100_mcdi_request,
783 .mcdi_poll_response = ef100_mcdi_poll_response,
784 .mcdi_read_response = ef100_mcdi_read_response,
785 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
786 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
787 .irq_enable_master = efx_port_dummy_op_void,
788 .irq_test_generate = efx_ef100_irq_test_generate,
789 .irq_disable_non_ev = efx_port_dummy_op_void,
790 .push_irq_moderation = efx_channel_dummy_op_void,
791 .min_interrupt_mode = EFX_INT_MODE_MSIX,
792 .map_reset_reason = ef100_map_reset_reason,
793 .map_reset_flags = ef100_map_reset_flags,
794 .reset = ef100_reset,
795 .check_caps = ef100_check_caps,
796 .ev_probe = ef100_ev_probe,
797 .ev_init = ef100_ev_init,
798 .ev_fini = efx_mcdi_ev_fini,
799 .ev_remove = efx_mcdi_ev_remove,
800 .irq_handle_msi = ef100_msi_interrupt,
801 .ev_process = ef100_ev_process,
802 .ev_read_ack = ef100_ev_read_ack,
803 .ev_test_generate = efx_ef100_ev_test_generate,
804 .tx_probe = ef100_tx_probe,
805 .tx_init = ef100_tx_init,
806 .tx_write = ef100_tx_write,
807 .tx_enqueue = ef100_enqueue_skb,
808 .rx_probe = efx_mcdi_rx_probe,
809 .rx_init = efx_mcdi_rx_init,
810 .rx_remove = efx_mcdi_rx_remove,
811 .rx_write = ef100_rx_write,
812 .rx_packet = __ef100_rx_packet,
813 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
814 .fini_dmaq = efx_fini_dmaq,
815 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
816 .filter_table_probe = ef100_filter_table_up,
817 .filter_table_restore = efx_mcdi_filter_table_restore,
818 .filter_table_remove = ef100_filter_table_down,
819 .filter_insert = efx_mcdi_filter_insert,
820 .filter_remove_safe = efx_mcdi_filter_remove_safe,
821 .filter_get_safe = efx_mcdi_filter_get_safe,
822 .filter_clear_rx = efx_mcdi_filter_clear_rx,
823 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
824 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
825 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
826 #ifdef CONFIG_RFS_ACCEL
827 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
828 #endif
829
830 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
831 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
832 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
833 .rx_hash_key_size = 40,
834 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
835 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
836 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
837
838 .reconfigure_mac = ef100_reconfigure_mac,
839 .test_nvram = efx_new_mcdi_nvram_test_all,
840 .describe_stats = ef100_describe_stats,
841 .start_stats = efx_mcdi_mac_start_stats,
842 .update_stats = ef100_update_stats,
843 .pull_stats = efx_mcdi_mac_pull_stats,
844 .stop_stats = efx_mcdi_mac_stop_stats,
845
846 .mem_bar = NULL,
847 .mem_map_size = NULL,
848
849 };
850
compare_versions(const char * a,const char * b)851 static int compare_versions(const char *a, const char *b)
852 {
853 int a_major, a_minor, a_point, a_patch;
854 int b_major, b_minor, b_point, b_patch;
855 int a_matched, b_matched;
856
857 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
858 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
859
860 if (a_matched == 4 && b_matched != 4)
861 return +1;
862
863 if (a_matched != 4 && b_matched == 4)
864 return -1;
865
866 if (a_matched != 4 && b_matched != 4)
867 return 0;
868
869 if (a_major != b_major)
870 return a_major - b_major;
871
872 if (a_minor != b_minor)
873 return a_minor - b_minor;
874
875 if (a_point != b_point)
876 return a_point - b_point;
877
878 return a_patch - b_patch;
879 }
880
881 enum ef100_tlv_state_machine {
882 EF100_TLV_TYPE,
883 EF100_TLV_TYPE_CONT,
884 EF100_TLV_LENGTH,
885 EF100_TLV_VALUE
886 };
887
888 struct ef100_tlv_state {
889 enum ef100_tlv_state_machine state;
890 u64 value;
891 u32 value_offset;
892 u16 type;
893 u8 len;
894 };
895
ef100_tlv_feed(struct ef100_tlv_state * state,u8 byte)896 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
897 {
898 switch (state->state) {
899 case EF100_TLV_TYPE:
900 state->type = byte & 0x7f;
901 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
902 : EF100_TLV_LENGTH;
903 /* Clear ready to read in a new entry */
904 state->value = 0;
905 state->value_offset = 0;
906 return 0;
907 case EF100_TLV_TYPE_CONT:
908 state->type |= byte << 7;
909 state->state = EF100_TLV_LENGTH;
910 return 0;
911 case EF100_TLV_LENGTH:
912 state->len = byte;
913 /* We only handle TLVs that fit in a u64 */
914 if (state->len > sizeof(state->value))
915 return -EOPNOTSUPP;
916 /* len may be zero, implying a value of zero */
917 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
918 return 0;
919 case EF100_TLV_VALUE:
920 state->value |= ((u64)byte) << (state->value_offset * 8);
921 state->value_offset++;
922 if (state->value_offset >= state->len)
923 state->state = EF100_TLV_TYPE;
924 return 0;
925 default: /* state machine error, can't happen */
926 WARN_ON_ONCE(1);
927 return -EIO;
928 }
929 }
930
ef100_process_design_param(struct efx_nic * efx,const struct ef100_tlv_state * reader)931 static int ef100_process_design_param(struct efx_nic *efx,
932 const struct ef100_tlv_state *reader)
933 {
934 struct ef100_nic_data *nic_data = efx->nic_data;
935
936 switch (reader->type) {
937 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
938 return 0;
939 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
940 /* Driver doesn't support timestamping yet, so we don't care */
941 return 0;
942 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
943 /* Driver doesn't support unsolicited-event credits yet, so
944 * we don't care
945 */
946 return 0;
947 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
948 /* Driver doesn't manage the NMMU (so we don't care) */
949 return 0;
950 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
951 /* Driver uses CHECKSUM_COMPLETE, so we don't care about
952 * protocol checksum validation
953 */
954 return 0;
955 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
956 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
957 return 0;
958 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
959 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
960 if (!reader->value) {
961 netif_err(efx, probe, efx->net_dev,
962 "TSO_MAX_HDR_NUM_SEGS < 1\n");
963 return -EOPNOTSUPP;
964 }
965 return 0;
966 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
967 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
968 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
969 * EFX_MIN_DMAQ_SIZE, so we just need to check that
970 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
971 * This is very unlikely to fail.
972 */
973 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
974 EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
975 netif_err(efx, probe, efx->net_dev,
976 "%s size granularity is %llu, can't guarantee safety\n",
977 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
978 reader->value);
979 return -EOPNOTSUPP;
980 }
981 return 0;
982 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
983 nic_data->tso_max_payload_len = min_t(u64, reader->value, GSO_MAX_SIZE);
984 efx->net_dev->gso_max_size = nic_data->tso_max_payload_len;
985 return 0;
986 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
987 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
988 efx->net_dev->gso_max_segs = nic_data->tso_max_payload_num_segs;
989 return 0;
990 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
991 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
992 return 0;
993 case ESE_EF100_DP_GZ_COMPAT:
994 if (reader->value) {
995 netif_err(efx, probe, efx->net_dev,
996 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
997 reader->value);
998 return -EOPNOTSUPP;
999 }
1000 return 0;
1001 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
1002 /* Driver doesn't use mem2mem transfers */
1003 return 0;
1004 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
1005 /* Driver doesn't currently use EVQ_TIMER */
1006 return 0;
1007 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
1008 /* Driver doesn't manage the NMMU (so we don't care) */
1009 return 0;
1010 case ESE_EF100_DP_GZ_VI_STRIDES:
1011 /* We never try to set the VI stride, and we don't rely on
1012 * being able to find VIs past VI 0 until after we've learned
1013 * the current stride from MC_CMD_GET_CAPABILITIES.
1014 * So the value of this shouldn't matter.
1015 */
1016 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
1017 netif_dbg(efx, probe, efx->net_dev,
1018 "NIC has other than default VI_STRIDES (mask "
1019 "%#llx), early probing might use wrong one\n",
1020 reader->value);
1021 return 0;
1022 case ESE_EF100_DP_GZ_RX_MAX_RUNT:
1023 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
1024 * care whether it indicates runt or overlength for any given
1025 * packet, so we don't care about this parameter.
1026 */
1027 return 0;
1028 default:
1029 /* Host interface says "Drivers should ignore design parameters
1030 * that they do not recognise."
1031 */
1032 netif_dbg(efx, probe, efx->net_dev,
1033 "Ignoring unrecognised design parameter %u\n",
1034 reader->type);
1035 return 0;
1036 }
1037 }
1038
ef100_check_design_params(struct efx_nic * efx)1039 static int ef100_check_design_params(struct efx_nic *efx)
1040 {
1041 struct ef100_tlv_state reader = {};
1042 u32 total_len, offset = 0;
1043 efx_dword_t reg;
1044 int rc = 0, i;
1045 u32 data;
1046
1047 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN);
1048 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1049 netif_dbg(efx, probe, efx->net_dev, "%u bytes of design parameters\n",
1050 total_len);
1051 while (offset < total_len) {
1052 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset);
1053 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1054 for (i = 0; i < sizeof(data); i++) {
1055 rc = ef100_tlv_feed(&reader, data);
1056 /* Got a complete value? */
1057 if (!rc && reader.state == EF100_TLV_TYPE)
1058 rc = ef100_process_design_param(efx, &reader);
1059 if (rc)
1060 goto out;
1061 data >>= 8;
1062 offset++;
1063 }
1064 }
1065 /* Check we didn't end halfway through a TLV entry, which could either
1066 * mean that the TLV stream is truncated or just that it's corrupted
1067 * and our state machine is out of sync.
1068 */
1069 if (reader.state != EF100_TLV_TYPE) {
1070 if (reader.state == EF100_TLV_TYPE_CONT)
1071 netif_err(efx, probe, efx->net_dev,
1072 "truncated design parameter (incomplete type %u)\n",
1073 reader.type);
1074 else
1075 netif_err(efx, probe, efx->net_dev,
1076 "truncated design parameter %u\n",
1077 reader.type);
1078 rc = -EIO;
1079 }
1080 out:
1081 return rc;
1082 }
1083
1084 /* NIC probe and remove
1085 */
ef100_probe_main(struct efx_nic * efx)1086 static int ef100_probe_main(struct efx_nic *efx)
1087 {
1088 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
1089 struct net_device *net_dev = efx->net_dev;
1090 struct ef100_nic_data *nic_data;
1091 char fw_version[32];
1092 int i, rc;
1093
1094 if (WARN_ON(bar_size == 0))
1095 return -EIO;
1096
1097 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1098 if (!nic_data)
1099 return -ENOMEM;
1100 efx->nic_data = nic_data;
1101 nic_data->efx = efx;
1102 net_dev->features |= efx->type->offload_features;
1103 net_dev->hw_features |= efx->type->offload_features;
1104
1105 /* Populate design-parameter defaults */
1106 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1107 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1108 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1109 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1110 net_dev->gso_max_segs = ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT;
1111 /* Read design parameters */
1112 rc = ef100_check_design_params(efx);
1113 if (rc) {
1114 netif_err(efx, probe, efx->net_dev,
1115 "Unsupported design parameters\n");
1116 goto fail;
1117 }
1118
1119 /* we assume later that we can copy from this buffer in dwords */
1120 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1121
1122 /* MCDI buffers must be 256 byte aligned. */
1123 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1124 GFP_KERNEL);
1125 if (rc)
1126 goto fail;
1127
1128 /* Get the MC's warm boot count. In case it's rebooting right
1129 * now, be prepared to retry.
1130 */
1131 i = 0;
1132 for (;;) {
1133 rc = ef100_get_warm_boot_count(efx);
1134 if (rc >= 0)
1135 break;
1136 if (++i == 5)
1137 goto fail;
1138 ssleep(1);
1139 }
1140 nic_data->warm_boot_count = rc;
1141
1142 /* In case we're recovering from a crash (kexec), we want to
1143 * cancel any outstanding request by the previous user of this
1144 * function. We send a special message using the least
1145 * significant bits of the 'high' (doorbell) register.
1146 */
1147 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1148
1149 /* Post-IO section. */
1150
1151 rc = efx_mcdi_init(efx);
1152 if (!rc && efx->mcdi->fn_flags &
1153 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT)) {
1154 netif_info(efx, probe, efx->net_dev,
1155 "No network port on this PCI function");
1156 rc = -ENODEV;
1157 }
1158 if (rc)
1159 goto fail;
1160 /* Reset (most) configuration for this function */
1161 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1162 if (rc)
1163 goto fail;
1164 /* Enable event logging */
1165 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1166 if (rc)
1167 goto fail;
1168
1169 rc = efx_get_pf_index(efx, &nic_data->pf_index);
1170 if (rc)
1171 goto fail;
1172
1173 rc = efx_ef100_init_datapath_caps(efx);
1174 if (rc < 0)
1175 goto fail;
1176
1177 efx->max_vis = EF100_MAX_VIS;
1178
1179 rc = efx_mcdi_port_get_number(efx);
1180 if (rc < 0)
1181 goto fail;
1182 efx->port_num = rc;
1183
1184 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1185 netif_dbg(efx, drv, efx->net_dev, "Firmware version %s\n", fw_version);
1186
1187 if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1188 netif_info(efx, drv, efx->net_dev, "Firmware uses old event descriptors\n");
1189 rc = -EINVAL;
1190 goto fail;
1191 }
1192
1193 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1194 netif_info(efx, drv, efx->net_dev, "Firmware uses unsolicited-event credits\n");
1195 rc = -EINVAL;
1196 goto fail;
1197 }
1198
1199 rc = ef100_phy_probe(efx);
1200 if (rc)
1201 goto fail;
1202
1203 down_write(&efx->filter_sem);
1204 rc = ef100_filter_table_probe(efx);
1205 up_write(&efx->filter_sem);
1206 if (rc)
1207 goto fail;
1208
1209 netdev_rss_key_fill(efx->rss_context.rx_hash_key,
1210 sizeof(efx->rss_context.rx_hash_key));
1211
1212 /* Don't fail init if RSS setup doesn't work. */
1213 efx_mcdi_push_default_indir_table(efx, efx->n_rx_channels);
1214
1215 rc = ef100_register_netdev(efx);
1216 if (rc)
1217 goto fail;
1218
1219 return 0;
1220 fail:
1221 return rc;
1222 }
1223
ef100_probe_pf(struct efx_nic * efx)1224 int ef100_probe_pf(struct efx_nic *efx)
1225 {
1226 struct net_device *net_dev = efx->net_dev;
1227 struct ef100_nic_data *nic_data;
1228 int rc = ef100_probe_main(efx);
1229
1230 if (rc)
1231 goto fail;
1232
1233 nic_data = efx->nic_data;
1234 rc = ef100_get_mac_address(efx, net_dev->perm_addr);
1235 if (rc)
1236 goto fail;
1237 /* Assign MAC address */
1238 memcpy(net_dev->dev_addr, net_dev->perm_addr, ETH_ALEN);
1239 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
1240
1241 return 0;
1242
1243 fail:
1244 return rc;
1245 }
1246
ef100_probe_vf(struct efx_nic * efx)1247 int ef100_probe_vf(struct efx_nic *efx)
1248 {
1249 return ef100_probe_main(efx);
1250 }
1251
ef100_remove(struct efx_nic * efx)1252 void ef100_remove(struct efx_nic *efx)
1253 {
1254 struct ef100_nic_data *nic_data = efx->nic_data;
1255
1256 ef100_unregister_netdev(efx);
1257
1258 down_write(&efx->filter_sem);
1259 efx_mcdi_filter_table_remove(efx);
1260 up_write(&efx->filter_sem);
1261 efx_fini_channels(efx);
1262 kfree(efx->phy_data);
1263 efx->phy_data = NULL;
1264 efx_mcdi_detach(efx);
1265 efx_mcdi_fini(efx);
1266 if (nic_data)
1267 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1268 kfree(nic_data);
1269 efx->nic_data = NULL;
1270 }
1271