1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
25 #include "hw/registerfields.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-common.h"
28 #include "exec/cpu-defs.h"
29 #include "exec/cpu-interrupt.h"
30 #include "exec/gdbstub.h"
31 #include "exec/page-protection.h"
32 #include "qapi/qapi-types-common.h"
33 #include "target/arm/multiprocessing.h"
34 #include "target/arm/gtimer.h"
35
36 #define EXCP_UDEF 1 /* undefined instruction */
37 #define EXCP_SWI 2 /* software interrupt */
38 #define EXCP_PREFETCH_ABORT 3
39 #define EXCP_DATA_ABORT 4
40 #define EXCP_IRQ 5
41 #define EXCP_FIQ 6
42 #define EXCP_BKPT 7
43 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
44 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
45 #define EXCP_HVC 11 /* HyperVisor Call */
46 #define EXCP_HYP_TRAP 12
47 #define EXCP_SMC 13 /* Secure Monitor Call */
48 #define EXCP_VIRQ 14
49 #define EXCP_VFIQ 15
50 #define EXCP_SEMIHOST 16 /* semihosting call */
51 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
52 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
53 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
54 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
55 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */
56 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
57 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
58 #define EXCP_VSERR 24
59 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */
60 #define EXCP_NMI 26
61 #define EXCP_VINMI 27
62 #define EXCP_VFNMI 28
63 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */
64 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
65
66 #define ARMV7M_EXCP_RESET 1
67 #define ARMV7M_EXCP_NMI 2
68 #define ARMV7M_EXCP_HARD 3
69 #define ARMV7M_EXCP_MEM 4
70 #define ARMV7M_EXCP_BUS 5
71 #define ARMV7M_EXCP_USAGE 6
72 #define ARMV7M_EXCP_SECURE 7
73 #define ARMV7M_EXCP_SVC 11
74 #define ARMV7M_EXCP_DEBUG 12
75 #define ARMV7M_EXCP_PENDSV 14
76 #define ARMV7M_EXCP_SYSTICK 15
77
78 /* ARM-specific interrupt pending bits. */
79 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
80 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
81 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
82 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
83 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4
84 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0
85 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1
86
87 /* The usual mapping for an AArch64 system register to its AArch32
88 * counterpart is for the 32 bit world to have access to the lower
89 * half only (with writes leaving the upper half untouched). It's
90 * therefore useful to be able to pass TCG the offset of the least
91 * significant half of a uint64_t struct member.
92 */
93 #if HOST_BIG_ENDIAN
94 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
95 #define offsetofhigh32(S, M) offsetof(S, M)
96 #else
97 #define offsetoflow32(S, M) offsetof(S, M)
98 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
99 #endif
100
101 /* The 2nd extra word holding syndrome info for data aborts does not use
102 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
103 * help the sleb128 encoder do a better job.
104 * When restoring the CPU state, we shift it back up.
105 */
106 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
107 #define ARM_INSN_START_WORD2_SHIFT 13
108
109 /* We currently assume float and double are IEEE single and double
110 precision respectively.
111 Doing runtime conversions is tricky because VFP registers may contain
112 integer values (eg. as the result of a FTOSI instruction).
113 s<2n> maps to the least significant half of d<n>
114 s<2n+1> maps to the most significant half of d<n>
115 */
116
117 /**
118 * DynamicGDBFeatureInfo:
119 * @desc: Contains the feature descriptions.
120 * @data: A union with data specific to the set of registers
121 * @cpregs_keys: Array that contains the corresponding Key of
122 * a given cpreg with the same order of the cpreg
123 * in the XML description.
124 */
125 typedef struct DynamicGDBFeatureInfo {
126 GDBFeature desc;
127 union {
128 struct {
129 uint32_t *keys;
130 } cpregs;
131 } data;
132 } DynamicGDBFeatureInfo;
133
134 /* CPU state for each instance of a generic timer (in cp15 c14) */
135 typedef struct ARMGenericTimer {
136 uint64_t cval; /* Timer CompareValue register */
137 uint64_t ctl; /* Timer Control register */
138 } ARMGenericTimer;
139
140 /* Define a maximum sized vector register.
141 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
142 * For 64-bit, this is a 2048-bit SVE register.
143 *
144 * Note that the mapping between S, D, and Q views of the register bank
145 * differs between AArch64 and AArch32.
146 * In AArch32:
147 * Qn = regs[n].d[1]:regs[n].d[0]
148 * Dn = regs[n / 2].d[n & 1]
149 * Sn = regs[n / 4].d[n % 4 / 2],
150 * bits 31..0 for even n, and bits 63..32 for odd n
151 * (and regs[16] to regs[31] are inaccessible)
152 * In AArch64:
153 * Zn = regs[n].d[*]
154 * Qn = regs[n].d[1]:regs[n].d[0]
155 * Dn = regs[n].d[0]
156 * Sn = regs[n].d[0] bits 31..0
157 * Hn = regs[n].d[0] bits 15..0
158 *
159 * This corresponds to the architecturally defined mapping between
160 * the two execution states, and means we do not need to explicitly
161 * map these registers when changing states.
162 *
163 * Align the data for use with TCG host vector operations.
164 */
165
166 #define ARM_MAX_VQ 16
167
168 typedef struct ARMVectorReg {
169 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
170 } ARMVectorReg;
171
172 /* In AArch32 mode, predicate registers do not exist at all. */
173 typedef struct ARMPredicateReg {
174 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
175 } ARMPredicateReg;
176
177 /* In AArch32 mode, PAC keys do not exist at all. */
178 typedef struct ARMPACKey {
179 uint64_t lo, hi;
180 } ARMPACKey;
181
182 /* See the commentary above the TBFLAG field definitions. */
183 typedef struct CPUARMTBFlags {
184 uint32_t flags;
185 uint64_t flags2;
186 } CPUARMTBFlags;
187
188 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
189
190 typedef struct NVICState NVICState;
191
192 /*
193 * Enum for indexing vfp.fp_status[].
194 *
195 * FPST_A32: is the "normal" fp status for AArch32 insns
196 * FPST_A64: is the "normal" fp status for AArch64 insns
197 * FPST_A32_F16: used for AArch32 half-precision calculations
198 * FPST_A64_F16: used for AArch64 half-precision calculations
199 * FPST_STD: the ARM "Standard FPSCR Value"
200 * FPST_STD_F16: used for half-precision
201 * calculations with the ARM "Standard FPSCR Value"
202 * FPST_AH: used for the A64 insns which change behaviour
203 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
204 * and the reciprocal and square root estimate/step insns)
205 * FPST_AH_F16: used for the A64 insns which change behaviour
206 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
207 * and the reciprocal and square root estimate/step insns);
208 * for half-precision
209 *
210 * Half-precision operations are governed by a separate
211 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
212 * status structure to control this.
213 *
214 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
215 * round-to-nearest and is used by any operations (generally
216 * Neon) which the architecture defines as controlled by the
217 * standard FPSCR value rather than the FPSCR.
218 *
219 * The "standard FPSCR but for fp16 ops" is needed because
220 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
221 * using a fixed value for it.
222 *
223 * FPST_AH is needed because some insns have different
224 * behaviour when FPCR.AH == 1: they don't update cumulative
225 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and
226 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16,
227 * which means we need an FPST_AH_F16 as well.
228 *
229 * To avoid having to transfer exception bits around, we simply
230 * say that the FPSCR cumulative exception flags are the logical
231 * OR of the flags in the four fp statuses. This relies on the
232 * only thing which needs to read the exception flags being
233 * an explicit FPSCR read.
234 */
235 typedef enum ARMFPStatusFlavour {
236 FPST_A32,
237 FPST_A64,
238 FPST_A32_F16,
239 FPST_A64_F16,
240 FPST_AH,
241 FPST_AH_F16,
242 FPST_STD,
243 FPST_STD_F16,
244 } ARMFPStatusFlavour;
245 #define FPST_COUNT 8
246
247 typedef struct CPUArchState {
248 /* Regs for current mode. */
249 uint32_t regs[16];
250
251 /* 32/64 switch only happens when taking and returning from
252 * exceptions so the overlap semantics are taken care of then
253 * instead of having a complicated union.
254 */
255 /* Regs for A64 mode. */
256 uint64_t xregs[32];
257 uint64_t pc;
258 /* PSTATE isn't an architectural register for ARMv8. However, it is
259 * convenient for us to assemble the underlying state into a 32 bit format
260 * identical to the architectural format used for the SPSR. (This is also
261 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
262 * 'pstate' register are.) Of the PSTATE bits:
263 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
264 * semantics as for AArch32, as described in the comments on each field)
265 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
266 * DAIF (exception masks) are kept in env->daif
267 * BTYPE is kept in env->btype
268 * SM and ZA are kept in env->svcr
269 * all other bits are stored in their correct places in env->pstate
270 */
271 uint32_t pstate;
272 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
273 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */
274
275 /* Cached TBFLAGS state. See below for which bits are included. */
276 CPUARMTBFlags hflags;
277
278 /* Frequently accessed CPSR bits are stored separately for efficiency.
279 This contains all the other bits. Use cpsr_{read,write} to access
280 the whole CPSR. */
281 uint32_t uncached_cpsr;
282 uint32_t spsr;
283
284 /* Banked registers. */
285 uint64_t banked_spsr[8];
286 uint32_t banked_r13[8];
287 uint32_t banked_r14[8];
288
289 /* These hold r8-r12. */
290 uint32_t usr_regs[5];
291 uint32_t fiq_regs[5];
292
293 /* cpsr flag cache for faster execution */
294 uint32_t CF; /* 0 or 1 */
295 uint32_t VF; /* V is the bit 31. All other bits are undefined */
296 uint32_t NF; /* N is bit 31. All other bits are undefined. */
297 uint32_t ZF; /* Z set if zero. */
298 uint32_t QF; /* 0 or 1 */
299 uint32_t GE; /* cpsr[19:16] */
300 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
301 uint32_t btype; /* BTI branch type. spsr[11:10]. */
302 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
303 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */
304
305 uint64_t elr_el[4]; /* AArch64 exception link regs */
306 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
307
308 /* System control coprocessor (cp15) */
309 struct {
310 uint32_t c0_cpuid;
311 union { /* Cache size selection */
312 struct {
313 uint64_t _unused_csselr0;
314 uint64_t csselr_ns;
315 uint64_t _unused_csselr1;
316 uint64_t csselr_s;
317 };
318 uint64_t csselr_el[4];
319 };
320 union { /* System control register. */
321 struct {
322 uint64_t _unused_sctlr;
323 uint64_t sctlr_ns;
324 uint64_t hsctlr;
325 uint64_t sctlr_s;
326 };
327 uint64_t sctlr_el[4];
328 };
329 uint64_t vsctlr; /* Virtualization System control register. */
330 uint64_t cpacr_el1; /* Architectural feature access control register */
331 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
332 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
333 uint64_t sder; /* Secure debug enable register. */
334 uint32_t nsacr; /* Non-secure access control register. */
335 union { /* MMU translation table base 0. */
336 struct {
337 uint64_t _unused_ttbr0_0;
338 uint64_t ttbr0_ns;
339 uint64_t _unused_ttbr0_1;
340 uint64_t ttbr0_s;
341 };
342 uint64_t ttbr0_el[4];
343 };
344 union { /* MMU translation table base 1. */
345 struct {
346 uint64_t _unused_ttbr1_0;
347 uint64_t ttbr1_ns;
348 uint64_t _unused_ttbr1_1;
349 uint64_t ttbr1_s;
350 };
351 uint64_t ttbr1_el[4];
352 };
353 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
354 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
355 /* MMU translation table base control. */
356 uint64_t tcr_el[4];
357 uint64_t vtcr_el2; /* Virtualization Translation Control. */
358 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */
359 uint32_t c2_data; /* MPU data cacheable bits. */
360 uint32_t c2_insn; /* MPU instruction cacheable bits. */
361 union { /* MMU domain access control register
362 * MPU write buffer control.
363 */
364 struct {
365 uint64_t dacr_ns;
366 uint64_t dacr_s;
367 };
368 struct {
369 uint64_t dacr32_el2;
370 };
371 };
372 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
373 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
374 uint64_t hcr_el2; /* Hypervisor configuration register */
375 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
376 uint64_t scr_el3; /* Secure configuration register. */
377 union { /* Fault status registers. */
378 struct {
379 uint64_t ifsr_ns;
380 uint64_t ifsr_s;
381 };
382 struct {
383 uint64_t ifsr32_el2;
384 };
385 };
386 union {
387 struct {
388 uint64_t _unused_dfsr;
389 uint64_t dfsr_ns;
390 uint64_t hsr;
391 uint64_t dfsr_s;
392 };
393 uint64_t esr_el[4];
394 };
395 uint32_t c6_region[8]; /* MPU base/size registers. */
396 union { /* Fault address registers. */
397 struct {
398 uint64_t _unused_far0;
399 #if HOST_BIG_ENDIAN
400 uint32_t ifar_ns;
401 uint32_t dfar_ns;
402 uint32_t ifar_s;
403 uint32_t dfar_s;
404 #else
405 uint32_t dfar_ns;
406 uint32_t ifar_ns;
407 uint32_t dfar_s;
408 uint32_t ifar_s;
409 #endif
410 uint64_t _unused_far3;
411 };
412 uint64_t far_el[4];
413 };
414 uint64_t hpfar_el2;
415 uint64_t hstr_el2;
416 union { /* Translation result. */
417 struct {
418 uint64_t _unused_par_0;
419 uint64_t par_ns;
420 uint64_t _unused_par_1;
421 uint64_t par_s;
422 };
423 uint64_t par_el[4];
424 };
425
426 uint32_t c9_insn; /* Cache lockdown registers. */
427 uint32_t c9_data;
428 uint64_t c9_pmcr; /* performance monitor control register */
429 uint64_t c9_pmcnten; /* perf monitor counter enables */
430 uint64_t c9_pmovsr; /* perf monitor overflow status */
431 uint64_t c9_pmuserenr; /* perf monitor user enable */
432 uint64_t c9_pmselr; /* perf monitor counter selection register */
433 uint64_t c9_pminten; /* perf monitor interrupt enables */
434 union { /* Memory attribute redirection */
435 struct {
436 #if HOST_BIG_ENDIAN
437 uint64_t _unused_mair_0;
438 uint32_t mair1_ns;
439 uint32_t mair0_ns;
440 uint64_t _unused_mair_1;
441 uint32_t mair1_s;
442 uint32_t mair0_s;
443 #else
444 uint64_t _unused_mair_0;
445 uint32_t mair0_ns;
446 uint32_t mair1_ns;
447 uint64_t _unused_mair_1;
448 uint32_t mair0_s;
449 uint32_t mair1_s;
450 #endif
451 };
452 uint64_t mair_el[4];
453 };
454 union { /* vector base address register */
455 struct {
456 uint64_t _unused_vbar;
457 uint64_t vbar_ns;
458 uint64_t hvbar;
459 uint64_t vbar_s;
460 };
461 uint64_t vbar_el[4];
462 };
463 uint32_t mvbar; /* (monitor) vector base address register */
464 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
465 struct { /* FCSE PID. */
466 uint32_t fcseidr_ns;
467 uint32_t fcseidr_s;
468 };
469 union { /* Context ID. */
470 struct {
471 uint64_t _unused_contextidr_0;
472 uint64_t contextidr_ns;
473 uint64_t _unused_contextidr_1;
474 uint64_t contextidr_s;
475 };
476 uint64_t contextidr_el[4];
477 };
478 union { /* User RW Thread register. */
479 struct {
480 uint64_t tpidrurw_ns;
481 uint64_t tpidrprw_ns;
482 uint64_t htpidr;
483 uint64_t _tpidr_el3;
484 };
485 uint64_t tpidr_el[4];
486 };
487 uint64_t tpidr2_el0;
488 /* The secure banks of these registers don't map anywhere */
489 uint64_t tpidrurw_s;
490 uint64_t tpidrprw_s;
491 uint64_t tpidruro_s;
492
493 union { /* User RO Thread register. */
494 uint64_t tpidruro_ns;
495 uint64_t tpidrro_el[1];
496 };
497 uint64_t c14_cntfrq; /* Counter Frequency register */
498 uint64_t c14_cntkctl; /* Timer Control register */
499 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
500 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
501 uint64_t cntpoff_el2; /* Counter Physical Offset register */
502 ARMGenericTimer c14_timer[NUM_GTIMERS];
503 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
504 uint32_t c15_ticonfig; /* TI925T configuration byte. */
505 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
506 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
507 uint32_t c15_threadid; /* TI debugger thread-ID. */
508 uint32_t c15_config_base_address; /* SCU base address. */
509 uint32_t c15_diagnostic; /* diagnostic register */
510 uint32_t c15_power_diagnostic;
511 uint32_t c15_power_control; /* power control */
512 uint64_t dbgbvr[16]; /* breakpoint value registers */
513 uint64_t dbgbcr[16]; /* breakpoint control registers */
514 uint64_t dbgwvr[16]; /* watchpoint value registers */
515 uint64_t dbgwcr[16]; /* watchpoint control registers */
516 uint64_t dbgclaim; /* DBGCLAIM bits */
517 uint64_t mdscr_el1;
518 uint64_t oslsr_el1; /* OS Lock Status */
519 uint64_t osdlr_el1; /* OS DoubleLock status */
520 uint64_t mdcr_el2;
521 uint64_t mdcr_el3;
522 /* Stores the architectural value of the counter *the last time it was
523 * updated* by pmccntr_op_start. Accesses should always be surrounded
524 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
525 * architecturally-correct value is being read/set.
526 */
527 uint64_t c15_ccnt;
528 /* Stores the delta between the architectural value and the underlying
529 * cycle count during normal operation. It is used to update c15_ccnt
530 * to be the correct architectural value before accesses. During
531 * accesses, c15_ccnt_delta contains the underlying count being used
532 * for the access, after which it reverts to the delta value in
533 * pmccntr_op_finish.
534 */
535 uint64_t c15_ccnt_delta;
536 uint64_t c14_pmevcntr[31];
537 uint64_t c14_pmevcntr_delta[31];
538 uint64_t c14_pmevtyper[31];
539 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
540 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
541 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
542 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
543 uint64_t gcr_el1;
544 uint64_t rgsr_el1;
545
546 /* Minimal RAS registers */
547 uint64_t disr_el1;
548 uint64_t vdisr_el2;
549 uint64_t vsesr_el2;
550
551 /*
552 * Fine-Grained Trap registers. We store these as arrays so the
553 * access checking code doesn't have to manually select
554 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
555 * FEAT_FGT2 will add more elements to these arrays.
556 */
557 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
558 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
559 uint64_t fgt_exec[1]; /* HFGITR */
560
561 /* RME registers */
562 uint64_t gpccr_el3;
563 uint64_t gptbr_el3;
564 uint64_t mfar_el3;
565
566 /* NV2 register */
567 uint64_t vncr_el2;
568 } cp15;
569
570 struct {
571 /* M profile has up to 4 stack pointers:
572 * a Main Stack Pointer and a Process Stack Pointer for each
573 * of the Secure and Non-Secure states. (If the CPU doesn't support
574 * the security extension then it has only two SPs.)
575 * In QEMU we always store the currently active SP in regs[13],
576 * and the non-active SP for the current security state in
577 * v7m.other_sp. The stack pointers for the inactive security state
578 * are stored in other_ss_msp and other_ss_psp.
579 * switch_v7m_security_state() is responsible for rearranging them
580 * when we change security state.
581 */
582 uint32_t other_sp;
583 uint32_t other_ss_msp;
584 uint32_t other_ss_psp;
585 uint32_t vecbase[M_REG_NUM_BANKS];
586 uint32_t basepri[M_REG_NUM_BANKS];
587 uint32_t control[M_REG_NUM_BANKS];
588 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
589 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
590 uint32_t hfsr; /* HardFault Status */
591 uint32_t dfsr; /* Debug Fault Status Register */
592 uint32_t sfsr; /* Secure Fault Status Register */
593 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
594 uint32_t bfar; /* BusFault Address */
595 uint32_t sfar; /* Secure Fault Address Register */
596 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
597 int exception;
598 uint32_t primask[M_REG_NUM_BANKS];
599 uint32_t faultmask[M_REG_NUM_BANKS];
600 uint32_t aircr; /* only holds r/w state if security extn implemented */
601 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
602 uint32_t csselr[M_REG_NUM_BANKS];
603 uint32_t scr[M_REG_NUM_BANKS];
604 uint32_t msplim[M_REG_NUM_BANKS];
605 uint32_t psplim[M_REG_NUM_BANKS];
606 uint32_t fpcar[M_REG_NUM_BANKS];
607 uint32_t fpccr[M_REG_NUM_BANKS];
608 uint32_t fpdscr[M_REG_NUM_BANKS];
609 uint32_t cpacr[M_REG_NUM_BANKS];
610 uint32_t nsacr;
611 uint32_t ltpsize;
612 uint32_t vpr;
613 } v7m;
614
615 /* Information associated with an exception about to be taken:
616 * code which raises an exception must set cs->exception_index and
617 * the relevant parts of this structure; the cpu_do_interrupt function
618 * will then set the guest-visible registers as part of the exception
619 * entry process.
620 */
621 struct {
622 uint32_t syndrome; /* AArch64 format syndrome register */
623 uint32_t fsr; /* AArch32 format fault status register info */
624 uint64_t vaddress; /* virtual addr associated with exception, if any */
625 uint32_t target_el; /* EL the exception should be targeted for */
626 /* If we implement EL2 we will also need to store information
627 * about the intermediate physical address for stage 2 faults.
628 */
629 } exception;
630
631 /* Information associated with an SError */
632 struct {
633 uint8_t pending;
634 uint8_t has_esr;
635 uint64_t esr;
636 } serror;
637
638 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
639
640 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
641 uint32_t irq_line_state;
642
643 /* Thumb-2 EE state. */
644 uint32_t teecr;
645 uint32_t teehbr;
646
647 /* VFP coprocessor state. */
648 struct {
649 ARMVectorReg zregs[32];
650
651 /* Store FFR as pregs[16] to make it easier to treat as any other. */
652 #define FFR_PRED_NUM 16
653 ARMPredicateReg pregs[17];
654 /* Scratch space for aa64 sve predicate temporary. */
655 ARMPredicateReg preg_tmp;
656
657 /* We store these fpcsr fields separately for convenience. */
658 uint32_t qc[4] QEMU_ALIGNED(16);
659 int vec_len;
660 int vec_stride;
661
662 /*
663 * Floating point status and control registers. Some bits are
664 * stored separately in other fields or in the float_status below.
665 */
666 uint64_t fpsr;
667 uint64_t fpcr;
668
669 uint32_t xregs[16];
670
671 /* Scratch space for aa32 neon expansion. */
672 uint32_t scratch[8];
673
674 /* There are a number of distinct float control structures. */
675 float_status fp_status[FPST_COUNT];
676
677 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
678 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
679 } vfp;
680
681 uint64_t exclusive_addr;
682 uint64_t exclusive_val;
683 /*
684 * Contains the 'val' for the second 64-bit register of LDXP, which comes
685 * from the higher address, not the high part of a complete 128-bit value.
686 * In some ways it might be more convenient to record the exclusive value
687 * as the low and high halves of a 128 bit data value, but the current
688 * semantics of these fields are baked into the migration format.
689 */
690 uint64_t exclusive_high;
691
692 /* iwMMXt coprocessor state. */
693 struct {
694 uint64_t regs[16];
695 uint64_t val;
696
697 uint32_t cregs[16];
698 } iwmmxt;
699
700 struct {
701 ARMPACKey apia;
702 ARMPACKey apib;
703 ARMPACKey apda;
704 ARMPACKey apdb;
705 ARMPACKey apga;
706 } keys;
707
708 uint64_t scxtnum_el[4];
709
710 /*
711 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
712 * as we do with vfp.zregs[]. This corresponds to the architectural ZA
713 * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
714 * When SVL is less than the architectural maximum, the accessible
715 * storage is restricted, such that if the SVL is X bytes the guest can
716 * see only the bottom X elements of zarray[], and only the least
717 * significant X bytes of each element of the array. (In other words,
718 * the observable part is always square.)
719 *
720 * The ZA storage can also be considered as a set of square tiles of
721 * elements of different sizes. The mapping from tiles to the ZA array
722 * is architecturally defined, such that for tiles of elements of esz
723 * bytes, the Nth row (or "horizontal slice") of tile T is in
724 * ZA[T + N * esz]. Note that this means that each tile is not contiguous
725 * in the ZA storage, because its rows are striped through the ZA array.
726 *
727 * Because this is so large, keep this toward the end of the reset area,
728 * to keep the offsets into the rest of the structure smaller.
729 */
730 ARMVectorReg zarray[ARM_MAX_VQ * 16];
731
732 struct CPUBreakpoint *cpu_breakpoint[16];
733 struct CPUWatchpoint *cpu_watchpoint[16];
734
735 /* Optional fault info across tlb lookup. */
736 ARMMMUFaultInfo *tlb_fi;
737
738 /* Fields up to this point are cleared by a CPU reset */
739 struct {} end_reset_fields;
740
741 /* Fields after this point are preserved across CPU reset. */
742
743 /* Internal CPU feature flags. */
744 uint64_t features;
745
746 /* PMSAv7 MPU */
747 struct {
748 uint32_t *drbar;
749 uint32_t *drsr;
750 uint32_t *dracr;
751 uint32_t rnr[M_REG_NUM_BANKS];
752 } pmsav7;
753
754 /* PMSAv8 MPU */
755 struct {
756 /* The PMSAv8 implementation also shares some PMSAv7 config
757 * and state:
758 * pmsav7.rnr (region number register)
759 * pmsav7_dregion (number of configured regions)
760 */
761 uint32_t *rbar[M_REG_NUM_BANKS];
762 uint32_t *rlar[M_REG_NUM_BANKS];
763 uint32_t *hprbar;
764 uint32_t *hprlar;
765 uint32_t mair0[M_REG_NUM_BANKS];
766 uint32_t mair1[M_REG_NUM_BANKS];
767 uint32_t hprselr;
768 } pmsav8;
769
770 /* v8M SAU */
771 struct {
772 uint32_t *rbar;
773 uint32_t *rlar;
774 uint32_t rnr;
775 uint32_t ctrl;
776 } sau;
777
778 #if !defined(CONFIG_USER_ONLY)
779 NVICState *nvic;
780 const struct arm_boot_info *boot_info;
781 /* Store GICv3CPUState to access from this struct */
782 void *gicv3state;
783 #else /* CONFIG_USER_ONLY */
784 /* For usermode syscall translation. */
785 bool eabi;
786 /* Linux syscall tagged address support */
787 bool tagged_addr_enable;
788 #endif /* CONFIG_USER_ONLY */
789 } CPUARMState;
790
set_feature(CPUARMState * env,int feature)791 static inline void set_feature(CPUARMState *env, int feature)
792 {
793 env->features |= 1ULL << feature;
794 }
795
unset_feature(CPUARMState * env,int feature)796 static inline void unset_feature(CPUARMState *env, int feature)
797 {
798 env->features &= ~(1ULL << feature);
799 }
800
801 /**
802 * ARMELChangeHookFn:
803 * type of a function which can be registered via arm_register_el_change_hook()
804 * to get callbacks when the CPU changes its exception level or mode.
805 */
806 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
807 typedef struct ARMELChangeHook ARMELChangeHook;
808 struct ARMELChangeHook {
809 ARMELChangeHookFn *hook;
810 void *opaque;
811 QLIST_ENTRY(ARMELChangeHook) node;
812 };
813
814 /* These values map onto the return values for
815 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
816 typedef enum ARMPSCIState {
817 PSCI_ON = 0,
818 PSCI_OFF = 1,
819 PSCI_ON_PENDING = 2
820 } ARMPSCIState;
821
822 typedef struct ARMISARegisters ARMISARegisters;
823
824 /*
825 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
826 * bytes, i.e. each bit number + 1 is the vector length in quadwords.
827 *
828 * While processing properties during initialization, corresponding init bits
829 * are set for bits in sve_vq_map that have been set by properties.
830 *
831 * Bits set in supported represent valid vector lengths for the CPU type.
832 */
833 typedef struct {
834 uint32_t map, init, supported;
835 } ARMVQMap;
836
837 /**
838 * ARMCPU:
839 * @env: #CPUARMState
840 *
841 * An ARM CPU core.
842 */
843 struct ArchCPU {
844 CPUState parent_obj;
845
846 CPUARMState env;
847
848 /* Coprocessor information */
849 GHashTable *cp_regs;
850 /* For marshalling (mostly coprocessor) register state between the
851 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
852 * we use these arrays.
853 */
854 /* List of register indexes managed via these arrays; (full KVM style
855 * 64 bit indexes, not CPRegInfo 32 bit indexes)
856 */
857 uint64_t *cpreg_indexes;
858 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
859 uint64_t *cpreg_values;
860 /* Length of the indexes, values, reset_values arrays */
861 int32_t cpreg_array_len;
862 /* These are used only for migration: incoming data arrives in
863 * these fields and is sanity checked in post_load before copying
864 * to the working data structures above.
865 */
866 uint64_t *cpreg_vmstate_indexes;
867 uint64_t *cpreg_vmstate_values;
868 int32_t cpreg_vmstate_array_len;
869
870 DynamicGDBFeatureInfo dyn_sysreg_feature;
871 DynamicGDBFeatureInfo dyn_svereg_feature;
872 DynamicGDBFeatureInfo dyn_m_systemreg_feature;
873 DynamicGDBFeatureInfo dyn_m_secextreg_feature;
874
875 /* Timers used by the generic (architected) timer */
876 QEMUTimer *gt_timer[NUM_GTIMERS];
877 /*
878 * Timer used by the PMU. Its state is restored after migration by
879 * pmu_op_finish() - it does not need other handling during migration
880 */
881 QEMUTimer *pmu_timer;
882 /* Timer used for WFxT timeouts */
883 QEMUTimer *wfxt_timer;
884
885 /* GPIO outputs for generic timer */
886 qemu_irq gt_timer_outputs[NUM_GTIMERS];
887 /* GPIO output for GICv3 maintenance interrupt signal */
888 qemu_irq gicv3_maintenance_interrupt;
889 /* GPIO output for the PMU interrupt */
890 qemu_irq pmu_interrupt;
891
892 /* MemoryRegion to use for secure physical accesses */
893 MemoryRegion *secure_memory;
894
895 /* MemoryRegion to use for allocation tag accesses */
896 MemoryRegion *tag_memory;
897 MemoryRegion *secure_tag_memory;
898
899 /* For v8M, pointer to the IDAU interface provided by board/SoC */
900 Object *idau;
901
902 /* 'compatible' string for this CPU for Linux device trees */
903 const char *dtb_compatible;
904
905 /* PSCI version for this CPU
906 * Bits[31:16] = Major Version
907 * Bits[15:0] = Minor Version
908 */
909 uint32_t psci_version;
910
911 /* Current power state, access guarded by BQL */
912 ARMPSCIState power_state;
913
914 /* CPU has virtualization extension */
915 bool has_el2;
916 /* CPU has security extension */
917 bool has_el3;
918 /* CPU has PMU (Performance Monitor Unit) */
919 bool has_pmu;
920 /* CPU has VFP */
921 bool has_vfp;
922 /* CPU has 32 VFP registers */
923 bool has_vfp_d32;
924 /* CPU has Neon */
925 bool has_neon;
926 /* CPU has M-profile DSP extension */
927 bool has_dsp;
928
929 /* CPU has memory protection unit */
930 bool has_mpu;
931 /* CPU has MTE enabled in KVM mode */
932 bool kvm_mte;
933 /* PMSAv7 MPU number of supported regions */
934 uint32_t pmsav7_dregion;
935 /* PMSAv8 MPU number of supported hyp regions */
936 uint32_t pmsav8r_hdregion;
937 /* v8M SAU number of supported regions */
938 uint32_t sau_sregion;
939
940 /* PSCI conduit used to invoke PSCI methods
941 * 0 - disabled, 1 - smc, 2 - hvc
942 */
943 uint32_t psci_conduit;
944
945 /* For v8M, initial value of the Secure VTOR */
946 uint32_t init_svtor;
947 /* For v8M, initial value of the Non-secure VTOR */
948 uint32_t init_nsvtor;
949
950 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
951 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
952 */
953 uint32_t kvm_target;
954
955 /* KVM init features for this CPU */
956 uint32_t kvm_init_features[7];
957
958 /* KVM CPU state */
959
960 /* KVM virtual time adjustment */
961 bool kvm_adjvtime;
962 bool kvm_vtime_dirty;
963 uint64_t kvm_vtime;
964
965 /* KVM steal time */
966 OnOffAuto kvm_steal_time;
967
968 /* Uniprocessor system with MP extensions */
969 bool mp_is_up;
970
971 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
972 * and the probe failed (so we need to report the error in realize)
973 */
974 bool host_cpu_probe_failed;
975
976 /* QOM property to indicate we should use the back-compat CNTFRQ default */
977 bool backcompat_cntfrq;
978
979 /* QOM property to indicate we should use the back-compat QARMA5 default */
980 bool backcompat_pauth_default_use_qarma5;
981
982 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
983 * register.
984 */
985 int32_t core_count;
986
987 /* The instance init functions for implementation-specific subclasses
988 * set these fields to specify the implementation-dependent values of
989 * various constant registers and reset values of non-constant
990 * registers.
991 * Some of these might become QOM properties eventually.
992 * Field names match the official register names as defined in the
993 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
994 * is used for reset values of non-constant registers; no reset_
995 * prefix means a constant register.
996 * Some of these registers are split out into a substructure that
997 * is shared with the translators to control the ISA.
998 *
999 * Note that if you add an ID register to the ARMISARegisters struct
1000 * you need to also update the 32-bit and 64-bit versions of the
1001 * kvm_arm_get_host_cpu_features() function to correctly populate the
1002 * field by reading the value from the KVM vCPU.
1003 */
1004 struct ARMISARegisters {
1005 uint32_t id_isar0;
1006 uint32_t id_isar1;
1007 uint32_t id_isar2;
1008 uint32_t id_isar3;
1009 uint32_t id_isar4;
1010 uint32_t id_isar5;
1011 uint32_t id_isar6;
1012 uint32_t id_mmfr0;
1013 uint32_t id_mmfr1;
1014 uint32_t id_mmfr2;
1015 uint32_t id_mmfr3;
1016 uint32_t id_mmfr4;
1017 uint32_t id_mmfr5;
1018 uint32_t id_pfr0;
1019 uint32_t id_pfr1;
1020 uint32_t id_pfr2;
1021 uint32_t mvfr0;
1022 uint32_t mvfr1;
1023 uint32_t mvfr2;
1024 uint32_t id_dfr0;
1025 uint32_t id_dfr1;
1026 uint32_t dbgdidr;
1027 uint32_t dbgdevid;
1028 uint32_t dbgdevid1;
1029 uint64_t id_aa64isar0;
1030 uint64_t id_aa64isar1;
1031 uint64_t id_aa64isar2;
1032 uint64_t id_aa64pfr0;
1033 uint64_t id_aa64pfr1;
1034 uint64_t id_aa64mmfr0;
1035 uint64_t id_aa64mmfr1;
1036 uint64_t id_aa64mmfr2;
1037 uint64_t id_aa64mmfr3;
1038 uint64_t id_aa64dfr0;
1039 uint64_t id_aa64dfr1;
1040 uint64_t id_aa64zfr0;
1041 uint64_t id_aa64smfr0;
1042 uint64_t reset_pmcr_el0;
1043 } isar;
1044 uint64_t midr;
1045 uint32_t revidr;
1046 uint32_t reset_fpsid;
1047 uint64_t ctr;
1048 uint32_t reset_sctlr;
1049 uint64_t pmceid0;
1050 uint64_t pmceid1;
1051 uint32_t id_afr0;
1052 uint64_t id_aa64afr0;
1053 uint64_t id_aa64afr1;
1054 uint64_t clidr;
1055 uint64_t mp_affinity; /* MP ID without feature bits */
1056 /* The elements of this array are the CCSIDR values for each cache,
1057 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
1058 */
1059 uint64_t ccsidr[16];
1060 uint64_t reset_cbar;
1061 uint32_t reset_auxcr;
1062 bool reset_hivecs;
1063 uint8_t reset_l0gptsz;
1064
1065 /*
1066 * Intermediate values used during property parsing.
1067 * Once finalized, the values should be read from ID_AA64*.
1068 */
1069 bool prop_pauth;
1070 bool prop_pauth_impdef;
1071 bool prop_pauth_qarma3;
1072 bool prop_pauth_qarma5;
1073 bool prop_lpa2;
1074
1075 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
1076 uint8_t dcz_blocksize;
1077 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
1078 uint8_t gm_blocksize;
1079
1080 uint64_t rvbar_prop; /* Property/input signals. */
1081
1082 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
1083 int gic_num_lrs; /* number of list registers */
1084 int gic_vpribits; /* number of virtual priority bits */
1085 int gic_vprebits; /* number of virtual preemption bits */
1086 int gic_pribits; /* number of physical priority bits */
1087
1088 /* Whether the cfgend input is high (i.e. this CPU should reset into
1089 * big-endian mode). This setting isn't used directly: instead it modifies
1090 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
1091 * architecture version.
1092 */
1093 bool cfgend;
1094
1095 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1096 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1097
1098 int32_t node_id; /* NUMA node this CPU belongs to */
1099
1100 /* Used to synchronize KVM and QEMU in-kernel device levels */
1101 uint8_t device_irq_level;
1102
1103 /* Used to set the maximum vector length the cpu will support. */
1104 uint32_t sve_max_vq;
1105
1106 #ifdef CONFIG_USER_ONLY
1107 /* Used to set the default vector length at process start. */
1108 uint32_t sve_default_vq;
1109 uint32_t sme_default_vq;
1110 #endif
1111
1112 ARMVQMap sve_vq;
1113 ARMVQMap sme_vq;
1114
1115 /* Generic timer counter frequency, in Hz */
1116 uint64_t gt_cntfrq_hz;
1117 };
1118
1119 typedef struct ARMCPUInfo {
1120 const char *name;
1121 const char *deprecation_note;
1122 void (*initfn)(Object *obj);
1123 void (*class_init)(ObjectClass *oc, const void *data);
1124 } ARMCPUInfo;
1125
1126 /**
1127 * ARMCPUClass:
1128 * @parent_realize: The parent class' realize handler.
1129 * @parent_phases: The parent class' reset phase handlers.
1130 *
1131 * An ARM CPU model.
1132 */
1133 struct ARMCPUClass {
1134 CPUClass parent_class;
1135
1136 const ARMCPUInfo *info;
1137 DeviceRealize parent_realize;
1138 ResettablePhases parent_phases;
1139 };
1140
1141 struct AArch64CPUClass {
1142 ARMCPUClass parent_class;
1143 };
1144
1145 /* Callback functions for the generic timer's timers. */
1146 void arm_gt_ptimer_cb(void *opaque);
1147 void arm_gt_vtimer_cb(void *opaque);
1148 void arm_gt_htimer_cb(void *opaque);
1149 void arm_gt_stimer_cb(void *opaque);
1150 void arm_gt_hvtimer_cb(void *opaque);
1151 void arm_gt_sel2timer_cb(void *opaque);
1152 void arm_gt_sel2vtimer_cb(void *opaque);
1153
1154 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1155 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
1156
1157 void arm_cpu_post_init(Object *obj);
1158
1159 #define ARM_AFF0_SHIFT 0
1160 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
1161 #define ARM_AFF1_SHIFT 8
1162 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
1163 #define ARM_AFF2_SHIFT 16
1164 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
1165 #define ARM_AFF3_SHIFT 32
1166 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
1167 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8
1168
1169 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
1170 #define ARM64_AFFINITY_MASK \
1171 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
1172 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
1173
1174 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
1175
1176 #ifndef CONFIG_USER_ONLY
1177 extern const VMStateDescription vmstate_arm_cpu;
1178
1179 void arm_cpu_do_interrupt(CPUState *cpu);
1180 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1181
1182 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1183 MemTxAttrs *attrs);
1184 #endif /* !CONFIG_USER_ONLY */
1185
1186 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1187 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1188
1189 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1190 int cpuid, DumpState *s);
1191 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1192 int cpuid, DumpState *s);
1193
1194 /**
1195 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
1196 * @cpu: CPU (which must have been freshly reset)
1197 * @target_el: exception level to put the CPU into
1198 * @secure: whether to put the CPU in secure state
1199 *
1200 * When QEMU is directly running a guest kernel at a lower level than
1201 * EL3 it implicitly emulates some aspects of the guest firmware.
1202 * This includes that on reset we need to configure the parts of the
1203 * CPU corresponding to EL3 so that the real guest code can run at its
1204 * lower exception level. This function does that post-reset CPU setup,
1205 * for when we do direct boot of a guest kernel, and for when we
1206 * emulate PSCI and similar firmware interfaces starting a CPU at a
1207 * lower exception level.
1208 *
1209 * @target_el must be an EL implemented by the CPU between 1 and 3.
1210 * We do not support dropping into a Secure EL other than 3.
1211 *
1212 * It is the responsibility of the caller to call arm_rebuild_hflags().
1213 */
1214 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
1215
1216 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1217 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1218 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1219 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1220 int new_el, bool el0_a64);
1221 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
1222
1223 /*
1224 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1225 * The byte at offset i from the start of the in-memory representation contains
1226 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1227 * lowest offsets are stored in the lowest memory addresses, then that nearly
1228 * matches QEMU's representation, which is to use an array of host-endian
1229 * uint64_t's, where the lower offsets are at the lower indices. To complete
1230 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1231 */
sve_bswap64(uint64_t * dst,uint64_t * src,int nr)1232 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1233 {
1234 #if HOST_BIG_ENDIAN
1235 int i;
1236
1237 for (i = 0; i < nr; ++i) {
1238 dst[i] = bswap64(src[i]);
1239 }
1240
1241 return dst;
1242 #else
1243 return src;
1244 #endif
1245 }
1246
1247 void aarch64_sync_32_to_64(CPUARMState *env);
1248 void aarch64_sync_64_to_32(CPUARMState *env);
1249
1250 int fp_exception_el(CPUARMState *env, int cur_el);
1251 int sve_exception_el(CPUARMState *env, int cur_el);
1252 int sme_exception_el(CPUARMState *env, int cur_el);
1253
1254 /**
1255 * sve_vqm1_for_el_sm:
1256 * @env: CPUARMState
1257 * @el: exception level
1258 * @sm: streaming mode
1259 *
1260 * Compute the current vector length for @el & @sm, in units of
1261 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1262 * If @sm, compute for SVL, otherwise NVL.
1263 */
1264 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1265
1266 /* Likewise, but using @sm = PSTATE.SM. */
1267 uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
1268
is_a64(CPUARMState * env)1269 static inline bool is_a64(CPUARMState *env)
1270 {
1271 return env->aarch64;
1272 }
1273
1274 /**
1275 * pmu_op_start/finish
1276 * @env: CPUARMState
1277 *
1278 * Convert all PMU counters between their delta form (the typical mode when
1279 * they are enabled) and the guest-visible values. These two calls must
1280 * surround any action which might affect the counters.
1281 */
1282 void pmu_op_start(CPUARMState *env);
1283 void pmu_op_finish(CPUARMState *env);
1284
1285 /*
1286 * Called when a PMU counter is due to overflow
1287 */
1288 void arm_pmu_timer_cb(void *opaque);
1289
1290 /**
1291 * Functions to register as EL change hooks for PMU mode filtering
1292 */
1293 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1294 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1295
1296 /*
1297 * pmu_init
1298 * @cpu: ARMCPU
1299 *
1300 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1301 * for the current configuration
1302 */
1303 void pmu_init(ARMCPU *cpu);
1304
1305 /* SCTLR bit meanings. Several bits have been reused in newer
1306 * versions of the architecture; in that case we define constants
1307 * for both old and new bit meanings. Code which tests against those
1308 * bits should probably check or otherwise arrange that the CPU
1309 * is the architectural version it expects.
1310 */
1311 #define SCTLR_M (1U << 0)
1312 #define SCTLR_A (1U << 1)
1313 #define SCTLR_C (1U << 2)
1314 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1315 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1316 #define SCTLR_SA (1U << 3) /* AArch64 only */
1317 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1318 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1319 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1320 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1321 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1322 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1323 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */
1324 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1325 #define SCTLR_ITD (1U << 7) /* v8 onward */
1326 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1327 #define SCTLR_SED (1U << 8) /* v8 onward */
1328 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1329 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1330 #define SCTLR_F (1U << 10) /* up to v6 */
1331 #define SCTLR_SW (1U << 10) /* v7 */
1332 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1333 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1334 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1335 #define SCTLR_I (1U << 12)
1336 #define SCTLR_V (1U << 13) /* AArch32 only */
1337 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1338 #define SCTLR_RR (1U << 14) /* up to v7 */
1339 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1340 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1341 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1342 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1343 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1344 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1345 #define SCTLR_BR (1U << 17) /* PMSA only */
1346 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1347 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1348 #define SCTLR_WXN (1U << 19)
1349 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1350 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1351 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1352 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1353 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1354 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1355 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1356 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1357 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1358 #define SCTLR_VE (1U << 24) /* up to v7 */
1359 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1360 #define SCTLR_EE (1U << 25)
1361 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1362 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1363 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1364 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1365 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1366 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1367 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1368 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1369 #define SCTLR_TE (1U << 30) /* AArch32 only */
1370 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1371 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1372 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1373 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */
1374 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
1375 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1376 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1377 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1378 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1379 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1380 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1381 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1382 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1383 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */
1384 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */
1385 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */
1386 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */
1387 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */
1388 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */
1389 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */
1390 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
1391 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
1392 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
1393 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
1394 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
1395 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1396 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
1397
1398 #define CPSR_M (0x1fU)
1399 #define CPSR_T (1U << 5)
1400 #define CPSR_F (1U << 6)
1401 #define CPSR_I (1U << 7)
1402 #define CPSR_A (1U << 8)
1403 #define CPSR_E (1U << 9)
1404 #define CPSR_IT_2_7 (0xfc00U)
1405 #define CPSR_GE (0xfU << 16)
1406 #define CPSR_IL (1U << 20)
1407 #define CPSR_DIT (1U << 21)
1408 #define CPSR_PAN (1U << 22)
1409 #define CPSR_SSBS (1U << 23)
1410 #define CPSR_J (1U << 24)
1411 #define CPSR_IT_0_1 (3U << 25)
1412 #define CPSR_Q (1U << 27)
1413 #define CPSR_V (1U << 28)
1414 #define CPSR_C (1U << 29)
1415 #define CPSR_Z (1U << 30)
1416 #define CPSR_N (1U << 31)
1417 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1418 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1419 #define ISR_FS (1U << 9)
1420 #define ISR_IS (1U << 10)
1421
1422 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1423 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1424 | CPSR_NZCV)
1425 /* Bits writable in user mode. */
1426 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1427 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1428 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1429
1430 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1431 #define XPSR_EXCP 0x1ffU
1432 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1433 #define XPSR_IT_2_7 CPSR_IT_2_7
1434 #define XPSR_GE CPSR_GE
1435 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1436 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1437 #define XPSR_IT_0_1 CPSR_IT_0_1
1438 #define XPSR_Q CPSR_Q
1439 #define XPSR_V CPSR_V
1440 #define XPSR_C CPSR_C
1441 #define XPSR_Z CPSR_Z
1442 #define XPSR_N CPSR_N
1443 #define XPSR_NZCV CPSR_NZCV
1444 #define XPSR_IT CPSR_IT
1445
1446 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1447 * Only these are valid when in AArch64 mode; in
1448 * AArch32 mode SPSRs are basically CPSR-format.
1449 */
1450 #define PSTATE_SP (1U)
1451 #define PSTATE_M (0xFU)
1452 #define PSTATE_nRW (1U << 4)
1453 #define PSTATE_F (1U << 6)
1454 #define PSTATE_I (1U << 7)
1455 #define PSTATE_A (1U << 8)
1456 #define PSTATE_D (1U << 9)
1457 #define PSTATE_BTYPE (3U << 10)
1458 #define PSTATE_SSBS (1U << 12)
1459 #define PSTATE_ALLINT (1U << 13)
1460 #define PSTATE_IL (1U << 20)
1461 #define PSTATE_SS (1U << 21)
1462 #define PSTATE_PAN (1U << 22)
1463 #define PSTATE_UAO (1U << 23)
1464 #define PSTATE_DIT (1U << 24)
1465 #define PSTATE_TCO (1U << 25)
1466 #define PSTATE_V (1U << 28)
1467 #define PSTATE_C (1U << 29)
1468 #define PSTATE_Z (1U << 30)
1469 #define PSTATE_N (1U << 31)
1470 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1471 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1472 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1473 /* Mode values for AArch64 */
1474 #define PSTATE_MODE_EL3h 13
1475 #define PSTATE_MODE_EL3t 12
1476 #define PSTATE_MODE_EL2h 9
1477 #define PSTATE_MODE_EL2t 8
1478 #define PSTATE_MODE_EL1h 5
1479 #define PSTATE_MODE_EL1t 4
1480 #define PSTATE_MODE_EL0t 0
1481
1482 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */
1483 FIELD(SVCR, SM, 0, 1)
1484 FIELD(SVCR, ZA, 1, 1)
1485
1486 /* Fields for SMCR_ELx. */
1487 FIELD(SMCR, LEN, 0, 4)
1488 FIELD(SMCR, FA64, 31, 1)
1489
1490 /* Write a new value to v7m.exception, thus transitioning into or out
1491 * of Handler mode; this may result in a change of active stack pointer.
1492 */
1493 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1494
1495 /* Map EL and handler into a PSTATE_MODE. */
aarch64_pstate_mode(unsigned int el,bool handler)1496 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1497 {
1498 return (el << 2) | handler;
1499 }
1500
1501 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1502 * interprocessing, so we don't attempt to sync with the cpsr state used by
1503 * the 32 bit decoder.
1504 */
pstate_read(CPUARMState * env)1505 static inline uint32_t pstate_read(CPUARMState *env)
1506 {
1507 int ZF;
1508
1509 ZF = (env->ZF == 0);
1510 return (env->NF & 0x80000000) | (ZF << 30)
1511 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1512 | env->pstate | env->daif | (env->btype << 10);
1513 }
1514
pstate_write(CPUARMState * env,uint32_t val)1515 static inline void pstate_write(CPUARMState *env, uint32_t val)
1516 {
1517 env->ZF = (~val) & PSTATE_Z;
1518 env->NF = val;
1519 env->CF = (val >> 29) & 1;
1520 env->VF = (val << 3) & 0x80000000;
1521 env->daif = val & PSTATE_DAIF;
1522 env->btype = (val >> 10) & 3;
1523 env->pstate = val & ~CACHED_PSTATE_BITS;
1524 }
1525
1526 /* Return the current CPSR value. */
1527 uint32_t cpsr_read(CPUARMState *env);
1528
1529 typedef enum CPSRWriteType {
1530 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1531 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1532 CPSRWriteRaw = 2,
1533 /* trust values, no reg bank switch, no hflags rebuild */
1534 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1535 } CPSRWriteType;
1536
1537 /*
1538 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1539 * This will do an arm_rebuild_hflags() if any of the bits in @mask
1540 * correspond to TB flags bits cached in the hflags, unless @write_type
1541 * is CPSRWriteRaw.
1542 */
1543 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1544 CPSRWriteType write_type);
1545
1546 /* Return the current xPSR value. */
xpsr_read(CPUARMState * env)1547 static inline uint32_t xpsr_read(CPUARMState *env)
1548 {
1549 int ZF;
1550 ZF = (env->ZF == 0);
1551 return (env->NF & 0x80000000) | (ZF << 30)
1552 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1553 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1554 | ((env->condexec_bits & 0xfc) << 8)
1555 | (env->GE << 16)
1556 | env->v7m.exception;
1557 }
1558
1559 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
xpsr_write(CPUARMState * env,uint32_t val,uint32_t mask)1560 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1561 {
1562 if (mask & XPSR_NZCV) {
1563 env->ZF = (~val) & XPSR_Z;
1564 env->NF = val;
1565 env->CF = (val >> 29) & 1;
1566 env->VF = (val << 3) & 0x80000000;
1567 }
1568 if (mask & XPSR_Q) {
1569 env->QF = ((val & XPSR_Q) != 0);
1570 }
1571 if (mask & XPSR_GE) {
1572 env->GE = (val & XPSR_GE) >> 16;
1573 }
1574 #ifndef CONFIG_USER_ONLY
1575 if (mask & XPSR_T) {
1576 env->thumb = ((val & XPSR_T) != 0);
1577 }
1578 if (mask & XPSR_IT_0_1) {
1579 env->condexec_bits &= ~3;
1580 env->condexec_bits |= (val >> 25) & 3;
1581 }
1582 if (mask & XPSR_IT_2_7) {
1583 env->condexec_bits &= 3;
1584 env->condexec_bits |= (val >> 8) & 0xfc;
1585 }
1586 if (mask & XPSR_EXCP) {
1587 /* Note that this only happens on exception exit */
1588 write_v7m_exception(env, val & XPSR_EXCP);
1589 }
1590 #endif
1591 }
1592
1593 #define HCR_VM (1ULL << 0)
1594 #define HCR_SWIO (1ULL << 1)
1595 #define HCR_PTW (1ULL << 2)
1596 #define HCR_FMO (1ULL << 3)
1597 #define HCR_IMO (1ULL << 4)
1598 #define HCR_AMO (1ULL << 5)
1599 #define HCR_VF (1ULL << 6)
1600 #define HCR_VI (1ULL << 7)
1601 #define HCR_VSE (1ULL << 8)
1602 #define HCR_FB (1ULL << 9)
1603 #define HCR_BSU_MASK (3ULL << 10)
1604 #define HCR_DC (1ULL << 12)
1605 #define HCR_TWI (1ULL << 13)
1606 #define HCR_TWE (1ULL << 14)
1607 #define HCR_TID0 (1ULL << 15)
1608 #define HCR_TID1 (1ULL << 16)
1609 #define HCR_TID2 (1ULL << 17)
1610 #define HCR_TID3 (1ULL << 18)
1611 #define HCR_TSC (1ULL << 19)
1612 #define HCR_TIDCP (1ULL << 20)
1613 #define HCR_TACR (1ULL << 21)
1614 #define HCR_TSW (1ULL << 22)
1615 #define HCR_TPCP (1ULL << 23)
1616 #define HCR_TPU (1ULL << 24)
1617 #define HCR_TTLB (1ULL << 25)
1618 #define HCR_TVM (1ULL << 26)
1619 #define HCR_TGE (1ULL << 27)
1620 #define HCR_TDZ (1ULL << 28)
1621 #define HCR_HCD (1ULL << 29)
1622 #define HCR_TRVM (1ULL << 30)
1623 #define HCR_RW (1ULL << 31)
1624 #define HCR_CD (1ULL << 32)
1625 #define HCR_ID (1ULL << 33)
1626 #define HCR_E2H (1ULL << 34)
1627 #define HCR_TLOR (1ULL << 35)
1628 #define HCR_TERR (1ULL << 36)
1629 #define HCR_TEA (1ULL << 37)
1630 #define HCR_MIOCNCE (1ULL << 38)
1631 #define HCR_TME (1ULL << 39)
1632 #define HCR_APK (1ULL << 40)
1633 #define HCR_API (1ULL << 41)
1634 #define HCR_NV (1ULL << 42)
1635 #define HCR_NV1 (1ULL << 43)
1636 #define HCR_AT (1ULL << 44)
1637 #define HCR_NV2 (1ULL << 45)
1638 #define HCR_FWB (1ULL << 46)
1639 #define HCR_FIEN (1ULL << 47)
1640 #define HCR_GPF (1ULL << 48)
1641 #define HCR_TID4 (1ULL << 49)
1642 #define HCR_TICAB (1ULL << 50)
1643 #define HCR_AMVOFFEN (1ULL << 51)
1644 #define HCR_TOCU (1ULL << 52)
1645 #define HCR_ENSCXT (1ULL << 53)
1646 #define HCR_TTLBIS (1ULL << 54)
1647 #define HCR_TTLBOS (1ULL << 55)
1648 #define HCR_ATA (1ULL << 56)
1649 #define HCR_DCT (1ULL << 57)
1650 #define HCR_TID5 (1ULL << 58)
1651 #define HCR_TWEDEN (1ULL << 59)
1652 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1653
1654 #define SCR_NS (1ULL << 0)
1655 #define SCR_IRQ (1ULL << 1)
1656 #define SCR_FIQ (1ULL << 2)
1657 #define SCR_EA (1ULL << 3)
1658 #define SCR_FW (1ULL << 4)
1659 #define SCR_AW (1ULL << 5)
1660 #define SCR_NET (1ULL << 6)
1661 #define SCR_SMD (1ULL << 7)
1662 #define SCR_HCE (1ULL << 8)
1663 #define SCR_SIF (1ULL << 9)
1664 #define SCR_RW (1ULL << 10)
1665 #define SCR_ST (1ULL << 11)
1666 #define SCR_TWI (1ULL << 12)
1667 #define SCR_TWE (1ULL << 13)
1668 #define SCR_TLOR (1ULL << 14)
1669 #define SCR_TERR (1ULL << 15)
1670 #define SCR_APK (1ULL << 16)
1671 #define SCR_API (1ULL << 17)
1672 #define SCR_EEL2 (1ULL << 18)
1673 #define SCR_EASE (1ULL << 19)
1674 #define SCR_NMEA (1ULL << 20)
1675 #define SCR_FIEN (1ULL << 21)
1676 #define SCR_ENSCXT (1ULL << 25)
1677 #define SCR_ATA (1ULL << 26)
1678 #define SCR_FGTEN (1ULL << 27)
1679 #define SCR_ECVEN (1ULL << 28)
1680 #define SCR_TWEDEN (1ULL << 29)
1681 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
1682 #define SCR_TME (1ULL << 34)
1683 #define SCR_AMVOFFEN (1ULL << 35)
1684 #define SCR_ENAS0 (1ULL << 36)
1685 #define SCR_ADEN (1ULL << 37)
1686 #define SCR_HXEN (1ULL << 38)
1687 #define SCR_TRNDR (1ULL << 40)
1688 #define SCR_ENTP2 (1ULL << 41)
1689 #define SCR_GPF (1ULL << 48)
1690 #define SCR_NSE (1ULL << 62)
1691
1692 /* Return the current FPSCR value. */
1693 uint32_t vfp_get_fpscr(CPUARMState *env);
1694 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1695
1696 /*
1697 * FPCR, Floating Point Control Register
1698 * FPSR, Floating Point Status Register
1699 *
1700 * For A64 floating point control and status bits are stored in
1701 * two logically distinct registers, FPCR and FPSR. We store these
1702 * in QEMU in vfp.fpcr and vfp.fpsr.
1703 * For A32 there was only one register, FPSCR. The bits are arranged
1704 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions,
1705 * so we can use appropriate masking to handle FPSCR reads and writes.
1706 * Note that the FPCR has some bits which are not visible in the
1707 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged.
1708 */
1709
1710 /* FPCR bits */
1711 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */
1712 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */
1713 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */
1714 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1715 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1716 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1717 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1718 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1719 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */
1720 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1721 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1722 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1723 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */
1724 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
1725 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1726 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1727 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1728
1729 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1730 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1731 #define FPCR_LTPSIZE_LENGTH 3
1732
1733 /* Cumulative exception trap enable bits */
1734 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE)
1735
1736 /* FPSR bits */
1737 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */
1738 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */
1739 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */
1740 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */
1741 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */
1742 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */
1743 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */
1744 #define FPSR_V (1 << 28) /* FP overflow flag */
1745 #define FPSR_C (1 << 29) /* FP carry flag */
1746 #define FPSR_Z (1 << 30) /* FP zero flag */
1747 #define FPSR_N (1 << 31) /* FP negative flag */
1748
1749 /* Cumulative exception status bits */
1750 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC)
1751
1752 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V)
1753 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC)
1754
1755 /* A32 FPSCR bits which architecturally map to FPSR bits */
1756 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK)
1757 /* A32 FPSCR bits which architecturally map to FPCR bits */
1758 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \
1759 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \
1760 FPCR_FZ | FPCR_DN | FPCR_AHP)
1761 /* These masks don't overlap: each bit lives in only one place */
1762 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK);
1763
1764 /**
1765 * vfp_get_fpsr: read the AArch64 FPSR
1766 * @env: CPU context
1767 *
1768 * Return the current AArch64 FPSR value
1769 */
1770 uint32_t vfp_get_fpsr(CPUARMState *env);
1771
1772 /**
1773 * vfp_get_fpcr: read the AArch64 FPCR
1774 * @env: CPU context
1775 *
1776 * Return the current AArch64 FPCR value
1777 */
1778 uint32_t vfp_get_fpcr(CPUARMState *env);
1779
1780 /**
1781 * vfp_set_fpsr: write the AArch64 FPSR
1782 * @env: CPU context
1783 * @value: new value
1784 */
1785 void vfp_set_fpsr(CPUARMState *env, uint32_t value);
1786
1787 /**
1788 * vfp_set_fpcr: write the AArch64 FPCR
1789 * @env: CPU context
1790 * @value: new value
1791 */
1792 void vfp_set_fpcr(CPUARMState *env, uint32_t value);
1793
1794 enum arm_cpu_mode {
1795 ARM_CPU_MODE_USR = 0x10,
1796 ARM_CPU_MODE_FIQ = 0x11,
1797 ARM_CPU_MODE_IRQ = 0x12,
1798 ARM_CPU_MODE_SVC = 0x13,
1799 ARM_CPU_MODE_MON = 0x16,
1800 ARM_CPU_MODE_ABT = 0x17,
1801 ARM_CPU_MODE_HYP = 0x1a,
1802 ARM_CPU_MODE_UND = 0x1b,
1803 ARM_CPU_MODE_SYS = 0x1f
1804 };
1805
1806 /* VFP system registers. */
1807 #define ARM_VFP_FPSID 0
1808 #define ARM_VFP_FPSCR 1
1809 #define ARM_VFP_MVFR2 5
1810 #define ARM_VFP_MVFR1 6
1811 #define ARM_VFP_MVFR0 7
1812 #define ARM_VFP_FPEXC 8
1813 #define ARM_VFP_FPINST 9
1814 #define ARM_VFP_FPINST2 10
1815 /* These ones are M-profile only */
1816 #define ARM_VFP_FPSCR_NZCVQC 2
1817 #define ARM_VFP_VPR 12
1818 #define ARM_VFP_P0 13
1819 #define ARM_VFP_FPCXT_NS 14
1820 #define ARM_VFP_FPCXT_S 15
1821
1822 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1823 #define QEMU_VFP_FPSCR_NZCV 0xffff
1824
1825 /* iwMMXt coprocessor control registers. */
1826 #define ARM_IWMMXT_wCID 0
1827 #define ARM_IWMMXT_wCon 1
1828 #define ARM_IWMMXT_wCSSF 2
1829 #define ARM_IWMMXT_wCASF 3
1830 #define ARM_IWMMXT_wCGR0 8
1831 #define ARM_IWMMXT_wCGR1 9
1832 #define ARM_IWMMXT_wCGR2 10
1833 #define ARM_IWMMXT_wCGR3 11
1834
1835 /* V7M CCR bits */
1836 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1837 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1838 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1839 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1840 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1841 FIELD(V7M_CCR, STKALIGN, 9, 1)
1842 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1843 FIELD(V7M_CCR, DC, 16, 1)
1844 FIELD(V7M_CCR, IC, 17, 1)
1845 FIELD(V7M_CCR, BP, 18, 1)
1846 FIELD(V7M_CCR, LOB, 19, 1)
1847 FIELD(V7M_CCR, TRD, 20, 1)
1848
1849 /* V7M SCR bits */
1850 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1851 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1852 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1853 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1854
1855 /* V7M AIRCR bits */
1856 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1857 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1858 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1859 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1860 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1861 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1862 FIELD(V7M_AIRCR, PRIS, 14, 1)
1863 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1864 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1865
1866 /* V7M CFSR bits for MMFSR */
1867 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1868 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1869 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1870 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1871 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1872 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1873
1874 /* V7M CFSR bits for BFSR */
1875 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1876 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1877 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1878 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1879 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1880 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1881 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1882
1883 /* V7M CFSR bits for UFSR */
1884 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1885 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1886 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1887 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1888 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1889 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1890 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1891
1892 /* V7M CFSR bit masks covering all of the subregister bits */
1893 FIELD(V7M_CFSR, MMFSR, 0, 8)
1894 FIELD(V7M_CFSR, BFSR, 8, 8)
1895 FIELD(V7M_CFSR, UFSR, 16, 16)
1896
1897 /* V7M HFSR bits */
1898 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1899 FIELD(V7M_HFSR, FORCED, 30, 1)
1900 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1901
1902 /* V7M DFSR bits */
1903 FIELD(V7M_DFSR, HALTED, 0, 1)
1904 FIELD(V7M_DFSR, BKPT, 1, 1)
1905 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1906 FIELD(V7M_DFSR, VCATCH, 3, 1)
1907 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1908
1909 /* V7M SFSR bits */
1910 FIELD(V7M_SFSR, INVEP, 0, 1)
1911 FIELD(V7M_SFSR, INVIS, 1, 1)
1912 FIELD(V7M_SFSR, INVER, 2, 1)
1913 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1914 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1915 FIELD(V7M_SFSR, LSPERR, 5, 1)
1916 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1917 FIELD(V7M_SFSR, LSERR, 7, 1)
1918
1919 /* v7M MPU_CTRL bits */
1920 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1921 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1922 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1923
1924 /* v7M CLIDR bits */
1925 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1926 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1927 FIELD(V7M_CLIDR, LOC, 24, 3)
1928 FIELD(V7M_CLIDR, LOUU, 27, 3)
1929 FIELD(V7M_CLIDR, ICB, 30, 2)
1930
1931 FIELD(V7M_CSSELR, IND, 0, 1)
1932 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1933 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1934 * define a mask for this and check that it doesn't permit running off
1935 * the end of the array.
1936 */
1937 FIELD(V7M_CSSELR, INDEX, 0, 4)
1938
1939 /* v7M FPCCR bits */
1940 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1941 FIELD(V7M_FPCCR, USER, 1, 1)
1942 FIELD(V7M_FPCCR, S, 2, 1)
1943 FIELD(V7M_FPCCR, THREAD, 3, 1)
1944 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1945 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1946 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1947 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1948 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1949 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1950 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1951 FIELD(V7M_FPCCR, RES0, 11, 15)
1952 FIELD(V7M_FPCCR, TS, 26, 1)
1953 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1954 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1955 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1956 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1957 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1958 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1959 #define R_V7M_FPCCR_BANKED_MASK \
1960 (R_V7M_FPCCR_LSPACT_MASK | \
1961 R_V7M_FPCCR_USER_MASK | \
1962 R_V7M_FPCCR_THREAD_MASK | \
1963 R_V7M_FPCCR_MMRDY_MASK | \
1964 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1965 R_V7M_FPCCR_UFRDY_MASK | \
1966 R_V7M_FPCCR_ASPEN_MASK)
1967
1968 /* v7M VPR bits */
1969 FIELD(V7M_VPR, P0, 0, 16)
1970 FIELD(V7M_VPR, MASK01, 16, 4)
1971 FIELD(V7M_VPR, MASK23, 20, 4)
1972
1973 /*
1974 * System register ID fields.
1975 */
1976 FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1977 FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1978 FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1979 FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1980 FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1981 FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1982 FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1983 FIELD(CLIDR_EL1, LOUIS, 21, 3)
1984 FIELD(CLIDR_EL1, LOC, 24, 3)
1985 FIELD(CLIDR_EL1, LOUU, 27, 3)
1986 FIELD(CLIDR_EL1, ICB, 30, 3)
1987
1988 /* When FEAT_CCIDX is implemented */
1989 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
1990 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
1991 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
1992
1993 /* When FEAT_CCIDX is not implemented */
1994 FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
1995 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
1996 FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
1997
1998 FIELD(CTR_EL0, IMINLINE, 0, 4)
1999 FIELD(CTR_EL0, L1IP, 14, 2)
2000 FIELD(CTR_EL0, DMINLINE, 16, 4)
2001 FIELD(CTR_EL0, ERG, 20, 4)
2002 FIELD(CTR_EL0, CWG, 24, 4)
2003 FIELD(CTR_EL0, IDC, 28, 1)
2004 FIELD(CTR_EL0, DIC, 29, 1)
2005 FIELD(CTR_EL0, TMINLINE, 32, 6)
2006
2007 FIELD(MIDR_EL1, REVISION, 0, 4)
2008 FIELD(MIDR_EL1, PARTNUM, 4, 12)
2009 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
2010 FIELD(MIDR_EL1, VARIANT, 20, 4)
2011 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
2012
2013 FIELD(ID_ISAR0, SWAP, 0, 4)
2014 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
2015 FIELD(ID_ISAR0, BITFIELD, 8, 4)
2016 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
2017 FIELD(ID_ISAR0, COPROC, 16, 4)
2018 FIELD(ID_ISAR0, DEBUG, 20, 4)
2019 FIELD(ID_ISAR0, DIVIDE, 24, 4)
2020
2021 FIELD(ID_ISAR1, ENDIAN, 0, 4)
2022 FIELD(ID_ISAR1, EXCEPT, 4, 4)
2023 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
2024 FIELD(ID_ISAR1, EXTEND, 12, 4)
2025 FIELD(ID_ISAR1, IFTHEN, 16, 4)
2026 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
2027 FIELD(ID_ISAR1, INTERWORK, 24, 4)
2028 FIELD(ID_ISAR1, JAZELLE, 28, 4)
2029
2030 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
2031 FIELD(ID_ISAR2, MEMHINT, 4, 4)
2032 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
2033 FIELD(ID_ISAR2, MULT, 12, 4)
2034 FIELD(ID_ISAR2, MULTS, 16, 4)
2035 FIELD(ID_ISAR2, MULTU, 20, 4)
2036 FIELD(ID_ISAR2, PSR_AR, 24, 4)
2037 FIELD(ID_ISAR2, REVERSAL, 28, 4)
2038
2039 FIELD(ID_ISAR3, SATURATE, 0, 4)
2040 FIELD(ID_ISAR3, SIMD, 4, 4)
2041 FIELD(ID_ISAR3, SVC, 8, 4)
2042 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2043 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2044 FIELD(ID_ISAR3, T32COPY, 20, 4)
2045 FIELD(ID_ISAR3, TRUENOP, 24, 4)
2046 FIELD(ID_ISAR3, T32EE, 28, 4)
2047
2048 FIELD(ID_ISAR4, UNPRIV, 0, 4)
2049 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2050 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2051 FIELD(ID_ISAR4, SMC, 12, 4)
2052 FIELD(ID_ISAR4, BARRIER, 16, 4)
2053 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2054 FIELD(ID_ISAR4, PSR_M, 24, 4)
2055 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2056
2057 FIELD(ID_ISAR5, SEVL, 0, 4)
2058 FIELD(ID_ISAR5, AES, 4, 4)
2059 FIELD(ID_ISAR5, SHA1, 8, 4)
2060 FIELD(ID_ISAR5, SHA2, 12, 4)
2061 FIELD(ID_ISAR5, CRC32, 16, 4)
2062 FIELD(ID_ISAR5, RDM, 24, 4)
2063 FIELD(ID_ISAR5, VCMA, 28, 4)
2064
2065 FIELD(ID_ISAR6, JSCVT, 0, 4)
2066 FIELD(ID_ISAR6, DP, 4, 4)
2067 FIELD(ID_ISAR6, FHM, 8, 4)
2068 FIELD(ID_ISAR6, SB, 12, 4)
2069 FIELD(ID_ISAR6, SPECRES, 16, 4)
2070 FIELD(ID_ISAR6, BF16, 20, 4)
2071 FIELD(ID_ISAR6, I8MM, 24, 4)
2072
2073 FIELD(ID_MMFR0, VMSA, 0, 4)
2074 FIELD(ID_MMFR0, PMSA, 4, 4)
2075 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2076 FIELD(ID_MMFR0, SHARELVL, 12, 4)
2077 FIELD(ID_MMFR0, TCM, 16, 4)
2078 FIELD(ID_MMFR0, AUXREG, 20, 4)
2079 FIELD(ID_MMFR0, FCSE, 24, 4)
2080 FIELD(ID_MMFR0, INNERSHR, 28, 4)
2081
2082 FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2083 FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2084 FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2085 FIELD(ID_MMFR1, L1UNISW, 12, 4)
2086 FIELD(ID_MMFR1, L1HVD, 16, 4)
2087 FIELD(ID_MMFR1, L1UNI, 20, 4)
2088 FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2089 FIELD(ID_MMFR1, BPRED, 28, 4)
2090
2091 FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2092 FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2093 FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2094 FIELD(ID_MMFR2, HVDTLB, 12, 4)
2095 FIELD(ID_MMFR2, UNITLB, 16, 4)
2096 FIELD(ID_MMFR2, MEMBARR, 20, 4)
2097 FIELD(ID_MMFR2, WFISTALL, 24, 4)
2098 FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2099
2100 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2101 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2102 FIELD(ID_MMFR3, BPMAINT, 8, 4)
2103 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2104 FIELD(ID_MMFR3, PAN, 16, 4)
2105 FIELD(ID_MMFR3, COHWALK, 20, 4)
2106 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2107 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2108
2109 FIELD(ID_MMFR4, SPECSEI, 0, 4)
2110 FIELD(ID_MMFR4, AC2, 4, 4)
2111 FIELD(ID_MMFR4, XNX, 8, 4)
2112 FIELD(ID_MMFR4, CNP, 12, 4)
2113 FIELD(ID_MMFR4, HPDS, 16, 4)
2114 FIELD(ID_MMFR4, LSM, 20, 4)
2115 FIELD(ID_MMFR4, CCIDX, 24, 4)
2116 FIELD(ID_MMFR4, EVT, 28, 4)
2117
2118 FIELD(ID_MMFR5, ETS, 0, 4)
2119 FIELD(ID_MMFR5, NTLBPA, 4, 4)
2120
2121 FIELD(ID_PFR0, STATE0, 0, 4)
2122 FIELD(ID_PFR0, STATE1, 4, 4)
2123 FIELD(ID_PFR0, STATE2, 8, 4)
2124 FIELD(ID_PFR0, STATE3, 12, 4)
2125 FIELD(ID_PFR0, CSV2, 16, 4)
2126 FIELD(ID_PFR0, AMU, 20, 4)
2127 FIELD(ID_PFR0, DIT, 24, 4)
2128 FIELD(ID_PFR0, RAS, 28, 4)
2129
2130 FIELD(ID_PFR1, PROGMOD, 0, 4)
2131 FIELD(ID_PFR1, SECURITY, 4, 4)
2132 FIELD(ID_PFR1, MPROGMOD, 8, 4)
2133 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2134 FIELD(ID_PFR1, GENTIMER, 16, 4)
2135 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2136 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2137 FIELD(ID_PFR1, GIC, 28, 4)
2138
2139 FIELD(ID_PFR2, CSV3, 0, 4)
2140 FIELD(ID_PFR2, SSBS, 4, 4)
2141 FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2142
2143 FIELD(ID_AA64ISAR0, AES, 4, 4)
2144 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2145 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2146 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2147 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
2148 FIELD(ID_AA64ISAR0, TME, 24, 4)
2149 FIELD(ID_AA64ISAR0, RDM, 28, 4)
2150 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2151 FIELD(ID_AA64ISAR0, SM3, 36, 4)
2152 FIELD(ID_AA64ISAR0, SM4, 40, 4)
2153 FIELD(ID_AA64ISAR0, DP, 44, 4)
2154 FIELD(ID_AA64ISAR0, FHM, 48, 4)
2155 FIELD(ID_AA64ISAR0, TS, 52, 4)
2156 FIELD(ID_AA64ISAR0, TLB, 56, 4)
2157 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2158
2159 FIELD(ID_AA64ISAR1, DPB, 0, 4)
2160 FIELD(ID_AA64ISAR1, APA, 4, 4)
2161 FIELD(ID_AA64ISAR1, API, 8, 4)
2162 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2163 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2164 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2165 FIELD(ID_AA64ISAR1, GPA, 24, 4)
2166 FIELD(ID_AA64ISAR1, GPI, 28, 4)
2167 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2168 FIELD(ID_AA64ISAR1, SB, 36, 4)
2169 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
2170 FIELD(ID_AA64ISAR1, BF16, 44, 4)
2171 FIELD(ID_AA64ISAR1, DGH, 48, 4)
2172 FIELD(ID_AA64ISAR1, I8MM, 52, 4)
2173 FIELD(ID_AA64ISAR1, XS, 56, 4)
2174 FIELD(ID_AA64ISAR1, LS64, 60, 4)
2175
2176 FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2177 FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2178 FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2179 FIELD(ID_AA64ISAR2, APA3, 12, 4)
2180 FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2181 FIELD(ID_AA64ISAR2, BC, 20, 4)
2182 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
2183 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)
2184 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)
2185 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
2186 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
2187 FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
2188 FIELD(ID_AA64ISAR2, CSSC, 52, 4)
2189 FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
2190
2191 FIELD(ID_AA64PFR0, EL0, 0, 4)
2192 FIELD(ID_AA64PFR0, EL1, 4, 4)
2193 FIELD(ID_AA64PFR0, EL2, 8, 4)
2194 FIELD(ID_AA64PFR0, EL3, 12, 4)
2195 FIELD(ID_AA64PFR0, FP, 16, 4)
2196 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2197 FIELD(ID_AA64PFR0, GIC, 24, 4)
2198 FIELD(ID_AA64PFR0, RAS, 28, 4)
2199 FIELD(ID_AA64PFR0, SVE, 32, 4)
2200 FIELD(ID_AA64PFR0, SEL2, 36, 4)
2201 FIELD(ID_AA64PFR0, MPAM, 40, 4)
2202 FIELD(ID_AA64PFR0, AMU, 44, 4)
2203 FIELD(ID_AA64PFR0, DIT, 48, 4)
2204 FIELD(ID_AA64PFR0, RME, 52, 4)
2205 FIELD(ID_AA64PFR0, CSV2, 56, 4)
2206 FIELD(ID_AA64PFR0, CSV3, 60, 4)
2207
2208 FIELD(ID_AA64PFR1, BT, 0, 4)
2209 FIELD(ID_AA64PFR1, SSBS, 4, 4)
2210 FIELD(ID_AA64PFR1, MTE, 8, 4)
2211 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2212 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2213 FIELD(ID_AA64PFR1, SME, 24, 4)
2214 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2215 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2216 FIELD(ID_AA64PFR1, NMI, 36, 4)
2217 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)
2218 FIELD(ID_AA64PFR1, GCS, 44, 4)
2219 FIELD(ID_AA64PFR1, THE, 48, 4)
2220 FIELD(ID_AA64PFR1, MTEX, 52, 4)
2221 FIELD(ID_AA64PFR1, DF2, 56, 4)
2222 FIELD(ID_AA64PFR1, PFAR, 60, 4)
2223
2224 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2225 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2226 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2227 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2228 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2229 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2230 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2231 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2232 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2233 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2234 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2235 FIELD(ID_AA64MMFR0, EXS, 44, 4)
2236 FIELD(ID_AA64MMFR0, FGT, 56, 4)
2237 FIELD(ID_AA64MMFR0, ECV, 60, 4)
2238
2239 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2240 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2241 FIELD(ID_AA64MMFR1, VH, 8, 4)
2242 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2243 FIELD(ID_AA64MMFR1, LO, 16, 4)
2244 FIELD(ID_AA64MMFR1, PAN, 20, 4)
2245 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2246 FIELD(ID_AA64MMFR1, XNX, 28, 4)
2247 FIELD(ID_AA64MMFR1, TWED, 32, 4)
2248 FIELD(ID_AA64MMFR1, ETS, 36, 4)
2249 FIELD(ID_AA64MMFR1, HCX, 40, 4)
2250 FIELD(ID_AA64MMFR1, AFP, 44, 4)
2251 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2252 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2253 FIELD(ID_AA64MMFR1, CMOW, 56, 4)
2254 FIELD(ID_AA64MMFR1, ECBHB, 60, 4)
2255
2256 FIELD(ID_AA64MMFR2, CNP, 0, 4)
2257 FIELD(ID_AA64MMFR2, UAO, 4, 4)
2258 FIELD(ID_AA64MMFR2, LSM, 8, 4)
2259 FIELD(ID_AA64MMFR2, IESB, 12, 4)
2260 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2261 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2262 FIELD(ID_AA64MMFR2, NV, 24, 4)
2263 FIELD(ID_AA64MMFR2, ST, 28, 4)
2264 FIELD(ID_AA64MMFR2, AT, 32, 4)
2265 FIELD(ID_AA64MMFR2, IDS, 36, 4)
2266 FIELD(ID_AA64MMFR2, FWB, 40, 4)
2267 FIELD(ID_AA64MMFR2, TTL, 48, 4)
2268 FIELD(ID_AA64MMFR2, BBM, 52, 4)
2269 FIELD(ID_AA64MMFR2, EVT, 56, 4)
2270 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2271
2272 FIELD(ID_AA64MMFR3, TCRX, 0, 4)
2273 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
2274 FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
2275 FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
2276 FIELD(ID_AA64MMFR3, S1POE, 16, 4)
2277 FIELD(ID_AA64MMFR3, S2POE, 20, 4)
2278 FIELD(ID_AA64MMFR3, AIE, 24, 4)
2279 FIELD(ID_AA64MMFR3, MEC, 28, 4)
2280 FIELD(ID_AA64MMFR3, D128, 32, 4)
2281 FIELD(ID_AA64MMFR3, D128_2, 36, 4)
2282 FIELD(ID_AA64MMFR3, SNERR, 40, 4)
2283 FIELD(ID_AA64MMFR3, ANERR, 44, 4)
2284 FIELD(ID_AA64MMFR3, SDERR, 52, 4)
2285 FIELD(ID_AA64MMFR3, ADERR, 56, 4)
2286 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
2287
2288 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2289 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2290 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2291 FIELD(ID_AA64DFR0, BRPS, 12, 4)
2292 FIELD(ID_AA64DFR0, PMSS, 16, 4)
2293 FIELD(ID_AA64DFR0, WRPS, 20, 4)
2294 FIELD(ID_AA64DFR0, SEBEP, 24, 4)
2295 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2296 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2297 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2298 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2299 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
2300 FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2301 FIELD(ID_AA64DFR0, BRBE, 52, 4)
2302 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)
2303 FIELD(ID_AA64DFR0, HPMN0, 60, 4)
2304
2305 FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2306 FIELD(ID_AA64ZFR0, AES, 4, 4)
2307 FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2308 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2309 FIELD(ID_AA64ZFR0, B16B16, 24, 4)
2310 FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2311 FIELD(ID_AA64ZFR0, SM4, 40, 4)
2312 FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2313 FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2314 FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2315
2316 FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2317 FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
2318 FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2319 FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2320 FIELD(ID_AA64SMFR0, I8I32, 36, 4)
2321 FIELD(ID_AA64SMFR0, F16F16, 42, 1)
2322 FIELD(ID_AA64SMFR0, B16B16, 43, 1)
2323 FIELD(ID_AA64SMFR0, I16I32, 44, 4)
2324 FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2325 FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2326 FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2327 FIELD(ID_AA64SMFR0, FA64, 63, 1)
2328
2329 FIELD(ID_DFR0, COPDBG, 0, 4)
2330 FIELD(ID_DFR0, COPSDBG, 4, 4)
2331 FIELD(ID_DFR0, MMAPDBG, 8, 4)
2332 FIELD(ID_DFR0, COPTRC, 12, 4)
2333 FIELD(ID_DFR0, MMAPTRC, 16, 4)
2334 FIELD(ID_DFR0, MPROFDBG, 20, 4)
2335 FIELD(ID_DFR0, PERFMON, 24, 4)
2336 FIELD(ID_DFR0, TRACEFILT, 28, 4)
2337
2338 FIELD(ID_DFR1, MTPMU, 0, 4)
2339 FIELD(ID_DFR1, HPMN0, 4, 4)
2340
2341 FIELD(DBGDIDR, SE_IMP, 12, 1)
2342 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2343 FIELD(DBGDIDR, VERSION, 16, 4)
2344 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2345 FIELD(DBGDIDR, BRPS, 24, 4)
2346 FIELD(DBGDIDR, WRPS, 28, 4)
2347
2348 FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2349 FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2350 FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2351 FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2352 FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2353 FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2354 FIELD(DBGDEVID, AUXREGS, 24, 4)
2355 FIELD(DBGDEVID, CIDMASK, 28, 4)
2356
2357 FIELD(DBGDEVID1, PCSROFFSET, 0, 4)
2358
2359 FIELD(MVFR0, SIMDREG, 0, 4)
2360 FIELD(MVFR0, FPSP, 4, 4)
2361 FIELD(MVFR0, FPDP, 8, 4)
2362 FIELD(MVFR0, FPTRAP, 12, 4)
2363 FIELD(MVFR0, FPDIVIDE, 16, 4)
2364 FIELD(MVFR0, FPSQRT, 20, 4)
2365 FIELD(MVFR0, FPSHVEC, 24, 4)
2366 FIELD(MVFR0, FPROUND, 28, 4)
2367
2368 FIELD(MVFR1, FPFTZ, 0, 4)
2369 FIELD(MVFR1, FPDNAN, 4, 4)
2370 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2371 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2372 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2373 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2374 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2375 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2376 FIELD(MVFR1, FPHP, 24, 4)
2377 FIELD(MVFR1, SIMDFMAC, 28, 4)
2378
2379 FIELD(MVFR2, SIMDMISC, 0, 4)
2380 FIELD(MVFR2, FPMISC, 4, 4)
2381
2382 FIELD(GPCCR, PPS, 0, 3)
2383 FIELD(GPCCR, IRGN, 8, 2)
2384 FIELD(GPCCR, ORGN, 10, 2)
2385 FIELD(GPCCR, SH, 12, 2)
2386 FIELD(GPCCR, PGS, 14, 2)
2387 FIELD(GPCCR, GPC, 16, 1)
2388 FIELD(GPCCR, GPCP, 17, 1)
2389 FIELD(GPCCR, L0GPTSZ, 20, 4)
2390
2391 FIELD(MFAR, FPA, 12, 40)
2392 FIELD(MFAR, NSE, 62, 1)
2393 FIELD(MFAR, NS, 63, 1)
2394
2395 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2396
2397 /* If adding a feature bit which corresponds to a Linux ELF
2398 * HWCAP bit, remember to update the feature-bit-to-hwcap
2399 * mapping in linux-user/elfload.c:get_elf_hwcap().
2400 */
2401 enum arm_features {
2402 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
2403 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
2404 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
2405 ARM_FEATURE_V6,
2406 ARM_FEATURE_V6K,
2407 ARM_FEATURE_V7,
2408 ARM_FEATURE_THUMB2,
2409 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
2410 ARM_FEATURE_NEON,
2411 ARM_FEATURE_M, /* Microcontroller profile. */
2412 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
2413 ARM_FEATURE_THUMB2EE,
2414 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
2415 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2416 ARM_FEATURE_V4T,
2417 ARM_FEATURE_V5,
2418 ARM_FEATURE_STRONGARM,
2419 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2420 ARM_FEATURE_GENERIC_TIMER,
2421 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2422 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2423 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2424 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2425 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
2426 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2427 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
2428 ARM_FEATURE_V8,
2429 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
2430 ARM_FEATURE_CBAR, /* has cp15 CBAR */
2431 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2432 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
2433 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
2434 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
2435 ARM_FEATURE_PMU, /* has PMU support */
2436 ARM_FEATURE_VBAR, /* has cp15 VBAR */
2437 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2438 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2439 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2440 /*
2441 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
2442 * if the board doesn't set a value, instead of 1GHz. It is for backwards
2443 * compatibility and used only with CPU definitions that were already
2444 * in QEMU before we changed the default. It should not be set on any
2445 * CPU types added in future.
2446 */
2447 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
2448 };
2449
arm_feature(CPUARMState * env,int feature)2450 static inline int arm_feature(CPUARMState *env, int feature)
2451 {
2452 return (env->features & (1ULL << feature)) != 0;
2453 }
2454
2455 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2456
2457 /*
2458 * ARM v9 security states.
2459 * The ordering of the enumeration corresponds to the low 2 bits
2460 * of the GPI value, and (except for Root) the concat of NSE:NS.
2461 */
2462
2463 typedef enum ARMSecuritySpace {
2464 ARMSS_Secure = 0,
2465 ARMSS_NonSecure = 1,
2466 ARMSS_Root = 2,
2467 ARMSS_Realm = 3,
2468 } ARMSecuritySpace;
2469
2470 /* Return true if @space is secure, in the pre-v9 sense. */
arm_space_is_secure(ARMSecuritySpace space)2471 static inline bool arm_space_is_secure(ARMSecuritySpace space)
2472 {
2473 return space == ARMSS_Secure || space == ARMSS_Root;
2474 }
2475
2476 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
arm_secure_to_space(bool secure)2477 static inline ARMSecuritySpace arm_secure_to_space(bool secure)
2478 {
2479 return secure ? ARMSS_Secure : ARMSS_NonSecure;
2480 }
2481
2482 #if !defined(CONFIG_USER_ONLY)
2483 /**
2484 * arm_security_space_below_el3:
2485 * @env: cpu context
2486 *
2487 * Return the security space of exception levels below EL3, following
2488 * an exception return to those levels. Unlike arm_security_space,
2489 * this doesn't care about the current EL.
2490 */
2491 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
2492
2493 /**
2494 * arm_is_secure_below_el3:
2495 * @env: cpu context
2496 *
2497 * Return true if exception levels below EL3 are in secure state,
2498 * or would be following an exception return to those levels.
2499 */
arm_is_secure_below_el3(CPUARMState * env)2500 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2501 {
2502 ARMSecuritySpace ss = arm_security_space_below_el3(env);
2503 return ss == ARMSS_Secure;
2504 }
2505
2506 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
arm_is_el3_or_mon(CPUARMState * env)2507 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2508 {
2509 assert(!arm_feature(env, ARM_FEATURE_M));
2510 if (arm_feature(env, ARM_FEATURE_EL3)) {
2511 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2512 /* CPU currently in AArch64 state and EL3 */
2513 return true;
2514 } else if (!is_a64(env) &&
2515 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2516 /* CPU currently in AArch32 state and monitor mode */
2517 return true;
2518 }
2519 }
2520 return false;
2521 }
2522
2523 /**
2524 * arm_security_space:
2525 * @env: cpu context
2526 *
2527 * Return the current security space of the cpu.
2528 */
2529 ARMSecuritySpace arm_security_space(CPUARMState *env);
2530
2531 /**
2532 * arm_is_secure:
2533 * @env: cpu context
2534 *
2535 * Return true if the processor is in secure state.
2536 */
arm_is_secure(CPUARMState * env)2537 static inline bool arm_is_secure(CPUARMState *env)
2538 {
2539 return arm_space_is_secure(arm_security_space(env));
2540 }
2541
2542 /*
2543 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2544 * This corresponds to the pseudocode EL2Enabled().
2545 */
arm_is_el2_enabled_secstate(CPUARMState * env,ARMSecuritySpace space)2546 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2547 ARMSecuritySpace space)
2548 {
2549 assert(space != ARMSS_Root);
2550 return arm_feature(env, ARM_FEATURE_EL2)
2551 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2));
2552 }
2553
arm_is_el2_enabled(CPUARMState * env)2554 static inline bool arm_is_el2_enabled(CPUARMState *env)
2555 {
2556 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env));
2557 }
2558
2559 #else
arm_security_space_below_el3(CPUARMState * env)2560 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
2561 {
2562 return ARMSS_NonSecure;
2563 }
2564
arm_is_secure_below_el3(CPUARMState * env)2565 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2566 {
2567 return false;
2568 }
2569
arm_is_el3_or_mon(CPUARMState * env)2570 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2571 {
2572 return false;
2573 }
2574
arm_security_space(CPUARMState * env)2575 static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
2576 {
2577 return ARMSS_NonSecure;
2578 }
2579
arm_is_secure(CPUARMState * env)2580 static inline bool arm_is_secure(CPUARMState *env)
2581 {
2582 return false;
2583 }
2584
arm_is_el2_enabled_secstate(CPUARMState * env,ARMSecuritySpace space)2585 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2586 ARMSecuritySpace space)
2587 {
2588 return false;
2589 }
2590
arm_is_el2_enabled(CPUARMState * env)2591 static inline bool arm_is_el2_enabled(CPUARMState *env)
2592 {
2593 return false;
2594 }
2595 #endif
2596
2597 /**
2598 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2599 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2600 * "for all purposes other than a direct read or write access of HCR_EL2."
2601 * Not included here is HCR_RW.
2602 */
2603 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space);
2604 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2605 uint64_t arm_hcrx_el2_eff(CPUARMState *env);
2606
2607 /*
2608 * Function for determining whether guest cp register reads and writes should
2609 * access the secure or non-secure bank of a cp register. When EL3 is
2610 * operating in AArch32 state, the NS-bit determines whether the secure
2611 * instance of a cp register should be used. When EL3 is AArch64 (or if
2612 * it doesn't exist at all) then there is no register banking, and all
2613 * accesses are to the non-secure version.
2614 */
2615 bool access_secure_reg(CPUARMState *env);
2616
2617 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2618 uint32_t cur_el, bool secure);
2619
2620 /* Return the highest implemented Exception Level */
arm_highest_el(CPUARMState * env)2621 static inline int arm_highest_el(CPUARMState *env)
2622 {
2623 if (arm_feature(env, ARM_FEATURE_EL3)) {
2624 return 3;
2625 }
2626 if (arm_feature(env, ARM_FEATURE_EL2)) {
2627 return 2;
2628 }
2629 return 1;
2630 }
2631
2632 /* Return true if a v7M CPU is in Handler mode */
arm_v7m_is_handler_mode(CPUARMState * env)2633 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2634 {
2635 return env->v7m.exception != 0;
2636 }
2637
2638 /**
2639 * write_list_to_cpustate
2640 * @cpu: ARMCPU
2641 *
2642 * For each register listed in the ARMCPU cpreg_indexes list, write
2643 * its value from the cpreg_values list into the ARMCPUState structure.
2644 * This updates TCG's working data structures from KVM data or
2645 * from incoming migration state.
2646 *
2647 * Returns: true if all register values were updated correctly,
2648 * false if some register was unknown or could not be written.
2649 * Note that we do not stop early on failure -- we will attempt
2650 * writing all registers in the list.
2651 */
2652 bool write_list_to_cpustate(ARMCPU *cpu);
2653
2654 /**
2655 * write_cpustate_to_list:
2656 * @cpu: ARMCPU
2657 * @kvm_sync: true if this is for syncing back to KVM
2658 *
2659 * For each register listed in the ARMCPU cpreg_indexes list, write
2660 * its value from the ARMCPUState structure into the cpreg_values list.
2661 * This is used to copy info from TCG's working data structures into
2662 * KVM or for outbound migration.
2663 *
2664 * @kvm_sync is true if we are doing this in order to sync the
2665 * register state back to KVM. In this case we will only update
2666 * values in the list if the previous list->cpustate sync actually
2667 * successfully wrote the CPU state. Otherwise we will keep the value
2668 * that is in the list.
2669 *
2670 * Returns: true if all register values were read correctly,
2671 * false if some register was unknown or could not be read.
2672 * Note that we do not stop early on failure -- we will attempt
2673 * reading all registers in the list.
2674 */
2675 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2676
2677 #define ARM_CPUID_TI915T 0x54029152
2678 #define ARM_CPUID_TI925T 0x54029252
2679
2680 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2681
2682 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2683
2684 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2685 *
2686 * If EL3 is 64-bit:
2687 * + NonSecure EL1 & 0 stage 1
2688 * + NonSecure EL1 & 0 stage 2
2689 * + NonSecure EL2
2690 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2691 * + Secure EL1 & 0 stage 1
2692 * + Secure EL1 & 0 stage 2 (FEAT_SEL2)
2693 * + Secure EL2 (FEAT_SEL2)
2694 * + Secure EL2 & 0 (FEAT_SEL2)
2695 * + Realm EL1 & 0 stage 1 (FEAT_RME)
2696 * + Realm EL1 & 0 stage 2 (FEAT_RME)
2697 * + Realm EL2 (FEAT_RME)
2698 * + EL3
2699 * If EL3 is 32-bit:
2700 * + NonSecure PL1 & 0 stage 1
2701 * + NonSecure PL1 & 0 stage 2
2702 * + NonSecure PL2
2703 * + Secure PL1 & 0
2704 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2705 *
2706 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2707 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2708 * because they may differ in access permissions even if the VA->PA map is
2709 * the same
2710 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2711 * translation, which means that we have one mmu_idx that deals with two
2712 * concatenated translation regimes [this sort of combined s1+2 TLB is
2713 * architecturally permitted]
2714 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2715 * handling via the TLB. The only way to do a stage 1 translation without
2716 * the immediate stage 2 translation is via the ATS or AT system insns,
2717 * which can be slow-pathed and always do a page table walk.
2718 * The only use of stage 2 translations is either as part of an s1+2
2719 * lookup or when loading the descriptors during a stage 1 page table walk,
2720 * and in both those cases we don't use the TLB.
2721 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2722 * translation regimes, because they map reasonably well to each other
2723 * and they can't both be active at the same time.
2724 * 5. we want to be able to use the TLB for accesses done as part of a
2725 * stage1 page table walk, rather than having to walk the stage2 page
2726 * table over and over.
2727 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2728 * Never (PAN) bit within PSTATE.
2729 * 7. we fold together most secure and non-secure regimes for A-profile,
2730 * because there are no banked system registers for aarch64, so the
2731 * process of switching between secure and non-secure is
2732 * already heavyweight.
2733 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure,
2734 * because both are in use simultaneously for Secure EL2.
2735 *
2736 * This gives us the following list of cases:
2737 *
2738 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2)
2739 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2)
2740 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN)
2741 * EL0 EL2&0
2742 * EL2 EL2&0
2743 * EL2 EL2&0 +PAN
2744 * EL2 (aka NS PL2)
2745 * EL3 (aka AArch32 S PL1 PL1&0)
2746 * AArch32 S PL0 PL1&0 (we call this EL30_0)
2747 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN)
2748 * Stage2 Secure
2749 * Stage2 NonSecure
2750 * plus one TLB per Physical address space: S, NS, Realm, Root
2751 *
2752 * for a total of 16 different mmu_idx.
2753 *
2754 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2755 * as A profile. They only need to distinguish EL0 and EL1 (and
2756 * EL2 for cores like the Cortex-R52).
2757 *
2758 * M profile CPUs are rather different as they do not have a true MMU.
2759 * They have the following different MMU indexes:
2760 * User
2761 * Privileged
2762 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2763 * Privileged, execution priority negative (ditto)
2764 * If the CPU supports the v8M Security Extension then there are also:
2765 * Secure User
2766 * Secure Privileged
2767 * Secure User, execution priority negative
2768 * Secure Privileged, execution priority negative
2769 *
2770 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2771 * are not quite the same -- different CPU types (most notably M profile
2772 * vs A/R profile) would like to use MMU indexes with different semantics,
2773 * but since we don't ever need to use all of those in a single CPU we
2774 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2775 * modes + total number of M profile MMU modes". The lower bits of
2776 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2777 * the same for any particular CPU.
2778 * Variables of type ARMMUIdx are always full values, and the core
2779 * index values are in variables of type 'int'.
2780 *
2781 * Our enumeration includes at the end some entries which are not "true"
2782 * mmu_idx values in that they don't have corresponding TLBs and are only
2783 * valid for doing slow path page table walks.
2784 *
2785 * The constant names here are patterned after the general style of the names
2786 * of the AT/ATS operations.
2787 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2788 * For M profile we arrange them to have a bit for priv, a bit for negpri
2789 * and a bit for secure.
2790 */
2791 #define ARM_MMU_IDX_A 0x10 /* A profile */
2792 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2793 #define ARM_MMU_IDX_M 0x40 /* M profile */
2794
2795 /* Meanings of the bits for M profile mmu idx values */
2796 #define ARM_MMU_IDX_M_PRIV 0x1
2797 #define ARM_MMU_IDX_M_NEGPRI 0x2
2798 #define ARM_MMU_IDX_M_S 0x4 /* Secure */
2799
2800 #define ARM_MMU_IDX_TYPE_MASK \
2801 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2802 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2803
2804 typedef enum ARMMMUIdx {
2805 /*
2806 * A-profile.
2807 */
2808 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2809 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2810 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2811 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A,
2812 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
2813 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
2814 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
2815 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
2816 ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A,
2817 ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A,
2818
2819 /*
2820 * Used for second stage of an S12 page table walk, or for descriptor
2821 * loads during first stage of an S1 page table walk. Note that both
2822 * are in use simultaneously for SecureEL2: the security state for
2823 * the S2 ptw is selected by the NS bit from the S1 ptw.
2824 */
2825 ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A,
2826 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,
2827
2828 /* TLBs with 1-1 mapping to the physical address spaces. */
2829 ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A,
2830 ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A,
2831 ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A,
2832 ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A,
2833
2834 /*
2835 * These are not allocated TLBs and are used only for AT system
2836 * instructions or for the first stage of an S12 page table walk.
2837 */
2838 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2839 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2840 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2841
2842 /*
2843 * M-profile.
2844 */
2845 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2846 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2847 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2848 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2849 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2850 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2851 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2852 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2853 } ARMMMUIdx;
2854
2855 /*
2856 * Bit macros for the core-mmu-index values for each index,
2857 * for use when calling tlb_flush_by_mmuidx() and friends.
2858 */
2859 #define TO_CORE_BIT(NAME) \
2860 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2861
2862 typedef enum ARMMMUIdxBit {
2863 TO_CORE_BIT(E10_0),
2864 TO_CORE_BIT(E20_0),
2865 TO_CORE_BIT(E10_1),
2866 TO_CORE_BIT(E10_1_PAN),
2867 TO_CORE_BIT(E2),
2868 TO_CORE_BIT(E20_2),
2869 TO_CORE_BIT(E20_2_PAN),
2870 TO_CORE_BIT(E3),
2871 TO_CORE_BIT(E30_0),
2872 TO_CORE_BIT(E30_3_PAN),
2873 TO_CORE_BIT(Stage2),
2874 TO_CORE_BIT(Stage2_S),
2875
2876 TO_CORE_BIT(MUser),
2877 TO_CORE_BIT(MPriv),
2878 TO_CORE_BIT(MUserNegPri),
2879 TO_CORE_BIT(MPrivNegPri),
2880 TO_CORE_BIT(MSUser),
2881 TO_CORE_BIT(MSPriv),
2882 TO_CORE_BIT(MSUserNegPri),
2883 TO_CORE_BIT(MSPrivNegPri),
2884 } ARMMMUIdxBit;
2885
2886 #undef TO_CORE_BIT
2887
2888 #define MMU_USER_IDX 0
2889
2890 /* Indexes used when registering address spaces with cpu_address_space_init */
2891 typedef enum ARMASIdx {
2892 ARMASIdx_NS = 0,
2893 ARMASIdx_S = 1,
2894 ARMASIdx_TagNS = 2,
2895 ARMASIdx_TagS = 3,
2896 } ARMASIdx;
2897
arm_space_to_phys(ARMSecuritySpace space)2898 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
2899 {
2900 /* Assert the relative order of the physical mmu indexes. */
2901 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
2902 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
2903 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
2904 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
2905
2906 return ARMMMUIdx_Phys_S + space;
2907 }
2908
arm_phys_to_space(ARMMMUIdx idx)2909 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
2910 {
2911 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
2912 return idx - ARMMMUIdx_Phys_S;
2913 }
2914
arm_v7m_csselr_razwi(ARMCPU * cpu)2915 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2916 {
2917 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
2918 * CSSELR is RAZ/WI.
2919 */
2920 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2921 }
2922
arm_sctlr_b(CPUARMState * env)2923 static inline bool arm_sctlr_b(CPUARMState *env)
2924 {
2925 return
2926 /* We need not implement SCTLR.ITD in user-mode emulation, so
2927 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2928 * This lets people run BE32 binaries with "-cpu any".
2929 */
2930 #ifndef CONFIG_USER_ONLY
2931 !arm_feature(env, ARM_FEATURE_V7) &&
2932 #endif
2933 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2934 }
2935
2936 uint64_t arm_sctlr(CPUARMState *env, int el);
2937
2938 /*
2939 * We have more than 32-bits worth of state per TB, so we split the data
2940 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
2941 * We collect these two parts in CPUARMTBFlags where they are named
2942 * flags and flags2 respectively.
2943 *
2944 * The flags that are shared between all execution modes, TBFLAG_ANY, are stored
2945 * in flags. The flags that are specific to a given mode are stored in flags2.
2946 * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32.
2947 *
2948 * The bits for 32-bit A-profile and M-profile partially overlap:
2949 *
2950 * 31 23 11 10 0
2951 * +-------------+----------+----------------+
2952 * | | | TBFLAG_A32 |
2953 * | TBFLAG_AM32 | +-----+----------+
2954 * | | |TBFLAG_M32|
2955 * +-------------+----------------+----------+
2956 * 31 23 6 5 0
2957 *
2958 * Unless otherwise noted, these bits are cached in env->hflags.
2959 */
2960 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
2961 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
2962 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
2963 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
2964 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
2965 /* Target EL if we take a floating-point-disabled exception */
2966 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
2967 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
2968 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
2969 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
2970 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
2971 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
2972
2973 /*
2974 * Bit usage when in AArch32 state, both A- and M-profile.
2975 */
2976 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */
2977 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
2978
2979 /*
2980 * Bit usage when in AArch32 state, for A-profile only.
2981 */
2982 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */
2983 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */
2984 /*
2985 * We store the bottom two bits of the CPAR as TB flags and handle
2986 * checks on the other bits at runtime. This shares the same bits as
2987 * VECSTRIDE, which is OK as no XScale CPU has VFP.
2988 * Not cached, because VECLEN+VECSTRIDE are not cached.
2989 */
2990 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
2991 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
2992 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
2993 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
2994 /*
2995 * Indicates whether cp register reads and writes by guest code should access
2996 * the secure or nonsecure bank of banked registers; note that this is not
2997 * the same thing as the current security state of the processor!
2998 */
2999 FIELD(TBFLAG_A32, NS, 10, 1)
3000 /*
3001 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
3002 * This requires an SME trap from AArch32 mode when using NEON.
3003 */
3004 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3005
3006 /*
3007 * Bit usage when in AArch32 state, for M-profile only.
3008 */
3009 /* Handler (ie not Thread) mode */
3010 FIELD(TBFLAG_M32, HANDLER, 0, 1)
3011 /* Whether we should generate stack-limit checks */
3012 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3013 /* Set if FPCCR.LSPACT is set */
3014 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
3015 /* Set if we must create a new FP context */
3016 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
3017 /* Set if FPCCR.S does not match current security state */
3018 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
3019 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
3020 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */
3021 /* Set if in secure mode */
3022 FIELD(TBFLAG_M32, SECURE, 6, 1)
3023
3024 /*
3025 * Bit usage when in AArch64 state
3026 */
3027 FIELD(TBFLAG_A64, TBII, 0, 2)
3028 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3029 /* The current vector length, either NVL or SVL. */
3030 FIELD(TBFLAG_A64, VL, 4, 4)
3031 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3032 FIELD(TBFLAG_A64, BT, 9, 1)
3033 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
3034 FIELD(TBFLAG_A64, TBID, 12, 2)
3035 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3036 FIELD(TBFLAG_A64, ATA, 15, 1)
3037 FIELD(TBFLAG_A64, TCMA, 16, 2)
3038 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3039 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3040 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
3041 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3042 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3043 FIELD(TBFLAG_A64, SVL, 24, 4)
3044 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
3045 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3046 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1)
3047 FIELD(TBFLAG_A64, NAA, 30, 1)
3048 FIELD(TBFLAG_A64, ATA0, 31, 1)
3049 FIELD(TBFLAG_A64, NV, 32, 1)
3050 FIELD(TBFLAG_A64, NV1, 33, 1)
3051 FIELD(TBFLAG_A64, NV2, 34, 1)
3052 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */
3053 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1)
3054 /* Set if FEAT_NV2 RAM accesses are big-endian */
3055 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
3056 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */
3057 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */
3058
3059 /*
3060 * Helpers for using the above. Note that only the A64 accessors use
3061 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags
3062 * word either is or might be 32 bits only.
3063 */
3064 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3065 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3066 #define DP_TBFLAG_A64(DST, WHICH, VAL) \
3067 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL))
3068 #define DP_TBFLAG_A32(DST, WHICH, VAL) \
3069 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3070 #define DP_TBFLAG_M32(DST, WHICH, VAL) \
3071 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3072 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3073 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3074
3075 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3076 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH)
3077 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3078 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3079 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3080
3081 /**
3082 * sve_vq
3083 * @env: the cpu context
3084 *
3085 * Return the VL cached within env->hflags, in units of quadwords.
3086 */
sve_vq(CPUARMState * env)3087 static inline int sve_vq(CPUARMState *env)
3088 {
3089 return EX_TBFLAG_A64(env->hflags, VL) + 1;
3090 }
3091
3092 /**
3093 * sme_vq
3094 * @env: the cpu context
3095 *
3096 * Return the SVL cached within env->hflags, in units of quadwords.
3097 */
sme_vq(CPUARMState * env)3098 static inline int sme_vq(CPUARMState *env)
3099 {
3100 return EX_TBFLAG_A64(env->hflags, SVL) + 1;
3101 }
3102
bswap_code(bool sctlr_b)3103 static inline bool bswap_code(bool sctlr_b)
3104 {
3105 #ifdef CONFIG_USER_ONLY
3106 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.
3107 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
3108 * would also end up as a mixed-endian mode with BE code, LE data.
3109 */
3110 return TARGET_BIG_ENDIAN ^ sctlr_b;
3111 #else
3112 /* All code access in ARM is little endian, and there are no loaders
3113 * doing swaps that need to be reversed
3114 */
3115 return 0;
3116 #endif
3117 }
3118
3119 enum {
3120 QEMU_PSCI_CONDUIT_DISABLED = 0,
3121 QEMU_PSCI_CONDUIT_SMC = 1,
3122 QEMU_PSCI_CONDUIT_HVC = 2,
3123 };
3124
3125 #ifndef CONFIG_USER_ONLY
3126 /* Return the address space index to use for a memory access */
arm_asidx_from_attrs(CPUState * cs,MemTxAttrs attrs)3127 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3128 {
3129 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3130 }
3131
3132 /* Return the AddressSpace to use for a memory access
3133 * (which depends on whether the access is S or NS, and whether
3134 * the board gave us a separate AddressSpace for S accesses).
3135 */
arm_addressspace(CPUState * cs,MemTxAttrs attrs)3136 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3137 {
3138 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3139 }
3140 #endif
3141
3142 /**
3143 * arm_register_pre_el_change_hook:
3144 * Register a hook function which will be called immediately before this
3145 * CPU changes exception level or mode. The hook function will be
3146 * passed a pointer to the ARMCPU and the opaque data pointer passed
3147 * to this function when the hook was registered.
3148 *
3149 * Note that if a pre-change hook is called, any registered post-change hooks
3150 * are guaranteed to subsequently be called.
3151 */
3152 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3153 void *opaque);
3154 /**
3155 * arm_register_el_change_hook:
3156 * Register a hook function which will be called immediately after this
3157 * CPU changes exception level or mode. The hook function will be
3158 * passed a pointer to the ARMCPU and the opaque data pointer passed
3159 * to this function when the hook was registered.
3160 *
3161 * Note that any registered hooks registered here are guaranteed to be called
3162 * if pre-change hooks have been.
3163 */
3164 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3165 *opaque);
3166
3167 /**
3168 * arm_rebuild_hflags:
3169 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3170 */
3171 void arm_rebuild_hflags(CPUARMState *env);
3172
3173 /**
3174 * aa32_vfp_dreg:
3175 * Return a pointer to the Dn register within env in 32-bit mode.
3176 */
aa32_vfp_dreg(CPUARMState * env,unsigned regno)3177 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3178 {
3179 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3180 }
3181
3182 /**
3183 * aa32_vfp_qreg:
3184 * Return a pointer to the Qn register within env in 32-bit mode.
3185 */
aa32_vfp_qreg(CPUARMState * env,unsigned regno)3186 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3187 {
3188 return &env->vfp.zregs[regno].d[0];
3189 }
3190
3191 /**
3192 * aa64_vfp_qreg:
3193 * Return a pointer to the Qn register within env in 64-bit mode.
3194 */
aa64_vfp_qreg(CPUARMState * env,unsigned regno)3195 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3196 {
3197 return &env->vfp.zregs[regno].d[0];
3198 }
3199
3200 /* Shared between translate-sve.c and sve_helper.c. */
3201 extern const uint64_t pred_esz_masks[5];
3202
3203 /*
3204 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3205 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
3206 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR.
3207 */
3208 #define PAGE_BTI PAGE_TARGET_1
3209 #define PAGE_MTE PAGE_TARGET_2
3210 #define PAGE_TARGET_STICKY PAGE_MTE
3211
3212 /* We associate one allocation tag per 16 bytes, the minimum. */
3213 #define LOG2_TAG_GRANULE 4
3214 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
3215
3216 #endif
3217