1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef __IA_CSS_EED1_8_PARAM_H 8 #define __IA_CSS_EED1_8_PARAM_H 9 10 #include <linux/math.h> 11 12 #include "type_support.h" 13 #include "vmem.h" /* needed for VMEM_ARRAY */ 14 15 #include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */ 16 17 /* Configuration parameters: */ 18 19 /* Enable median for false color correction 20 * 0: Do not use median 21 * 1: Use median 22 * Default: 1 23 */ 24 #define EED1_8_FC_ENABLE_MEDIAN 1 25 26 /* Coring Threshold minima 27 * Used in Tint color suppression. 28 * Default: 1 29 */ 30 #define EED1_8_CORINGTHMIN 1 31 32 /* Define size of the state..... TODO: check if this is the correct place */ 33 /* 4 planes : GR, R, B, GB */ 34 #define NUM_PLANES 4 35 36 /* 5 lines state per color plane input_line_state */ 37 #define EED1_8_STATE_INPUT_BUFFER_HEIGHT (5 * NUM_PLANES) 38 39 /* Each plane has width equal to half frame line */ 40 #define EED1_8_STATE_INPUT_BUFFER_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 41 42 /* 1 line state per color plane LD_H state */ 43 #define EED1_8_STATE_LD_H_HEIGHT (1 * NUM_PLANES) 44 #define EED1_8_STATE_LD_H_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 45 46 /* 1 line state per color plane LD_V state */ 47 #define EED1_8_STATE_LD_V_HEIGHT (1 * NUM_PLANES) 48 #define EED1_8_STATE_LD_V_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 49 50 /* 1 line (single plane) state for D_Hr state */ 51 #define EED1_8_STATE_D_HR_HEIGHT 1 52 #define EED1_8_STATE_D_HR_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 53 54 /* 1 line (single plane) state for D_Hb state */ 55 #define EED1_8_STATE_D_HB_HEIGHT 1 56 #define EED1_8_STATE_D_HB_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 57 58 /* 2 lines (single plane) state for D_Vr state */ 59 #define EED1_8_STATE_D_VR_HEIGHT 2 60 #define EED1_8_STATE_D_VR_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 61 62 /* 2 line (single plane) state for D_Vb state */ 63 #define EED1_8_STATE_D_VB_HEIGHT 2 64 #define EED1_8_STATE_D_VB_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 65 66 /* 2 lines state for R and B (= 2 planes) rb_zipped_state */ 67 #define EED1_8_STATE_RB_ZIPPED_HEIGHT (2 * 2) 68 #define EED1_8_STATE_RB_ZIPPED_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 69 70 #if EED1_8_FC_ENABLE_MEDIAN 71 /* 1 full input line (GR-R color line) for Yc state */ 72 #define EED1_8_STATE_YC_HEIGHT 1 73 #define EED1_8_STATE_YC_WIDTH MAX_FRAME_SIMDWIDTH 74 75 /* 1 line state per color plane Cg_state */ 76 #define EED1_8_STATE_CG_HEIGHT (1 * NUM_PLANES) 77 #define EED1_8_STATE_CG_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 78 79 /* 1 line state per color plane Co_state */ 80 #define EED1_8_STATE_CO_HEIGHT (1 * NUM_PLANES) 81 #define EED1_8_STATE_CO_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2) 82 83 /* 1 full input line (GR-R color line) for AbsK state */ 84 #define EED1_8_STATE_ABSK_HEIGHT 1 85 #define EED1_8_STATE_ABSK_WIDTH MAX_FRAME_SIMDWIDTH 86 #endif 87 88 struct eed1_8_vmem_params { 89 VMEM_ARRAY(e_dew_enh_x, ISP_VEC_NELEMS); 90 SVMEM_ARRAY(e_dew_enh_y, ISP_VEC_NELEMS); 91 SVMEM_ARRAY(e_dew_enh_a, ISP_VEC_NELEMS); 92 VMEM_ARRAY(e_dew_enh_f, ISP_VEC_NELEMS); 93 VMEM_ARRAY(chgrinv_x, ISP_VEC_NELEMS); 94 VMEM_ARRAY(chgrinv_a, ISP_VEC_NELEMS); 95 VMEM_ARRAY(chgrinv_b, ISP_VEC_NELEMS); 96 VMEM_ARRAY(chgrinv_c, ISP_VEC_NELEMS); 97 VMEM_ARRAY(fcinv_x, ISP_VEC_NELEMS); 98 VMEM_ARRAY(fcinv_a, ISP_VEC_NELEMS); 99 VMEM_ARRAY(fcinv_b, ISP_VEC_NELEMS); 100 VMEM_ARRAY(fcinv_c, ISP_VEC_NELEMS); 101 VMEM_ARRAY(tcinv_x, ISP_VEC_NELEMS); 102 VMEM_ARRAY(tcinv_a, ISP_VEC_NELEMS); 103 VMEM_ARRAY(tcinv_b, ISP_VEC_NELEMS); 104 VMEM_ARRAY(tcinv_c, ISP_VEC_NELEMS); 105 }; 106 107 /* EED (Edge Enhancing Demosaic) ISP parameters */ 108 struct eed1_8_dmem_params { 109 s32 rbzp_strength; 110 111 s32 fcstrength; 112 s32 fcthres_0; 113 s32 fc_sat_coef; 114 s32 fc_coring_prm; 115 s32 fc_slope; 116 117 s32 aerel_thres0; 118 s32 aerel_gain0; 119 s32 aerel_thres_diff; 120 s32 aerel_gain_diff; 121 122 s32 derel_thres0; 123 s32 derel_gain0; 124 s32 derel_thres_diff; 125 s32 derel_gain_diff; 126 127 s32 coring_pos0; 128 s32 coring_pos_diff; 129 s32 coring_neg0; 130 s32 coring_neg_diff; 131 132 s32 gain_exp; 133 s32 gain_pos0; 134 s32 gain_pos_diff; 135 s32 gain_neg0; 136 s32 gain_neg_diff; 137 138 s32 margin_pos0; 139 s32 margin_pos_diff; 140 s32 margin_neg0; 141 s32 margin_neg_diff; 142 143 s32 e_dew_enh_asr; 144 s32 dedgew_max; 145 }; 146 147 #endif /* __IA_CSS_EED1_8_PARAM_H */ 148