1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
5
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7 *******************************************************************************/
8
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include "common.h"
12 #include "dwmac_dma.h"
13 #include "stmmac.h"
14
15 #define GMAC_HI_REG_AE 0x80000000
16
dwmac_dma_reset(void __iomem * ioaddr)17 int dwmac_dma_reset(void __iomem *ioaddr)
18 {
19 u32 value = readl(ioaddr + DMA_BUS_MODE);
20
21 /* DMA SW reset */
22 value |= DMA_BUS_MODE_SFT_RESET;
23 writel(value, ioaddr + DMA_BUS_MODE);
24
25 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
26 !(value & DMA_BUS_MODE_SFT_RESET),
27 10000, 200000);
28 }
29
30 /* CSR1 enables the transmit DMA to check for new descriptor */
dwmac_enable_dma_transmission(void __iomem * ioaddr,u32 chan)31 void dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan)
32 {
33 writel(1, ioaddr + DMA_CHAN_XMT_POLL_DEMAND(chan));
34 }
35
dwmac_enable_dma_reception(void __iomem * ioaddr,u32 chan)36 void dwmac_enable_dma_reception(void __iomem *ioaddr, u32 chan)
37 {
38 writel(1, ioaddr + DMA_CHAN_RCV_POLL_DEMAND(chan));
39 }
40
dwmac_enable_dma_irq(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan,bool rx,bool tx)41 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
42 u32 chan, bool rx, bool tx)
43 {
44 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
45
46 if (rx)
47 value |= DMA_INTR_DEFAULT_RX;
48 if (tx)
49 value |= DMA_INTR_DEFAULT_TX;
50
51 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
52 }
53
dwmac_disable_dma_irq(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan,bool rx,bool tx)54 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
55 u32 chan, bool rx, bool tx)
56 {
57 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
58
59 if (rx)
60 value &= ~DMA_INTR_DEFAULT_RX;
61 if (tx)
62 value &= ~DMA_INTR_DEFAULT_TX;
63
64 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
65 }
66
dwmac_dma_start_tx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)67 void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
68 u32 chan)
69 {
70 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
71 value |= DMA_CONTROL_ST;
72 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
73 }
74
dwmac_dma_stop_tx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)75 void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
76 {
77 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
78 value &= ~DMA_CONTROL_ST;
79 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
80 }
81
dwmac_dma_start_rx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)82 void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
83 u32 chan)
84 {
85 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
86 value |= DMA_CONTROL_SR;
87 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
88 }
89
dwmac_dma_stop_rx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)90 void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
91 {
92 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
93 value &= ~DMA_CONTROL_SR;
94 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
95 }
96
97 #ifdef DWMAC_DMA_DEBUG
show_tx_process_state(unsigned int status)98 static void show_tx_process_state(unsigned int status)
99 {
100 switch (FIELD_GET(DMA_STATUS_TS_MASK, status)) {
101 case 0:
102 pr_debug("- TX (Stopped): Reset or Stop command\n");
103 break;
104 case 1:
105 pr_debug("- TX (Running): Fetching the Tx desc\n");
106 break;
107 case 2:
108 pr_debug("- TX (Running): Waiting for end of tx\n");
109 break;
110 case 3:
111 pr_debug("- TX (Running): Reading the data "
112 "and queuing the data into the Tx buf\n");
113 break;
114 case 6:
115 pr_debug("- TX (Suspended): Tx Buff Underflow "
116 "or an unavailable Transmit descriptor\n");
117 break;
118 case 7:
119 pr_debug("- TX (Running): Closing Tx descriptor\n");
120 break;
121 default:
122 break;
123 }
124 }
125
show_rx_process_state(unsigned int status)126 static void show_rx_process_state(unsigned int status)
127 {
128 switch (FIELD_GET(DMA_STATUS_RS_MASK, status)) {
129 case 0:
130 pr_debug("- RX (Stopped): Reset or Stop command\n");
131 break;
132 case 1:
133 pr_debug("- RX (Running): Fetching the Rx desc\n");
134 break;
135 case 2:
136 pr_debug("- RX (Running): Checking for end of pkt\n");
137 break;
138 case 3:
139 pr_debug("- RX (Running): Waiting for Rx pkt\n");
140 break;
141 case 4:
142 pr_debug("- RX (Suspended): Unavailable Rx buf\n");
143 break;
144 case 5:
145 pr_debug("- RX (Running): Closing Rx descriptor\n");
146 break;
147 case 6:
148 pr_debug("- RX(Running): Flushing the current frame"
149 " from the Rx buf\n");
150 break;
151 case 7:
152 pr_debug("- RX (Running): Queuing the Rx frame"
153 " from the Rx buf into memory\n");
154 break;
155 default:
156 break;
157 }
158 }
159 #endif
160
dwmac_dma_interrupt(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 chan,u32 dir)161 int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
162 struct stmmac_extra_stats *x, u32 chan, u32 dir)
163 {
164 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats);
165 int ret = 0;
166 /* read the status register (CSR5) */
167 u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
168
169 #ifdef DWMAC_DMA_DEBUG
170 /* Enable it to monitor DMA rx/tx status in case of critical problems */
171 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
172 show_tx_process_state(intr_status);
173 show_rx_process_state(intr_status);
174 #endif
175
176 if (dir == DMA_DIR_RX)
177 intr_status &= DMA_STATUS_MSK_RX;
178 else if (dir == DMA_DIR_TX)
179 intr_status &= DMA_STATUS_MSK_TX;
180
181 /* ABNORMAL interrupts */
182 if (unlikely(intr_status & DMA_STATUS_AIS)) {
183 if (unlikely(intr_status & DMA_STATUS_UNF)) {
184 ret = tx_hard_error_bump_tc;
185 x->tx_undeflow_irq++;
186 }
187 if (unlikely(intr_status & DMA_STATUS_TJT))
188 x->tx_jabber_irq++;
189
190 if (unlikely(intr_status & DMA_STATUS_OVF))
191 x->rx_overflow_irq++;
192
193 if (unlikely(intr_status & DMA_STATUS_RU))
194 x->rx_buf_unav_irq++;
195 if (unlikely(intr_status & DMA_STATUS_RPS))
196 x->rx_process_stopped_irq++;
197 if (unlikely(intr_status & DMA_STATUS_RWT))
198 x->rx_watchdog_irq++;
199 if (unlikely(intr_status & DMA_STATUS_ETI))
200 x->tx_early_irq++;
201 if (unlikely(intr_status & DMA_STATUS_TPS)) {
202 x->tx_process_stopped_irq++;
203 ret = tx_hard_error;
204 }
205 if (unlikely(intr_status & DMA_STATUS_FBI)) {
206 x->fatal_bus_error_irq++;
207 ret = tx_hard_error;
208 }
209 }
210 /* TX/RX NORMAL interrupts */
211 if (likely(intr_status & DMA_STATUS_NIS)) {
212 if (likely(intr_status & DMA_STATUS_RI)) {
213 u32 value = readl(ioaddr + DMA_INTR_ENA);
214 /* to schedule NAPI on real RIE event. */
215 if (likely(value & DMA_INTR_ENA_RIE)) {
216 u64_stats_update_begin(&stats->syncp);
217 u64_stats_inc(&stats->rx_normal_irq_n[chan]);
218 u64_stats_update_end(&stats->syncp);
219 ret |= handle_rx;
220 }
221 }
222 if (likely(intr_status & DMA_STATUS_TI)) {
223 u64_stats_update_begin(&stats->syncp);
224 u64_stats_inc(&stats->tx_normal_irq_n[chan]);
225 u64_stats_update_end(&stats->syncp);
226 ret |= handle_tx;
227 }
228 if (unlikely(intr_status & DMA_STATUS_ERI))
229 x->rx_early_irq++;
230 }
231 /* Optional hardware blocks, interrupts should be disabled */
232 if (unlikely(intr_status &
233 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
234 pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
235
236 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
237 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
238
239 return ret;
240 }
241
dwmac_dma_flush_tx_fifo(void __iomem * ioaddr)242 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
243 {
244 u32 csr6 = readl(ioaddr + DMA_CONTROL);
245 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
246
247 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
248 }
249
stmmac_set_mac_addr(void __iomem * ioaddr,const u8 addr[6],unsigned int high,unsigned int low)250 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
251 unsigned int high, unsigned int low)
252 {
253 u32 data;
254
255 data = (addr[5] << 8) | addr[4];
256 /* For MAC Addr registers we have to set the Address Enable (AE)
257 * bit that has no effect on the High Reg 0 where the bit 31 (MO)
258 * is RO.
259 */
260 writel(data | GMAC_HI_REG_AE, ioaddr + high);
261 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
262 writel(data, ioaddr + low);
263 }
264 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr);
265
266 /* Enable disable MAC RX/TX */
stmmac_set_mac(void __iomem * ioaddr,bool enable)267 void stmmac_set_mac(void __iomem *ioaddr, bool enable)
268 {
269 u32 old_val, value;
270
271 old_val = readl(ioaddr + MAC_CTRL_REG);
272 value = old_val;
273
274 if (enable)
275 value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
276 else
277 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
278
279 if (value != old_val)
280 writel(value, ioaddr + MAC_CTRL_REG);
281 }
282
stmmac_get_mac_addr(void __iomem * ioaddr,unsigned char * addr,unsigned int high,unsigned int low)283 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
284 unsigned int high, unsigned int low)
285 {
286 unsigned int hi_addr, lo_addr;
287
288 /* Read the MAC address from the hardware */
289 hi_addr = readl(ioaddr + high);
290 lo_addr = readl(ioaddr + low);
291
292 /* Extract the MAC address from the high and low words */
293 addr[0] = lo_addr & 0xff;
294 addr[1] = (lo_addr >> 8) & 0xff;
295 addr[2] = (lo_addr >> 16) & 0xff;
296 addr[3] = (lo_addr >> 24) & 0xff;
297 addr[4] = hi_addr & 0xff;
298 addr[5] = (hi_addr >> 8) & 0xff;
299 }
300 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr);
301