1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * core.c - DesignWare HS OTG Controller common routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 */
7
8 /*
9 * The Core code provides basic services for accessing and managing the
10 * DWC_otg hardware. These services are used by both the Host Controller
11 * Driver and the Peripheral Controller Driver.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22 #include <linux/usb.h>
23
24 #include <linux/usb/hcd.h>
25 #include <linux/usb/ch11.h>
26
27 #include "core.h"
28 #include "hcd.h"
29
30 /**
31 * dwc2_backup_global_registers() - Backup global controller registers.
32 * When suspending usb bus, registers needs to be backuped
33 * if controller power is disabled once suspended.
34 *
35 * @hsotg: Programming view of the DWC_otg controller
36 */
dwc2_backup_global_registers(struct dwc2_hsotg * hsotg)37 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
38 {
39 struct dwc2_gregs_backup *gr;
40
41 dev_dbg(hsotg->dev, "%s\n", __func__);
42
43 /* Backup global regs */
44 gr = &hsotg->gr_backup;
45
46 gr->gintsts = dwc2_readl(hsotg, GINTSTS);
47 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
48 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
49 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
50 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
51 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
52 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
53 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
54 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
55 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
56 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
57 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
58
59 gr->valid = true;
60 return 0;
61 }
62
63 /**
64 * dwc2_restore_global_registers() - Restore controller global registers.
65 * When resuming usb bus, device registers needs to be restored
66 * if controller power were disabled.
67 *
68 * @hsotg: Programming view of the DWC_otg controller
69 */
dwc2_restore_global_registers(struct dwc2_hsotg * hsotg)70 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
71 {
72 struct dwc2_gregs_backup *gr;
73
74 dev_dbg(hsotg->dev, "%s\n", __func__);
75
76 /* Restore global regs */
77 gr = &hsotg->gr_backup;
78 if (!gr->valid) {
79 dev_err(hsotg->dev, "%s: no global registers to restore\n",
80 __func__);
81 return -EINVAL;
82 }
83 gr->valid = false;
84
85 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
86 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
87 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
88 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
89 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
90 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
91 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
92 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
93 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
94 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
95 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
96 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
97
98 return 0;
99 }
100
101 /**
102 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
103 *
104 * @hsotg: Programming view of the DWC_otg controller
105 * @rem_wakeup: indicates whether resume is initiated by Reset.
106 * @restore: Controller registers need to be restored
107 */
dwc2_exit_partial_power_down(struct dwc2_hsotg * hsotg,int rem_wakeup,bool restore)108 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
109 bool restore)
110 {
111 struct dwc2_gregs_backup *gr;
112
113 gr = &hsotg->gr_backup;
114
115 /*
116 * Restore host or device regisers with the same mode core enterted
117 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
118 * value of the "gotgctl" register.
119 */
120 if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
121 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
122 restore);
123 else
124 return dwc2_gadget_exit_partial_power_down(hsotg, restore);
125 }
126
127 /**
128 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
129 *
130 * @hsotg: Programming view of the DWC_otg controller
131 */
dwc2_enter_partial_power_down(struct dwc2_hsotg * hsotg)132 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
133 {
134 if (dwc2_is_host_mode(hsotg))
135 return dwc2_host_enter_partial_power_down(hsotg);
136 else
137 return dwc2_gadget_enter_partial_power_down(hsotg);
138 }
139
140 /**
141 * dwc2_restore_essential_regs() - Restore essiential regs of core.
142 *
143 * @hsotg: Programming view of the DWC_otg controller
144 * @rmode: Restore mode, enabled in case of remote-wakeup.
145 * @is_host: Host or device mode.
146 */
dwc2_restore_essential_regs(struct dwc2_hsotg * hsotg,int rmode,int is_host)147 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
148 int is_host)
149 {
150 u32 pcgcctl;
151 struct dwc2_gregs_backup *gr;
152 struct dwc2_dregs_backup *dr;
153 struct dwc2_hregs_backup *hr;
154
155 gr = &hsotg->gr_backup;
156 dr = &hsotg->dr_backup;
157 hr = &hsotg->hr_backup;
158
159 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
160
161 /* Load restore values for [31:14] bits */
162 pcgcctl = (gr->pcgcctl & 0xffffc000);
163 /* If High Speed */
164 if (is_host) {
165 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
166 pcgcctl |= BIT(17);
167 } else {
168 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
169 pcgcctl |= BIT(17);
170 }
171 dwc2_writel(hsotg, pcgcctl, PCGCTL);
172
173 /* Umnask global Interrupt in GAHBCFG and restore it */
174 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
175
176 /* Clear all pending interupts */
177 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
178
179 /* Unmask restore done interrupt */
180 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
181
182 /* Restore GUSBCFG and HCFG/DCFG */
183 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
184
185 if (is_host) {
186 dwc2_writel(hsotg, hr->hcfg, HCFG);
187 if (rmode)
188 pcgcctl |= PCGCTL_RESTOREMODE;
189 dwc2_writel(hsotg, pcgcctl, PCGCTL);
190 udelay(10);
191
192 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
193 dwc2_writel(hsotg, pcgcctl, PCGCTL);
194 udelay(10);
195 } else {
196 dwc2_writel(hsotg, dr->dcfg, DCFG);
197 if (!rmode)
198 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
199 dwc2_writel(hsotg, pcgcctl, PCGCTL);
200 udelay(10);
201
202 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
203 dwc2_writel(hsotg, pcgcctl, PCGCTL);
204 udelay(10);
205 }
206 }
207
208 /**
209 * dwc2_hib_restore_common() - Common part of restore routine.
210 *
211 * @hsotg: Programming view of the DWC_otg controller
212 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
213 * @is_host: Host or device mode.
214 */
dwc2_hib_restore_common(struct dwc2_hsotg * hsotg,int rem_wakeup,int is_host)215 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
216 int is_host)
217 {
218 u32 gpwrdn;
219
220 /* Switch-on voltage to the core */
221 gpwrdn = dwc2_readl(hsotg, GPWRDN);
222 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
223 dwc2_writel(hsotg, gpwrdn, GPWRDN);
224 udelay(10);
225
226 /* Reset core */
227 gpwrdn = dwc2_readl(hsotg, GPWRDN);
228 gpwrdn &= ~GPWRDN_PWRDNRSTN;
229 dwc2_writel(hsotg, gpwrdn, GPWRDN);
230 udelay(10);
231
232 /* Enable restore from PMU */
233 gpwrdn = dwc2_readl(hsotg, GPWRDN);
234 gpwrdn |= GPWRDN_RESTORE;
235 dwc2_writel(hsotg, gpwrdn, GPWRDN);
236 udelay(10);
237
238 /* Disable Power Down Clamp */
239 gpwrdn = dwc2_readl(hsotg, GPWRDN);
240 gpwrdn &= ~GPWRDN_PWRDNCLMP;
241 dwc2_writel(hsotg, gpwrdn, GPWRDN);
242 udelay(50);
243
244 if (!is_host && rem_wakeup)
245 udelay(70);
246
247 /* Deassert reset core */
248 gpwrdn = dwc2_readl(hsotg, GPWRDN);
249 gpwrdn |= GPWRDN_PWRDNRSTN;
250 dwc2_writel(hsotg, gpwrdn, GPWRDN);
251 udelay(10);
252
253 /* Reset ULPI latch */
254 gpwrdn = dwc2_readl(hsotg, GPWRDN);
255 gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
256 dwc2_writel(hsotg, gpwrdn, GPWRDN);
257
258 /* Disable PMU interrupt */
259 gpwrdn = dwc2_readl(hsotg, GPWRDN);
260 gpwrdn &= ~GPWRDN_PMUINTSEL;
261 dwc2_writel(hsotg, gpwrdn, GPWRDN);
262 udelay(10);
263
264 /* Set Restore Essential Regs bit in PCGCCTL register */
265 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
266
267 /*
268 * Wait For Restore_done Interrupt. This mechanism of polling the
269 * interrupt is introduced to avoid any possible race conditions
270 */
271 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
272 20000)) {
273 dev_dbg(hsotg->dev,
274 "%s: Restore Done wasn't generated here\n",
275 __func__);
276 } else {
277 dev_dbg(hsotg->dev, "restore done generated here\n");
278
279 /*
280 * To avoid restore done interrupt storm after restore is
281 * generated clear GINTSTS_RESTOREDONE bit.
282 */
283 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
284 }
285 }
286
287 /**
288 * dwc2_wait_for_mode() - Waits for the controller mode.
289 * @hsotg: Programming view of the DWC_otg controller.
290 * @host_mode: If true, waits for host mode, otherwise device mode.
291 */
dwc2_wait_for_mode(struct dwc2_hsotg * hsotg,bool host_mode)292 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
293 bool host_mode)
294 {
295 ktime_t start;
296 ktime_t end;
297 unsigned int timeout = 110;
298
299 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
300 host_mode ? "host" : "device");
301
302 start = ktime_get();
303
304 while (1) {
305 s64 ms;
306
307 if (dwc2_is_host_mode(hsotg) == host_mode) {
308 dev_vdbg(hsotg->dev, "%s mode set\n",
309 host_mode ? "Host" : "Device");
310 break;
311 }
312
313 end = ktime_get();
314 ms = ktime_to_ms(ktime_sub(end, start));
315
316 if (ms >= (s64)timeout) {
317 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
318 __func__, host_mode ? "host" : "device");
319 break;
320 }
321
322 usleep_range(1000, 2000);
323 }
324 }
325
326 /**
327 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
328 * filter is enabled.
329 *
330 * @hsotg: Programming view of DWC_otg controller
331 */
dwc2_iddig_filter_enabled(struct dwc2_hsotg * hsotg)332 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
333 {
334 u32 gsnpsid;
335 u32 ghwcfg4;
336
337 if (!dwc2_hw_is_otg(hsotg))
338 return false;
339
340 /* Check if core configuration includes the IDDIG filter. */
341 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
342 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
343 return false;
344
345 /*
346 * Check if the IDDIG debounce filter is bypassed. Available
347 * in core version >= 3.10a.
348 */
349 gsnpsid = dwc2_readl(hsotg, GSNPSID);
350 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
351 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
352
353 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
354 return false;
355 }
356
357 return true;
358 }
359
360 /*
361 * dwc2_enter_hibernation() - Common function to enter hibernation.
362 *
363 * @hsotg: Programming view of the DWC_otg controller
364 * @is_host: True if core is in host mode.
365 *
366 * Return: 0 if successful, negative error code otherwise
367 */
dwc2_enter_hibernation(struct dwc2_hsotg * hsotg,int is_host)368 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
369 {
370 if (is_host)
371 return dwc2_host_enter_hibernation(hsotg);
372 else
373 return dwc2_gadget_enter_hibernation(hsotg);
374 }
375
376 /*
377 * dwc2_exit_hibernation() - Common function to exit from hibernation.
378 *
379 * @hsotg: Programming view of the DWC_otg controller
380 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
381 * @reset: Enabled in case of restore with reset.
382 * @is_host: True if core is in host mode.
383 *
384 * Return: 0 if successful, negative error code otherwise
385 */
dwc2_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset,int is_host)386 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
387 int reset, int is_host)
388 {
389 if (is_host)
390 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
391 else
392 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
393 }
394
395 /*
396 * Do core a soft reset of the core. Be careful with this because it
397 * resets all the internal state machines of the core.
398 */
dwc2_core_reset(struct dwc2_hsotg * hsotg,bool skip_wait)399 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
400 {
401 u32 greset;
402 bool wait_for_host_mode = false;
403
404 dev_vdbg(hsotg->dev, "%s()\n", __func__);
405
406 /*
407 * If the current mode is host, either due to the force mode
408 * bit being set (which persists after core reset) or the
409 * connector id pin, a core soft reset will temporarily reset
410 * the mode to device. A delay from the IDDIG debounce filter
411 * will occur before going back to host mode.
412 *
413 * Determine whether we will go back into host mode after a
414 * reset and account for this delay after the reset.
415 */
416 if (dwc2_iddig_filter_enabled(hsotg)) {
417 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
418 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
419
420 if (!(gotgctl & GOTGCTL_CONID_B) ||
421 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
422 wait_for_host_mode = true;
423 }
424 }
425
426 /* Core Soft Reset */
427 greset = dwc2_readl(hsotg, GRSTCTL);
428 greset |= GRSTCTL_CSFTRST;
429 dwc2_writel(hsotg, greset, GRSTCTL);
430
431 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
432 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
433 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
434 GRSTCTL_CSFTRST, 10000)) {
435 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
436 __func__);
437 return -EBUSY;
438 }
439 } else {
440 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
441 GRSTCTL_CSFTRST_DONE, 10000)) {
442 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
443 __func__);
444 return -EBUSY;
445 }
446 greset = dwc2_readl(hsotg, GRSTCTL);
447 greset &= ~GRSTCTL_CSFTRST;
448 greset |= GRSTCTL_CSFTRST_DONE;
449 dwc2_writel(hsotg, greset, GRSTCTL);
450 }
451
452 /*
453 * Switching from device mode to host mode by disconnecting
454 * device cable core enters and exits form hibernation.
455 * However, the fifo map remains not cleared. It results
456 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
457 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
458 * if in host mode we disconnect the micro a to b host
459 * cable. Because core reset occurs.
460 * To avoid the WARNING, fifo_map should be cleared
461 * in dwc2_core_reset() function by taking into account configs.
462 * fifo_map must be cleared only if driver is configured in
463 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
464 * mode.
465 */
466 dwc2_clear_fifo_map(hsotg);
467
468 /* Wait for AHB master IDLE state */
469 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
470 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
471 __func__);
472 return -EBUSY;
473 }
474
475 if (wait_for_host_mode && !skip_wait)
476 dwc2_wait_for_mode(hsotg, true);
477
478 return 0;
479 }
480
481 /**
482 * dwc2_force_mode() - Force the mode of the controller.
483 *
484 * Forcing the mode is needed for two cases:
485 *
486 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
487 * controller to stay in a particular mode regardless of ID pin
488 * changes. We do this once during probe.
489 *
490 * 2) During probe we want to read reset values of the hw
491 * configuration registers that are only available in either host or
492 * device mode. We may need to force the mode if the current mode does
493 * not allow us to access the register in the mode that we want.
494 *
495 * In either case it only makes sense to force the mode if the
496 * controller hardware is OTG capable.
497 *
498 * Checks are done in this function to determine whether doing a force
499 * would be valid or not.
500 *
501 * If a force is done, it requires a IDDIG debounce filter delay if
502 * the filter is configured and enabled. We poll the current mode of
503 * the controller to account for this delay.
504 *
505 * @hsotg: Programming view of DWC_otg controller
506 * @host: Host mode flag
507 */
dwc2_force_mode(struct dwc2_hsotg * hsotg,bool host)508 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
509 {
510 u32 gusbcfg;
511 u32 set;
512 u32 clear;
513
514 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
515
516 /*
517 * Force mode has no effect if the hardware is not OTG.
518 */
519 if (!dwc2_hw_is_otg(hsotg))
520 return;
521
522 /*
523 * If dr_mode is either peripheral or host only, there is no
524 * need to ever force the mode to the opposite mode.
525 */
526 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
527 return;
528
529 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
530 return;
531
532 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
533
534 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
535 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
536
537 gusbcfg &= ~clear;
538 gusbcfg |= set;
539 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
540
541 dwc2_wait_for_mode(hsotg, host);
542 return;
543 }
544
545 /**
546 * dwc2_clear_force_mode() - Clears the force mode bits.
547 *
548 * After clearing the bits, wait up to 100 ms to account for any
549 * potential IDDIG filter delay. We can't know if we expect this delay
550 * or not because the value of the connector ID status is affected by
551 * the force mode. We only need to call this once during probe if
552 * dr_mode == OTG.
553 *
554 * @hsotg: Programming view of DWC_otg controller
555 */
dwc2_clear_force_mode(struct dwc2_hsotg * hsotg)556 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
557 {
558 u32 gusbcfg;
559
560 if (!dwc2_hw_is_otg(hsotg))
561 return;
562
563 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
564
565 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
566 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
567 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
568 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
569
570 if (dwc2_iddig_filter_enabled(hsotg))
571 msleep(100);
572 }
573
574 /*
575 * Sets or clears force mode based on the dr_mode parameter.
576 */
dwc2_force_dr_mode(struct dwc2_hsotg * hsotg)577 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
578 {
579 switch (hsotg->dr_mode) {
580 case USB_DR_MODE_HOST:
581 /*
582 * NOTE: This is required for some rockchip soc based
583 * platforms on their host-only dwc2.
584 */
585 if (!dwc2_hw_is_otg(hsotg))
586 msleep(50);
587
588 break;
589 case USB_DR_MODE_PERIPHERAL:
590 dwc2_force_mode(hsotg, false);
591 break;
592 case USB_DR_MODE_OTG:
593 dwc2_clear_force_mode(hsotg);
594 break;
595 default:
596 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
597 __func__, hsotg->dr_mode);
598 break;
599 }
600 }
601
602 /*
603 * dwc2_enable_acg - enable active clock gating feature
604 */
dwc2_enable_acg(struct dwc2_hsotg * hsotg)605 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
606 {
607 if (hsotg->params.acg_enable) {
608 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
609
610 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
611 pcgcctl1 |= PCGCCTL1_GATEEN;
612 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
613 }
614 }
615
616 /**
617 * dwc2_dump_host_registers() - Prints the host registers
618 *
619 * @hsotg: Programming view of DWC_otg controller
620 *
621 * NOTE: This function will be removed once the peripheral controller code
622 * is integrated and the driver is stable
623 */
dwc2_dump_host_registers(struct dwc2_hsotg * hsotg)624 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
625 {
626 #ifdef DEBUG
627 u32 __iomem *addr;
628 int i;
629
630 dev_dbg(hsotg->dev, "Host Global Registers\n");
631 addr = hsotg->regs + HCFG;
632 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
633 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
634 addr = hsotg->regs + HFIR;
635 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
636 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
637 addr = hsotg->regs + HFNUM;
638 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
639 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
640 addr = hsotg->regs + HPTXSTS;
641 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
642 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
643 addr = hsotg->regs + HAINT;
644 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
645 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
646 addr = hsotg->regs + HAINTMSK;
647 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
648 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
649 if (hsotg->params.dma_desc_enable) {
650 addr = hsotg->regs + HFLBADDR;
651 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
652 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
653 }
654
655 addr = hsotg->regs + HPRT0;
656 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
657 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
658
659 for (i = 0; i < hsotg->params.host_channels; i++) {
660 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
661 addr = hsotg->regs + HCCHAR(i);
662 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
663 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
664 addr = hsotg->regs + HCSPLT(i);
665 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
666 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
667 addr = hsotg->regs + HCINT(i);
668 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
669 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
670 addr = hsotg->regs + HCINTMSK(i);
671 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
672 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
673 addr = hsotg->regs + HCTSIZ(i);
674 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
675 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
676 addr = hsotg->regs + HCDMA(i);
677 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
678 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
679 if (hsotg->params.dma_desc_enable) {
680 addr = hsotg->regs + HCDMAB(i);
681 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
682 (unsigned long)addr, dwc2_readl(hsotg,
683 HCDMAB(i)));
684 }
685 }
686 #endif
687 }
688
689 /**
690 * dwc2_dump_global_registers() - Prints the core global registers
691 *
692 * @hsotg: Programming view of DWC_otg controller
693 *
694 * NOTE: This function will be removed once the peripheral controller code
695 * is integrated and the driver is stable
696 */
dwc2_dump_global_registers(struct dwc2_hsotg * hsotg)697 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
698 {
699 #ifdef DEBUG
700 u32 __iomem *addr;
701
702 dev_dbg(hsotg->dev, "Core Global Registers\n");
703 addr = hsotg->regs + GOTGCTL;
704 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
705 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
706 addr = hsotg->regs + GOTGINT;
707 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
708 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
709 addr = hsotg->regs + GAHBCFG;
710 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
711 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
712 addr = hsotg->regs + GUSBCFG;
713 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
714 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
715 addr = hsotg->regs + GRSTCTL;
716 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
717 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
718 addr = hsotg->regs + GINTSTS;
719 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
720 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
721 addr = hsotg->regs + GINTMSK;
722 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
723 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
724 addr = hsotg->regs + GRXSTSR;
725 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
726 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
727 addr = hsotg->regs + GRXFSIZ;
728 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
729 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
730 addr = hsotg->regs + GNPTXFSIZ;
731 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
732 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
733 addr = hsotg->regs + GNPTXSTS;
734 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
735 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
736 addr = hsotg->regs + GI2CCTL;
737 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
738 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
739 addr = hsotg->regs + GPVNDCTL;
740 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
741 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
742 addr = hsotg->regs + GGPIO;
743 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
744 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
745 addr = hsotg->regs + GUID;
746 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
747 (unsigned long)addr, dwc2_readl(hsotg, GUID));
748 addr = hsotg->regs + GSNPSID;
749 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
750 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
751 addr = hsotg->regs + GHWCFG1;
752 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
753 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
754 addr = hsotg->regs + GHWCFG2;
755 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
756 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
757 addr = hsotg->regs + GHWCFG3;
758 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
759 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
760 addr = hsotg->regs + GHWCFG4;
761 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
762 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
763 addr = hsotg->regs + GLPMCFG;
764 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
765 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
766 addr = hsotg->regs + GPWRDN;
767 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
768 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
769 addr = hsotg->regs + GDFIFOCFG;
770 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
771 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
772 addr = hsotg->regs + HPTXFSIZ;
773 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
774 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
775
776 addr = hsotg->regs + PCGCTL;
777 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
778 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
779 #endif
780 }
781
782 /**
783 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
784 *
785 * @hsotg: Programming view of DWC_otg controller
786 * @num: Tx FIFO to flush
787 */
dwc2_flush_tx_fifo(struct dwc2_hsotg * hsotg,const int num)788 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
789 {
790 u32 greset;
791
792 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
793
794 /* Wait for AHB master IDLE state */
795 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
796 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
797 __func__);
798
799 greset = GRSTCTL_TXFFLSH;
800 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
801 dwc2_writel(hsotg, greset, GRSTCTL);
802
803 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
804 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
805 __func__);
806
807 /* Wait for at least 3 PHY Clocks */
808 udelay(1);
809 }
810
811 /**
812 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
813 *
814 * @hsotg: Programming view of DWC_otg controller
815 */
dwc2_flush_rx_fifo(struct dwc2_hsotg * hsotg)816 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
817 {
818 u32 greset;
819
820 dev_vdbg(hsotg->dev, "%s()\n", __func__);
821
822 /* Wait for AHB master IDLE state */
823 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
824 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
825 __func__);
826
827 greset = GRSTCTL_RXFFLSH;
828 dwc2_writel(hsotg, greset, GRSTCTL);
829
830 /* Wait for RxFIFO flush done */
831 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
832 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
833 __func__);
834
835 /* Wait for at least 3 PHY Clocks */
836 udelay(1);
837 }
838
dwc2_is_controller_alive(struct dwc2_hsotg * hsotg)839 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
840 {
841 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
842 return false;
843 else
844 return true;
845 }
846
847 /**
848 * dwc2_enable_global_interrupts() - Enables the controller's Global
849 * Interrupt in the AHB Config register
850 *
851 * @hsotg: Programming view of DWC_otg controller
852 */
dwc2_enable_global_interrupts(struct dwc2_hsotg * hsotg)853 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
854 {
855 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
856
857 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
858 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
859 }
860
861 /**
862 * dwc2_disable_global_interrupts() - Disables the controller's Global
863 * Interrupt in the AHB Config register
864 *
865 * @hsotg: Programming view of DWC_otg controller
866 */
dwc2_disable_global_interrupts(struct dwc2_hsotg * hsotg)867 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
868 {
869 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
870
871 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
872 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
873 }
874
875 /* Returns the controller's GHWCFG2.OTG_MODE. */
dwc2_op_mode(struct dwc2_hsotg * hsotg)876 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
877 {
878 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
879
880 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
881 GHWCFG2_OP_MODE_SHIFT;
882 }
883
884 /* Returns true if the controller is capable of DRD. */
dwc2_hw_is_otg(struct dwc2_hsotg * hsotg)885 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
886 {
887 unsigned int op_mode = dwc2_op_mode(hsotg);
888
889 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
890 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
891 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
892 }
893
894 /* Returns true if the controller is host-only. */
dwc2_hw_is_host(struct dwc2_hsotg * hsotg)895 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
896 {
897 unsigned int op_mode = dwc2_op_mode(hsotg);
898
899 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
900 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
901 }
902
903 /* Returns true if the controller is device-only. */
dwc2_hw_is_device(struct dwc2_hsotg * hsotg)904 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
905 {
906 unsigned int op_mode = dwc2_op_mode(hsotg);
907
908 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
909 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
910 }
911
912 /**
913 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
914 * @hsotg: Programming view of DWC_otg controller.
915 * @offset: Register's offset where bit/bits must be set.
916 * @mask: Mask of the bit/bits which must be set.
917 * @timeout: Timeout to wait.
918 *
919 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
920 */
dwc2_hsotg_wait_bit_set(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)921 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
922 u32 timeout)
923 {
924 u32 i;
925
926 for (i = 0; i < timeout; i++) {
927 if (dwc2_readl(hsotg, offset) & mask)
928 return 0;
929 udelay(1);
930 }
931
932 return -ETIMEDOUT;
933 }
934
935 /**
936 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
937 * @hsotg: Programming view of DWC_otg controller.
938 * @offset: Register's offset where bit/bits must be set.
939 * @mask: Mask of the bit/bits which must be set.
940 * @timeout: Timeout to wait.
941 *
942 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
943 */
dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)944 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
945 u32 timeout)
946 {
947 u32 i;
948
949 for (i = 0; i < timeout; i++) {
950 if (!(dwc2_readl(hsotg, offset) & mask))
951 return 0;
952 udelay(1);
953 }
954
955 return -ETIMEDOUT;
956 }
957
958 /*
959 * Initializes the FSLSPClkSel field of the HCFG register depending on the
960 * PHY type
961 */
dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg * hsotg)962 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
963 {
964 u32 hcfg, val;
965
966 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
967 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
968 hsotg->params.ulpi_fs_ls) ||
969 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
970 /* Full speed PHY */
971 val = HCFG_FSLSPCLKSEL_48_MHZ;
972 } else {
973 /* High speed PHY running at full speed or high speed */
974 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
975 }
976
977 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
978 hcfg = dwc2_readl(hsotg, HCFG);
979 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
980 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
981 dwc2_writel(hsotg, hcfg, HCFG);
982 }
983
dwc2_set_clock_switch_timer(struct dwc2_hsotg * hsotg)984 static void dwc2_set_clock_switch_timer(struct dwc2_hsotg *hsotg)
985 {
986 u32 grstctl, gsnpsid, val = 0;
987
988 gsnpsid = dwc2_readl(hsotg, GSNPSID);
989
990 /*
991 * Applicable only to HSOTG core v5.00a or higher.
992 * Not applicable to HS/FS IOT devices.
993 */
994 if ((gsnpsid & ~DWC2_CORE_REV_MASK) != DWC2_OTG_ID ||
995 gsnpsid < DWC2_CORE_REV_5_00a)
996 return;
997
998 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI &&
999 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) ||
1000 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1001 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) ||
1002 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED &&
1003 hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED)) {
1004 val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_DIS;
1005 }
1006
1007 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW &&
1008 hsotg->hw_params.hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED &&
1009 hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) {
1010 val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_147;
1011 }
1012
1013 grstctl = dwc2_readl(hsotg, GRSTCTL);
1014 grstctl &= ~GRSTCTL_CLOCK_SWITH_TIMER_MASK;
1015 grstctl |= GRSTCTL_CLOCK_SWITH_TIMER(val);
1016 dwc2_writel(hsotg, grstctl, GRSTCTL);
1017 }
1018
dwc2_fs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1019 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1020 {
1021 u32 usbcfg, ggpio, i2cctl;
1022 int retval = 0;
1023
1024 /*
1025 * core_init() is now called on every switch so only call the
1026 * following for the first time through
1027 */
1028 if (select_phy) {
1029 dev_dbg(hsotg->dev, "FS PHY selected\n");
1030
1031 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1032 if (!(usbcfg & GUSBCFG_PHYSEL)) {
1033 usbcfg |= GUSBCFG_PHYSEL;
1034 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1035
1036 dwc2_set_clock_switch_timer(hsotg);
1037
1038 /* Reset after a PHY select */
1039 retval = dwc2_core_reset(hsotg, false);
1040
1041 if (retval) {
1042 dev_err(hsotg->dev,
1043 "%s: Reset failed, aborting", __func__);
1044 return retval;
1045 }
1046 }
1047
1048 if (hsotg->params.activate_stm_fs_transceiver) {
1049 ggpio = dwc2_readl(hsotg, GGPIO);
1050 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1051 dev_dbg(hsotg->dev, "Activating transceiver\n");
1052 /*
1053 * STM32F4x9 uses the GGPIO register as general
1054 * core configuration register.
1055 */
1056 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1057 dwc2_writel(hsotg, ggpio, GGPIO);
1058 }
1059 }
1060 }
1061
1062 /*
1063 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1064 * do this on HNP Dev/Host mode switches (done in dev_init and
1065 * host_init).
1066 */
1067 if (dwc2_is_host_mode(hsotg))
1068 dwc2_init_fs_ls_pclk_sel(hsotg);
1069
1070 if (hsotg->params.i2c_enable) {
1071 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1072
1073 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1074 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1075 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1076 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1077
1078 /* Program GI2CCTL.I2CEn */
1079 i2cctl = dwc2_readl(hsotg, GI2CCTL);
1080 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1081 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1082 i2cctl &= ~GI2CCTL_I2CEN;
1083 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1084 i2cctl |= GI2CCTL_I2CEN;
1085 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1086 }
1087
1088 return retval;
1089 }
1090
dwc2_hs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1091 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1092 {
1093 u32 usbcfg, usbcfg_old;
1094 int retval = 0;
1095
1096 if (!select_phy)
1097 return 0;
1098
1099 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1100 usbcfg_old = usbcfg;
1101
1102 /*
1103 * HS PHY parameters. These parameters are preserved during soft reset
1104 * so only program the first time. Do a soft reset immediately after
1105 * setting phyif.
1106 */
1107 switch (hsotg->params.phy_type) {
1108 case DWC2_PHY_TYPE_PARAM_ULPI:
1109 /* ULPI interface */
1110 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1111 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1112 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1113 if (hsotg->params.phy_ulpi_ddr)
1114 usbcfg |= GUSBCFG_DDRSEL;
1115
1116 /* Set external VBUS indicator as needed. */
1117 if (hsotg->params.oc_disable)
1118 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1119 GUSBCFG_INDICATORPASSTHROUGH);
1120 break;
1121 case DWC2_PHY_TYPE_PARAM_UTMI:
1122 /* UTMI+ interface */
1123 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1124 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1125 if (hsotg->params.phy_utmi_width == 16)
1126 usbcfg |= GUSBCFG_PHYIF16;
1127 break;
1128 default:
1129 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1130 break;
1131 }
1132
1133 if (usbcfg != usbcfg_old) {
1134 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1135
1136 /* Reset after setting the PHY parameters */
1137 retval = dwc2_core_reset(hsotg, false);
1138 if (retval) {
1139 dev_err(hsotg->dev,
1140 "%s: Reset failed, aborting", __func__);
1141 return retval;
1142 }
1143 }
1144
1145 return retval;
1146 }
1147
dwc2_set_turnaround_time(struct dwc2_hsotg * hsotg)1148 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1149 {
1150 u32 usbcfg;
1151
1152 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1153 return;
1154
1155 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1156
1157 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1158 if (hsotg->params.phy_utmi_width == 16)
1159 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1160 else
1161 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1162
1163 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1164 }
1165
dwc2_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1166 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1167 {
1168 u32 usbcfg;
1169 u32 otgctl;
1170 int retval = 0;
1171
1172 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1173 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1174 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1175 /* If FS/LS mode with FS/LS PHY */
1176 retval = dwc2_fs_phy_init(hsotg, select_phy);
1177 if (retval)
1178 return retval;
1179 } else {
1180 /* High speed PHY */
1181 retval = dwc2_hs_phy_init(hsotg, select_phy);
1182 if (retval)
1183 return retval;
1184
1185 if (dwc2_is_device_mode(hsotg))
1186 dwc2_set_turnaround_time(hsotg);
1187 }
1188
1189 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1190 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1191 hsotg->params.ulpi_fs_ls) {
1192 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1193 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1194 usbcfg |= GUSBCFG_ULPI_FS_LS;
1195 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1196 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1197 } else {
1198 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1199 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1200 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1201 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1202 }
1203
1204 if (!hsotg->params.activate_ingenic_overcurrent_detection) {
1205 if (dwc2_is_host_mode(hsotg)) {
1206 otgctl = readl(hsotg->regs + GOTGCTL);
1207 otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
1208 writel(otgctl, hsotg->regs + GOTGCTL);
1209 }
1210 }
1211
1212 return retval;
1213 }
1214
1215 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1216 MODULE_AUTHOR("Synopsys, Inc.");
1217 MODULE_LICENSE("Dual BSD/GPL");
1218