1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/align.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma/edma.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/ioport.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/pcie-dwc.h>
21 #include <linux/platform_device.h>
22 #include <linux/sizes.h>
23 #include <linux/types.h>
24
25 #include "../../pci.h"
26 #include "pcie-designware.h"
27
28 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = {
29 [DW_PCIE_DBI_CLK] = "dbi",
30 [DW_PCIE_MSTR_CLK] = "mstr",
31 [DW_PCIE_SLV_CLK] = "slv",
32 };
33
34 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = {
35 [DW_PCIE_PIPE_CLK] = "pipe",
36 [DW_PCIE_CORE_CLK] = "core",
37 [DW_PCIE_AUX_CLK] = "aux",
38 [DW_PCIE_REF_CLK] = "ref",
39 };
40
41 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = {
42 [DW_PCIE_DBI_RST] = "dbi",
43 [DW_PCIE_MSTR_RST] = "mstr",
44 [DW_PCIE_SLV_RST] = "slv",
45 };
46
47 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = {
48 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
49 [DW_PCIE_STICKY_RST] = "sticky",
50 [DW_PCIE_CORE_RST] = "core",
51 [DW_PCIE_PIPE_RST] = "pipe",
52 [DW_PCIE_PHY_RST] = "phy",
53 [DW_PCIE_HOT_RST] = "hot",
54 [DW_PCIE_PWR_RST] = "pwr",
55 };
56
dw_pcie_get_clocks(struct dw_pcie * pci)57 static int dw_pcie_get_clocks(struct dw_pcie *pci)
58 {
59 int i, ret;
60
61 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++)
62 pci->app_clks[i].id = dw_pcie_app_clks[i];
63
64 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++)
65 pci->core_clks[i].id = dw_pcie_core_clks[i];
66
67 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS,
68 pci->app_clks);
69 if (ret)
70 return ret;
71
72 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS,
73 pci->core_clks);
74 }
75
dw_pcie_get_resets(struct dw_pcie * pci)76 static int dw_pcie_get_resets(struct dw_pcie *pci)
77 {
78 int i, ret;
79
80 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++)
81 pci->app_rsts[i].id = dw_pcie_app_rsts[i];
82
83 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++)
84 pci->core_rsts[i].id = dw_pcie_core_rsts[i];
85
86 ret = devm_reset_control_bulk_get_optional_shared(pci->dev,
87 DW_PCIE_NUM_APP_RSTS,
88 pci->app_rsts);
89 if (ret)
90 return ret;
91
92 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev,
93 DW_PCIE_NUM_CORE_RSTS,
94 pci->core_rsts);
95 if (ret)
96 return ret;
97
98 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH);
99 if (IS_ERR(pci->pe_rst))
100 return PTR_ERR(pci->pe_rst);
101
102 return 0;
103 }
104
dw_pcie_get_resources(struct dw_pcie * pci)105 int dw_pcie_get_resources(struct dw_pcie *pci)
106 {
107 struct platform_device *pdev = to_platform_device(pci->dev);
108 struct device_node *np = dev_of_node(pci->dev);
109 struct resource *res;
110 int ret;
111
112 if (!pci->dbi_base) {
113 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
114 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res);
115 if (IS_ERR(pci->dbi_base))
116 return PTR_ERR(pci->dbi_base);
117 pci->dbi_phys_addr = res->start;
118 }
119
120 /* DBI2 is mainly useful for the endpoint controller */
121 if (!pci->dbi_base2) {
122 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
123 if (res) {
124 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res);
125 if (IS_ERR(pci->dbi_base2))
126 return PTR_ERR(pci->dbi_base2);
127 } else {
128 pci->dbi_base2 = pci->dbi_base + SZ_4K;
129 }
130 }
131
132 /* For non-unrolled iATU/eDMA platforms this range will be ignored */
133 if (!pci->atu_base) {
134 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
135 if (res) {
136 pci->atu_size = resource_size(res);
137 pci->atu_base = devm_ioremap_resource(pci->dev, res);
138 if (IS_ERR(pci->atu_base))
139 return PTR_ERR(pci->atu_base);
140 pci->atu_phys_addr = res->start;
141 } else {
142 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
143 }
144 }
145
146 /* Set a default value suitable for at most 8 in and 8 out windows */
147 if (!pci->atu_size)
148 pci->atu_size = SZ_4K;
149
150 /* eDMA region can be mapped to a custom base address */
151 if (!pci->edma.reg_base) {
152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
153 if (res) {
154 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
155 if (IS_ERR(pci->edma.reg_base))
156 return PTR_ERR(pci->edma.reg_base);
157 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
158 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
159 }
160 }
161
162 /* LLDD is supposed to manually switch the clocks and resets state */
163 if (dw_pcie_cap_is(pci, REQ_RES)) {
164 ret = dw_pcie_get_clocks(pci);
165 if (ret)
166 return ret;
167
168 ret = dw_pcie_get_resets(pci);
169 if (ret)
170 return ret;
171 }
172
173 if (pci->max_link_speed < 1)
174 pci->max_link_speed = of_pci_get_max_link_speed(np);
175
176 of_property_read_u32(np, "num-lanes", &pci->num_lanes);
177
178 if (of_property_read_bool(np, "snps,enable-cdm-check"))
179 dw_pcie_cap_set(pci, CDM_CHECK);
180
181 return 0;
182 }
183
dw_pcie_version_detect(struct dw_pcie * pci)184 void dw_pcie_version_detect(struct dw_pcie *pci)
185 {
186 u32 ver;
187
188 /* The content of the CSR is zero on DWC PCIe older than v4.70a */
189 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER);
190 if (!ver)
191 return;
192
193 if (pci->version && pci->version != ver)
194 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n",
195 pci->version, ver);
196 else
197 pci->version = ver;
198
199 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE);
200
201 if (pci->type && pci->type != ver)
202 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n",
203 pci->type, ver);
204 else
205 pci->type = ver;
206 }
207
208 /*
209 * These interfaces resemble the pci_find_*capability() interfaces, but these
210 * are for configuring host controllers, which are bridges *to* PCI devices but
211 * are not PCI devices themselves.
212 */
__dw_pcie_find_next_cap(struct dw_pcie * pci,u8 cap_ptr,u8 cap)213 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
214 u8 cap)
215 {
216 u8 cap_id, next_cap_ptr;
217 u16 reg;
218
219 if (!cap_ptr)
220 return 0;
221
222 reg = dw_pcie_readw_dbi(pci, cap_ptr);
223 cap_id = (reg & 0x00ff);
224
225 if (cap_id > PCI_CAP_ID_MAX)
226 return 0;
227
228 if (cap_id == cap)
229 return cap_ptr;
230
231 next_cap_ptr = (reg & 0xff00) >> 8;
232 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
233 }
234
dw_pcie_find_capability(struct dw_pcie * pci,u8 cap)235 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
236 {
237 u8 next_cap_ptr;
238 u16 reg;
239
240 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
241 next_cap_ptr = (reg & 0x00ff);
242
243 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
244 }
245 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
246
dw_pcie_find_next_ext_capability(struct dw_pcie * pci,u16 start,u8 cap)247 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
248 u8 cap)
249 {
250 u32 header;
251 int ttl;
252 int pos = PCI_CFG_SPACE_SIZE;
253
254 /* minimum 8 bytes per capability */
255 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
256
257 if (start)
258 pos = start;
259
260 header = dw_pcie_readl_dbi(pci, pos);
261 /*
262 * If we have no capabilities, this is indicated by cap ID,
263 * cap version and next pointer all being 0.
264 */
265 if (header == 0)
266 return 0;
267
268 while (ttl-- > 0) {
269 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
270 return pos;
271
272 pos = PCI_EXT_CAP_NEXT(header);
273 if (pos < PCI_CFG_SPACE_SIZE)
274 break;
275
276 header = dw_pcie_readl_dbi(pci, pos);
277 }
278
279 return 0;
280 }
281
dw_pcie_find_ext_capability(struct dw_pcie * pci,u8 cap)282 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
283 {
284 return dw_pcie_find_next_ext_capability(pci, 0, cap);
285 }
286 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
287
__dw_pcie_find_vsec_capability(struct dw_pcie * pci,u16 vendor_id,u16 vsec_id)288 static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id,
289 u16 vsec_id)
290 {
291 u16 vsec = 0;
292 u32 header;
293
294 if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID))
295 return 0;
296
297 while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec,
298 PCI_EXT_CAP_ID_VNDR))) {
299 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
300 if (PCI_VNDR_HEADER_ID(header) == vsec_id)
301 return vsec;
302 }
303
304 return 0;
305 }
306
dw_pcie_find_vsec_capability(struct dw_pcie * pci,const struct dwc_pcie_vsec_id * vsec_ids)307 static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci,
308 const struct dwc_pcie_vsec_id *vsec_ids)
309 {
310 const struct dwc_pcie_vsec_id *vid;
311 u16 vsec;
312 u32 header;
313
314 for (vid = vsec_ids; vid->vendor_id; vid++) {
315 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id,
316 vid->vsec_id);
317 if (vsec) {
318 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
319 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev)
320 return vsec;
321 }
322 }
323
324 return 0;
325 }
326
dw_pcie_find_rasdes_capability(struct dw_pcie * pci)327 u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci)
328 {
329 return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids);
330 }
331 EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability);
332
dw_pcie_read(void __iomem * addr,int size,u32 * val)333 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
334 {
335 if (!IS_ALIGNED((uintptr_t)addr, size)) {
336 *val = 0;
337 return PCIBIOS_BAD_REGISTER_NUMBER;
338 }
339
340 if (size == 4) {
341 *val = readl(addr);
342 } else if (size == 2) {
343 *val = readw(addr);
344 } else if (size == 1) {
345 *val = readb(addr);
346 } else {
347 *val = 0;
348 return PCIBIOS_BAD_REGISTER_NUMBER;
349 }
350
351 return PCIBIOS_SUCCESSFUL;
352 }
353 EXPORT_SYMBOL_GPL(dw_pcie_read);
354
dw_pcie_write(void __iomem * addr,int size,u32 val)355 int dw_pcie_write(void __iomem *addr, int size, u32 val)
356 {
357 if (!IS_ALIGNED((uintptr_t)addr, size))
358 return PCIBIOS_BAD_REGISTER_NUMBER;
359
360 if (size == 4)
361 writel(val, addr);
362 else if (size == 2)
363 writew(val, addr);
364 else if (size == 1)
365 writeb(val, addr);
366 else
367 return PCIBIOS_BAD_REGISTER_NUMBER;
368
369 return PCIBIOS_SUCCESSFUL;
370 }
371 EXPORT_SYMBOL_GPL(dw_pcie_write);
372
dw_pcie_read_dbi(struct dw_pcie * pci,u32 reg,size_t size)373 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
374 {
375 int ret;
376 u32 val;
377
378 if (pci->ops && pci->ops->read_dbi)
379 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
380
381 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
382 if (ret)
383 dev_err(pci->dev, "Read DBI address failed\n");
384
385 return val;
386 }
387 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
388
dw_pcie_write_dbi(struct dw_pcie * pci,u32 reg,size_t size,u32 val)389 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
390 {
391 int ret;
392
393 if (pci->ops && pci->ops->write_dbi) {
394 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
395 return;
396 }
397
398 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
399 if (ret)
400 dev_err(pci->dev, "Write DBI address failed\n");
401 }
402 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
403
dw_pcie_write_dbi2(struct dw_pcie * pci,u32 reg,size_t size,u32 val)404 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
405 {
406 int ret;
407
408 if (pci->ops && pci->ops->write_dbi2) {
409 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
410 return;
411 }
412
413 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
414 if (ret)
415 dev_err(pci->dev, "write DBI address failed\n");
416 }
417 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2);
418
dw_pcie_select_atu(struct dw_pcie * pci,u32 dir,u32 index)419 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
420 u32 index)
421 {
422 if (dw_pcie_cap_is(pci, IATU_UNROLL))
423 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index);
424
425 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index);
426 return pci->atu_base;
427 }
428
dw_pcie_readl_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg)429 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg)
430 {
431 void __iomem *base;
432 int ret;
433 u32 val;
434
435 base = dw_pcie_select_atu(pci, dir, index);
436
437 if (pci->ops && pci->ops->read_dbi)
438 return pci->ops->read_dbi(pci, base, reg, 4);
439
440 ret = dw_pcie_read(base + reg, 4, &val);
441 if (ret)
442 dev_err(pci->dev, "Read ATU address failed\n");
443
444 return val;
445 }
446
dw_pcie_writel_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg,u32 val)447 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index,
448 u32 reg, u32 val)
449 {
450 void __iomem *base;
451 int ret;
452
453 base = dw_pcie_select_atu(pci, dir, index);
454
455 if (pci->ops && pci->ops->write_dbi) {
456 pci->ops->write_dbi(pci, base, reg, 4, val);
457 return;
458 }
459
460 ret = dw_pcie_write(base + reg, 4, val);
461 if (ret)
462 dev_err(pci->dev, "Write ATU address failed\n");
463 }
464
dw_pcie_readl_atu_ob(struct dw_pcie * pci,u32 index,u32 reg)465 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg)
466 {
467 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg);
468 }
469
dw_pcie_writel_atu_ob(struct dw_pcie * pci,u32 index,u32 reg,u32 val)470 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg,
471 u32 val)
472 {
473 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val);
474 }
475
dw_pcie_enable_ecrc(u32 val)476 static inline u32 dw_pcie_enable_ecrc(u32 val)
477 {
478 /*
479 * DesignWare core version 4.90A has a design issue where the 'TD'
480 * bit in the Control register-1 of the ATU outbound region acts
481 * like an override for the ECRC setting, i.e., the presence of TLP
482 * Digest (ECRC) in the outgoing TLPs is solely determined by this
483 * bit. This is contrary to the PCIe spec which says that the
484 * enablement of the ECRC is solely determined by the AER
485 * registers.
486 *
487 * Because of this, even when the ECRC is enabled through AER
488 * registers, the transactions going through ATU won't have TLP
489 * Digest as there is no way the PCI core AER code could program
490 * the TD bit which is specific to the DesignWare core.
491 *
492 * The best way to handle this scenario is to program the TD bit
493 * always. It affects only the traffic from root port to downstream
494 * devices.
495 *
496 * At this point,
497 * When ECRC is enabled in AER registers, everything works normally
498 * When ECRC is NOT enabled in AER registers, then,
499 * on Root Port:- TLP Digest (DWord size) gets appended to each packet
500 * even through it is not required. Since downstream
501 * TLPs are mostly for configuration accesses and BAR
502 * accesses, they are not in critical path and won't
503 * have much negative effect on the performance.
504 * on End Point:- TLP Digest is received for some/all the packets coming
505 * from the root port. TLP Digest is ignored because,
506 * as per the PCIe Spec r5.0 v1.0 section 2.2.3
507 * "TLP Digest Rules", when an endpoint receives TLP
508 * Digest when its ECRC check functionality is disabled
509 * in AER registers, received TLP Digest is just ignored.
510 * Since there is no issue or error reported either side, best way to
511 * handle the scenario is to program TD bit by default.
512 */
513
514 return val | PCIE_ATU_TD;
515 }
516
dw_pcie_prog_outbound_atu(struct dw_pcie * pci,const struct dw_pcie_ob_atu_cfg * atu)517 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
518 const struct dw_pcie_ob_atu_cfg *atu)
519 {
520 u64 parent_bus_addr = atu->parent_bus_addr;
521 u32 retries, val;
522 u64 limit_addr;
523
524 limit_addr = parent_bus_addr + atu->size - 1;
525
526 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
527 !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
528 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
529 return -EINVAL;
530 }
531
532 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
533 lower_32_bits(parent_bus_addr));
534 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
535 upper_32_bits(parent_bus_addr));
536
537 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
538 lower_32_bits(limit_addr));
539 if (dw_pcie_ver_is_ge(pci, 460A))
540 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
541 upper_32_bits(limit_addr));
542
543 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
544 lower_32_bits(atu->pci_addr));
545 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
546 upper_32_bits(atu->pci_addr));
547
548 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
549 if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
550 dw_pcie_ver_is_ge(pci, 460A))
551 val |= PCIE_ATU_INCREASE_REGION_SIZE;
552 if (dw_pcie_ver_is(pci, 490A))
553 val = dw_pcie_enable_ecrc(val);
554 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
555
556 val = PCIE_ATU_ENABLE;
557 if (atu->type == PCIE_ATU_TYPE_MSG) {
558 /* The data-less messages only for now */
559 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
560 }
561 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
562
563 /*
564 * Make sure ATU enable takes effect before any subsequent config
565 * and I/O accesses.
566 */
567 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
568 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
569 if (val & PCIE_ATU_ENABLE)
570 return 0;
571
572 mdelay(LINK_WAIT_IATU);
573 }
574
575 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
576
577 return -ETIMEDOUT;
578 }
579
dw_pcie_readl_atu_ib(struct dw_pcie * pci,u32 index,u32 reg)580 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
581 {
582 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
583 }
584
dw_pcie_writel_atu_ib(struct dw_pcie * pci,u32 index,u32 reg,u32 val)585 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg,
586 u32 val)
587 {
588 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val);
589 }
590
dw_pcie_prog_inbound_atu(struct dw_pcie * pci,int index,int type,u64 parent_bus_addr,u64 pci_addr,u64 size)591 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
592 u64 parent_bus_addr, u64 pci_addr, u64 size)
593 {
594 u64 limit_addr = pci_addr + size - 1;
595 u32 retries, val;
596
597 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
598 !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
599 !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
600 return -EINVAL;
601 }
602
603 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE,
604 lower_32_bits(pci_addr));
605 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE,
606 upper_32_bits(pci_addr));
607
608 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT,
609 lower_32_bits(limit_addr));
610 if (dw_pcie_ver_is_ge(pci, 460A))
611 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT,
612 upper_32_bits(limit_addr));
613
614 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
615 lower_32_bits(parent_bus_addr));
616 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
617 upper_32_bits(parent_bus_addr));
618
619 val = type;
620 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) &&
621 dw_pcie_ver_is_ge(pci, 460A))
622 val |= PCIE_ATU_INCREASE_REGION_SIZE;
623 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val);
624 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
625
626 /*
627 * Make sure ATU enable takes effect before any subsequent config
628 * and I/O accesses.
629 */
630 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
631 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
632 if (val & PCIE_ATU_ENABLE)
633 return 0;
634
635 mdelay(LINK_WAIT_IATU);
636 }
637
638 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
639
640 return -ETIMEDOUT;
641 }
642
dw_pcie_prog_ep_inbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 parent_bus_addr,u8 bar,size_t size)643 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
644 int type, u64 parent_bus_addr, u8 bar, size_t size)
645 {
646 u32 retries, val;
647
648 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) ||
649 !IS_ALIGNED(parent_bus_addr, size))
650 return -EINVAL;
651
652 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
653 lower_32_bits(parent_bus_addr));
654 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
655 upper_32_bits(parent_bus_addr));
656
657 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type |
658 PCIE_ATU_FUNC_NUM(func_no));
659 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2,
660 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN |
661 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
662
663 /*
664 * Make sure ATU enable takes effect before any subsequent config
665 * and I/O accesses.
666 */
667 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
668 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
669 if (val & PCIE_ATU_ENABLE)
670 return 0;
671
672 mdelay(LINK_WAIT_IATU);
673 }
674
675 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
676
677 return -ETIMEDOUT;
678 }
679
dw_pcie_disable_atu(struct dw_pcie * pci,u32 dir,int index)680 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
681 {
682 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
683 }
684
dw_pcie_wait_for_link(struct dw_pcie * pci)685 int dw_pcie_wait_for_link(struct dw_pcie *pci)
686 {
687 u32 offset, val;
688 int retries;
689
690 /* Check if the link is up or not */
691 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
692 if (dw_pcie_link_up(pci))
693 break;
694
695 msleep(LINK_WAIT_SLEEP_MS);
696 }
697
698 if (retries >= LINK_WAIT_MAX_RETRIES) {
699 dev_info(pci->dev, "Phy link never came up\n");
700 return -ETIMEDOUT;
701 }
702
703 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
704 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
705
706 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
707 FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
708 FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
709
710 return 0;
711 }
712 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
713
dw_pcie_link_up(struct dw_pcie * pci)714 int dw_pcie_link_up(struct dw_pcie *pci)
715 {
716 u32 val;
717
718 if (pci->ops && pci->ops->link_up)
719 return pci->ops->link_up(pci);
720
721 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1);
722 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
723 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
724 }
725 EXPORT_SYMBOL_GPL(dw_pcie_link_up);
726
dw_pcie_upconfig_setup(struct dw_pcie * pci)727 void dw_pcie_upconfig_setup(struct dw_pcie *pci)
728 {
729 u32 val;
730
731 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
732 val |= PORT_MLTI_UPCFG_SUPPORT;
733 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
734 }
735 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
736
dw_pcie_link_set_max_speed(struct dw_pcie * pci)737 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
738 {
739 u32 cap, ctrl2, link_speed;
740 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
741
742 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
743
744 /*
745 * Even if the platform doesn't want to limit the maximum link speed,
746 * just cache the hardware default value so that the vendor drivers can
747 * use it to do any link specific configuration.
748 */
749 if (pci->max_link_speed < 1) {
750 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
751 return;
752 }
753
754 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
755 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
756
757 switch (pcie_link_speed[pci->max_link_speed]) {
758 case PCIE_SPEED_2_5GT:
759 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
760 break;
761 case PCIE_SPEED_5_0GT:
762 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
763 break;
764 case PCIE_SPEED_8_0GT:
765 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
766 break;
767 case PCIE_SPEED_16_0GT:
768 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
769 break;
770 default:
771 /* Use hardware capability */
772 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
773 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
774 break;
775 }
776
777 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
778
779 cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
780 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
781
782 }
783
dw_pcie_link_set_max_link_width(struct dw_pcie * pci,u32 num_lanes)784 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
785 {
786 u32 lnkcap, lwsc, plc;
787 u8 cap;
788
789 if (!num_lanes)
790 return;
791
792 /* Set the number of lanes */
793 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
794 plc &= ~PORT_LINK_FAST_LINK_MODE;
795 plc &= ~PORT_LINK_MODE_MASK;
796
797 /* Set link width speed control register */
798 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
799 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
800 switch (num_lanes) {
801 case 1:
802 plc |= PORT_LINK_MODE_1_LANES;
803 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
804 break;
805 case 2:
806 plc |= PORT_LINK_MODE_2_LANES;
807 lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
808 break;
809 case 4:
810 plc |= PORT_LINK_MODE_4_LANES;
811 lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
812 break;
813 case 8:
814 plc |= PORT_LINK_MODE_8_LANES;
815 lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
816 break;
817 default:
818 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
819 return;
820 }
821 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
822 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
823
824 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
825 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
826 lnkcap &= ~PCI_EXP_LNKCAP_MLW;
827 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
828 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
829 }
830
dw_pcie_iatu_detect(struct dw_pcie * pci)831 void dw_pcie_iatu_detect(struct dw_pcie *pci)
832 {
833 int max_region, ob, ib;
834 u32 val, min, dir;
835 u64 max;
836
837 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
838 if (val == 0xFFFFFFFF) {
839 dw_pcie_cap_set(pci, IATU_UNROLL);
840
841 max_region = min((int)pci->atu_size / 512, 256);
842 } else {
843 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
844 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
845
846 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
847 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
848 }
849
850 for (ob = 0; ob < max_region; ob++) {
851 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000);
852 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET);
853 if (val != 0x11110000)
854 break;
855 }
856
857 for (ib = 0; ib < max_region; ib++) {
858 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000);
859 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET);
860 if (val != 0x11110000)
861 break;
862 }
863
864 if (ob) {
865 dir = PCIE_ATU_REGION_DIR_OB;
866 } else if (ib) {
867 dir = PCIE_ATU_REGION_DIR_IB;
868 } else {
869 dev_err(pci->dev, "No iATU regions found\n");
870 return;
871 }
872
873 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0);
874 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT);
875
876 if (dw_pcie_ver_is_ge(pci, 460A)) {
877 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
878 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
879 } else {
880 max = 0;
881 }
882
883 pci->num_ob_windows = ob;
884 pci->num_ib_windows = ib;
885 pci->region_align = 1 << fls(min);
886 pci->region_limit = (max << 32) | (SZ_4G - 1);
887
888 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
889 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
890 pci->num_ob_windows, pci->num_ib_windows,
891 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
892 }
893
dw_pcie_readl_dma(struct dw_pcie * pci,u32 reg)894 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg)
895 {
896 u32 val = 0;
897 int ret;
898
899 if (pci->ops && pci->ops->read_dbi)
900 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4);
901
902 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val);
903 if (ret)
904 dev_err(pci->dev, "Read DMA address failed\n");
905
906 return val;
907 }
908
dw_pcie_edma_irq_vector(struct device * dev,unsigned int nr)909 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr)
910 {
911 struct platform_device *pdev = to_platform_device(dev);
912 char name[6];
913 int ret;
914
915 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH)
916 return -EINVAL;
917
918 ret = platform_get_irq_byname_optional(pdev, "dma");
919 if (ret > 0)
920 return ret;
921
922 snprintf(name, sizeof(name), "dma%u", nr);
923
924 return platform_get_irq_byname_optional(pdev, name);
925 }
926
927 static struct dw_edma_plat_ops dw_pcie_edma_ops = {
928 .irq_vector = dw_pcie_edma_irq_vector,
929 };
930
dw_pcie_edma_init_data(struct dw_pcie * pci)931 static void dw_pcie_edma_init_data(struct dw_pcie *pci)
932 {
933 pci->edma.dev = pci->dev;
934
935 if (!pci->edma.ops)
936 pci->edma.ops = &dw_pcie_edma_ops;
937
938 pci->edma.flags |= DW_EDMA_CHIP_LOCAL;
939 }
940
dw_pcie_edma_find_mf(struct dw_pcie * pci)941 static int dw_pcie_edma_find_mf(struct dw_pcie *pci)
942 {
943 u32 val;
944
945 /*
946 * Bail out finding the mapping format if it is already set by the glue
947 * driver. Also ensure that the edma.reg_base is pointing to a valid
948 * memory region.
949 */
950 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY)
951 return pci->edma.reg_base ? 0 : -ENODEV;
952
953 /*
954 * Indirect eDMA CSRs access has been completely removed since v5.40a
955 * thus no space is now reserved for the eDMA channels viewport and
956 * former DMA CTRL register is no longer fixed to FFs.
957 */
958 if (dw_pcie_ver_is_ge(pci, 540A))
959 val = 0xFFFFFFFF;
960 else
961 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
962
963 if (val == 0xFFFFFFFF && pci->edma.reg_base) {
964 pci->edma.mf = EDMA_MF_EDMA_UNROLL;
965 } else if (val != 0xFFFFFFFF) {
966 pci->edma.mf = EDMA_MF_EDMA_LEGACY;
967
968 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE;
969 } else {
970 return -ENODEV;
971 }
972
973 return 0;
974 }
975
dw_pcie_edma_find_channels(struct dw_pcie * pci)976 static int dw_pcie_edma_find_channels(struct dw_pcie *pci)
977 {
978 u32 val;
979
980 /*
981 * Autodetect the read/write channels count only for non-HDMA platforms.
982 * HDMA platforms with native CSR mapping doesn't support autodetect,
983 * so the glue drivers should've passed the valid count already. If not,
984 * the below sanity check will catch it.
985 */
986 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) {
987 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
988
989 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
990 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
991 }
992
993 /* Sanity check the channels count if the mapping was incorrect */
994 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH ||
995 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH)
996 return -EINVAL;
997
998 return 0;
999 }
1000
dw_pcie_edma_find_chip(struct dw_pcie * pci)1001 static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
1002 {
1003 int ret;
1004
1005 dw_pcie_edma_init_data(pci);
1006
1007 ret = dw_pcie_edma_find_mf(pci);
1008 if (ret)
1009 return ret;
1010
1011 return dw_pcie_edma_find_channels(pci);
1012 }
1013
dw_pcie_edma_irq_verify(struct dw_pcie * pci)1014 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci)
1015 {
1016 struct platform_device *pdev = to_platform_device(pci->dev);
1017 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt;
1018 char name[15];
1019 int ret;
1020
1021 if (pci->edma.nr_irqs == 1)
1022 return 0;
1023 else if (pci->edma.nr_irqs > 1)
1024 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0;
1025
1026 ret = platform_get_irq_byname_optional(pdev, "dma");
1027 if (ret > 0) {
1028 pci->edma.nr_irqs = 1;
1029 return 0;
1030 }
1031
1032 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) {
1033 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs);
1034
1035 ret = platform_get_irq_byname_optional(pdev, name);
1036 if (ret <= 0)
1037 return -EINVAL;
1038 }
1039
1040 return 0;
1041 }
1042
dw_pcie_edma_ll_alloc(struct dw_pcie * pci)1043 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci)
1044 {
1045 struct dw_edma_region *ll;
1046 dma_addr_t paddr;
1047 int i;
1048
1049 for (i = 0; i < pci->edma.ll_wr_cnt; i++) {
1050 ll = &pci->edma.ll_region_wr[i];
1051 ll->sz = DMA_LLP_MEM_SIZE;
1052 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
1053 &paddr, GFP_KERNEL);
1054 if (!ll->vaddr.mem)
1055 return -ENOMEM;
1056
1057 ll->paddr = paddr;
1058 }
1059
1060 for (i = 0; i < pci->edma.ll_rd_cnt; i++) {
1061 ll = &pci->edma.ll_region_rd[i];
1062 ll->sz = DMA_LLP_MEM_SIZE;
1063 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
1064 &paddr, GFP_KERNEL);
1065 if (!ll->vaddr.mem)
1066 return -ENOMEM;
1067
1068 ll->paddr = paddr;
1069 }
1070
1071 return 0;
1072 }
1073
dw_pcie_edma_detect(struct dw_pcie * pci)1074 int dw_pcie_edma_detect(struct dw_pcie *pci)
1075 {
1076 int ret;
1077
1078 /* Don't fail if no eDMA was found (for the backward compatibility) */
1079 ret = dw_pcie_edma_find_chip(pci);
1080 if (ret)
1081 return 0;
1082
1083 /* Don't fail on the IRQs verification (for the backward compatibility) */
1084 ret = dw_pcie_edma_irq_verify(pci);
1085 if (ret) {
1086 dev_err(pci->dev, "Invalid eDMA IRQs found\n");
1087 return 0;
1088 }
1089
1090 ret = dw_pcie_edma_ll_alloc(pci);
1091 if (ret) {
1092 dev_err(pci->dev, "Couldn't allocate LLP memory\n");
1093 return ret;
1094 }
1095
1096 /* Don't fail if the DW eDMA driver can't find the device */
1097 ret = dw_edma_probe(&pci->edma);
1098 if (ret && ret != -ENODEV) {
1099 dev_err(pci->dev, "Couldn't register eDMA device\n");
1100 return ret;
1101 }
1102
1103 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n",
1104 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F",
1105 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt);
1106
1107 return 0;
1108 }
1109
dw_pcie_edma_remove(struct dw_pcie * pci)1110 void dw_pcie_edma_remove(struct dw_pcie *pci)
1111 {
1112 dw_edma_remove(&pci->edma);
1113 }
1114
dw_pcie_setup(struct dw_pcie * pci)1115 void dw_pcie_setup(struct dw_pcie *pci)
1116 {
1117 u32 val;
1118
1119 dw_pcie_link_set_max_speed(pci);
1120
1121 /* Configure Gen1 N_FTS */
1122 if (pci->n_fts[0]) {
1123 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
1124 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
1125 val |= PORT_AFR_N_FTS(pci->n_fts[0]);
1126 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
1127 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
1128 }
1129
1130 /* Configure Gen2+ N_FTS */
1131 if (pci->n_fts[1]) {
1132 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
1133 val &= ~PORT_LOGIC_N_FTS_MASK;
1134 val |= pci->n_fts[1];
1135 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
1136 }
1137
1138 if (dw_pcie_cap_is(pci, CDM_CHECK)) {
1139 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
1140 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
1141 PCIE_PL_CHK_REG_CHK_REG_START;
1142 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
1143 }
1144
1145 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
1146 val &= ~PORT_LINK_FAST_LINK_MODE;
1147 val |= PORT_LINK_DLL_LINK_EN;
1148 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
1149
1150 dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
1151 }
1152
dw_pcie_parent_bus_offset(struct dw_pcie * pci,const char * reg_name,resource_size_t cpu_phys_addr)1153 resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
1154 const char *reg_name,
1155 resource_size_t cpu_phys_addr)
1156 {
1157 struct device *dev = pci->dev;
1158 struct device_node *np = dev->of_node;
1159 int index;
1160 u64 reg_addr, fixup_addr;
1161 u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr);
1162
1163 /* Look up reg_name address on parent bus */
1164 index = of_property_match_string(np, "reg-names", reg_name);
1165
1166 if (index < 0) {
1167 dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
1168 return 0;
1169 }
1170
1171 of_property_read_reg(np, index, ®_addr, NULL);
1172
1173 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL;
1174 if (fixup) {
1175 fixup_addr = fixup(pci, cpu_phys_addr);
1176 if (reg_addr == fixup_addr) {
1177 dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n",
1178 reg_name, index, reg_addr, fixup_addr,
1179 (unsigned long long) cpu_phys_addr, fixup);
1180 } else {
1181 dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n",
1182 reg_name, index, reg_addr, fixup_addr,
1183 (unsigned long long) cpu_phys_addr);
1184 reg_addr = fixup_addr;
1185 }
1186
1187 return cpu_phys_addr - reg_addr;
1188 }
1189
1190 if (pci->use_parent_dt_ranges) {
1191
1192 /*
1193 * This platform once had a fixup, presumably because it
1194 * translates between CPU and PCI controller addresses.
1195 * Log a note if devicetree didn't describe a translation.
1196 */
1197 if (reg_addr == cpu_phys_addr)
1198 dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n",
1199 reg_name, index, reg_addr,
1200 (unsigned long long) cpu_phys_addr);
1201 } else {
1202 if (reg_addr != cpu_phys_addr) {
1203 dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n",
1204 reg_name, index, reg_addr,
1205 (unsigned long long) cpu_phys_addr);
1206 return 0;
1207 }
1208 }
1209
1210 return cpu_phys_addr - reg_addr;
1211 }
1212