1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * 64-bit pSeries and RS/6000 setup code.
4 *
5 * Copyright (C) 1995 Linus Torvalds
6 * Adapted from 'alpha' version by Gary Thomas
7 * Modified by Cort Dougan (cort@cs.nmt.edu)
8 * Modified by PPC64 Team, IBM Corp
9 */
10
11 /*
12 * bootup setup stuff..
13 */
14
15 #include <linux/cpu.h>
16 #include <linux/errno.h>
17 #include <linux/platform_device.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/mm.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/user.h>
24 #include <linux/tty.h>
25 #include <linux/major.h>
26 #include <linux/interrupt.h>
27 #include <linux/reboot.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/console.h>
31 #include <linux/pci.h>
32 #include <linux/utsname.h>
33 #include <linux/adb.h>
34 #include <linux/export.h>
35 #include <linux/delay.h>
36 #include <linux/irq.h>
37 #include <linux/seq_file.h>
38 #include <linux/root_dev.h>
39 #include <linux/of.h>
40 #include <linux/of_irq.h>
41 #include <linux/of_pci.h>
42 #include <linux/memblock.h>
43 #include <linux/swiotlb.h>
44 #include <linux/seq_buf.h>
45 #include <linux/sched/cputime.h>
46
47 #include <asm/mmu.h>
48 #include <asm/processor.h>
49 #include <asm/io.h>
50 #include <asm/rtas.h>
51 #include <asm/pci-bridge.h>
52 #include <asm/iommu.h>
53 #include <asm/dma.h>
54 #include <asm/machdep.h>
55 #include <asm/irq.h>
56 #include <asm/time.h>
57 #include <asm/nvram.h>
58 #include <asm/pmc.h>
59 #include <asm/xics.h>
60 #include <asm/xive.h>
61 #include <asm/papr-sysparm.h>
62 #include <asm/ppc-pci.h>
63 #include <asm/i8259.h>
64 #include <asm/udbg.h>
65 #include <asm/smp.h>
66 #include <asm/firmware.h>
67 #include <asm/eeh.h>
68 #include <asm/reg.h>
69 #include <asm/plpar_wrappers.h>
70 #include <asm/kexec.h>
71 #include <asm/isa-bridge.h>
72 #include <asm/security_features.h>
73 #include <asm/asm-const.h>
74 #include <asm/idle.h>
75 #include <asm/swiotlb.h>
76 #include <asm/svm.h>
77 #include <asm/dtl.h>
78 #include <asm/hvconsole.h>
79 #include <asm/setup.h>
80
81 #include "pseries.h"
82
83 DEFINE_STATIC_KEY_FALSE(shared_processor);
84 EXPORT_SYMBOL(shared_processor);
85
86 #ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING
87 static bool steal_acc = true;
parse_no_stealacc(char * arg)88 static int __init parse_no_stealacc(char *arg)
89 {
90 steal_acc = false;
91 return 0;
92 }
93
94 early_param("no-steal-acc", parse_no_stealacc);
95 #endif
96
97 int CMO_PrPSP = -1;
98 int CMO_SecPSP = -1;
99 unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K);
100 EXPORT_SYMBOL(CMO_PageSize);
101
102 int fwnmi_active; /* TRUE if an FWNMI handler is present */
103 int ibm_nmi_interlock_token;
104 u32 pseries_security_flavor;
105
pSeries_show_cpuinfo(struct seq_file * m)106 static void pSeries_show_cpuinfo(struct seq_file *m)
107 {
108 struct device_node *root;
109 const char *model = "";
110
111 root = of_find_node_by_path("/");
112 if (root)
113 model = of_get_property(root, "model", NULL);
114 seq_printf(m, "machine\t\t: CHRP %s\n", model);
115 of_node_put(root);
116 if (radix_enabled())
117 seq_printf(m, "MMU\t\t: Radix\n");
118 else
119 seq_printf(m, "MMU\t\t: Hash\n");
120 }
121
122 /* Initialize firmware assisted non-maskable interrupts if
123 * the firmware supports this feature.
124 */
fwnmi_init(void)125 static void __init fwnmi_init(void)
126 {
127 unsigned long system_reset_addr, machine_check_addr;
128 u8 *mce_data_buf;
129 unsigned int i;
130 int nr_cpus = num_possible_cpus();
131 #ifdef CONFIG_PPC_64S_HASH_MMU
132 struct slb_entry *slb_ptr;
133 size_t size;
134 #endif
135 int ibm_nmi_register_token;
136
137 ibm_nmi_register_token = rtas_function_token(RTAS_FN_IBM_NMI_REGISTER);
138 if (ibm_nmi_register_token == RTAS_UNKNOWN_SERVICE)
139 return;
140
141 ibm_nmi_interlock_token = rtas_function_token(RTAS_FN_IBM_NMI_INTERLOCK);
142 if (WARN_ON(ibm_nmi_interlock_token == RTAS_UNKNOWN_SERVICE))
143 return;
144
145 /* If the kernel's not linked at zero we point the firmware at low
146 * addresses anyway, and use a trampoline to get to the real code. */
147 system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START;
148 machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START;
149
150 if (0 == rtas_call(ibm_nmi_register_token, 2, 1, NULL,
151 system_reset_addr, machine_check_addr))
152 fwnmi_active = 1;
153
154 /*
155 * Allocate a chunk for per cpu buffer to hold rtas errorlog.
156 * It will be used in real mode mce handler, hence it needs to be
157 * below RMA.
158 */
159 mce_data_buf = memblock_alloc_try_nid_raw(RTAS_ERROR_LOG_MAX * nr_cpus,
160 RTAS_ERROR_LOG_MAX, MEMBLOCK_LOW_LIMIT,
161 ppc64_rma_size, NUMA_NO_NODE);
162 if (!mce_data_buf)
163 panic("Failed to allocate %d bytes below %pa for MCE buffer\n",
164 RTAS_ERROR_LOG_MAX * nr_cpus, &ppc64_rma_size);
165
166 for_each_possible_cpu(i) {
167 paca_ptrs[i]->mce_data_buf = mce_data_buf +
168 (RTAS_ERROR_LOG_MAX * i);
169 }
170
171 #ifdef CONFIG_PPC_64S_HASH_MMU
172 if (!radix_enabled()) {
173 /* Allocate per cpu area to save old slb contents during MCE */
174 size = sizeof(struct slb_entry) * mmu_slb_size * nr_cpus;
175 slb_ptr = memblock_alloc_try_nid_raw(size,
176 sizeof(struct slb_entry), MEMBLOCK_LOW_LIMIT,
177 ppc64_rma_size, NUMA_NO_NODE);
178 if (!slb_ptr)
179 panic("Failed to allocate %zu bytes below %pa for slb area\n",
180 size, &ppc64_rma_size);
181
182 for_each_possible_cpu(i)
183 paca_ptrs[i]->mce_faulty_slbs = slb_ptr + (mmu_slb_size * i);
184 }
185 #endif
186 }
187
188 /*
189 * Affix a device for the first timer to the platform bus if
190 * we have firmware support for the H_WATCHDOG hypercall.
191 */
pseries_wdt_init(void)192 static __init int pseries_wdt_init(void)
193 {
194 if (firmware_has_feature(FW_FEATURE_WATCHDOG))
195 platform_device_register_simple("pseries-wdt", 0, NULL, 0);
196 return 0;
197 }
198 machine_subsys_initcall(pseries, pseries_wdt_init);
199
pseries_8259_cascade(struct irq_desc * desc)200 static void pseries_8259_cascade(struct irq_desc *desc)
201 {
202 struct irq_chip *chip = irq_desc_get_chip(desc);
203 unsigned int cascade_irq = i8259_irq();
204
205 if (cascade_irq)
206 generic_handle_irq(cascade_irq);
207
208 chip->irq_eoi(&desc->irq_data);
209 }
210
pseries_setup_i8259_cascade(void)211 static void __init pseries_setup_i8259_cascade(void)
212 {
213 struct device_node *np, *old, *found = NULL;
214 unsigned int cascade;
215 const u32 *addrp;
216 unsigned long intack = 0;
217 int naddr;
218
219 for_each_node_by_type(np, "interrupt-controller") {
220 if (of_device_is_compatible(np, "chrp,iic")) {
221 found = np;
222 break;
223 }
224 }
225
226 if (found == NULL) {
227 printk(KERN_DEBUG "pic: no ISA interrupt controller\n");
228 return;
229 }
230
231 cascade = irq_of_parse_and_map(found, 0);
232 if (!cascade) {
233 printk(KERN_ERR "pic: failed to map cascade interrupt");
234 return;
235 }
236 pr_debug("pic: cascade mapped to irq %d\n", cascade);
237
238 for (old = of_node_get(found); old != NULL ; old = np) {
239 np = of_get_parent(old);
240 of_node_put(old);
241 if (np == NULL)
242 break;
243 if (!of_node_name_eq(np, "pci"))
244 continue;
245 addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
246 if (addrp == NULL)
247 continue;
248 naddr = of_n_addr_cells(np);
249 intack = addrp[naddr-1];
250 if (naddr > 1)
251 intack |= ((unsigned long)addrp[naddr-2]) << 32;
252 }
253 if (intack)
254 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
255 i8259_init(found, intack);
256 of_node_put(found);
257 irq_set_chained_handler(cascade, pseries_8259_cascade);
258 }
259
pseries_init_irq(void)260 static void __init pseries_init_irq(void)
261 {
262 /* Try using a XIVE if available, otherwise use a XICS */
263 if (!xive_spapr_init()) {
264 xics_init();
265 pseries_setup_i8259_cascade();
266 }
267 }
268
pseries_lpar_enable_pmcs(void)269 static void pseries_lpar_enable_pmcs(void)
270 {
271 unsigned long set, reset;
272
273 set = 1UL << 63;
274 reset = 0;
275 plpar_hcall_norets(H_PERFMON, set, reset);
276 }
277
pci_dn_reconfig_notifier(struct notifier_block * nb,unsigned long action,void * data)278 static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
279 {
280 struct of_reconfig_data *rd = data;
281 struct device_node *parent, *np = rd->dn;
282 struct pci_dn *pdn;
283 int err = NOTIFY_OK;
284
285 switch (action) {
286 case OF_RECONFIG_ATTACH_NODE:
287 parent = of_get_parent(np);
288 pdn = parent ? PCI_DN(parent) : NULL;
289 if (pdn)
290 pci_add_device_node_info(pdn->phb, np);
291
292 of_node_put(parent);
293 break;
294 case OF_RECONFIG_DETACH_NODE:
295 pdn = PCI_DN(np);
296 if (pdn)
297 list_del(&pdn->list);
298 break;
299 default:
300 err = NOTIFY_DONE;
301 break;
302 }
303 return err;
304 }
305
306 static struct notifier_block pci_dn_reconfig_nb = {
307 .notifier_call = pci_dn_reconfig_notifier,
308 };
309
310 struct kmem_cache *dtl_cache;
311
312 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
313 /*
314 * Allocate space for the dispatch trace log for all possible cpus
315 * and register the buffers with the hypervisor. This is used for
316 * computing time stolen by the hypervisor.
317 */
alloc_dispatch_logs(void)318 static int alloc_dispatch_logs(void)
319 {
320 if (!firmware_has_feature(FW_FEATURE_SPLPAR))
321 return 0;
322
323 if (!dtl_cache)
324 return 0;
325
326 alloc_dtl_buffers(0);
327
328 /* Register the DTL for the current (boot) cpu */
329 register_dtl_buffer(smp_processor_id());
330
331 return 0;
332 }
333 #else /* !CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
alloc_dispatch_logs(void)334 static inline int alloc_dispatch_logs(void)
335 {
336 return 0;
337 }
338 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
339
alloc_dispatch_log_kmem_cache(void)340 static int alloc_dispatch_log_kmem_cache(void)
341 {
342 void (*ctor)(void *) = get_dtl_cache_ctor();
343
344 dtl_cache = kmem_cache_create_usercopy("dtl", DISPATCH_LOG_BYTES,
345 DISPATCH_LOG_BYTES, 0, 0, DISPATCH_LOG_BYTES, ctor);
346 if (!dtl_cache) {
347 pr_warn("Failed to create dispatch trace log buffer cache\n");
348 pr_warn("Stolen time statistics will be unreliable\n");
349 return 0;
350 }
351
352 return alloc_dispatch_logs();
353 }
354 machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache);
355
356 DEFINE_PER_CPU(u64, idle_spurr_cycles);
357 DEFINE_PER_CPU(u64, idle_entry_purr_snap);
358 DEFINE_PER_CPU(u64, idle_entry_spurr_snap);
pseries_lpar_idle(void)359 static void pseries_lpar_idle(void)
360 {
361 /*
362 * Default handler to go into low thread priority and possibly
363 * low power mode by ceding processor to hypervisor
364 */
365
366 if (!prep_irq_for_idle())
367 return;
368
369 /* Indicate to hypervisor that we are idle. */
370 pseries_idle_prolog();
371
372 /*
373 * Yield the processor to the hypervisor. We return if
374 * an external interrupt occurs (which are driven prior
375 * to returning here) or if a prod occurs from another
376 * processor. When returning here, external interrupts
377 * are enabled.
378 */
379 cede_processor();
380
381 pseries_idle_epilog();
382 }
383
384 static bool pseries_reloc_on_exception_enabled;
385
pseries_reloc_on_exception(void)386 bool pseries_reloc_on_exception(void)
387 {
388 return pseries_reloc_on_exception_enabled;
389 }
390 EXPORT_SYMBOL_GPL(pseries_reloc_on_exception);
391
392 /*
393 * Enable relocation on during exceptions. This has partition wide scope and
394 * may take a while to complete, if it takes longer than one second we will
395 * just give up rather than wasting any more time on this - if that turns out
396 * to ever be a problem in practice we can move this into a kernel thread to
397 * finish off the process later in boot.
398 */
pseries_enable_reloc_on_exc(void)399 bool pseries_enable_reloc_on_exc(void)
400 {
401 long rc;
402 unsigned int delay, total_delay = 0;
403
404 while (1) {
405 rc = enable_reloc_on_exceptions();
406 if (!H_IS_LONG_BUSY(rc)) {
407 if (rc == H_P2) {
408 pr_info("Relocation on exceptions not"
409 " supported\n");
410 return false;
411 } else if (rc != H_SUCCESS) {
412 pr_warn("Unable to enable relocation"
413 " on exceptions: %ld\n", rc);
414 return false;
415 }
416 pseries_reloc_on_exception_enabled = true;
417 return true;
418 }
419
420 delay = get_longbusy_msecs(rc);
421 total_delay += delay;
422 if (total_delay > 1000) {
423 pr_warn("Warning: Giving up waiting to enable "
424 "relocation on exceptions (%u msec)!\n",
425 total_delay);
426 return false;
427 }
428
429 mdelay(delay);
430 }
431 }
432 EXPORT_SYMBOL(pseries_enable_reloc_on_exc);
433
pseries_disable_reloc_on_exc(void)434 void pseries_disable_reloc_on_exc(void)
435 {
436 long rc;
437
438 while (1) {
439 rc = disable_reloc_on_exceptions();
440 if (!H_IS_LONG_BUSY(rc))
441 break;
442 mdelay(get_longbusy_msecs(rc));
443 }
444 if (rc == H_SUCCESS)
445 pseries_reloc_on_exception_enabled = false;
446 else
447 pr_warn("Warning: Failed to disable relocation on exceptions: %ld\n",
448 rc);
449 }
450 EXPORT_SYMBOL(pseries_disable_reloc_on_exc);
451
452 #ifdef __LITTLE_ENDIAN__
pseries_big_endian_exceptions(void)453 void pseries_big_endian_exceptions(void)
454 {
455 long rc;
456
457 while (1) {
458 rc = enable_big_endian_exceptions();
459 if (!H_IS_LONG_BUSY(rc))
460 break;
461 mdelay(get_longbusy_msecs(rc));
462 }
463
464 /*
465 * At this point it is unlikely panic() will get anything
466 * out to the user, since this is called very late in kexec
467 * but at least this will stop us from continuing on further
468 * and creating an even more difficult to debug situation.
469 *
470 * There is a known problem when kdump'ing, if cpus are offline
471 * the above call will fail. Rather than panicking again, keep
472 * going and hope the kdump kernel is also little endian, which
473 * it usually is.
474 */
475 if (rc && !kdump_in_progress())
476 panic("Could not enable big endian exceptions");
477 }
478
pseries_little_endian_exceptions(void)479 void __init pseries_little_endian_exceptions(void)
480 {
481 long rc;
482
483 while (1) {
484 rc = enable_little_endian_exceptions();
485 if (!H_IS_LONG_BUSY(rc))
486 break;
487 mdelay(get_longbusy_msecs(rc));
488 }
489 if (rc) {
490 ppc_md.progress("H_SET_MODE LE exception fail", 0);
491 panic("Could not enable little endian exceptions");
492 }
493 }
494 #endif
495
pSeries_discover_phbs(void)496 static void __init pSeries_discover_phbs(void)
497 {
498 struct device_node *node;
499 struct pci_controller *phb;
500 struct device_node *root = of_find_node_by_path("/");
501
502 for_each_child_of_node(root, node) {
503 if (!of_node_is_type(node, "pci") &&
504 !of_node_is_type(node, "pciex"))
505 continue;
506
507 phb = pcibios_alloc_controller(node);
508 if (!phb)
509 continue;
510 rtas_setup_phb(phb);
511 pci_process_bridge_OF_ranges(phb, node, 0);
512 isa_bridge_find_early(phb);
513 phb->controller_ops = pseries_pci_controller_ops;
514
515 /* create pci_dn's for DT nodes under this PHB */
516 pci_devs_phb_init_dynamic(phb);
517
518 pseries_msi_allocate_domains(phb);
519 }
520
521 of_node_put(root);
522
523 /*
524 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
525 * in chosen.
526 */
527 of_pci_check_probe_only();
528 }
529
init_cpu_char_feature_flags(struct h_cpu_char_result * result)530 static void init_cpu_char_feature_flags(struct h_cpu_char_result *result)
531 {
532 /*
533 * The features below are disabled by default, so we instead look to see
534 * if firmware has *enabled* them, and set them if so.
535 */
536 if (result->character & H_CPU_CHAR_SPEC_BAR_ORI31)
537 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
538
539 if (result->character & H_CPU_CHAR_BCCTRL_SERIALISED)
540 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
541
542 if (result->character & H_CPU_CHAR_L1D_FLUSH_ORI30)
543 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
544
545 if (result->character & H_CPU_CHAR_L1D_FLUSH_TRIG2)
546 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
547
548 if (result->character & H_CPU_CHAR_L1D_THREAD_PRIV)
549 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
550
551 if (result->character & H_CPU_CHAR_COUNT_CACHE_DISABLED)
552 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
553
554 if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST)
555 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
556
557 if (result->character & H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST)
558 security_ftr_set(SEC_FTR_BCCTR_LINK_FLUSH_ASSIST);
559
560 if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE)
561 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
562
563 if (result->behaviour & H_CPU_BEHAV_FLUSH_LINK_STACK)
564 security_ftr_set(SEC_FTR_FLUSH_LINK_STACK);
565
566 /*
567 * The features below are enabled by default, so we instead look to see
568 * if firmware has *disabled* them, and clear them if so.
569 * H_CPU_BEHAV_FAVOUR_SECURITY_H could be set only if
570 * H_CPU_BEHAV_FAVOUR_SECURITY is.
571 */
572 if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)) {
573 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
574 pseries_security_flavor = 0;
575 } else if (result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY_H)
576 pseries_security_flavor = 1;
577 else
578 pseries_security_flavor = 2;
579
580 if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR))
581 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
582
583 if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY)
584 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
585
586 if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS)
587 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
588
589 if (result->behaviour & H_CPU_BEHAV_NO_STF_BARRIER)
590 security_ftr_clear(SEC_FTR_STF_BARRIER);
591
592 if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR))
593 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
594 }
595
pseries_setup_security_mitigations(void)596 void pseries_setup_security_mitigations(void)
597 {
598 struct h_cpu_char_result result;
599 enum l1d_flush_type types;
600 bool enable;
601 long rc;
602
603 /*
604 * Set features to the defaults assumed by init_cpu_char_feature_flags()
605 * so it can set/clear again any features that might have changed after
606 * migration, and in case the hypercall fails and it is not even called.
607 */
608 powerpc_security_features = SEC_FTR_DEFAULT;
609
610 rc = plpar_get_cpu_characteristics(&result);
611 if (rc == H_SUCCESS)
612 init_cpu_char_feature_flags(&result);
613
614 /*
615 * We're the guest so this doesn't apply to us, clear it to simplify
616 * handling of it elsewhere.
617 */
618 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
619
620 types = L1D_FLUSH_FALLBACK;
621
622 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
623 types |= L1D_FLUSH_MTTRIG;
624
625 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
626 types |= L1D_FLUSH_ORI;
627
628 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
629 security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR);
630
631 setup_rfi_flush(types, enable);
632 setup_count_cache_flush();
633
634 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
635 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
636 setup_entry_flush(enable);
637
638 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
639 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
640 setup_uaccess_flush(enable);
641
642 setup_stf_barrier();
643 }
644
645 #ifdef CONFIG_PCI_IOV
646 enum rtas_iov_fw_value_map {
647 NUM_RES_PROPERTY = 0, /* Number of Resources */
648 LOW_INT = 1, /* Lowest 32 bits of Address */
649 START_OF_ENTRIES = 2, /* Always start of entry */
650 APERTURE_PROPERTY = 2, /* Start of entry+ to Aperture Size */
651 WDW_SIZE_PROPERTY = 4, /* Start of entry+ to Window Size */
652 NEXT_ENTRY = 7 /* Go to next entry on array */
653 };
654
655 enum get_iov_fw_value_index {
656 BAR_ADDRS = 1, /* Get Bar Address */
657 APERTURE_SIZE = 2, /* Get Aperture Size */
658 WDW_SIZE = 3 /* Get Window Size */
659 };
660
pseries_get_iov_fw_value(struct pci_dev * dev,int resno,enum get_iov_fw_value_index value)661 static resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int resno,
662 enum get_iov_fw_value_index value)
663 {
664 const int *indexes;
665 struct device_node *dn = pci_device_to_OF_node(dev);
666 int i, num_res, ret = 0;
667
668 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
669 if (!indexes)
670 return 0;
671
672 /*
673 * First element in the array is the number of Bars
674 * returned. Search through the list to find the matching
675 * bar
676 */
677 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
678 if (resno >= num_res)
679 return 0; /* or an error */
680
681 i = START_OF_ENTRIES + NEXT_ENTRY * resno;
682 switch (value) {
683 case BAR_ADDRS:
684 ret = of_read_number(&indexes[i], 2);
685 break;
686 case APERTURE_SIZE:
687 ret = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
688 break;
689 case WDW_SIZE:
690 ret = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
691 break;
692 }
693
694 return ret;
695 }
696
of_pci_set_vf_bar_size(struct pci_dev * dev,const int * indexes)697 static void of_pci_set_vf_bar_size(struct pci_dev *dev, const int *indexes)
698 {
699 struct resource *res;
700 resource_size_t base, size;
701 int i, r, num_res;
702
703 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
704 num_res = min_t(int, num_res, PCI_SRIOV_NUM_BARS);
705 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
706 i += NEXT_ENTRY, r++) {
707 res = &dev->resource[r + PCI_IOV_RESOURCES];
708 base = of_read_number(&indexes[i], 2);
709 size = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
710 res->flags = pci_parse_of_flags(of_read_number
711 (&indexes[i + LOW_INT], 1), 0);
712 res->flags |= (IORESOURCE_MEM_64 | IORESOURCE_PCI_FIXED);
713 res->name = pci_name(dev);
714 res->start = base;
715 res->end = base + size - 1;
716 }
717 }
718
of_pci_parse_iov_addrs(struct pci_dev * dev,const int * indexes)719 static void of_pci_parse_iov_addrs(struct pci_dev *dev, const int *indexes)
720 {
721 struct resource *res, *root, *conflict;
722 resource_size_t base, size;
723 int i, r, num_res;
724
725 /*
726 * First element in the array is the number of Bars
727 * returned. Search through the list to find the matching
728 * bars assign them from firmware into resources structure.
729 */
730 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
731 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
732 i += NEXT_ENTRY, r++) {
733 res = &dev->resource[r + PCI_IOV_RESOURCES];
734 base = of_read_number(&indexes[i], 2);
735 size = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
736 res->name = pci_name(dev);
737 res->start = base;
738 res->end = base + size - 1;
739 root = &iomem_resource;
740 dev_dbg(&dev->dev,
741 "pSeries IOV BAR %d: trying firmware assignment %pR\n",
742 r + PCI_IOV_RESOURCES, res);
743 conflict = request_resource_conflict(root, res);
744 if (conflict) {
745 dev_info(&dev->dev,
746 "BAR %d: %pR conflicts with %s %pR\n",
747 r + PCI_IOV_RESOURCES, res,
748 conflict->name, conflict);
749 res->flags |= IORESOURCE_UNSET;
750 }
751 }
752 }
753
pseries_disable_sriov_resources(struct pci_dev * pdev)754 static void pseries_disable_sriov_resources(struct pci_dev *pdev)
755 {
756 int i;
757
758 pci_warn(pdev, "No hypervisor support for SR-IOV on this device, IOV BARs disabled.\n");
759 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
760 pdev->resource[i + PCI_IOV_RESOURCES].flags = 0;
761 }
762
pseries_pci_fixup_resources(struct pci_dev * pdev)763 static void pseries_pci_fixup_resources(struct pci_dev *pdev)
764 {
765 const int *indexes;
766 struct device_node *dn = pci_device_to_OF_node(pdev);
767
768 /*Firmware must support open sriov otherwise dont configure*/
769 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
770 if (indexes)
771 of_pci_set_vf_bar_size(pdev, indexes);
772 else
773 pseries_disable_sriov_resources(pdev);
774 }
775
pseries_pci_fixup_iov_resources(struct pci_dev * pdev)776 static void pseries_pci_fixup_iov_resources(struct pci_dev *pdev)
777 {
778 const int *indexes;
779 struct device_node *dn = pci_device_to_OF_node(pdev);
780
781 if (!pdev->is_physfn)
782 return;
783 /*Firmware must support open sriov otherwise don't configure*/
784 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
785 if (indexes)
786 of_pci_parse_iov_addrs(pdev, indexes);
787 else
788 pseries_disable_sriov_resources(pdev);
789 }
790
pseries_pci_iov_resource_alignment(struct pci_dev * pdev,int resno)791 static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *pdev,
792 int resno)
793 {
794 const __be32 *reg;
795 struct device_node *dn = pci_device_to_OF_node(pdev);
796
797 /*Firmware must support open sriov otherwise report regular alignment*/
798 reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL);
799 if (!reg)
800 return pci_iov_resource_size(pdev, resno);
801
802 if (!pdev->is_physfn)
803 return 0;
804 return pseries_get_iov_fw_value(pdev,
805 resno - PCI_IOV_RESOURCES,
806 APERTURE_SIZE);
807 }
808 #endif
809
pSeries_setup_arch(void)810 static void __init pSeries_setup_arch(void)
811 {
812 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
813
814 /* Discover PIC type and setup ppc_md accordingly */
815 smp_init_pseries();
816
817 // Setup CPU hotplug callbacks
818 pseries_cpu_hotplug_init();
819
820 if (radix_enabled() && !mmu_has_feature(MMU_FTR_GTSE))
821 if (!firmware_has_feature(FW_FEATURE_RPT_INVALIDATE))
822 panic("BUG: Radix support requires either GTSE or RPT_INVALIDATE\n");
823
824
825 /* openpic global configuration register (64-bit format). */
826 /* openpic Interrupt Source Unit pointer (64-bit format). */
827 /* python0 facility area (mmio) (64-bit format) REAL address. */
828
829 /* init to some ~sane value until calibrate_delay() runs */
830 loops_per_jiffy = 50000000;
831
832 fwnmi_init();
833
834 pseries_setup_security_mitigations();
835 if (!radix_enabled())
836 pseries_lpar_read_hblkrm_characteristics();
837
838 /* By default, only probe PCI (can be overridden by rtas_pci) */
839 pci_add_flags(PCI_PROBE_ONLY);
840
841 /* Find and initialize PCI host bridges */
842 init_pci_config_tokens();
843 of_reconfig_notifier_register(&pci_dn_reconfig_nb);
844
845 pSeries_nvram_init();
846
847 if (firmware_has_feature(FW_FEATURE_LPAR)) {
848 vpa_init(boot_cpuid);
849
850 if (lppaca_shared_proc()) {
851 static_branch_enable(&shared_processor);
852 pv_spinlocks_init();
853 #ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING
854 static_key_slow_inc(¶virt_steal_enabled);
855 if (steal_acc)
856 static_key_slow_inc(¶virt_steal_rq_enabled);
857 #endif
858 }
859
860 ppc_md.power_save = pseries_lpar_idle;
861 ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
862 #ifdef CONFIG_PCI_IOV
863 ppc_md.pcibios_fixup_resources =
864 pseries_pci_fixup_resources;
865 ppc_md.pcibios_fixup_sriov =
866 pseries_pci_fixup_iov_resources;
867 ppc_md.pcibios_iov_resource_alignment =
868 pseries_pci_iov_resource_alignment;
869 #endif
870 } else {
871 /* No special idle routine */
872 ppc_md.enable_pmcs = power4_enable_pmcs;
873 }
874
875 ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare;
876 pseries_rng_init();
877 }
878
pseries_panic(char * str)879 static void pseries_panic(char *str)
880 {
881 panic_flush_kmsg_end();
882 rtas_os_term(str);
883 }
884
pSeries_init_panel(void)885 static int __init pSeries_init_panel(void)
886 {
887 /* Manually leave the kernel version on the panel. */
888 #ifdef __BIG_ENDIAN__
889 ppc_md.progress("Linux ppc64\n", 0);
890 #else
891 ppc_md.progress("Linux ppc64le\n", 0);
892 #endif
893 ppc_md.progress(init_utsname()->version, 0);
894
895 return 0;
896 }
897 machine_arch_initcall(pseries, pSeries_init_panel);
898
pseries_set_dabr(unsigned long dabr,unsigned long dabrx)899 static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx)
900 {
901 return plpar_hcall_norets(H_SET_DABR, dabr);
902 }
903
pseries_set_xdabr(unsigned long dabr,unsigned long dabrx)904 static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx)
905 {
906 /* Have to set at least one bit in the DABRX according to PAPR */
907 if (dabrx == 0 && dabr == 0)
908 dabrx = DABRX_USER;
909 /* PAPR says we can only set kernel and user bits */
910 dabrx &= DABRX_KERNEL | DABRX_USER;
911
912 return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx);
913 }
914
pseries_set_dawr(int nr,unsigned long dawr,unsigned long dawrx)915 static int pseries_set_dawr(int nr, unsigned long dawr, unsigned long dawrx)
916 {
917 /* PAPR says we can't set HYP */
918 dawrx &= ~DAWRX_HYP;
919
920 if (nr == 0)
921 return plpar_set_watchpoint0(dawr, dawrx);
922 else
923 return plpar_set_watchpoint1(dawr, dawrx);
924 }
925
926 #define CMO_CHARACTERISTICS_TOKEN 44
927 #define CMO_MAXLENGTH 1026
928
pSeries_coalesce_init(void)929 void pSeries_coalesce_init(void)
930 {
931 struct hvcall_mpp_x_data mpp_x_data;
932
933 if (firmware_has_feature(FW_FEATURE_CMO) && !h_get_mpp_x(&mpp_x_data))
934 powerpc_firmware_features |= FW_FEATURE_XCMO;
935 else
936 powerpc_firmware_features &= ~FW_FEATURE_XCMO;
937 }
938
939 /**
940 * fw_cmo_feature_init - FW_FEATURE_CMO is not stored in ibm,hypertas-functions,
941 * handle that here. (Stolen from parse_system_parameter_string)
942 */
pSeries_cmo_feature_init(void)943 static void __init pSeries_cmo_feature_init(void)
944 {
945 static struct papr_sysparm_buf buf __initdata;
946 static_assert(sizeof(buf.val) >= CMO_MAXLENGTH);
947 char *ptr, *key, *value, *end;
948 int page_order = IOMMU_PAGE_SHIFT_4K;
949
950 pr_debug(" -> fw_cmo_feature_init()\n");
951
952 if (papr_sysparm_get(PAPR_SYSPARM_COOP_MEM_OVERCOMMIT_ATTRS, &buf)) {
953 pr_debug("CMO not available\n");
954 pr_debug(" <- fw_cmo_feature_init()\n");
955 return;
956 }
957
958 end = &buf.val[CMO_MAXLENGTH];
959 ptr = &buf.val[0];
960 key = value = ptr;
961
962 while (*ptr && (ptr <= end)) {
963 /* Separate the key and value by replacing '=' with '\0' and
964 * point the value at the string after the '='
965 */
966 if (ptr[0] == '=') {
967 ptr[0] = '\0';
968 value = ptr + 1;
969 } else if (ptr[0] == '\0' || ptr[0] == ',') {
970 /* Terminate the string containing the key/value pair */
971 ptr[0] = '\0';
972
973 if (key == value) {
974 pr_debug("Malformed key/value pair\n");
975 /* Never found a '=', end processing */
976 break;
977 }
978
979 if (0 == strcmp(key, "CMOPageSize"))
980 page_order = simple_strtol(value, NULL, 10);
981 else if (0 == strcmp(key, "PrPSP"))
982 CMO_PrPSP = simple_strtol(value, NULL, 10);
983 else if (0 == strcmp(key, "SecPSP"))
984 CMO_SecPSP = simple_strtol(value, NULL, 10);
985 value = key = ptr + 1;
986 }
987 ptr++;
988 }
989
990 /* Page size is returned as the power of 2 of the page size,
991 * convert to the page size in bytes before returning
992 */
993 CMO_PageSize = 1 << page_order;
994 pr_debug("CMO_PageSize = %lu\n", CMO_PageSize);
995
996 if (CMO_PrPSP != -1 || CMO_SecPSP != -1) {
997 pr_info("CMO enabled\n");
998 pr_debug("CMO enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
999 CMO_SecPSP);
1000 powerpc_firmware_features |= FW_FEATURE_CMO;
1001 pSeries_coalesce_init();
1002 } else
1003 pr_debug("CMO not enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
1004 CMO_SecPSP);
1005 pr_debug(" <- fw_cmo_feature_init()\n");
1006 }
1007
pseries_add_hw_description(void)1008 static void __init pseries_add_hw_description(void)
1009 {
1010 struct device_node *dn;
1011 const char *s;
1012
1013 dn = of_find_node_by_path("/openprom");
1014 if (dn) {
1015 if (of_property_read_string(dn, "model", &s) == 0)
1016 seq_buf_printf(&ppc_hw_desc, "of:%s ", s);
1017
1018 of_node_put(dn);
1019 }
1020
1021 dn = of_find_node_by_path("/hypervisor");
1022 if (dn) {
1023 if (of_property_read_string(dn, "compatible", &s) == 0)
1024 seq_buf_printf(&ppc_hw_desc, "hv:%s ", s);
1025
1026 of_node_put(dn);
1027 return;
1028 }
1029
1030 dn = of_find_node_by_path("/");
1031 if (of_property_read_bool(dn, "ibm,powervm-partition") ||
1032 of_property_read_bool(dn, "ibm,fw-net-version"))
1033 seq_buf_printf(&ppc_hw_desc, "hv:phyp ");
1034 of_node_put(dn);
1035 }
1036
1037 /*
1038 * Early initialization. Relocation is on but do not reference unbolted pages
1039 */
pseries_init(void)1040 static void __init pseries_init(void)
1041 {
1042 pr_debug(" -> pseries_init()\n");
1043
1044 pseries_add_hw_description();
1045
1046 #ifdef CONFIG_HVC_CONSOLE
1047 if (firmware_has_feature(FW_FEATURE_LPAR))
1048 hvc_vio_init_early();
1049 #endif
1050 if (firmware_has_feature(FW_FEATURE_XDABR))
1051 ppc_md.set_dabr = pseries_set_xdabr;
1052 else if (firmware_has_feature(FW_FEATURE_DABR))
1053 ppc_md.set_dabr = pseries_set_dabr;
1054
1055 if (firmware_has_feature(FW_FEATURE_SET_MODE))
1056 ppc_md.set_dawr = pseries_set_dawr;
1057
1058 pSeries_cmo_feature_init();
1059 iommu_init_early_pSeries();
1060
1061 pr_debug(" <- pseries_init()\n");
1062 }
1063
1064 /**
1065 * pseries_power_off - tell firmware about how to power off the system.
1066 *
1067 * This function calls either the power-off rtas token in normal cases
1068 * or the ibm,power-off-ups token (if present & requested) in case of
1069 * a power failure. If power-off token is used, power on will only be
1070 * possible with power button press. If ibm,power-off-ups token is used
1071 * it will allow auto poweron after power is restored.
1072 */
pseries_power_off(void)1073 static void pseries_power_off(void)
1074 {
1075 int rc;
1076 int rtas_poweroff_ups_token = rtas_function_token(RTAS_FN_IBM_POWER_OFF_UPS);
1077
1078 if (rtas_flash_term_hook)
1079 rtas_flash_term_hook(SYS_POWER_OFF);
1080
1081 if (rtas_poweron_auto == 0 ||
1082 rtas_poweroff_ups_token == RTAS_UNKNOWN_SERVICE) {
1083 rc = rtas_call(rtas_function_token(RTAS_FN_POWER_OFF), 2, 1, NULL, -1, -1);
1084 printk(KERN_INFO "RTAS power-off returned %d\n", rc);
1085 } else {
1086 rc = rtas_call(rtas_poweroff_ups_token, 0, 1, NULL);
1087 printk(KERN_INFO "RTAS ibm,power-off-ups returned %d\n", rc);
1088 }
1089 for (;;);
1090 }
1091
pSeries_probe(void)1092 static int __init pSeries_probe(void)
1093 {
1094 struct device_node *root = of_find_node_by_path("/");
1095 bool ret = of_node_is_type(root, "chrp");
1096
1097 of_node_put(root);
1098 if (!ret)
1099 return 0;
1100
1101 /* Cell blades firmware claims to be chrp while it's not. Until this
1102 * is fixed, we need to avoid those here.
1103 */
1104 if (of_machine_is_compatible("IBM,CPBW-1.0") ||
1105 of_machine_is_compatible("IBM,CBEA"))
1106 return 0;
1107
1108 pm_power_off = pseries_power_off;
1109
1110 pr_debug("Machine is%s LPAR !\n",
1111 (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not");
1112
1113 pseries_init();
1114
1115 return 1;
1116 }
1117
pSeries_pci_probe_mode(struct pci_bus * bus)1118 static int pSeries_pci_probe_mode(struct pci_bus *bus)
1119 {
1120 if (firmware_has_feature(FW_FEATURE_LPAR))
1121 return PCI_PROBE_DEVTREE;
1122 return PCI_PROBE_NORMAL;
1123 }
1124
1125 #ifdef CONFIG_MEMORY_HOTPLUG
pseries_memory_block_size(void)1126 static unsigned long pseries_memory_block_size(void)
1127 {
1128 return memory_block_size;
1129 }
1130 #endif
1131
1132 struct pci_controller_ops pseries_pci_controller_ops = {
1133 .probe_mode = pSeries_pci_probe_mode,
1134 #ifdef CONFIG_SPAPR_TCE_IOMMU
1135 .device_group = pSeries_pci_device_group,
1136 #endif
1137 };
1138
define_machine(pseries)1139 define_machine(pseries) {
1140 .name = "pSeries",
1141 .probe = pSeries_probe,
1142 .setup_arch = pSeries_setup_arch,
1143 .init_IRQ = pseries_init_irq,
1144 .show_cpuinfo = pSeries_show_cpuinfo,
1145 .log_error = pSeries_log_error,
1146 .discover_phbs = pSeries_discover_phbs,
1147 .pcibios_fixup = pSeries_final_fixup,
1148 .restart = rtas_restart,
1149 .halt = rtas_halt,
1150 .panic = pseries_panic,
1151 .get_boot_time = rtas_get_boot_time,
1152 .get_rtc_time = rtas_get_rtc_time,
1153 .set_rtc_time = rtas_set_rtc_time,
1154 .progress = rtas_progress,
1155 .system_reset_exception = pSeries_system_reset_exception,
1156 .machine_check_early = pseries_machine_check_realmode,
1157 .machine_check_exception = pSeries_machine_check_exception,
1158 .machine_check_log_err = pSeries_machine_check_log_err,
1159 #ifdef CONFIG_KEXEC_CORE
1160 .kexec_cpu_down = pseries_kexec_cpu_down,
1161 #endif
1162 #ifdef CONFIG_MEMORY_HOTPLUG
1163 .memory_block_size = pseries_memory_block_size,
1164 #endif
1165 };
1166